diff options
Diffstat (limited to 'src/soc/intel/common/block')
31 files changed, 184 insertions, 84 deletions
diff --git a/src/soc/intel/common/block/acpi/cpu_hybrid.c b/src/soc/intel/common/block/acpi/cpu_hybrid.c index f52b68f7e222..68abba7eb8d6 100644 --- a/src/soc/intel/common/block/acpi/cpu_hybrid.c +++ b/src/soc/intel/common/block/acpi/cpu_hybrid.c @@ -9,6 +9,7 @@ #include <device/path.h> #include <intelblocks/acpi.h> #include <soc/cpu.h> +#include <stdio.h> #include <types.h> #define CPPC_NOM_FREQ_IDX 22 diff --git a/src/soc/intel/common/block/cnvi/cnvi.c b/src/soc/intel/common/block/cnvi/cnvi.c index fed95492f7e8..62c4615d602d 100644 --- a/src/soc/intel/common/block/cnvi/cnvi.c +++ b/src/soc/intel/common/block/cnvi/cnvi.c @@ -21,6 +21,14 @@ static struct device_operations cnvi_wifi_ops = { }; static const unsigned short wifi_pci_device_ids[] = { + PCI_DID_INTEL_PTL_CNVI_WIFI_0, + PCI_DID_INTEL_PTL_CNVI_WIFI_1, + PCI_DID_INTEL_PTL_CNVI_WIFI_2, + PCI_DID_INTEL_PTL_CNVI_WIFI_3, + PCI_DID_INTEL_LNL_CNVI_WIFI_0, + PCI_DID_INTEL_LNL_CNVI_WIFI_1, + PCI_DID_INTEL_LNL_CNVI_WIFI_2, + PCI_DID_INTEL_LNL_CNVI_WIFI_3, PCI_DID_INTEL_MTL_CNVI_WIFI_0, PCI_DID_INTEL_MTL_CNVI_WIFI_1, PCI_DID_INTEL_MTL_CNVI_WIFI_2, diff --git a/src/soc/intel/common/block/cpu/mp_init.c b/src/soc/intel/common/block/cpu/mp_init.c index 7abbb4063e2e..d5cc88397397 100644 --- a/src/soc/intel/common/block/cpu/mp_init.c +++ b/src/soc/intel/common/block/cpu/mp_init.c @@ -32,7 +32,9 @@ static struct device_operations cpu_dev_ops = { }; static const struct cpu_device_id cpu_table[] = { + { X86_VENDOR_INTEL, CPUID_PANTHERLAKE_A0, CPUID_EXACT_MATCH_MASK }, { X86_VENDOR_INTEL, CPUID_LUNARLAKE_A0_1, CPUID_EXACT_MATCH_MASK }, + { X86_VENDOR_INTEL, CPUID_LUNARLAKE_A0_2, CPUID_EXACT_MATCH_MASK }, { X86_VENDOR_INTEL, CPUID_METEORLAKE_A0_1, CPUID_EXACT_MATCH_MASK }, { X86_VENDOR_INTEL, CPUID_METEORLAKE_A0_2, CPUID_EXACT_MATCH_MASK }, { X86_VENDOR_INTEL, CPUID_METEORLAKE_B0, CPUID_EXACT_MATCH_MASK }, diff --git a/src/soc/intel/common/block/crashlog/crashlog.c b/src/soc/intel/common/block/crashlog/crashlog.c index a9ac8a530ecd..d92d7bc69b8b 100644 --- a/src/soc/intel/common/block/crashlog/crashlog.c +++ b/src/soc/intel/common/block/crashlog/crashlog.c @@ -112,7 +112,7 @@ int cpu_cl_poll_mailbox_ready(u32 cl_mailbox_addr) u16 stall_cnt = 0; do { - cl_mailbox_interface.data = read32((u32 *)cl_mailbox_addr); + cl_mailbox_interface.data = read32((u32 *)(uintptr_t)cl_mailbox_addr); udelay(CPU_CRASHLOG_WAIT_STALL); stall_cnt++; } while ((cl_mailbox_interface.fields.busy == 1) @@ -140,7 +140,7 @@ int cpu_cl_mailbox_cmd(u8 cmd, u8 param) cl_mailbox_intf.fields.param = param; cl_mailbox_intf.fields.busy = 1; - write32((u32 *)(cl_base_addr + cl_get_cpu_mb_int_addr()), + write32((u32 *)(uintptr_t)(cl_base_addr + cl_get_cpu_mb_int_addr()), cl_mailbox_intf.data); cpu_cl_poll_mailbox_ready(cl_base_addr + cl_get_cpu_mb_int_addr()); @@ -167,7 +167,7 @@ int pmc_cl_gen_descriptor_table(u32 desc_table_addr, pmc_crashlog_desc_table_t *descriptor_table) { int total_data_size = 0; - descriptor_table->numb_regions = read32((u32 *)desc_table_addr); + descriptor_table->numb_regions = read32((u32 *)(uintptr_t)desc_table_addr); printk(BIOS_DEBUG, "CL PMC desc table: numb of regions is 0x%x at addr 0x%x\n", descriptor_table->numb_regions, desc_table_addr); for (int i = 0; i < descriptor_table->numb_regions; i++) { @@ -178,7 +178,7 @@ int pmc_cl_gen_descriptor_table(u32 desc_table_addr, break; } desc_table_addr += 4; - descriptor_table->regions[i].data = read32((u32 *)(desc_table_addr)); + descriptor_table->regions[i].data = read32((u32 *)(uintptr_t)(desc_table_addr)); total_data_size += descriptor_table->regions[i].bits.size * sizeof(u32); printk(BIOS_DEBUG, "CL PMC desc table: region 0x%x has size 0x%x at offset 0x%x\n", i, descriptor_table->regions[i].bits.size, @@ -295,7 +295,7 @@ bool cl_copy_data_from_sram(u32 src_bar, u32 src_addr = src_bar + offset; - u32 data = read32((u32 *)src_addr); + u32 data = read32((u32 *)(uintptr_t)src_addr); /* First 32bits of the record must not be 0xdeadbeef */ if (data == INVALID_CRASHLOG_RECORD) { @@ -320,7 +320,7 @@ bool cl_copy_data_from_sram(u32 src_bar, u32 copied = 0; while (copied < size) { /* DW by DW copy: byte access to PMC SRAM not allowed */ - *dest_addr = read32((u32 *)src_addr); + *dest_addr = read32((u32 *)(uintptr_t)src_addr); dest_addr++; src_addr += 4; copied++; diff --git a/src/soc/intel/common/block/cse/Kconfig b/src/soc/intel/common/block/cse/Kconfig index b0524ea4f808..edc7e23d1b3b 100644 --- a/src/soc/intel/common/block/cse/Kconfig +++ b/src/soc/intel/common/block/cse/Kconfig @@ -150,6 +150,16 @@ config SOC_INTEL_CSE_SEND_EOP_BY_PAYLOAD In this case, the HECI interface needs to stay visible and the payload must support sending commands to CSE. +config SOC_INTEL_CSE_LITE_SYNC_BY_PAYLOAD + bool + depends on SOC_INTEL_COMMON_BLOCK_CSE + help + Use this config to specify that the payload will update the CSE RW partition instead + of coreboot. + + In this case, CSE shall not switch to RW partition and the payload must support + CSE RW update. + config SOC_INTEL_CSE_LITE_SKU bool default n diff --git a/src/soc/intel/common/block/cse/cse.c b/src/soc/intel/common/block/cse/cse.c index d0ca57bc054f..d78b8a010129 100644 --- a/src/soc/intel/common/block/cse/cse.c +++ b/src/soc/intel/common/block/cse/cse.c @@ -1475,6 +1475,7 @@ struct device_operations cse_ops = { }; static const unsigned short pci_device_ids[] = { + PCI_DID_INTEL_PTL_CSE0, PCI_DID_INTEL_LNL_CSE0, PCI_DID_INTEL_MTL_CSE0, PCI_DID_INTEL_APL_CSE0, diff --git a/src/soc/intel/common/block/cse/cse_lite.c b/src/soc/intel/common/block/cse/cse_lite.c index 3579bcea78dd..6e5b451c1249 100644 --- a/src/soc/intel/common/block/cse/cse_lite.c +++ b/src/soc/intel/common/block/cse/cse_lite.c @@ -923,6 +923,9 @@ static bool is_cse_fw_update_enabled(void) if (!CONFIG(SOC_INTEL_CSE_RW_UPDATE)) return false; + if (CONFIG(SOC_INTEL_CSE_LITE_SYNC_BY_PAYLOAD)) + return false; + if (CONFIG(SOC_INTEL_COMMON_BASECODE_DEBUG_FEATURE)) return !is_debug_cse_fw_update_disable(); @@ -1499,6 +1502,9 @@ static void do_cse_fw_sync(void) void cse_fw_sync(void) { + if (CONFIG(SOC_INTEL_CSE_LITE_SYNC_BY_PAYLOAD)) + return; + timestamp_add_now(TS_CSE_FW_SYNC_START); do_cse_fw_sync(); timestamp_add_now(TS_CSE_FW_SYNC_END); diff --git a/src/soc/intel/common/block/dsp/dsp.c b/src/soc/intel/common/block/dsp/dsp.c index 1f11df06cf2d..7e8322e38290 100644 --- a/src/soc/intel/common/block/dsp/dsp.c +++ b/src/soc/intel/common/block/dsp/dsp.c @@ -13,6 +13,14 @@ static struct device_operations dsp_dev_ops = { }; static const unsigned short pci_device_ids[] = { + PCI_DID_INTEL_PTL_AUDIO_1, + PCI_DID_INTEL_PTL_AUDIO_2, + PCI_DID_INTEL_PTL_AUDIO_3, + PCI_DID_INTEL_PTL_AUDIO_4, + PCI_DID_INTEL_PTL_AUDIO_5, + PCI_DID_INTEL_PTL_AUDIO_6, + PCI_DID_INTEL_PTL_AUDIO_7, + PCI_DID_INTEL_PTL_AUDIO_8, PCI_DID_INTEL_LNL_AUDIO_1, PCI_DID_INTEL_LNL_AUDIO_2, PCI_DID_INTEL_LNL_AUDIO_3, diff --git a/src/soc/intel/common/block/fast_spi/fast_spi_flash.c b/src/soc/intel/common/block/fast_spi/fast_spi_flash.c index e9cfc230a409..a7762711fa76 100644 --- a/src/soc/intel/common/block/fast_spi/fast_spi_flash.c +++ b/src/soc/intel/common/block/fast_spi/fast_spi_flash.c @@ -75,18 +75,28 @@ static uint32_t fast_spi_flash_read_sfdp(struct fast_spi_flash_ctx *ctx, /* Fill FDATAn FIFO in preparation for a write transaction. */ static void fill_xfer_fifo(struct fast_spi_flash_ctx *ctx, const void *data, - size_t len) + size_t len) { - /* YES! memcpy() works. FDATAn does not require 32-bit accesses. */ - memcpy((void *)(ctx->mmio_base + SPIBAR_FDATA(0)), data, len); + const uint32_t *data32 = (const uint32_t *)data; + for (size_t i = 0; i < len / sizeof(uint32_t); i++) + write32p(ctx->mmio_base + SPIBAR_FDATA(i), *data32++); + + const uint8_t *data8 = (const uint8_t *)data32; + for (size_t i = 0; i < len % sizeof(uint32_t); i++) + write8p(ctx->mmio_base + SPIBAR_FDATA(len / sizeof(uint32_t)) + i, *data8++); } /* Drain FDATAn FIFO after a read transaction populates data. */ -static void drain_xfer_fifo(struct fast_spi_flash_ctx *ctx, void *dest, +static void drain_xfer_fifo(struct fast_spi_flash_ctx *ctx, void *data, size_t len) { - /* YES! memcpy() works. FDATAn does not require 32-bit accesses. */ - memcpy(dest, (void *)(ctx->mmio_base + SPIBAR_FDATA(0)), len); + uint32_t *data32 = (uint32_t *)data; + for (size_t i = 0; i < len / sizeof(uint32_t); i++) + *data32++ = read32p(ctx->mmio_base + SPIBAR_FDATA(i)); + + uint8_t *data8 = (uint8_t *)data32; + for (size_t i = 0; i < len % sizeof(uint32_t); i++) + *data8++ = read8p(ctx->mmio_base + SPIBAR_FDATA(len / sizeof(uint32_t)) + i); } /* Fire up a transfer using the hardware sequencer. */ diff --git a/src/soc/intel/common/block/graphics/Kconfig b/src/soc/intel/common/block/graphics/Kconfig index b5776b049fa4..eaa429ed393e 100644 --- a/src/soc/intel/common/block/graphics/Kconfig +++ b/src/soc/intel/common/block/graphics/Kconfig @@ -8,10 +8,20 @@ config SOC_INTEL_COMMON_BLOCK_GRAPHICS if SOC_INTEL_COMMON_BLOCK_GRAPHICS -config SOC_INTEL_CONFIGURE_DDI_A_4_LANES +config SOC_INTEL_GFX_HAVE_DDI_A_BIFURCATION bool help - Selected by platforms that require DDI-A bifurcation setup. + Skylake, Kaby Lake and Coffee Lake desktop CPUs support eDP + bifurcation, i.e. 4 eDP lanes get split between DDI-A (eDP) + and DDI-E (DP, used for VGA). Selected from SoC Kconfig, if + applicable. + +config SOC_INTEL_GFX_ENABLE_DDI_E_BIFURCATION + bool + depends on SOC_INTEL_GFX_HAVE_DDI_A_BIFURCATION + help + Selected by mainboards that use DDI-E, which is most commonly + used to drive a DP-to-VGA adapter to provide a VGA connector. config SOC_INTEL_DISABLE_IGD bool "Disable Integrated GFX Controller (0:2:0)" diff --git a/src/soc/intel/common/block/graphics/graphics.c b/src/soc/intel/common/block/graphics/graphics.c index eabcb9a5a8ca..1606b96485c7 100644 --- a/src/soc/intel/common/block/graphics/graphics.c +++ b/src/soc/intel/common/block/graphics/graphics.c @@ -124,6 +124,21 @@ int fsp_soc_report_external_display(void) return graphics_get_framebuffer_address() && get_external_display_status(); } +static void configure_ddi_a_bifurcation(void) +{ + u32 ddi_buf_ctl = graphics_gtt_read(DDI_BUF_CTL_A); + /* Only program if the buffer is not enabled yet. */ + if (ddi_buf_ctl & DDI_BUF_CTL_ENABLE) + return; + + if (CONFIG(SOC_INTEL_GFX_ENABLE_DDI_E_BIFURCATION)) + ddi_buf_ctl &= ~DDI_A_4_LANES; + else + ddi_buf_ctl |= DDI_A_4_LANES; + + graphics_gtt_write(DDI_BUF_CTL_A, ddi_buf_ctl); +} + static void gma_init(struct device *const dev) { intel_gma_init_igd_opregion(); @@ -135,12 +150,8 @@ static void gma_init(struct device *const dev) if (!CONFIG(RUN_FSP_GOP)) graphics_soc_panel_init(dev); - if (CONFIG(SOC_INTEL_CONFIGURE_DDI_A_4_LANES) && !acpi_is_wakeup_s3()) { - const u32 ddi_buf_ctl = graphics_gtt_read(DDI_BUF_CTL_A); - /* Only program if the buffer is not enabled yet. */ - if (!(ddi_buf_ctl & DDI_BUF_CTL_ENABLE)) - graphics_gtt_write(DDI_BUF_CTL_A, ddi_buf_ctl | DDI_A_4_LANES); - } + if (CONFIG(SOC_INTEL_GFX_HAVE_DDI_A_BIFURCATION) && !acpi_is_wakeup_s3()) + configure_ddi_a_bifurcation(); /* * GFX PEIM module inside FSP binary is taking care of graphics @@ -332,6 +343,7 @@ const struct device_operations graphics_ops = { }; static const unsigned short pci_device_ids[] = { + PCI_DID_INTEL_PTL_GT2, PCI_DID_INTEL_LNL_M_GT2, PCI_DID_INTEL_RPL_U_GT1, PCI_DID_INTEL_RPL_U_GT2, @@ -348,6 +360,7 @@ static const unsigned short pci_device_ids[] = { PCI_DID_INTEL_MTL_P_GT2_2, PCI_DID_INTEL_MTL_P_GT2_3, PCI_DID_INTEL_MTL_P_GT2_4, + PCI_DID_INTEL_MTL_P_GT2_5, PCI_DID_INTEL_APL_IGD_HD_505, PCI_DID_INTEL_APL_IGD_HD_500, PCI_DID_INTEL_CNL_GT2_ULX_1, diff --git a/src/soc/intel/common/block/hda/hda.c b/src/soc/intel/common/block/hda/hda.c index 44c03417b20c..ca503126752b 100644 --- a/src/soc/intel/common/block/hda/hda.c +++ b/src/soc/intel/common/block/hda/hda.c @@ -21,6 +21,14 @@ struct device_operations hda_ops = { }; static const unsigned short pci_device_ids[] = { + PCI_DID_INTEL_PTL_AUDIO_1, + PCI_DID_INTEL_PTL_AUDIO_2, + PCI_DID_INTEL_PTL_AUDIO_3, + PCI_DID_INTEL_PTL_AUDIO_4, + PCI_DID_INTEL_PTL_AUDIO_5, + PCI_DID_INTEL_PTL_AUDIO_6, + PCI_DID_INTEL_PTL_AUDIO_7, + PCI_DID_INTEL_PTL_AUDIO_8, PCI_DID_INTEL_LNL_AUDIO_1, PCI_DID_INTEL_LNL_AUDIO_2, PCI_DID_INTEL_LNL_AUDIO_3, diff --git a/src/soc/intel/common/block/i2c/i2c.c b/src/soc/intel/common/block/i2c/i2c.c index c0f0b6e0bab6..f84b2cd32850 100644 --- a/src/soc/intel/common/block/i2c/i2c.c +++ b/src/soc/intel/common/block/i2c/i2c.c @@ -174,6 +174,12 @@ struct device_operations i2c_dev_ops = { }; static const unsigned short pci_device_ids[] = { + PCI_DID_INTEL_PTL_I2C0, + PCI_DID_INTEL_PTL_I2C1, + PCI_DID_INTEL_PTL_I2C2, + PCI_DID_INTEL_PTL_I2C3, + PCI_DID_INTEL_PTL_I2C4, + PCI_DID_INTEL_PTL_I2C5, PCI_DID_INTEL_LNL_I2C0, PCI_DID_INTEL_LNL_I2C1, PCI_DID_INTEL_LNL_I2C2, diff --git a/src/soc/intel/common/block/include/intelblocks/vtd.h b/src/soc/intel/common/block/include/intelblocks/vtd.h index 222101a2444e..137124b43a61 100644 --- a/src/soc/intel/common/block/include/intelblocks/vtd.h +++ b/src/soc/intel/common/block/include/intelblocks/vtd.h @@ -3,8 +3,42 @@ #ifndef SOC_INTEL_COMMON_BLOCK_VTD_H #define SOC_INTEL_COMMON_BLOCK_VTD_H +#include <device/mmio.h> #include <stdint.h> +/* VT-d specification: https://cdrdv2.intel.com/v1/dl/getContent/671081 */ +#define VER_REG 0x0 +#define CAP_REG 0x8 +#define CAP_PMR_LO BIT(5) +#define CAP_PMR_HI BIT(6) +#define PMEN_REG 0x64 +#define PMEN_EPM BIT(31) +#define PMEN_PRS BIT(0) +#define PLMBASE_REG 0x68 +#define PLMLIMIT_REG 0x6C +#define PHMBASE_REG 0x70 +#define PHMLIMIT_REG 0x78 + +static __always_inline uint32_t vtd_read32(uintptr_t vtd_base, uint32_t reg) +{ + return read32p(vtd_base + reg); +} + +static __always_inline void vtd_write32(uintptr_t vtd_base, uint32_t reg, uint32_t value) +{ + return write32p(vtd_base + reg, value); +} + +static __always_inline uint64_t vtd_read64(uintptr_t vtd_base, uint32_t reg) +{ + return read64p(vtd_base + reg); +} + +static __always_inline void vtd_write64(uintptr_t vtd_base, uint32_t reg, uint64_t value) +{ + return write64p(vtd_base + reg, value); +} + /* * Enable DMA protection by setting PMR registers in VT-d for whole DRAM memory. */ diff --git a/src/soc/intel/common/block/ipu/ipu.c b/src/soc/intel/common/block/ipu/ipu.c index b2d3904b06d1..989da2e76a01 100644 --- a/src/soc/intel/common/block/ipu/ipu.c +++ b/src/soc/intel/common/block/ipu/ipu.c @@ -12,6 +12,7 @@ struct device_operations ipu_pci_ops = { }; static const uint16_t pci_device_ids[] = { + PCI_DID_INTEL_PTL_IPU, PCI_DID_INTEL_LNL_IPU, PCI_DID_INTEL_RPL_IPU, PCI_DID_INTEL_MTL_IPU, diff --git a/src/soc/intel/common/block/irq/irq.c b/src/soc/intel/common/block/irq/irq.c index 4ffe1387983a..386538e61b4d 100644 --- a/src/soc/intel/common/block/irq/irq.c +++ b/src/soc/intel/common/block/irq/irq.c @@ -373,7 +373,7 @@ bool generate_pin_irq_map(void) if (!cached_entries) return false; - pin_irq_map = calloc(MAX_SLOTS, sizeof(struct slot_pin_irq_map) * PCI_INT_MAX); + pin_irq_map = calloc(MAX_SLOTS * PCI_INT_MAX, sizeof(struct slot_pin_irq_map)); pirq_map.type = PIRQ_GSI; legacy_pirq_routing = lpc_get_pic_pirq_routing(&pirq_routes); diff --git a/src/soc/intel/common/block/lpc/lpc.c b/src/soc/intel/common/block/lpc/lpc.c index e8050354bcdf..0b8c722a69ac 100644 --- a/src/soc/intel/common/block/lpc/lpc.c +++ b/src/soc/intel/common/block/lpc/lpc.c @@ -141,6 +141,14 @@ struct device_operations lpc_ops = { }; static const unsigned short pci_device_ids[] = { + PCI_DID_INTEL_PTL_ESPI_0, + PCI_DID_INTEL_PTL_ESPI_1, + PCI_DID_INTEL_PTL_ESPI_2, + PCI_DID_INTEL_PTL_ESPI_3, + PCI_DID_INTEL_PTL_ESPI_4, + PCI_DID_INTEL_PTL_ESPI_5, + PCI_DID_INTEL_PTL_ESPI_6, + PCI_DID_INTEL_PTL_ESPI_7, PCI_DID_INTEL_LNL_ESPI_0, PCI_DID_INTEL_LNL_ESPI_1, PCI_DID_INTEL_LNL_ESPI_2, diff --git a/src/soc/intel/common/block/pcie/pcie.c b/src/soc/intel/common/block/pcie/pcie.c index 5c6681d0d097..3c5e26a2e386 100644 --- a/src/soc/intel/common/block/pcie/pcie.c +++ b/src/soc/intel/common/block/pcie/pcie.c @@ -67,6 +67,14 @@ struct device_operations pcie_rp_ops = { }; static const unsigned short pcie_device_ids[] = { + PCI_DID_INTEL_PTL_PCIE_RP1, + PCI_DID_INTEL_PTL_PCIE_RP2, + PCI_DID_INTEL_PTL_PCIE_RP3, + PCI_DID_INTEL_PTL_PCIE_RP4, + PCI_DID_INTEL_PTL_PCIE_RP5, + PCI_DID_INTEL_PTL_PCIE_RP6, + PCI_DID_INTEL_PTL_PCIE_RP7, + PCI_DID_INTEL_PTL_PCIE_RP8, PCI_DID_INTEL_LNL_PCIE_RP1, PCI_DID_INTEL_LNL_PCIE_RP2, PCI_DID_INTEL_LNL_PCIE_RP3, diff --git a/src/soc/intel/common/block/pmc/pmc.c b/src/soc/intel/common/block/pmc/pmc.c index ca575ff7b0d3..bc70b1ac4388 100644 --- a/src/soc/intel/common/block/pmc/pmc.c +++ b/src/soc/intel/common/block/pmc/pmc.c @@ -111,6 +111,7 @@ struct device_operations pmc_ops = { }; static const unsigned short pci_device_ids[] = { + PCI_DID_INTEL_PTL_PMC, PCI_DID_INTEL_LNL_PMC, PCI_DID_INTEL_MTL_SOC_PMC, PCI_DID_INTEL_MTL_IOE_M_PMC, diff --git a/src/soc/intel/common/block/smbus/smbus.c b/src/soc/intel/common/block/smbus/smbus.c index 97651c0f098e..7f87a523e8a5 100644 --- a/src/soc/intel/common/block/smbus/smbus.c +++ b/src/soc/intel/common/block/smbus/smbus.c @@ -49,6 +49,7 @@ struct device_operations smbus_ops = { }; static const unsigned short pci_device_ids[] = { + PCI_DID_INTEL_PTL_SMBUS, PCI_DID_INTEL_LNL_SMBUS, PCI_DID_INTEL_MTL_SMBUS, PCI_DID_INTEL_RPP_P_SMBUS, diff --git a/src/soc/intel/common/block/spi/spi.c b/src/soc/intel/common/block/spi/spi.c index d1063f10a8fc..0e8aa261ce33 100644 --- a/src/soc/intel/common/block/spi/spi.c +++ b/src/soc/intel/common/block/spi/spi.c @@ -123,6 +123,10 @@ struct device_operations spi_dev_ops = { }; static const unsigned short pci_device_ids[] = { + PCI_DID_INTEL_PTL_HWSEQ_SPI, + PCI_DID_INTEL_PTL_SPI0, + PCI_DID_INTEL_PTL_SPI1, + PCI_DID_INTEL_PTL_SPI2, PCI_DID_INTEL_LNL_GSPI0, PCI_DID_INTEL_LNL_GSPI1, PCI_DID_INTEL_LNL_GSPI2, diff --git a/src/soc/intel/common/block/sram/sram.c b/src/soc/intel/common/block/sram/sram.c index cd8c3fd0aa1e..649a6c6cb0f3 100644 --- a/src/soc/intel/common/block/sram/sram.c +++ b/src/soc/intel/common/block/sram/sram.c @@ -33,6 +33,7 @@ static const struct device_operations device_ops = { }; static const unsigned short pci_device_ids[] = { + PCI_DID_INTEL_PTL_SRAM, PCI_DID_INTEL_LNL_SRAM, PCI_DID_INTEL_MTL_SOC_SRAM, PCI_DID_INTEL_MTL_IOE_M_SRAM, diff --git a/src/soc/intel/common/block/systemagent/systemagent.c b/src/soc/intel/common/block/systemagent/systemagent.c index b53814e35dfc..e8e75d7eb2b6 100644 --- a/src/soc/intel/common/block/systemagent/systemagent.c +++ b/src/soc/intel/common/block/systemagent/systemagent.c @@ -414,7 +414,9 @@ struct device_operations systemagent_ops = { }; static const unsigned short systemagent_ids[] = { + PCI_DID_INTEL_PTL_ID, PCI_DID_INTEL_LNL_M_ID, + PCI_DID_INTEL_LNL_M_ID_1, PCI_DID_INTEL_MTL_M_ID, PCI_DID_INTEL_MTL_P_ID_1, PCI_DID_INTEL_MTL_P_ID_2, diff --git a/src/soc/intel/common/block/tcss/Kconfig b/src/soc/intel/common/block/tcss/Kconfig index 25113d33f36c..89bab79235b0 100644 --- a/src/soc/intel/common/block/tcss/Kconfig +++ b/src/soc/intel/common/block/tcss/Kconfig @@ -6,10 +6,18 @@ config SOC_INTEL_COMMON_BLOCK_TCSS help Sets up USB2/3 port mapping in TCSS MUX +config SOC_INTEL_TCSS_USE_PDC_PMC_USBC_MUX_CONFIGURATION + def_bool n + help + TCSS uses PDC<->PMC communication to perform mux configuration. When this config is + enabled, communication happens directly between PDC and PMC. Avoid sending PMC + commands from AP/EC. + config TCSS_HAS_USBC_OPS bool "Enable USB-C MUX operations via the EC" default y if EC_GOOGLE_CHROMEEC - depends on SOC_INTEL_COMMON_BLOCK_TCSS + depends on SOC_INTEL_COMMON_BLOCK_TCSS && \ + !SOC_INTEL_TCSS_USE_PDC_PMC_USBC_MUX_CONFIGURATION help Enable USB-C operations via the EC. Requires `usbc_get_ops` to control features such as HPD and DP Mode entry. Currently, only the ChromeEC implements this, see diff --git a/src/soc/intel/common/block/tracehub/tracehub.c b/src/soc/intel/common/block/tracehub/tracehub.c index 4faa9ebc9124..480e9efe0f7f 100644 --- a/src/soc/intel/common/block/tracehub/tracehub.c +++ b/src/soc/intel/common/block/tracehub/tracehub.c @@ -43,6 +43,7 @@ static struct device_operations dev_ops = { static const unsigned short pci_device_ids[] = { PCI_DID_INTEL_MTL_TRACEHUB, + PCI_DID_INTEL_RPL_TRACEHUB, 0 }; diff --git a/src/soc/intel/common/block/uart/chip.h b/src/soc/intel/common/block/uart/chip.h deleted file mode 100644 index 5981126fa91f..000000000000 --- a/src/soc/intel/common/block/uart/chip.h +++ /dev/null @@ -1,15 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#include <stdint.h> -/* Indirect include for static.c: */ -#include <device/pci_ids.h> - -#ifndef _SOC_INTEL_COMMON_BLOCK_UART_CHIP_H_ -#define _SOC_INTEL_COMMON_BLOCK_UART_CHIP_H_ - -struct soc_intel_common_block_uart_config { - /* The Device ID read from config space at offset[2:4] when not hidden */ - u16 devid; -}; - -#endif /* _SOC_INTEL_COMMON_BLOCK_UART_CHIP_H_ */ diff --git a/src/soc/intel/common/block/uart/uart.c b/src/soc/intel/common/block/uart/uart.c index c03f5a9d367d..e454f7e91ae8 100644 --- a/src/soc/intel/common/block/uart/uart.c +++ b/src/soc/intel/common/block/uart/uart.c @@ -14,7 +14,6 @@ #include <soc/pci_devs.h> #include <soc/iomap.h> #include <soc/nvs.h> -#include "chip.h" #define UART_PCI_ENABLE (PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER) @@ -309,6 +308,7 @@ static const char *uart_acpi_hid(const struct device *dev) static const char *uart_acpi_name(const struct device *dev) { switch (dev->device) { + case PCI_DID_INTEL_PTL_UART0: case PCI_DID_INTEL_LNL_UART0: case PCI_DID_INTEL_ADP_P_UART0: case PCI_DID_INTEL_APL_UART0: @@ -317,6 +317,7 @@ static const char *uart_acpi_name(const struct device *dev) case PCI_DID_INTEL_SPT_H_UART0: case PCI_DID_INTEL_CNP_H_UART0: return "UAR0"; + case PCI_DID_INTEL_PTL_UART1: case PCI_DID_INTEL_LNL_UART1: case PCI_DID_INTEL_ADP_P_UART1: case PCI_DID_INTEL_APL_UART1: @@ -325,6 +326,7 @@ static const char *uart_acpi_name(const struct device *dev) case PCI_DID_INTEL_SPT_H_UART1: case PCI_DID_INTEL_CNP_H_UART1: return "UAR1"; + case PCI_DID_INTEL_PTL_UART2: case PCI_DID_INTEL_LNL_UART2: case PCI_DID_INTEL_ADP_P_UART2: case PCI_DID_INTEL_APL_UART2: @@ -352,6 +354,9 @@ struct device_operations uart_ops = { }; static const unsigned short pci_device_ids[] = { + PCI_DID_INTEL_PTL_UART0, + PCI_DID_INTEL_PTL_UART1, + PCI_DID_INTEL_PTL_UART2, PCI_DID_INTEL_LNL_UART0, PCI_DID_INTEL_LNL_UART1, PCI_DID_INTEL_LNL_UART2, @@ -424,17 +429,4 @@ static const struct pci_driver pch_uart __pci_driver = { .vendor = PCI_VID_INTEL, .devices = pci_device_ids, }; - -static void uart_enable(struct device *dev) -{ - struct soc_intel_common_block_uart_config *conf = dev->chip_info; - dev->ops = &uart_ops; - dev->device = conf ? conf->devid : 0; -} - -struct chip_operations soc_intel_common_block_uart_ops = { - .name = "LPSS UART in ACPI mode", - .enable_dev = uart_enable -}; - #endif /* ENV_RAMSTAGE */ diff --git a/src/soc/intel/common/block/usb4/usb4.c b/src/soc/intel/common/block/usb4/usb4.c index a47bb9b221ca..ff898abb125e 100644 --- a/src/soc/intel/common/block/usb4/usb4.c +++ b/src/soc/intel/common/block/usb4/usb4.c @@ -52,6 +52,8 @@ static void tbt_dma_fill_ssdt(const struct device *dev) #endif static const unsigned short pci_device_ids[] = { + PCI_DID_INTEL_PTL_TBT_DMA0, + PCI_DID_INTEL_PTL_TBT_DMA1, PCI_DID_INTEL_LNL_TBT_DMA0, PCI_DID_INTEL_LNL_TBT_DMA1, PCI_DID_INTEL_RPL_TBT_DMA0, diff --git a/src/soc/intel/common/block/usb4/xhci.c b/src/soc/intel/common/block/usb4/xhci.c index 4912e1a1ebae..4e1a2a8815ad 100644 --- a/src/soc/intel/common/block/usb4/xhci.c +++ b/src/soc/intel/common/block/usb4/xhci.c @@ -26,6 +26,7 @@ static struct device_operations usb4_xhci_ops = { }; static const unsigned short pci_device_ids[] = { + PCI_DID_INTEL_PTL_TCSS_XHCI, PCI_DID_INTEL_LNL_TCSS_XHCI, PCI_DID_INTEL_RPP_P_TCSS_XHCI, PCI_DID_INTEL_MTL_M_TCSS_XHCI, diff --git a/src/soc/intel/common/block/vtd/vtd.c b/src/soc/intel/common/block/vtd/vtd.c index f67d8dbfd5ab..12ca151c7af6 100644 --- a/src/soc/intel/common/block/vtd/vtd.c +++ b/src/soc/intel/common/block/vtd/vtd.c @@ -12,19 +12,6 @@ #include <soc/iomap.h> #include <soc/pci_devs.h> -/* VT-d specification: https://cdrdv2.intel.com/v1/dl/getContent/671081 */ -#define VER_REG 0x0 -#define CAP_REG 0x8 -#define CAP_PMR_LO BIT(5) -#define CAP_PMR_HI BIT(6) -#define PMEN_REG 0x64 -#define PMEN_EPM BIT(31) -#define PMEN_PRS BIT(0) -#define PLMBASE_REG 0x68 -#define PLMLIMIT_REG 0x6C -#define PHMBASE_REG 0x70 -#define PHMLIMIT_REG 0x78 - /* FSP 2.x VT-d HOB from edk2-platforms */ static const uint8_t vtd_pmr_info_data_hob_guid[16] = { 0x45, 0x16, 0xb6, 0x6f, 0x68, 0xf1, 0xbe, 0x46, @@ -40,26 +27,6 @@ struct vtd_pmr_info_hob { static struct vtd_pmr_info_hob *pmr_hob; -static __always_inline uint32_t vtd_read32(uintptr_t vtd_base, uint32_t reg) -{ - return read32p(vtd_base + reg); -} - -static __always_inline void vtd_write32(uintptr_t vtd_base, uint32_t reg, uint32_t value) -{ - return write32p(vtd_base + reg, value); -} - -static __always_inline uint64_t vtd_read64(uintptr_t vtd_base, uint32_t reg) -{ - return read64p(vtd_base + reg); -} - -static __always_inline void vtd_write64(uintptr_t vtd_base, uint32_t reg, uint64_t value) -{ - return write64p(vtd_base + reg, value); -} - static bool is_vtd_enabled(uintptr_t vtd_base) { uint32_t version = vtd_read32(vtd_base, VER_REG); diff --git a/src/soc/intel/common/block/xhci/xhci.c b/src/soc/intel/common/block/xhci/xhci.c index 03ed578e2735..dd4e5de84901 100644 --- a/src/soc/intel/common/block/xhci/xhci.c +++ b/src/soc/intel/common/block/xhci/xhci.c @@ -131,6 +131,7 @@ struct device_operations usb_xhci_ops = { }; static const unsigned short pci_device_ids[] = { + PCI_DID_INTEL_PTL_XHCI, PCI_DID_INTEL_LNL_XHCI, PCI_DID_INTEL_MTL_XHCI, PCI_DID_INTEL_APL_XHCI, |