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Diffstat (limited to 'src/soc/intel/meteorlake/chip.c')
| -rw-r--r-- | src/soc/intel/meteorlake/chip.c | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/src/soc/intel/meteorlake/chip.c b/src/soc/intel/meteorlake/chip.c index 03adfdb73888..51e89dcf3a40 100644 --- a/src/soc/intel/meteorlake/chip.c +++ b/src/soc/intel/meteorlake/chip.c @@ -185,6 +185,9 @@ void soc_init_pre_device(void *chip_info) /* Swap enabled PCI ports in device tree if needed. */ pcie_rp_update_devicetree(get_pcie_rp_table()); + /* Swap enabled TBT root ports in device tree if needed. */ + pcie_rp_update_devicetree(get_tbt_pcie_rp_table()); + /* * Earlier when coreboot used to send EOP at late as possible caused * issue of delayed response from CSE since CSE was busy loading payload. |