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-rw-r--r--src/soc/intel/meteorlake/Kconfig8
-rw-r--r--src/soc/intel/meteorlake/acpi/tcss.asl8
-rw-r--r--src/soc/intel/meteorlake/bootblock/report_platform.c1
-rw-r--r--src/soc/intel/meteorlake/chip.c3
-rw-r--r--src/soc/intel/meteorlake/chip.h4
-rw-r--r--src/soc/intel/meteorlake/crashlog.c12
-rw-r--r--src/soc/intel/meteorlake/fsp_params.c15
-rw-r--r--src/soc/intel/meteorlake/include/soc/pcie.h1
-rw-r--r--src/soc/intel/meteorlake/include/soc/usb.h2
-rw-r--r--src/soc/intel/meteorlake/meminit.c4
-rw-r--r--src/soc/intel/meteorlake/pcie_rp.c16
-rw-r--r--src/soc/intel/meteorlake/romstage/fsp_params.c18
12 files changed, 63 insertions, 29 deletions
diff --git a/src/soc/intel/meteorlake/Kconfig b/src/soc/intel/meteorlake/Kconfig
index a4ebad47068b..622d35f529d7 100644
--- a/src/soc/intel/meteorlake/Kconfig
+++ b/src/soc/intel/meteorlake/Kconfig
@@ -42,7 +42,8 @@ config SOC_INTEL_METEORLAKE
select MRC_SETTINGS_PROTECT
select PARALLEL_MP_AP_WORK
select PCIE_CLOCK_CONTROL_THROUGH_P2SB
- select PLATFORM_USES_FSP2_3
+ select PLATFORM_USES_FSP2_4 if HAVE_X86_64_SUPPORT
+ select PLATFORM_USES_FSP2_3 if !HAVE_X86_64_SUPPORT
select PMC_GLOBAL_RESET_ENABLE_LOCK
select SOC_INTEL_COMMON
select SOC_INTEL_COMMON_ACPI_WAKE_SOURCE
@@ -347,7 +348,8 @@ config CONSOLE_CBMEM_BUFFER_SIZE
config FSP_HEADER_PATH
string "Location of FSP headers"
- default "src/vendorcode/intel/fsp/fsp2_0/meteorlake/"
+ default "src/vendorcode/intel/fsp/fsp2_0/meteorlake/x86_64/" if HAVE_X86_64_SUPPORT
+ default "src/vendorcode/intel/fsp/fsp2_0/meteorlake/x86_32/"
config FSP_FD_PATH
string
@@ -457,7 +459,7 @@ config SOC_INTEL_COMMON_BLOCK_ACPI_SLP_S0_FREQ_HZ
config SOC_INTEL_METEORLAKE_SIGN_OF_LIFE
bool
- default y if !SOC_INTEL_METEORLAKE_PRE_PRODUCTION_SILICON
+ default y if !SOC_INTEL_METEORLAKE_PRE_PRODUCTION_SILICON || !HAVE_X86_64_SUPPORT
depends on MAINBOARD_HAS_CHROMEOS
select VBT_CBFS_COMPRESSION_DEFAULT_LZ4
help
diff --git a/src/soc/intel/meteorlake/acpi/tcss.asl b/src/soc/intel/meteorlake/acpi/tcss.asl
index 84e15fd128ca..dbe76f25ced8 100644
--- a/src/soc/intel/meteorlake/acpi/tcss.asl
+++ b/src/soc/intel/meteorlake/acpi/tcss.asl
@@ -718,7 +718,7 @@ Scope (\_SB.PCI0)
Method (_STA, 0x0, NotSerialized)
{
- If (TRE0 == 1) {
+ If (VDID != 0xFFFFFFFF) {
Return (0x0F)
} Else {
Return (0x0)
@@ -748,7 +748,7 @@ Scope (\_SB.PCI0)
Method (_STA, 0x0, NotSerialized)
{
- If (TRE1 == 1) {
+ If (VDID != 0xFFFFFFFF) {
Return (0x0F)
} Else {
Return (0x0)
@@ -778,7 +778,7 @@ Scope (\_SB.PCI0)
Method (_STA, 0x0, NotSerialized)
{
- If (TRE2 == 1) {
+ If (VDID != 0xFFFFFFFF) {
Return (0x0F)
} Else {
Return (0x0)
@@ -808,7 +808,7 @@ Scope (\_SB.PCI0)
Method (_STA, 0x0, NotSerialized)
{
- If (TRE3 == 1) {
+ If (VDID != 0xFFFFFFFF) {
Return (0x0F)
} Else {
Return (0x0)
diff --git a/src/soc/intel/meteorlake/bootblock/report_platform.c b/src/soc/intel/meteorlake/bootblock/report_platform.c
index 49d0661f30c5..bc8ae920c101 100644
--- a/src/soc/intel/meteorlake/bootblock/report_platform.c
+++ b/src/soc/intel/meteorlake/bootblock/report_platform.c
@@ -58,6 +58,7 @@ static struct {
{ PCI_DID_INTEL_MTL_P_GT2_2, "MeteorLake-P GT2" },
{ PCI_DID_INTEL_MTL_P_GT2_3, "MeteorLake-P GT2" },
{ PCI_DID_INTEL_MTL_P_GT2_4, "Meteorlake-P GT2" },
+ { PCI_DID_INTEL_MTL_P_GT2_5, "Meteorlake-P GT2" },
};
static inline uint8_t get_dev_revision(pci_devfn_t dev)
diff --git a/src/soc/intel/meteorlake/chip.c b/src/soc/intel/meteorlake/chip.c
index 03adfdb73888..51e89dcf3a40 100644
--- a/src/soc/intel/meteorlake/chip.c
+++ b/src/soc/intel/meteorlake/chip.c
@@ -185,6 +185,9 @@ void soc_init_pre_device(void *chip_info)
/* Swap enabled PCI ports in device tree if needed. */
pcie_rp_update_devicetree(get_pcie_rp_table());
+ /* Swap enabled TBT root ports in device tree if needed. */
+ pcie_rp_update_devicetree(get_tbt_pcie_rp_table());
+
/*
* Earlier when coreboot used to send EOP at late as possible caused
* issue of delayed response from CSE since CSE was busy loading payload.
diff --git a/src/soc/intel/meteorlake/chip.h b/src/soc/intel/meteorlake/chip.h
index 1b08ccdbd647..716836994826 100644
--- a/src/soc/intel/meteorlake/chip.h
+++ b/src/soc/intel/meteorlake/chip.h
@@ -247,6 +247,7 @@ struct soc_intel_meteorlake_config {
uint16_t sata_ports_dito_val[8];
/* Audio related */
+ uint8_t pch_hda_audio_link_hda_enable;
uint8_t pch_hda_dsp_enable;
bool pch_hda_sdi_enable[MAX_HD_AUDIO_SDI_LINKS];
@@ -515,6 +516,9 @@ struct soc_intel_meteorlake_config {
/* Platform Power Pmax in Watts. Zero means automatic. */
uint16_t psys_pmax_watts;
+ /* Platform Power Limit 2 in Watts. */
+ uint16_t psys_pl2_watts;
+
/* Enable or Disable Acoustic Noise Mitigation feature */
uint8_t enable_acoustic_noise_mitigation;
/* Disable Fast Slew Rate for Deep Package C States for VR domains */
diff --git a/src/soc/intel/meteorlake/crashlog.c b/src/soc/intel/meteorlake/crashlog.c
index 6d654d7e0b1e..0321e0040647 100644
--- a/src/soc/intel/meteorlake/crashlog.c
+++ b/src/soc/intel/meteorlake/crashlog.c
@@ -34,7 +34,7 @@ static u32 disc_tab_addr;
static u64 get_disc_tab_header(void)
{
- return read64((void *)disc_tab_addr);
+ return read64((void *)(uintptr_t)disc_tab_addr);
}
/* Get the SRAM BAR. */
@@ -338,7 +338,7 @@ static bool cpu_cl_gen_discovery_table(void)
disc_tab_addr = bar_addr + get_disc_table_offset();
- u32 dw0 = read32((u32 *)disc_tab_addr);
+ u32 dw0 = read32((u32 *)(uintptr_t)disc_tab_addr);
if (!is_crashlog_data_valid(dw0))
return false;
@@ -351,7 +351,7 @@ static bool cpu_cl_gen_discovery_table(void)
for (int i = 0; i < cpu_cl_disc_tab.header.fields.count; i++) {
cur_offset = 8 + 24 * i;
- dw0 = read32((u32 *)disc_tab_addr + cur_offset);
+ dw0 = read32((u32 *)(uintptr_t)disc_tab_addr + cur_offset);
if (!is_crashlog_data_valid(dw0))
continue;
@@ -361,7 +361,7 @@ static bool cpu_cl_gen_discovery_table(void)
break;
}
- cpu_cl_disc_tab.buffers[i].data = read64((void *)(disc_tab_addr + cur_offset));
+ cpu_cl_disc_tab.buffers[i].data = read64((void *)(uintptr_t)(disc_tab_addr + cur_offset));
printk(BIOS_DEBUG, "cpu_crashlog_discovery_table buffer: 0x%x size: "
"0x%x offset: 0x%x\n", i, cpu_cl_disc_tab.buffers[i].fields.size,
cpu_cl_disc_tab.buffers[i].fields.offset);
@@ -450,7 +450,7 @@ void cpu_cl_rearm(void)
cl_punit_control_interface_t punit_ctrl_intfc;
memset(&punit_ctrl_intfc, 0, sizeof(cl_punit_control_interface_t));
punit_ctrl_intfc.fields.set_re_arm = 1;
- write32((u32 *)(ctrl_sts_intfc_addr), punit_ctrl_intfc.data);
+ write32((u32 *)(uintptr_t)(ctrl_sts_intfc_addr), punit_ctrl_intfc.data);
if (!wait_and_check(CRASHLOG_RE_ARM_STATUS_MASK))
printk(BIOS_ERR, "CPU crashlog re_arm not asserted\n");
@@ -480,7 +480,7 @@ void cpu_cl_cleanup(void)
cl_punit_control_interface_t punit_ctrl_intfc;
memset(&punit_ctrl_intfc, 0, sizeof(cl_punit_control_interface_t));
punit_ctrl_intfc.fields.set_storage_off = 1;
- write32((u32 *)(ctrl_sts_intfc_addr), punit_ctrl_intfc.data);
+ write32((u32 *)(uintptr_t)(ctrl_sts_intfc_addr), punit_ctrl_intfc.data);
if (!wait_and_check(CRASHLOG_PUNIT_STORAGE_OFF_MASK))
printk(BIOS_ERR, "CPU crashlog storage_off not asserted\n");
diff --git a/src/soc/intel/meteorlake/fsp_params.c b/src/soc/intel/meteorlake/fsp_params.c
index a02d4b99c679..bf1d9d54f120 100644
--- a/src/soc/intel/meteorlake/fsp_params.c
+++ b/src/soc/intel/meteorlake/fsp_params.c
@@ -476,6 +476,8 @@ static void fill_fsps_xhci_params(FSP_S_CONFIG *s_cfg,
s_cfg->Usb2OverCurrentPin[i] = config->usb2_ports[i].ocpin;
else
s_cfg->Usb2OverCurrentPin[i] = OC_SKIP;
+
+ s_cfg->PortResetMessageEnable[i] = config->usb2_ports[i].type_c;
}
max_port = get_max_usb30_port();
@@ -703,18 +705,27 @@ static void fill_fsps_irq_params(FSP_S_CONFIG *s_cfg,
printk(BIOS_INFO, "IRQ: Using dynamically assigned PCI IO-APIC IRQs\n");
}
-static void arch_silicon_init_params(FSPS_ARCH_UPD *s_arch_cfg)
+static void arch_silicon_init_params(FSPS_ARCHx_UPD *s_arch_cfg)
{
+
+#if !CONFIG(PLATFORM_USES_FSP2_4)
/*
* EnableMultiPhaseSiliconInit for running MultiPhaseSiInit
*/
s_arch_cfg->EnableMultiPhaseSiliconInit = 1;
+#endif
/* Assign FspEventHandler arch Upd to use coreboot debug event handler */
if (CONFIG(FSP_USES_CB_DEBUG_EVENT_HANDLER) && CONFIG(CONSOLE_SERIAL) &&
CONFIG(FSP_ENABLE_SERIAL_DEBUG))
+
+#if CONFIG(PLATFORM_USES_FSP2_X86_32)
s_arch_cfg->FspEventHandler = (FSP_EVENT_HANDLER)
fsp_debug_event_handler;
+#else
+ s_arch_cfg->FspEventHandler = (EFI_PHYSICAL_ADDRESS)
+ fsp_debug_event_handler;
+#endif
}
static void evaluate_ssid(const struct device *dev, uint16_t *svid, uint16_t *ssid)
@@ -822,7 +833,7 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd)
{
struct soc_intel_meteorlake_config *config;
FSP_S_CONFIG *s_cfg = &supd->FspsConfig;
- FSPS_ARCH_UPD *s_arch_cfg = &supd->FspsArchUpd;
+ FSPS_ARCHx_UPD *s_arch_cfg = &supd->FspsArchUpd;
config = config_of_soc();
arch_silicon_init_params(s_arch_cfg);
diff --git a/src/soc/intel/meteorlake/include/soc/pcie.h b/src/soc/intel/meteorlake/include/soc/pcie.h
index f97543c9167d..7c098e9ca59f 100644
--- a/src/soc/intel/meteorlake/include/soc/pcie.h
+++ b/src/soc/intel/meteorlake/include/soc/pcie.h
@@ -6,5 +6,6 @@
#include <intelblocks/pcie_rp.h>
const struct pcie_rp_group *get_pcie_rp_table(void);
+const struct pcie_rp_group *get_tbt_pcie_rp_table(void);
#endif /* __SOC_METEORLAKE_PCIE_H__ */
diff --git a/src/soc/intel/meteorlake/include/soc/usb.h b/src/soc/intel/meteorlake/include/soc/usb.h
index e339c7261e0a..70a367ec5909 100644
--- a/src/soc/intel/meteorlake/include/soc/usb.h
+++ b/src/soc/intel/meteorlake/include/soc/usb.h
@@ -31,6 +31,7 @@ struct usb2_port_config {
uint8_t tx_emp_enable;
uint8_t pre_emp_bias;
uint8_t pre_emp_bit;
+ uint8_t type_c;
};
/* USB Overcurrent pins definition */
@@ -112,6 +113,7 @@ enum {
.tx_emp_enable = USB2_PRE_EMP_ON, \
.pre_emp_bias = USB2_BIAS_56P3MV, \
.pre_emp_bit = USB2_HALF_BIT_PRE_EMP, \
+ .type_c = 1, \
}
struct usb3_port_config {
diff --git a/src/soc/intel/meteorlake/meminit.c b/src/soc/intel/meteorlake/meminit.c
index fa7e1fd09a76..32ab358b46be 100644
--- a/src/soc/intel/meteorlake/meminit.c
+++ b/src/soc/intel/meteorlake/meminit.c
@@ -77,7 +77,7 @@ static const struct soc_mem_cfg soc_mem_cfg[] = {
static void mem_init_spd_upds(FSP_M_CONFIG *mem_cfg, const struct mem_channel_data *data)
{
- uint32_t *spd_upds[MRC_CHANNELS][CONFIG_DIMMS_PER_CHANNEL] = {
+ efi_uintn_t *spd_upds[MRC_CHANNELS][CONFIG_DIMMS_PER_CHANNEL] = {
[0] = { &mem_cfg->MemorySpdPtr000, &mem_cfg->MemorySpdPtr001, },
[1] = { &mem_cfg->MemorySpdPtr010, &mem_cfg->MemorySpdPtr011, },
[2] = { &mem_cfg->MemorySpdPtr020, &mem_cfg->MemorySpdPtr021, },
@@ -106,7 +106,7 @@ static void mem_init_spd_upds(FSP_M_CONFIG *mem_cfg, const struct mem_channel_da
bool enable_channel = 0;
for (dimm = 0; dimm < CONFIG_DIMMS_PER_CHANNEL; dimm++) {
- uint32_t *spd_ptr = spd_upds[ch][dimm];
+ efi_uintn_t *spd_ptr = spd_upds[ch][dimm];
*spd_ptr = data->spd[ch][dimm];
if (*spd_ptr)
diff --git a/src/soc/intel/meteorlake/pcie_rp.c b/src/soc/intel/meteorlake/pcie_rp.c
index 9f59ce1f9701..7cfe3ed29181 100644
--- a/src/soc/intel/meteorlake/pcie_rp.c
+++ b/src/soc/intel/meteorlake/pcie_rp.c
@@ -5,6 +5,17 @@
#include <soc/pcie.h>
#include <soc/soc_info.h>
+/*
+ * TBT's LCAP registers are returning port index which starts from 0x10 (Usually for other PCIe
+ * root ports index starts from 1). Thus keeping lcap_port_base 0x10 for TBT, so that coreboot's
+ * PCIe remapping logic can return correct index (0-based)
+ */
+
+static const struct pcie_rp_group tbt_rp_groups[] = {
+ { .slot = PCI_DEV_SLOT_TBT, .count = CONFIG_MAX_TBT_ROOT_PORTS, .lcap_port_base = 0x10 },
+ { 0 }
+};
+
static const struct pcie_rp_group mtlp_rp_groups[] = {
{ .slot = PCI_DEV_SLOT_PCIE_1, .start = 0, .count = 8, .lcap_port_base = 1 },
{ .slot = PCI_DEV_SLOT_PCIE_2, .start = 0, .count = 3, .lcap_port_base = 1 },
@@ -17,6 +28,11 @@ const struct pcie_rp_group *get_pcie_rp_table(void)
return mtlp_rp_groups;
}
+const struct pcie_rp_group *get_tbt_pcie_rp_table(void)
+{
+ return tbt_rp_groups;
+}
+
enum pcie_rp_type soc_get_pcie_rp_type(const struct device *dev)
{
return PCIE_RP_PCH;
diff --git a/src/soc/intel/meteorlake/romstage/fsp_params.c b/src/soc/intel/meteorlake/romstage/fsp_params.c
index caf57a3e9d22..ec0bb8dae6f2 100644
--- a/src/soc/intel/meteorlake/romstage/fsp_params.c
+++ b/src/soc/intel/meteorlake/romstage/fsp_params.c
@@ -288,17 +288,11 @@ static void fill_fspm_audio_params(FSP_M_CONFIG *m_cfg,
m_cfg->PchHdaIDispLinkTmode = config->pch_hda_idisp_link_tmode;
m_cfg->PchHdaIDispLinkFrequency = config->pch_hda_idisp_link_frequency;
m_cfg->PchHdaIDispCodecDisconnect = !config->pch_hda_idisp_codec_enable;
+ m_cfg->PchHdaAudioLinkHdaEnable = config->pch_hda_audio_link_hda_enable;
for (int i = 0; i < MAX_HD_AUDIO_SDI_LINKS; i++)
m_cfg->PchHdaSdiEnable[i] = config->pch_hda_sdi_enable[i];
- /*
- * All the PchHdaAudioLink{Hda|Dmic|Ssp|Sndw}Enable UPDs are used by FSP only to
- * configure GPIO pads for audio. Mainboard is expected to perform all GPIO
- * configuration in coreboot and hence these UPDs are set to 0 to skip FSP GPIO
- * configuration for audio pads.
- */
- m_cfg->PchHdaAudioLinkHdaEnable = 0;
memset(m_cfg->PchHdaAudioLinkDmicEnable, 0, sizeof(m_cfg->PchHdaAudioLinkDmicEnable));
memset(m_cfg->PchHdaAudioLinkSspEnable, 0, sizeof(m_cfg->PchHdaAudioLinkSspEnable));
memset(m_cfg->PchHdaAudioLinkSndwEnable, 0, sizeof(m_cfg->PchHdaAudioLinkSndwEnable));
@@ -446,7 +440,7 @@ static void soc_memory_init_params(FSP_M_CONFIG *m_cfg,
#define VGA_INIT_CONTROL_TEAR_DOWN BIT(1)
static void fill_fspm_sign_of_life(FSP_M_CONFIG *m_cfg,
- FSPM_ARCH_UPD *arch_upd)
+ FSPM_ARCHx_UPD *arch_upd)
{
void *vbt;
size_t vbt_size;
@@ -485,22 +479,22 @@ static void fill_fspm_sign_of_life(FSP_M_CONFIG *m_cfg,
elog_add_event_byte(ELOG_TYPE_FW_EARLY_SOL, sol_type);
m_cfg->VgaInitControl = vga_init_control;
- m_cfg->VbtPtr = (UINT32)vbt;
+ m_cfg->VbtPtr = (efi_uintn_t)vbt;
m_cfg->VbtSize = vbt_size;
m_cfg->LidStatus = CONFIG(VBOOT_LID_SWITCH) ? get_lid_switch() : CONFIG(RUN_FSP_GOP);
- m_cfg->VgaMessage = (UINT32)text;
+ m_cfg->VgaMessage = (efi_uintn_t)text;
}
void platform_fsp_memory_init_params_cb(FSPM_UPD *mupd, uint32_t version)
{
const struct soc_intel_meteorlake_config *config;
FSP_M_CONFIG *m_cfg = &mupd->FspmConfig;
- FSPM_ARCH_UPD *arch_upd = &mupd->FspmArchUpd;
+ FSPM_ARCHx_UPD *arch_upd = &mupd->FspmArchUpd;
if (CONFIG(FSP_USES_CB_DEBUG_EVENT_HANDLER)) {
if (CONFIG(CONSOLE_SERIAL) && CONFIG(FSP_ENABLE_SERIAL_DEBUG)) {
enum fsp_log_level log_level = fsp_map_console_log_level();
- arch_upd->FspEventHandler = (UINT32)((FSP_EVENT_HANDLER *)
+ arch_upd->FspEventHandler = (efi_uintn_t)((FSP_EVENT_HANDLER *)
fsp_debug_event_handler);
/* Set Serial debug message level */
m_cfg->PcdSerialDebugLevel = log_level;
generated by cgit v1.2.3 (git 2.25.1) at 2024-06-15 23:17:54 +0000