diff options
Diffstat (limited to 'src/soc/intel/skylake/include/soc/pci_devs.h')
| -rw-r--r-- | src/soc/intel/skylake/include/soc/pci_devs.h | 16 |
1 files changed, 16 insertions, 0 deletions
diff --git a/src/soc/intel/skylake/include/soc/pci_devs.h b/src/soc/intel/skylake/include/soc/pci_devs.h index 240bd4a4e115..62c982037694 100644 --- a/src/soc/intel/skylake/include/soc/pci_devs.h +++ b/src/soc/intel/skylake/include/soc/pci_devs.h @@ -48,10 +48,14 @@ #define SA_DEV_IGD _SA_DEV(IGD) /* PCH Devices */ +#define PCH_DEV_SLOT_ISH 0x13 +#define PCH_DEVFN_ISH _PCH_DEVFN(ISH, 0) + #define PCH_DEV_SLOT_XHCI 0x14 #define PCH_DEVFN_XHCI _PCH_DEVFN(XHCI, 0) #define PCH_DEVFN_USBOTG _PCH_DEVFN(XHCI, 1) #define PCH_DEVFN_THERMAL _PCH_DEVFN(XHCI, 2) +#define PCH_DEVFN_CIO _PCH_DEVFN(XHCI, 3) #define PCH_DEV_XHCI _PCH_DEV(XHCI, 0) #define PCH_DEV_USBOTG _PCH_DEV(XHCI, 1) #define PCH_DEV_THERMAL _PCH_DEV(XHCI, 2) @@ -97,6 +101,8 @@ #define PCH_DEVFN_PCIE4 _PCH_DEVFN(PCIE, 3) #define PCH_DEVFN_PCIE5 _PCH_DEVFN(PCIE, 4) #define PCH_DEVFN_PCIE6 _PCH_DEVFN(PCIE, 5) +#define PCH_DEVFN_PCIE7 _PCH_DEVFN(PCIE, 6) +#define PCH_DEVFN_PCIE8 _PCH_DEVFN(PCIE, 7) #define PCH_DEV_PCIE1 _PCH_DEV(PCIE, 0) #define PCH_DEV_PCIE2 _PCH_DEV(PCIE, 1) #define PCH_DEV_PCIE3 _PCH_DEV(PCIE, 2) @@ -104,10 +110,19 @@ #define PCH_DEV_PCIE5 _PCH_DEV(PCIE, 4) #define PCH_DEV_PCIE6 _PCH_DEV(PCIE, 5) +#define PCH_DEV_SLOT_PCIE_1 0x1d +#define PCH_DEVFN_PCIE9 _PCH_DEVFN(PCIE_1, 0) +#define PCH_DEVFN_PCIE10 _PCH_DEVFN(PCIE_1, 1) +#define PCH_DEVFN_PCIE11 _PCH_DEVFN(PCIE_1, 2) +#define PCH_DEVFN_PCIE12 _PCH_DEVFN(PCIE_1, 3) + #define PCH_DEV_SLOT_STORAGE 0x1e #define PCH_DEVFN_UART0 _PCH_DEVFN(STORAGE, 0) #define PCH_DEVFN_UART1 _PCH_DEVFN(STORAGE, 1) +#define PCH_DEVFN_GSPI0 _PCH_DEVFN(STORAGE, 2) +#define PCH_DEVFN_GSPI1 _PCH_DEVFN(STORAGE, 3) #define PCH_DEVFN_EMMC _PCH_DEVFN(STORAGE, 4) +#define PCH_DEVFN_SDIO _PCH_DEVFN(STORAGE, 5) #define PCH_DEVFN_SDCARD _PCH_DEVFN(STORAGE, 6) #define PCH_DEV_UART0 _PCH_DEV(STORAGE, 0) #define PCH_DEV_UART1 _PCH_DEV(STORAGE, 1) @@ -121,6 +136,7 @@ #define PCH_DEVFN_SMBUS _PCH_DEVFN(LPC, 4) #define PCH_DEVFN_SPI _PCH_DEVFN(LPC, 5) #define PCH_DEVFN_GBE _PCH_DEVFN(LPC, 6) +#define PCH_DEVFN_TRACEHUB _PCH_DEVFN(LPC, 7) #define PCH_DEV_LPC _PCH_DEV(LPC, 0) #define PCH_DEV_PMC _PCH_DEV(LPC, 2) #define PCH_DEV_HDA _PCH_DEV(LPC, 3) |