5 files changed, 55 insertions, 4 deletions

diff --git a/src/soc/intel/xeon_sp/include/soc/acpi.h b/src/soc/intel/xeon_sp/include/soc/acpi.h
index e37454496238..7c7aee0ad40f 100644
--- a/src/soc/intel/xeon_sp/include/soc/acpi.h
+++ b/src/soc/intel/xeon_sp/include/soc/acpi.h
@@ -18,11 +18,25 @@ enum acpi_cstate_mode {
 
 unsigned long northbridge_write_acpi_tables(const struct device *device,
 	unsigned long current, struct acpi_rsdp *rsdp);
-unsigned long xeonsp_acpi_create_madt_lapics(unsigned long current);
 unsigned long acpi_fill_cedt(unsigned long current);
 unsigned long acpi_fill_hmat(unsigned long current);
 unsigned long cxl_fill_srat(unsigned long current);
 
 void iio_domain_set_acpi_name(struct device *dev, const char *prefix);
 
+#define PCIE_NATIVE_HOTPLUG_CONTROL  0x01
+#define SHPC_NATIVE_HOTPLUG_CONTROL  0x02
+#define PCIE_PME_CONTROL             0x04
+#define PCIE_AER_CONTROL             0x08
+#define PCIE_CAP_STRUCTURE_CONTROL   0x10
+#define PCIE_LTR_CONTROL             0x20
+#define PCIE_DPC_COTROL              0x80
+
+#define CXL_ERROR_REPORTING_CONTROL  0x01
+
+void acpigen_write_OSC_pci_domain_fixed_caps(const struct device *domain,
+				const uint32_t granted_pcie_features,
+				const bool is_cxl_domain,
+				const uint32_t granted_cxl_features);
+
 #endif /* _SOC_ACPI_H_ */
diff --git a/src/soc/intel/xeon_sp/include/soc/config.h b/src/soc/intel/xeon_sp/include/soc/config.h
new file mode 100644
index 000000000000..6d5f3d587d43
--- /dev/null
+++ b/src/soc/intel/xeon_sp/include/soc/config.h
@@ -0,0 +1,14 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+
+#ifndef _XEON_SP_SOC_CONFIG_H_
+#define _XEON_SP_SOC_CONFIG_H_
+
+enum xeonsp_cxl_mode {
+	XEONSP_CXL_DISABLED = 0,
+	XEONSP_CXL_SYS_MEM,
+	XEONSP_CXL_SP_MEM,
+};
+
+enum xeonsp_cxl_mode get_cxl_mode(void);
+
+#endif
diff --git a/src/soc/intel/xeon_sp/include/soc/ddr.h b/src/soc/intel/xeon_sp/include/soc/ddr.h
index bb10caaf1fb0..0b5bdb6b1529 100644
--- a/src/soc/intel/xeon_sp/include/soc/ddr.h
+++ b/src/soc/intel/xeon_sp/include/soc/ddr.h
@@ -9,7 +9,6 @@
  * currently DDR4 only supports 1.2V, DDR5 only supports 1.1V. */
 #define SPD_VDD_DDR4 3
 #define SPD_VDD_DDR5 0
-#define SPD_TYPE_DDR5 0x12
 
 /* DDR_*_TCK_MIN are in picoseconds */
 #define DDR_800_TCK_MIN                2500
diff --git a/src/soc/intel/xeon_sp/include/soc/numa.h b/src/soc/intel/xeon_sp/include/soc/numa.h
index aba3f0926bc3..b64488190fa2 100644
--- a/src/soc/intel/xeon_sp/include/soc/numa.h
+++ b/src/soc/intel/xeon_sp/include/soc/numa.h
@@ -7,8 +7,11 @@
 #ifndef NUMA_H
 #define NUMA_H
 
+#include <soc/soc_util.h>
 #include <types.h>
 
+#define XEONSP_INVALID_PD_INDEX	UINT32_MAX
+
 enum proximity_domain_type {
 	PD_TYPE_PROCESSOR,
 	/*
@@ -16,6 +19,18 @@ enum proximity_domain_type {
 	 * Generic Initiator domain is a CXL memory device.
 	 */
 	PD_TYPE_GENERIC_INITIATOR,
+	/*
+	 * PD_TYPE_CLUSTER is for Sub-NUMA cluster (SNC). SNC is localization
+	 * domain within a socket, composed of a set of CPU cores, last-level
+	 * cache pieces and memory controllers, which are close to each other.
+	 * SNC will be reported as NUMA nodes to OS so that the performance
+	 * proximity could be fully exploited for task assignment and scheduling.
+	 *
+	 * For more, please refer to
+	 * https://www.intel.com/content/www/us/en/developer/articles/technical/xeon-processor-scalable-family-technical-overview.html
+	 */
+	PD_TYPE_CLUSTER,
+	PD_TYPE_MAX
 };
 
 /*
@@ -36,6 +51,7 @@ struct proximity_domain {
 	 * sockets, so we need a bitmap.
 	 */
 	uint8_t socket_bitmap;
+	uint8_t cluster_bitmap;
 	/* Relative distances (memory latency) from all domains */
 	uint8_t *distances;
 	/*
@@ -53,8 +69,7 @@ struct proximity_domains {
 
 extern struct proximity_domains pds;
 
-void dump_pds(void);
-void fill_pds(void);
+void setup_pds(void);
 
 /*
  * Return the total size of memory regions in generic initiator affinity
@@ -62,4 +77,10 @@ void fill_pds(void);
  */
 uint32_t get_generic_initiator_mem_size(void);
 
+uint32_t memory_to_pd(const struct SystemMemoryMapElement *mem);
+uint32_t device_to_pd(const struct device *dev);
+
+uint8_t soc_get_cluster_count(void);
+void soc_set_cpu_node_id(struct device *cpu);
+
 #endif /* NUMA_H */
diff --git a/src/soc/intel/xeon_sp/include/soc/util.h b/src/soc/intel/xeon_sp/include/soc/util.h
index 177d6d50e338..e694af3e3ca8 100644
--- a/src/soc/intel/xeon_sp/include/soc/util.h
+++ b/src/soc/intel/xeon_sp/include/soc/util.h
@@ -4,6 +4,7 @@
 #define _XEON_SP_SOC_UTIL_H_
 
 #include <cpu/x86/msr.h>
+#include <intelblocks/p2sb.h>
 #include <soc/soc_util.h>
 
 #define MEM_ADDR_64MB_SHIFT_BITS 26
@@ -27,5 +28,7 @@ bool is_ubox_stack_res(const xSTACK_RES *res);
 bool is_ioat_iio_stack_res(const xSTACK_RES *res);
 bool is_iio_cxl_stack_res(const xSTACK_RES *res);
 void bios_done_msr(void *unused);
+union p2sb_bdf soc_get_hpet_bdf(void);
+union p2sb_bdf soc_get_ioapic_bdf(void);
 
 #endif