diff options
Diffstat (limited to 'src/soc/intel/xeon_sp/spr')
| -rw-r--r-- | src/soc/intel/xeon_sp/spr/Kconfig | 3 | ||||
| -rw-r--r-- | src/soc/intel/xeon_sp/spr/chip.c | 3 | ||||
| -rw-r--r-- | src/soc/intel/xeon_sp/spr/cpu.c | 26 | ||||
| -rw-r--r-- | src/soc/intel/xeon_sp/spr/ioat.c | 18 | ||||
| -rw-r--r-- | src/soc/intel/xeon_sp/spr/romstage.c | 80 | ||||
| -rw-r--r-- | src/soc/intel/xeon_sp/spr/soc_acpi.c | 20 | ||||
| -rw-r--r-- | src/soc/intel/xeon_sp/spr/soc_util.c | 5 |
7 files changed, 30 insertions, 125 deletions
diff --git a/src/soc/intel/xeon_sp/spr/Kconfig b/src/soc/intel/xeon_sp/spr/Kconfig index 401c8e498159..b84a8ff26771 100644 --- a/src/soc/intel/xeon_sp/spr/Kconfig +++ b/src/soc/intel/xeon_sp/spr/Kconfig @@ -107,9 +107,6 @@ config SOC_INTEL_HAS_BIOS_DONE_MSR config SOC_INTEL_HAS_NCMEM def_bool y -config SOC_INTEL_PCIE_64BIT_ALLOC - def_bool y - config SOC_INTEL_MMAPVTD_ONLY_FOR_DPR def_bool y diff --git a/src/soc/intel/xeon_sp/spr/chip.c b/src/soc/intel/xeon_sp/spr/chip.c index ec23940f2bba..e179df0e1516 100644 --- a/src/soc/intel/xeon_sp/spr/chip.c +++ b/src/soc/intel/xeon_sp/spr/chip.c @@ -125,6 +125,7 @@ static void chip_init(void *data) printk(BIOS_DEBUG, "coreboot: calling fsp_silicon_init\n"); fsp_silicon_init(); + setup_pds(); attach_iio_stacks(); override_hpet_ioapic_bdf(); @@ -175,7 +176,7 @@ static void rcec_init(struct device *dev) uint32_t ep_bus; uint8_t i; for (i = 0; i < pds.num_pds; i++) { - if (pds.pds[i].pd_type == PD_TYPE_PROCESSOR) + if (pds.pds[i].pd_type != PD_TYPE_GENERIC_INITIATOR) continue; ep_bus = PCI_BDF(pds.pds[i].dev) >> 20; if (ep_bus == ecrc_bus + 1) diff --git a/src/soc/intel/xeon_sp/spr/cpu.c b/src/soc/intel/xeon_sp/spr/cpu.c index f9c8e2627393..ad099ab70b71 100644 --- a/src/soc/intel/xeon_sp/spr/cpu.c +++ b/src/soc/intel/xeon_sp/spr/cpu.c @@ -1,28 +1,17 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#include <acpi/acpigen.h> -#include <acpi/acpi.h> -#include <console/console.h> #include <console/debug.h> -#include <cpu/cpu.h> -#include <cpu/intel/cpu_ids.h> #include <cpu/intel/common/common.h> -#include <cpu/intel/em64t101_save_state.h> #include <cpu/intel/microcode.h> #include <cpu/intel/smm_reloc.h> #include <cpu/intel/turbo.h> -#include <cpu/x86/lapic.h> #include <cpu/x86/mp.h> -#include <cpu/x86/mtrr.h> #include <cpu/x86/topology.h> -#include <device/pci_mmio_cfg.h> #include <intelblocks/cpulib.h> #include <intelblocks/mp_init.h> #include <intelpch/lockdown.h> #include <soc/msr.h> -#include <soc/pci_devs.h> #include <soc/pm.h> -#include <soc/soc_util.h> #include <soc/smmrelocate.h> #include <soc/util.h> @@ -235,6 +224,12 @@ static int get_thread_count(void) { unsigned int num_phys = 0, num_virts = 0; + /* + * This call calculates the thread count which is corresponding to num_virts + * (logical cores), while num_phys is corresponding to physical cores (in SMT + * system, one physical core has multiple threads, a.k.a. logical cores). + * Hence num_phys is not actually used. + */ cpu_read_topology(&num_phys, &num_virts); printk(BIOS_SPEW, "Detected %u cores and %u threads\n", num_phys, num_virts); return num_virts * soc_get_num_cpus(); @@ -273,12 +268,9 @@ void mp_init_cpus(struct bus *bus) chip_config = bus->dev->chip_info; microcode_patch = intel_microcode_find(); - - if (!microcode_patch) - printk(BIOS_ERR, "microcode not found in CBFS!\n"); - intel_microcode_load_unlocked(microcode_patch); - if (mp_init_with_smm(bus, &mp_ops) < 0) - printk(BIOS_ERR, "MP initialization failure.\n"); + enum cb_err ret = mp_init_with_smm(bus, &mp_ops); + if (ret != CB_SUCCESS) + printk(BIOS_ERR, "MP initialization failure %d.\n", ret); } diff --git a/src/soc/intel/xeon_sp/spr/ioat.c b/src/soc/intel/xeon_sp/spr/ioat.c index 9ed9576ef369..a0babee5feec 100644 --- a/src/soc/intel/xeon_sp/spr/ioat.c +++ b/src/soc/intel/xeon_sp/spr/ioat.c @@ -61,21 +61,11 @@ static void create_ioat_domain(const union xeon_domain_path dp, struct bus *cons unsigned int index = 0; - if (mem32_base <= mem32_limit) { - struct resource *const res = new_resource(domain, index++); - res->base = mem32_base; - res->limit = mem32_limit; - res->size = res->limit - res->base + 1; - res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED; - } + if (mem32_base <= mem32_limit) + domain_mem_window_from_to(domain, index++, mem32_base, mem32_limit + 1); - if (mem64_base <= mem64_limit) { - struct resource *const res = new_resource(domain, index++); - res->base = mem64_base; - res->limit = mem64_limit; - res->size = res->limit - res->base + 1; - res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED; - } + if (mem64_base <= mem64_limit) + domain_mem_window_from_to(domain, index++, mem64_base, mem64_limit + 1); } void create_ioat_domains(const union xeon_domain_path path, diff --git a/src/soc/intel/xeon_sp/spr/romstage.c b/src/soc/intel/xeon_sp/spr/romstage.c index 3e16608ca4c8..26bb3081a121 100644 --- a/src/soc/intel/xeon_sp/spr/romstage.c +++ b/src/soc/intel/xeon_sp/spr/romstage.c @@ -13,12 +13,16 @@ #include <fsp/util.h> #include <hob_iiouds.h> #include <hob_memmap.h> +#include <spd.h> +#include <soc/chip_common.h> #include <soc/romstage.h> #include <soc/pci_devs.h> #include <soc/soc_pch.h> #include <soc/intel/common/smbios.h> #include <string.h> +#include <soc/config.h> #include <soc/soc_util.h> +#include <soc/util.h> #include <soc/ddr.h> #include "chip.h" @@ -32,73 +36,10 @@ void __weak mainboard_memory_init_params(FSPM_UPD *mupd) /* Default weak implementation */ } -/* - * Search from VPD_RW first then VPD_RO for UPD config variables, - * overwrites them from VPD if it's found. - */ -static void config_upd_from_vpd(FSPM_UPD *mupd) +static void config_upd(FSPM_UPD *mupd) { - uint8_t val; - int val_int, cxl_mode; - - /* Send FSP log message to SOL */ - if (vpd_get_bool(FSP_LOG, VPD_RW_THEN_RO, &val)) - mupd->FspmConfig.SerialIoUartDebugEnable = val; - else { - printk(BIOS_INFO, - "Not able to get VPD %s, default set " - "SerialIoUartDebugEnable to %d\n", - FSP_LOG, FSP_LOG_DEFAULT); - mupd->FspmConfig.SerialIoUartDebugEnable = FSP_LOG_DEFAULT; - } - - if (mupd->FspmConfig.SerialIoUartDebugEnable) { - /* FSP memory debug log level */ - if (vpd_get_int(FSP_MEM_LOG_LEVEL, VPD_RW_THEN_RO, &val_int)) { - if (val_int < 0 || val_int > 4) { - printk(BIOS_DEBUG, - "Invalid serialDebugMsgLvl value from VPD: " - "%d\n", - val_int); - val_int = FSP_MEM_LOG_LEVEL_DEFAULT; - } - printk(BIOS_DEBUG, "Setting serialDebugMsgLvl to %d\n", val_int); - mupd->FspmConfig.serialDebugMsgLvl = (uint8_t)val_int; - } else { - printk(BIOS_INFO, - "Not able to get VPD %s, default set " - "DebugPrintLevel to %d\n", - FSP_MEM_LOG_LEVEL, FSP_MEM_LOG_LEVEL_DEFAULT); - mupd->FspmConfig.serialDebugMsgLvl = FSP_MEM_LOG_LEVEL_DEFAULT; - } - /* If serialDebugMsgLvl less than 1, disable FSP memory train results */ - if (mupd->FspmConfig.serialDebugMsgLvl <= 1) { - printk(BIOS_DEBUG, "Setting serialDebugMsgLvlTrainResults to 0\n"); - mupd->FspmConfig.serialDebugMsgLvlTrainResults = 0x0; - } - } - - /* FSP Dfx PMIC Secure mode */ - if (vpd_get_int(FSP_PMIC_SECURE_MODE, VPD_RW_THEN_RO, &val_int)) { - if (val_int < 0 || val_int > 2) { - printk(BIOS_DEBUG, - "Invalid PMIC secure mode value from VPD: " - "%d\n", - val_int); - val_int = FSP_PMIC_SECURE_MODE_DEFAULT; - } - printk(BIOS_DEBUG, "Setting PMIC secure mode to %d\n", val_int); - mupd->FspmConfig.DfxPmicSecureMode = (uint8_t)val_int; - } else { - printk(BIOS_INFO, - "Not able to get VPD %s, default set " - "PMIC secure mode to %d\n", - FSP_PMIC_SECURE_MODE, FSP_PMIC_SECURE_MODE_DEFAULT); - mupd->FspmConfig.DfxPmicSecureMode = FSP_PMIC_SECURE_MODE_DEFAULT; - } - - cxl_mode = get_cxl_mode_from_vpd(); - if (cxl_mode == CXL_SYSTEM_MEMORY || cxl_mode == CXL_SPM) + int cxl_mode = get_cxl_mode(); + if (cxl_mode == XEONSP_CXL_SYS_MEM || cxl_mode == XEONSP_CXL_SP_MEM) mupd->FspmConfig.DfxCxlType3LegacyEn = 1; else /* Disable CXL */ mupd->FspmConfig.DfxCxlType3LegacyEn = 0; @@ -272,9 +213,8 @@ void platform_fsp_memory_init_params_cb(FSPM_UPD *mupd, uint32_t version) printk(BIOS_DEBUG, "CPU is D stepping, setting package C state to C0/C1\n"); mupd->FspmConfig.CpuPmPackageCState = 0; } - /* Set some common UPDs from VPD, mainboard can still override them if needed */ - if (CONFIG(VPD)) - config_upd_from_vpd(mupd); + + config_upd(mupd); initialize_iio_upd(mupd); mainboard_memory_init_params(mupd); @@ -392,7 +332,7 @@ void save_dimm_info(void) dest_dimm->soc_num = soc; - if (hob->DramType == SPD_TYPE_DDR5) { + if (hob->DramType == SPD_MEMORY_TYPE_DDR5_SDRAM) { /* hard-coded memory device type as DDR5 */ mem_dev_type = 0x22; data_width = 64; diff --git a/src/soc/intel/xeon_sp/spr/soc_acpi.c b/src/soc/intel/xeon_sp/spr/soc_acpi.c index 1249b8ff041d..32ef1edb20f2 100644 --- a/src/soc/intel/xeon_sp/spr/soc_acpi.c +++ b/src/soc/intel/xeon_sp/spr/soc_acpi.c @@ -12,6 +12,7 @@ #include <intelblocks/pmclib.h> #include <soc/acpi.h> #include <soc/iomap.h> +#include <soc/numa.h> #include <soc/msr.h> #include <soc/pci_devs.h> #include <soc/pm.h> @@ -155,25 +156,6 @@ void soc_power_states_generation(int core, int cores_per_package) acpigen_pop_len(); } -unsigned long xeonsp_acpi_create_madt_lapics(unsigned long current) -{ - struct device *cpu; - uint8_t num_cpus = 0; - - for (cpu = all_devices; cpu; cpu = cpu->next) { - if ((cpu->path.type != DEVICE_PATH_APIC) - || (cpu->upstream->dev->path.type != DEVICE_PATH_CPU_CLUSTER)) { - continue; - } - if (!cpu->enabled) - continue; - current = acpi_create_madt_one_lapic(current, num_cpus, cpu->path.apic.apic_id); - num_cpus++; - } - - return current; -} - unsigned long acpi_fill_cedt(unsigned long current) { const IIO_UDS *hob = get_iio_uds(); diff --git a/src/soc/intel/xeon_sp/spr/soc_util.c b/src/soc/intel/xeon_sp/spr/soc_util.c index 9ad09f4c4be8..584532785e1a 100644 --- a/src/soc/intel/xeon_sp/spr/soc_util.c +++ b/src/soc/intel/xeon_sp/spr/soc_util.c @@ -90,8 +90,11 @@ bool is_ioat_iio_stack_res(const STACK_RES *res) */ bool is_iio_cxl_stack_res(const STACK_RES *res) { + /* pds should be setup ahead of this call */ + assert(pds.num_pds); + for (uint8_t i = 0; i < pds.num_pds; i++) { - if (pds.pds[i].pd_type == PD_TYPE_PROCESSOR) + if (pds.pds[i].pd_type != PD_TYPE_GENERIC_INITIATOR) continue; uint32_t bus = PCI_BDF(pds.pds[i].dev) >> 20; |