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-rw-r--r--src/southbridge/via/k8t890/k8m890_chrome.c8
-rw-r--r--src/southbridge/via/k8t890/k8t890_dram.c12
-rw-r--r--src/southbridge/via/k8t890/k8t890_early_car.c4
-rw-r--r--src/southbridge/via/k8t890/k8t890_pcie.c4
-rw-r--r--src/southbridge/via/vt8231/vt8231.c2
-rw-r--r--src/southbridge/via/vt8231/vt8231_acpi.c2
-rw-r--r--src/southbridge/via/vt8231/vt8231_ide.c18
-rw-r--r--src/southbridge/via/vt8231/vt8231_lpc.c20
-rw-r--r--src/southbridge/via/vt8231/vt8231_nic.c2
-rw-r--r--src/southbridge/via/vt8235/vt8235.c12
-rw-r--r--src/southbridge/via/vt8235/vt8235_ide.c20
-rw-r--r--src/southbridge/via/vt8235/vt8235_lpc.c22
-rw-r--r--src/southbridge/via/vt8235/vt8235_nic.c2
-rw-r--r--src/southbridge/via/vt8235/vt8235_usb.c2
-rw-r--r--src/southbridge/via/vt8237r/vt8237r.c8
-rw-r--r--src/southbridge/via/vt8237r/vt8237r_ide.c8
-rw-r--r--src/southbridge/via/vt8237r/vt8237r_lpc.c8
-rw-r--r--src/southbridge/via/vt8237r/vt8237r_sata.c2
-rw-r--r--src/southbridge/via/vt8237r/vt8237r_usb.c10
19 files changed, 83 insertions, 83 deletions
diff --git a/src/southbridge/via/k8t890/k8m890_chrome.c b/src/southbridge/via/k8t890/k8m890_chrome.c
index fdf55aa929c4..2cbd9382ae64 100644
--- a/src/southbridge/via/k8t890/k8m890_chrome.c
+++ b/src/southbridge/via/k8t890/k8m890_chrome.c
@@ -125,7 +125,7 @@ chrome_init(struct device *dev)
fb_size = k8m890_host_fb_size_get();
if (!fb_size) {
- printk_warning("Chrome: Device has not been initialised in the"
+ printk(BIOS_WARNING, "Chrome: Device has not been initialised in the"
" ramcontroller!\n");
return;
}
@@ -133,11 +133,11 @@ chrome_init(struct device *dev)
fb_address = pci_read_config32(dev, 0x10);
fb_address &= ~0x0F;
if (!fb_address) {
- printk_warning("Chrome: No FB BAR assigned!\n");
+ printk(BIOS_WARNING, "Chrome: No FB BAR assigned!\n");
return;
}
- printk_info("Chrome: Using %dMB Framebuffer at 0x%08X.\n",
+ printk(BIOS_INFO, "Chrome: Using %dMB Framebuffer at 0x%08X.\n",
fb_size, fb_address);
//k8m890_host_fb_direct_set(fb_address);
@@ -154,7 +154,7 @@ chrome_init(struct device *dev)
vga_console_init();
#endif
- printk_info("Chrome VGA Textmode initialized.\n");
+ printk(BIOS_INFO, "Chrome VGA Textmode initialized.\n");
#if CONFIG_CONSOLE_VGA == 0
/* if we don't have console, at least print something... */
diff --git a/src/southbridge/via/k8t890/k8t890_dram.c b/src/southbridge/via/k8t890/k8t890_dram.c
index 84a41a46b8ed..ac67d4a5b626 100644
--- a/src/southbridge/via/k8t890/k8t890_dram.c
+++ b/src/southbridge/via/k8t890/k8t890_dram.c
@@ -82,7 +82,7 @@ static void get_memres(void *gp, struct device *dev, struct resource *res)
unsigned int *fbsize = (unsigned int *) gp;
uint64_t proposed_base = res->base + res->size - *fbsize;
- printk_debug("get_memres: res->base=%llx res->size=%llx %d %d %d\n",
+ printk(BIOS_DEBUG, "get_memres: res->base=%llx res->size=%llx %d %d %d\n",
res->base, res->size, (res->size > *fbsize),
(!(proposed_base & (*fbsize - 1))),
(proposed_base < ((uint64_t) 0xffffffff)));
@@ -99,7 +99,7 @@ extern uint64_t high_tables_base, high_tables_size;
if ((high_tables_base) && ((high_tables_base > proposed_base) &&
(high_tables_base < (res->base + res->size)))) {
high_tables_base = proposed_base - high_tables_size;
- printk_debug("Moving the high_tables_base pointer to "
+ printk(BIOS_DEBUG, "Moving the high_tables_base pointer to "
"new base %llx\n", high_tables_base);
}
#endif
@@ -140,12 +140,12 @@ static void dram_init_fb(struct device *dev)
ret = get_option(&fbbits, "videoram_size");
if (ret) {
- printk_warning("Failed to get videoram size (error %d), using default.\n", ret);
+ printk(BIOS_WARNING, "Failed to get videoram size (error %d), using default.\n", ret);
fbbits = 5;
}
if ((fbbits < 1) || (fbbits > 7)) {
- printk_warning("Invalid videoram size (%d), using default.\n",
+ printk(BIOS_WARNING, "Invalid videoram size (%d), using default.\n",
4 << fbbits);
fbbits = 5;
}
@@ -159,14 +159,14 @@ static void dram_init_fb(struct device *dev)
/* no space for FB */
if (!resmax) {
- printk_err("VIA FB: no space for framebuffer in RAM\n");
+ printk(BIOS_ERR, "VIA FB: no space for framebuffer in RAM\n");
return;
}
proposed_base = resmax->base + resmax->size - fbsize;
resmax->size -= fbsize;
- printk_info("K8M890: Using a %dMB framebuffer.\n", 4 << fbbits);
+ printk(BIOS_INFO, "K8M890: Using a %dMB framebuffer.\n", 4 << fbbits);
/* Step 1: enable UMA but no FB */
pci_write_config8(dev, 0xa1, 0x80);
diff --git a/src/southbridge/via/k8t890/k8t890_early_car.c b/src/southbridge/via/k8t890/k8t890_early_car.c
index 2b0c9e160926..a0a269bb944c 100644
--- a/src/southbridge/via/k8t890/k8t890_early_car.c
+++ b/src/southbridge/via/k8t890/k8t890_early_car.c
@@ -114,7 +114,7 @@ u8 k8t890_early_setup_ht(void)
int s3_save_nvram_early(u32 dword, int size, int nvram_pos) {
- printk_debug("Writing %x of size %d to nvram pos: %d\n", dword, size, nvram_pos);
+ printk(BIOS_DEBUG, "Writing %x of size %d to nvram pos: %d\n", dword, size, nvram_pos);
switch (size) {
case 1:
outb((dword & 0xff), K8T890_NVRAM_IO_BASE+nvram_pos);
@@ -149,6 +149,6 @@ int s3_load_nvram_early(int size, u32 *old_dword, int nvram_pos) {
nvram_pos +=4;
break;
}
- printk_debug("Loading %x of size %d to nvram pos:%d\n", * old_dword, size, nvram_pos-size);
+ printk(BIOS_DEBUG, "Loading %x of size %d to nvram pos:%d\n", * old_dword, size, nvram_pos-size);
return nvram_pos;
}
diff --git a/src/southbridge/via/k8t890/k8t890_pcie.c b/src/southbridge/via/k8t890/k8t890_pcie.c
index 645296d40f10..804398cf8894 100644
--- a/src/southbridge/via/k8t890/k8t890_pcie.c
+++ b/src/southbridge/via/k8t890/k8t890_pcie.c
@@ -28,7 +28,7 @@ static void peg_init(struct device *dev)
{
u8 reg;
- printk_debug("Configuring PCIe PEG\n");
+ printk(BIOS_DEBUG, "Configuring PCIe PEG\n");
dump_south(dev);
/* Disable link. */
@@ -68,7 +68,7 @@ static void pcie_init(struct device *dev)
{
u8 reg;
- printk_debug("Configuring PCIe PEXs\n");
+ printk(BIOS_DEBUG, "Configuring PCIe PEXs\n");
dump_south(dev);
/* Disable link. */
diff --git a/src/southbridge/via/vt8231/vt8231.c b/src/southbridge/via/vt8231/vt8231.c
index 5f8ab4500902..f94352466518 100644
--- a/src/southbridge/via/vt8231/vt8231.c
+++ b/src/southbridge/via/vt8231/vt8231.c
@@ -14,7 +14,7 @@ static device_t lpc_dev;
void hard_reset(void)
{
- printk_err("NO HARD RESET ON VT8231! FIX ME!\n");
+ printk(BIOS_ERR, "NO HARD RESET ON VT8231! FIX ME!\n");
}
static void keyboard_on(void)
diff --git a/src/southbridge/via/vt8231/vt8231_acpi.c b/src/southbridge/via/vt8231/vt8231_acpi.c
index 87c5e876fd03..6cbf4c591f19 100644
--- a/src/southbridge/via/vt8231/vt8231_acpi.c
+++ b/src/southbridge/via/vt8231/vt8231_acpi.c
@@ -6,7 +6,7 @@
static void acpi_init(struct device *dev)
{
- printk_debug("Configuring VIA ACPI\n");
+ printk(BIOS_DEBUG, "Configuring VIA ACPI\n");
// Set ACPI base address to IO 0x4000
pci_write_config32(dev, 0x48, 0x4001);
diff --git a/src/southbridge/via/vt8231/vt8231_ide.c b/src/southbridge/via/vt8231/vt8231_ide.c
index a151ca06c956..c1df5ef5cd10 100644
--- a/src/southbridge/via/vt8231/vt8231_ide.c
+++ b/src/southbridge/via/vt8231/vt8231_ide.c
@@ -19,22 +19,22 @@ static void ide_init(struct device *dev)
*/
/*
- printk_info("%s: enabling compatibility IDE addresses\n", __func__);
+ printk(BIOS_INFO, "%s: enabling compatibility IDE addresses\n", __func__);
enables = pci_read_config8(dev, 0x42);
- printk_debug("enables in reg 0x42 0x%x\n", enables);
+ printk(BIOS_DEBUG, "enables in reg 0x42 0x%x\n", enables);
enables &= ~0xc0; // compatability mode
pci_write_config8(dev, 0x42, enables);
enables = pci_read_config8(dev, 0x42);
- printk_debug("enables in reg 0x42 read back as 0x%x\n", enables);
+ printk(BIOS_DEBUG, "enables in reg 0x42 read back as 0x%x\n", enables);
*/
}
enables = pci_read_config8(dev, 0x40);
- printk_debug("enables in reg 0x40 0x%x\n", enables);
+ printk(BIOS_DEBUG, "enables in reg 0x40 0x%x\n", enables);
enables |= 3;
pci_write_config8(dev, 0x40, enables);
enables = pci_read_config8(dev, 0x40);
- printk_debug("enables in reg 0x40 read back as 0x%x\n", enables);
+ printk(BIOS_DEBUG, "enables in reg 0x40 read back as 0x%x\n", enables);
// Enable prefetch buffers
enables = pci_read_config8(dev, 0x41);
@@ -58,7 +58,7 @@ static void ide_init(struct device *dev)
// kevinh@ispiri.com - the standard linux drivers seem ass slow when
// used in native mode - I've changed back to classic
enables = pci_read_config8(dev, 0x9);
- printk_debug("enables in reg 0x9 0x%x\n", enables);
+ printk(BIOS_DEBUG, "enables in reg 0x9 0x%x\n", enables);
// by the book, set the low-order nibble to 0xa.
if (conf->enable_native_ide) {
enables &= ~0xf;
@@ -70,11 +70,11 @@ static void ide_init(struct device *dev)
pci_write_config8(dev, 0x9, enables);
enables = pci_read_config8(dev, 0x9);
- printk_debug("enables in reg 0x9 read back as 0x%x\n", enables);
+ printk(BIOS_DEBUG, "enables in reg 0x9 read back as 0x%x\n", enables);
// standard bios sets master bit.
enables = pci_read_config8(dev, 0x4);
- printk_debug("command in reg 0x4 0x%x\n", enables);
+ printk(BIOS_DEBUG, "command in reg 0x4 0x%x\n", enables);
enables |= 7;
// No need for stepping - kevinh@ispiri.com
@@ -82,7 +82,7 @@ static void ide_init(struct device *dev)
pci_write_config8(dev, 0x4, enables);
enables = pci_read_config8(dev, 0x4);
- printk_debug("command in reg 0x4 reads back as 0x%x\n", enables);
+ printk(BIOS_DEBUG, "command in reg 0x4 reads back as 0x%x\n", enables);
if (!conf->enable_native_ide) {
// Use compatability mode - per award bios
diff --git a/src/southbridge/via/vt8231/vt8231_lpc.c b/src/southbridge/via/vt8231/vt8231_lpc.c
index cee46b51bb56..9799195d87ac 100644
--- a/src/southbridge/via/vt8231/vt8231_lpc.c
+++ b/src/southbridge/via/vt8231/vt8231_lpc.c
@@ -23,7 +23,7 @@ static const unsigned char slotIrqs[4] = { 5, 10, 12, 11 };
static void pci_routing_fixup(struct device *dev)
{
- printk_info("%s: dev is %p\n", __func__, dev);
+ printk(BIOS_INFO, "%s: dev is %p\n", __func__, dev);
if (dev) {
/* initialize PCI interupts - these assignments depend
on the PCB routing of PINTA-D
@@ -39,17 +39,17 @@ static void pci_routing_fixup(struct device *dev)
}
// Standard southbridge components
- printk_info("setting southbridge\n");
+ printk(BIOS_INFO, "setting southbridge\n");
pci_assign_irqs(0, 0x11, southbridgeIrqs);
// Ethernet built into southbridge
- printk_info("setting ethernet\n");
+ printk(BIOS_INFO, "setting ethernet\n");
pci_assign_irqs(0, 0x12, enetIrqs);
// PCI slot
- printk_info("setting pci slot\n");
+ printk(BIOS_INFO, "setting pci slot\n");
pci_assign_irqs(0, 0x14, slotIrqs);
- printk_info("%s: DONE\n", __func__);
+ printk(BIOS_INFO, "%s: DONE\n", __func__);
}
static void vt8231_init(struct device *dev)
@@ -57,7 +57,7 @@ static void vt8231_init(struct device *dev)
unsigned char enables;
struct southbridge_via_vt8231_config *conf = dev->chip_info;
- printk_debug("vt8231 init\n");
+ printk(BIOS_DEBUG, "vt8231 init\n");
// enable the internal I/O decode
enables = pci_read_config8(dev, 0x6C);
@@ -102,18 +102,18 @@ static void vt8231_init(struct device *dev)
// First do some more things to devfn (17,0)
// note: this should already be cleared, according to the book.
enables = pci_read_config8(dev, 0x50);
- printk_debug("IDE enable in reg. 50 is 0x%x\n", enables);
+ printk(BIOS_DEBUG, "IDE enable in reg. 50 is 0x%x\n", enables);
enables &= ~8; // need manifest constant here!
- printk_debug("set IDE reg. 50 to 0x%x\n", enables);
+ printk(BIOS_DEBUG, "set IDE reg. 50 to 0x%x\n", enables);
pci_write_config8(dev, 0x50, enables);
// set default interrupt values (IDE)
enables = pci_read_config8(dev, 0x4c);
- printk_debug("IRQs in reg. 4c are 0x%x\n", enables & 0xf);
+ printk(BIOS_DEBUG, "IRQs in reg. 4c are 0x%x\n", enables & 0xf);
// clear out whatever was there.
enables &= ~0xf;
enables |= 4;
- printk_debug("setting reg. 4c to 0x%x\n", enables);
+ printk(BIOS_DEBUG, "setting reg. 4c to 0x%x\n", enables);
pci_write_config8(dev, 0x4c, enables);
// set up the serial port interrupts.
diff --git a/src/southbridge/via/vt8231/vt8231_nic.c b/src/southbridge/via/vt8231/vt8231_nic.c
index 828cdaf2f639..d4771f68160f 100644
--- a/src/southbridge/via/vt8231/vt8231_nic.c
+++ b/src/southbridge/via/vt8231/vt8231_nic.c
@@ -12,7 +12,7 @@ static void nic_init(struct device *dev)
{
uint8_t byte;
- printk_debug("Configuring VIA LAN\n");
+ printk(BIOS_DEBUG, "Configuring VIA LAN\n");
/* We don't need stepping - though the device supports it */
byte = pci_read_config8(dev, PCI_COMMAND);
diff --git a/src/southbridge/via/vt8235/vt8235.c b/src/southbridge/via/vt8235/vt8235.c
index f384847d5c88..228da0f9483e 100644
--- a/src/southbridge/via/vt8235/vt8235.c
+++ b/src/southbridge/via/vt8235/vt8235.c
@@ -14,7 +14,7 @@ static int enabled = 0;
void hard_reset(void)
{
- printk_err("NO HARD RESET ON VT8235! FIX ME!\n");
+ printk(BIOS_ERR, "NO HARD RESET ON VT8235! FIX ME!\n");
}
static void keyboard_on(struct device *dev)
@@ -34,11 +34,11 @@ void dump_south(device_t dev0)
int i,j;
for(i = 0; i < 256; i += 16) {
- printk_debug("0x%x: ", i);
+ printk(BIOS_DEBUG, "0x%x: ", i);
for(j = 0; j < 16; j++) {
- printk_debug("%02x ", pci_read_config8(dev0, i+j));
+ printk(BIOS_DEBUG, "%02x ", pci_read_config8(dev0, i+j));
}
- printk_debug("\n");
+ printk(BIOS_DEBUG, "\n");
}
}
@@ -61,7 +61,7 @@ static void vt8235_enable(struct device *dev)
vendor = pci_read_config16(dev,0);
model = pci_read_config16(dev,0x2);
- printk_debug("In vt8235_enable %04x %04x.\n",vendor,model);
+ printk(BIOS_DEBUG, "In vt8235_enable %04x %04x.\n",vendor,model);
/* if this is not the southbridge itself just return */
/* this is necessary because USB devices are slot 10, whereas this device is slot 11
@@ -70,7 +70,7 @@ static void vt8235_enable(struct device *dev)
if( (vendor != PCI_VENDOR_ID_VIA) || (model != PCI_DEVICE_ID_VIA_8235))
return;
- printk_debug("Initialising Devices\n");
+ printk(BIOS_DEBUG, "Initialising Devices\n");
setup_i8259(); // make sure interupt controller is configured before keyboard init
diff --git a/src/southbridge/via/vt8235/vt8235_ide.c b/src/southbridge/via/vt8235/vt8235_ide.c
index 9c2af3c7813a..ec22f9053bed 100644
--- a/src/southbridge/via/vt8235/vt8235_ide.c
+++ b/src/southbridge/via/vt8235/vt8235_ide.c
@@ -10,7 +10,7 @@ static void ide_init(struct device *dev)
struct southbridge_via_vt8235_config *conf = dev->chip_info;
unsigned char enables;
- printk_info("Enabling VIA IDE.\n");
+ printk(BIOS_INFO, "Enabling VIA IDE.\n");
/*if (!conf->enable_native_ide) { */
/*
@@ -18,23 +18,23 @@ static void ide_init(struct device *dev)
* use PCI interrupts. Using PCI ints confuses linux for some
* reason.
*/
- printk_info("%s: enabling compatibility IDE addresses\n",
+ printk(BIOS_INFO, "%s: enabling compatibility IDE addresses\n",
__func__);
enables = pci_read_config8(dev, 0x42);
- printk_debug("enables in reg 0x42 0x%x\n", enables);
+ printk(BIOS_DEBUG, "enables in reg 0x42 0x%x\n", enables);
enables &= ~0xc0; // compatability mode
pci_write_config8(dev, 0x42, enables);
enables = pci_read_config8(dev, 0x42);
- printk_debug("enables in reg 0x42 read back as 0x%x\n",
+ printk(BIOS_DEBUG, "enables in reg 0x42 read back as 0x%x\n",
enables);
/* } */
enables = pci_read_config8(dev, 0x40);
- printk_debug("enables in reg 0x40 0x%x\n", enables);
+ printk(BIOS_DEBUG, "enables in reg 0x40 0x%x\n", enables);
enables |= 3;
pci_write_config8(dev, 0x40, enables);
enables = pci_read_config8(dev, 0x40);
- printk_debug("enables in reg 0x40 read back as 0x%x\n", enables);
+ printk(BIOS_DEBUG, "enables in reg 0x40 read back as 0x%x\n", enables);
// Enable prefetch buffers
enables = pci_read_config8(dev, 0x41);
@@ -58,7 +58,7 @@ static void ide_init(struct device *dev)
// kevinh@ispiri.com - the standard linux drivers seem ass slow when
// used in native mode - I've changed back to classic
enables = pci_read_config8(dev, 0x9);
- printk_debug("enables in reg 0x9 0x%x\n", enables);
+ printk(BIOS_DEBUG, "enables in reg 0x9 0x%x\n", enables);
// by the book, set the low-order nibble to 0xa.
if (conf->enable_native_ide) {
enables &= ~0xf;
@@ -70,11 +70,11 @@ static void ide_init(struct device *dev)
pci_write_config8(dev, 0x9, enables);
enables = pci_read_config8(dev, 0x9);
- printk_debug("enables in reg 0x9 read back as 0x%x\n", enables);
+ printk(BIOS_DEBUG, "enables in reg 0x9 read back as 0x%x\n", enables);
// standard bios sets master bit.
enables = pci_read_config8(dev, 0x4);
- printk_debug("command in reg 0x4 0x%x\n", enables);
+ printk(BIOS_DEBUG, "command in reg 0x4 0x%x\n", enables);
enables |= 7;
// No need for stepping - kevinh@ispiri.com
@@ -82,7 +82,7 @@ static void ide_init(struct device *dev)
pci_write_config8(dev, 0x4, enables);
enables = pci_read_config8(dev, 0x4);
- printk_debug("command in reg 0x4 reads back as 0x%x\n", enables);
+ printk(BIOS_DEBUG, "command in reg 0x4 reads back as 0x%x\n", enables);
if (!conf->enable_native_ide) {
// Use compatability mode - per award bios
diff --git a/src/southbridge/via/vt8235/vt8235_lpc.c b/src/southbridge/via/vt8235/vt8235_lpc.c
index 052c4c9415c9..92ba973661fd 100644
--- a/src/southbridge/via/vt8235/vt8235_lpc.c
+++ b/src/southbridge/via/vt8235/vt8235_lpc.c
@@ -56,7 +56,7 @@ static unsigned char *pin_to_irq(const unsigned char *pin)
static void pci_routing_fixup(struct device *dev)
{
- printk_info("%s: dev is %p\n", __func__, dev);
+ printk(BIOS_INFO, "%s: dev is %p\n", __func__, dev);
/* set up PCI IRQ routing */
pci_write_config8(dev, 0x55, pciIrqs[0] << 4);
@@ -65,38 +65,38 @@ static void pci_routing_fixup(struct device *dev)
// firewire built into southbridge
- printk_info("setting firewire\n");
+ printk(BIOS_INFO, "setting firewire\n");
pci_assign_irqs(0, 0x0d, pin_to_irq(firewirePins));
// Standard usb components
- printk_info("setting usb\n");
+ printk(BIOS_INFO, "setting usb\n");
pci_assign_irqs(0, 0x10, pin_to_irq(usbPins));
// VT8235 + sound hardware
- printk_info("setting vt8235\n");
+ printk(BIOS_INFO, "setting vt8235\n");
pci_assign_irqs(0, 0x11, pin_to_irq(vt8235Pins));
// Ethernet built into southbridge
- printk_info("setting ethernet\n");
+ printk(BIOS_INFO, "setting ethernet\n");
pci_assign_irqs(0, 0x12, pin_to_irq(enetPins));
// VGA
- printk_info("setting vga\n");
+ printk(BIOS_INFO, "setting vga\n");
pci_assign_irqs(1, 0x00, pin_to_irq(vgaPins));
// PCI slot
- printk_info("setting pci slot\n");
+ printk(BIOS_INFO, "setting pci slot\n");
pci_assign_irqs(0, 0x14, pin_to_irq(slotPins));
// Cardbus slot
- printk_info("setting cardbus slot\n");
+ printk(BIOS_INFO, "setting cardbus slot\n");
pci_assign_irqs(0, 0x0a, pin_to_irq(cbPins));
// Via 2 slot riser card 2nd slot
- printk_info("setting riser slot\n");
+ printk(BIOS_INFO, "setting riser slot\n");
pci_assign_irqs(0, 0x13, pin_to_irq(riserPins));
- printk_spew("%s: DONE\n", __func__);
+ printk(BIOS_SPEW, "%s: DONE\n", __func__);
}
/*
@@ -154,7 +154,7 @@ static void vt8235_init(struct device *dev)
{
unsigned char enables;
- printk_debug("vt8235 init\n");
+ printk(BIOS_DEBUG, "vt8235 init\n");
// enable the internal I/O decode
enables = pci_read_config8(dev, 0x6C);
diff --git a/src/southbridge/via/vt8235/vt8235_nic.c b/src/southbridge/via/vt8235/vt8235_nic.c
index 09ea17e07836..86fef895de49 100644
--- a/src/southbridge/via/vt8235/vt8235_nic.c
+++ b/src/southbridge/via/vt8235/vt8235_nic.c
@@ -12,7 +12,7 @@ static void nic_init(struct device *dev)
{
uint8_t byte;
- printk_debug("Configuring VIA Rhine LAN\n");
+ printk(BIOS_DEBUG, "Configuring VIA Rhine LAN\n");
/* We don't need stepping - though the device supports it */
byte = pci_read_config8(dev, PCI_COMMAND);
diff --git a/src/southbridge/via/vt8235/vt8235_usb.c b/src/southbridge/via/vt8235/vt8235_usb.c
index 231846505866..8b2a6858076d 100644
--- a/src/southbridge/via/vt8235/vt8235_usb.c
+++ b/src/southbridge/via/vt8235/vt8235_usb.c
@@ -9,7 +9,7 @@
static void usb_init(struct device *dev)
{
- printk_debug("Configuring VIA USB 1.1\n");
+ printk(BIOS_DEBUG, "Configuring VIA USB 1.1\n");
/* pci_write_config8(dev, 0x04, 0x07); */
diff --git a/src/southbridge/via/vt8237r/vt8237r.c b/src/southbridge/via/vt8237r/vt8237r.c
index 8be26db6082c..2b5d34bccc21 100644
--- a/src/southbridge/via/vt8237r/vt8237r.c
+++ b/src/southbridge/via/vt8237r/vt8237r.c
@@ -30,7 +30,7 @@
void hard_reset(void)
{
- printk_err("NO HARD RESET ON VT8237R! FIX ME!\n");
+ printk(BIOS_ERR, "NO HARD RESET ON VT8237R! FIX ME!\n");
}
#if CONFIG_DEFAULT_CONSOLE_LOGLEVEL > 7
@@ -61,10 +61,10 @@ void dump_south(device_t dev)
int i, j;
for (i = 0; i < 256; i += 16) {
- printk_debug("%02x: ", i);
+ printk(BIOS_DEBUG, "%02x: ", i);
for (j = 0; j < 16; j++)
- printk_debug("%02x ", pci_read_config8(dev, i + j));
- printk_debug("\n");
+ printk(BIOS_DEBUG, "%02x ", pci_read_config8(dev, i + j));
+ printk(BIOS_DEBUG, "\n");
}
}
diff --git a/src/southbridge/via/vt8237r/vt8237r_ide.c b/src/southbridge/via/vt8237r/vt8237r_ide.c
index 86a87ac79198..0b4dccc2f053 100644
--- a/src/southbridge/via/vt8237r/vt8237r_ide.c
+++ b/src/southbridge/via/vt8237r/vt8237r_ide.c
@@ -40,15 +40,15 @@ static void ide_init(struct device *dev)
device_t lpc_dev;
int i, j;
- printk_info("%s IDE interface %s\n", "Primary",
+ printk(BIOS_INFO, "%s IDE interface %s\n", "Primary",
sb->ide0_enable ? "enabled" : "disabled");
- printk_info("%s IDE interface %s\n", "Secondary",
+ printk(BIOS_INFO, "%s IDE interface %s\n", "Secondary",
sb->ide1_enable ? "enabled" : "disabled");
enables = pci_read_config8(dev, IDE_CS) & ~0x3;
enables |= (sb->ide0_enable << 1) | sb->ide1_enable;
pci_write_config8(dev, IDE_CS, enables);
enables = pci_read_config8(dev, IDE_CS);
- printk_debug("Enables in reg 0x40 read back as 0x%x\n", enables);
+ printk(BIOS_DEBUG, "Enables in reg 0x40 read back as 0x%x\n", enables);
/* Enable only compatibility mode. */
enables = pci_read_config8(dev, 0x09);
@@ -59,7 +59,7 @@ static void ide_init(struct device *dev)
enables &= ~0xc0;
pci_write_config8(dev, IDE_CONF_II, enables);
enables = pci_read_config8(dev, IDE_CONF_II);
- printk_debug("Enables in reg 0x42 read back as 0x%x\n", enables);
+ printk(BIOS_DEBUG, "Enables in reg 0x42 read back as 0x%x\n", enables);
/* Enable prefetch buffers. */
enables = pci_read_config8(dev, IDE_CONF_I);
diff --git a/src/southbridge/via/vt8237r/vt8237r_lpc.c b/src/southbridge/via/vt8237r/vt8237r_lpc.c
index d53028128fbb..4e09823a6909 100644
--- a/src/southbridge/via/vt8237r/vt8237r_lpc.c
+++ b/src/southbridge/via/vt8237r/vt8237r_lpc.c
@@ -238,7 +238,7 @@ static void setup_pm(device_t dev)
tmp = inw(VT8237R_ACPI_IO_BASE + 0x04);
#if CONFIG_HAVE_ACPI_RESUME == 1
acpi_slp_type = ((tmp & (7 << 10)) >> 10) == 1 ? 3 : 0 ;
- printk_debug("SLP_TYP type was %x %x\n", tmp, acpi_slp_type);
+ printk(BIOS_DEBUG, "SLP_TYP type was %x %x\n", tmp, acpi_slp_type);
#endif
/* clear sleep */
tmp &= ~(7 << 10);
@@ -251,7 +251,7 @@ static void vt8237r_init(struct device *dev)
u8 enables, reg8;
#if CONFIG_EPIA_VT8237R_INIT
- printk_spew("Entering vt8237r_init, for EPIA.\n");
+ printk(BIOS_SPEW, "Entering vt8237r_init, for EPIA.\n");
/*
* TODO: Looks like stock BIOS can do this but causes a hang
* Enable SATA LED, disable special CPU Frequency Change -
@@ -277,7 +277,7 @@ static void vt8237r_init(struct device *dev)
pci_write_config8(dev, 0x4E, enables);
#else
- printk_spew("Entering vt8237r_init.\n");
+ printk(BIOS_SPEW, "Entering vt8237r_init.\n");
/*
* Enable SATA LED, disable special CPU Frequency Change -
* GPIO28 GPIO22 GPIO29 GPIO23 are GPIOs.
@@ -318,7 +318,7 @@ static void vt8237r_init(struct device *dev)
outb(0x1, VT8237R_ACPI_IO_BASE + 0x11);
#endif
- printk_spew("Leaving %s.\n", __func__);
+ printk(BIOS_SPEW, "Leaving %s.\n", __func__);
}
static void vt8237s_init(struct device *dev)
diff --git a/src/southbridge/via/vt8237r/vt8237r_sata.c b/src/southbridge/via/vt8237r/vt8237r_sata.c
index b0c58aa9c14e..8d09057f2788 100644
--- a/src/southbridge/via/vt8237r/vt8237r_sata.c
+++ b/src/southbridge/via/vt8237r/vt8237r_sata.c
@@ -28,7 +28,7 @@ static void sata_i_init(struct device *dev)
{
u8 reg;
- printk_debug("Configuring VIA SATA controller\n");
+ printk(BIOS_DEBUG, "Configuring VIA SATA controller\n");
/* Class IDE Disk */
reg = pci_read_config8(dev, SATA_MISC_CTRL);
diff --git a/src/southbridge/via/vt8237r/vt8237r_usb.c b/src/southbridge/via/vt8237r/vt8237r_usb.c
index 2c554ca3da5e..4bd33d6346f2 100644
--- a/src/southbridge/via/vt8237r/vt8237r_usb.c
+++ b/src/southbridge/via/vt8237r/vt8237r_usb.c
@@ -34,16 +34,16 @@ static void usb_i_init(struct device *dev)
#if CONFIG_EPIA_VT8237R_INIT
u8 reg8;
- printk_debug("Entering %s\n", __func__);
+ printk(BIOS_DEBUG, "Entering %s\n", __func__);
- printk_spew("%s Read %02X from PCI Command Reg\n", dev_path(dev), reg8);
+ printk(BIOS_SPEW, "%s Read %02X from PCI Command Reg\n", dev_path(dev), reg8);
reg8 = pci_read_config8(dev, 0x04);
reg8 = reg8 | PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY;
pci_write_config8(dev, 0x04, reg8);
- printk_spew("%s Wrote %02X to PCI Command Reg\n", dev_path(dev), reg8);
+ printk(BIOS_SPEW, "%s Wrote %02X to PCI Command Reg\n", dev_path(dev), reg8);
/* Set Cache Line Size and Latency Timer */
pci_write_config8(dev, 0x0c, 0x08);
@@ -74,7 +74,7 @@ static void vt8237_usb_i_read_resources(struct device *dev)
struct resource *res;
u8 function = (u8) dev->path.pci.devfn & 0x7;
- printk_spew("VT8237R Fixing USB 1.1 fn %d I/O resource = 0x%04X\n", function, usb_io_addr[function]);
+ printk(BIOS_SPEW, "VT8237R Fixing USB 1.1 fn %d I/O resource = 0x%04X\n", function, usb_io_addr[function]);
/* Fix the I/O Resources of the USB1.1 Interfaces */
/* Auto PCI probe seems to size the resources */
@@ -98,7 +98,7 @@ static void usb_ii_init(struct device *dev)
#if CONFIG_EPIA_VT8237R_INIT
u8 reg8;
- printk_debug("Entering %s\n", __func__);
+ printk(BIOS_DEBUG, "Entering %s\n", __func__);
/* Set memory Write and Invalidate */
reg8 = pci_read_config8(dev, 0x04);
generated by cgit v1.2.3 (git 2.25.1) at 2024-07-16 07:25:02 +0000