diff options
Diffstat (limited to 'src/vendorcode/amd/agesa/f15tn/Proc/GNB')
9 files changed, 22 insertions, 17 deletions
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbCommonLib/GnbLib.c b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbCommonLib/GnbLib.c index 7f701f078cfc..69137a0cbb51 100644 --- a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbCommonLib/GnbLib.c +++ b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbCommonLib/GnbLib.c @@ -473,7 +473,7 @@ GnbLibDebugDumpBuffer ( Index += 4; break; case 4: - IDS_HDT_CONSOLE (GNB_TRACE, "%08x%08", *(UINT32 *) ((UINT8 *) Buffer + Index), *(UINT32 *) ((UINT8 *) Buffer + Index + 4)); + IDS_HDT_CONSOLE (GNB_TRACE, "%016llx", *(UINT64 *) ((UINT8 *) Buffer + Index)); Index += 8; break; default: diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbGfxConfig/GfxConfigLib.c b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbGfxConfig/GfxConfigLib.c index 8befb2cd5e4f..05b11fe416b3 100644 --- a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbGfxConfig/GfxConfigLib.c +++ b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbGfxConfig/GfxConfigLib.c @@ -223,7 +223,7 @@ GfxConfigDebugDump ( ); IDS_HDT_CONSOLE (GFX_MISC, " UmaMode - %s\n", (Gfx->UmaInfo.UmaMode == UMA_NONE) ? "No UMA" : "UMA"); if (Gfx->UmaInfo.UmaMode != UMA_NONE) { - IDS_HDT_CONSOLE (GFX_MISC, " UmaBase - 0x%x\n", Gfx->UmaInfo.UmaBase); + IDS_HDT_CONSOLE (GFX_MISC, " UmaBase - 0x%llx\n", Gfx->UmaInfo.UmaBase); IDS_HDT_CONSOLE (GFX_MISC, " UmaSize - 0x%x\n", Gfx->UmaInfo.UmaSize); IDS_HDT_CONSOLE (GFX_MISC, " UmaAttributes - 0x%x\n", Gfx->UmaInfo.UmaAttributes); } diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbGfxInitLibV1/GfxPowerPlayTable.c b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbGfxInitLibV1/GfxPowerPlayTable.c index 422cbae00719..7cb69fd37438 100644 --- a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbGfxInitLibV1/GfxPowerPlayTable.c +++ b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbGfxInitLibV1/GfxPowerPlayTable.c @@ -895,7 +895,7 @@ GfxIntegratedDebugDumpPpTable ( ClockInfoArrayPtr = (CLOCK_INFO_ARRAY *) ((UINT8 *) PpTable + PpTable->usClockInfoArrayOffset); IDS_HDT_CONSOLE (GFX_MISC, " < --- SW State Table ---------> \n"); for (Index = 0; Index < StateArray->ucNumEntries; Index++) { - IDS_HDT_CONSOLE (GFX_MISC, " State #%d\n", Index + 1 + IDS_HDT_CONSOLE (GFX_MISC, " State #%ld\n", Index + 1 ); IDS_HDT_CONSOLE (GFX_MISC, " Classification 0x%x\n", NonClockInfoArrayPtr->NonClockInfo[StatesPtr->nonClockInfoIndex].usClassification @@ -922,7 +922,7 @@ GfxIntegratedDebugDumpPpTable ( for (Index = 0; Index < ClockInfoArrayPtr->ucNumEntries; Index++) { UINT32 Sclk; Sclk = ClockInfoArrayPtr->ClockInfo[Index].usEngineClockLow | (ClockInfoArrayPtr->ClockInfo[Index].ucEngineClockHigh << 16); - IDS_HDT_CONSOLE (GFX_MISC, " DPM State #%d\n", + IDS_HDT_CONSOLE (GFX_MISC, " DPM State #%ld\n", Index ); IDS_HDT_CONSOLE (GFX_MISC, " SCLK = %d\n", @@ -951,7 +951,7 @@ GfxIntegratedDebugDumpPpTable ( for (Index = 0; Index < VceStateTable->numEntries; Index++) { SclkIndex = VceStateTable->entries[Index].ucClockInfoIndex & 0x3F; EclkIndex = VceStateTable->entries[Index].ucVCEClockInfoIndex; - IDS_HDT_CONSOLE (GFX_MISC, " VCE State #%d\n", Index + IDS_HDT_CONSOLE (GFX_MISC, " VCE State #%ld\n", Index ); if ((VceClockInfoArray->entries[EclkIndex].usECClkLow | (VceClockInfoArray->entries[EclkIndex].ucECClkHigh << 16)) == 0) { IDS_HDT_CONSOLE (GFX_MISC, " Disable\n"); @@ -973,7 +973,7 @@ GfxIntegratedDebugDumpPpTable ( IDS_HDT_CONSOLE (GFX_MISC, " < --- VCE Voltage Record Table ---> \n"); for (Index = 0; Index < VceClockVoltageLimitTable->numEntries; Index++) { EclkIndex = VceClockVoltageLimitTable->entries[Index].ucVCEClockInfoIndex; - IDS_HDT_CONSOLE (GFX_MISC, " VCE Voltage Record #%d\n", Index + IDS_HDT_CONSOLE (GFX_MISC, " VCE Voltage Record #%ld\n", Index ); IDS_HDT_CONSOLE (GFX_MISC, " ECLK = %d\n", VceClockInfoArray->entries[EclkIndex].usECClkLow | (VceClockInfoArray->entries[EclkIndex].ucECClkHigh << 16) diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/GnbEarlyInitTN.c b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/GnbEarlyInitTN.c index 8b388d583eb5..15c067969132 100644 --- a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/GnbEarlyInitTN.c +++ b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/GnbEarlyInitTN.c @@ -337,7 +337,7 @@ GnbTjOffsetUpdateTN ( ASSERT (GnbHandle != NULL); GetLogicalIdOfSocket (GnbGetSocketId (GnbHandle), &LogicalId, StdHeader); if ((LogicalId.Revision & 0x0000000000000100ull ) != 0x0000000000000100ull ) { - IDS_HDT_CONSOLE (GNB_TRACE, "CPU Rev = %x, Skip GnbTjOffsetUpdateTN\n", LogicalId.Revision); + IDS_HDT_CONSOLE (GNB_TRACE, "CPU Rev = %llx, Skip GnbTjOffsetUpdateTN\n", LogicalId.Revision); return; } GnbRegisterReadTN (D0F0xBC_xE0104040_TYPE, D0F0xBC_xE0104040_ADDRESS, &D0F0xBC_xE0104040, 0, StdHeader); diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/GnbFuseTableTN.c b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/GnbFuseTableTN.c index 8c580a07b751..d5dcdad0c673 100644 --- a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/GnbFuseTableTN.c +++ b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/GnbFuseTableTN.c @@ -888,7 +888,7 @@ GnbFuseTableDebugDumpTN ( IN AMD_CONFIG_PARAMS *StdHeader ) { - UINTN Index; + UINT32 Index; IDS_HDT_CONSOLE (NB_MISC, "<------------ GNB FUSE TABLE------------>\n"); for (Index = 0; Index < 4; Index++) { @@ -945,7 +945,7 @@ GnbFuseTableDebugDumpTN ( ); IDS_HDT_CONSOLE ( NB_MISC, - " VCE Flags[ % d] - 0x % 02x\n", + " VCE Flags[%d] - 0x%02x\n", Index, PpFuseArray->VceFlags[Index] ); diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbIommuIvrs/GnbIommuIvrs.c b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbIommuIvrs/GnbIommuIvrs.c index b6b98e01fadb..1eb8d9bc5d22 100644 --- a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbIommuIvrs/GnbIommuIvrs.c +++ b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbIommuIvrs/GnbIommuIvrs.c @@ -292,7 +292,7 @@ GnbIommuIvrsTableDump ( Entry = Entry + 4; break; default: - IDS_HDT_CONSOLE (GNB_TRACE, " Unsupported entry type [%d]\n"); + IDS_HDT_CONSOLE (GNB_TRACE, " Unsupported entry type [%d]\n", *Entry); ASSERT (FALSE); } } diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbNbInitLibV4/GnbNbInitLibV4.c b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbNbInitLibV4/GnbNbInitLibV4.c index 84a02d11cd7c..b67d3c5394e5 100644 --- a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbNbInitLibV4/GnbNbInitLibV4.c +++ b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbNbInitLibV4/GnbNbInitLibV4.c @@ -578,7 +578,7 @@ GnbEnableIommuMmioV4 ( BaseAddress |= Value; if ((BaseAddress & 0xfffffffffffffffe) != 0x0) { - IDS_HDT_CONSOLE (GNB_TRACE, " Enable IOMMU MMIO at address %x for Socket %d Silicon %d\n", BaseAddress, GnbGetSocketId (GnbHandle) , GnbGetSiliconId (GnbHandle)); + IDS_HDT_CONSOLE (GNB_TRACE, " Enable IOMMU MMIO at address %llx for Socket %d Silicon %d\n", BaseAddress, GnbGetSocketId (GnbHandle) , GnbGetSiliconId (GnbHandle)); GnbLibPciRMW (GnbIommuPciAddress.AddressValue | (CapabilityOffset + 0x8), AccessS3SaveWidth32, 0xFFFFFFFF, 0x0, StdHeader); GnbLibPciRMW (GnbIommuPciAddress.AddressValue | (CapabilityOffset + 0x4), AccessS3SaveWidth32, 0xFFFFFFFE, 0x1, StdHeader); } else { diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieConfig/PcieConfigLib.c b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieConfig/PcieConfigLib.c index 9b7bcbded216..e839a1dff00d 100644 --- a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieConfig/PcieConfigLib.c +++ b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieConfig/PcieConfigLib.c @@ -557,7 +557,10 @@ PcieConfigEngineDebugDump ( EngineList->Type.Port.Address.Address.Device, EngineList->Type.Port.Address.Address.Function ); - IDS_HDT_CONSOLE (PCIE_MISC, " Misc Control - 0x%02x\n", EngineList->Type.Port.PortData.MiscControls); + IDS_HDT_CONSOLE (PCIE_MISC, " Misc Control, Compliance Mode - %u\n", EngineList->Type.Port.PortData.MiscControls.LinkComplianceMode); + IDS_HDT_CONSOLE (PCIE_MISC, " Misc Control, Safe Mode - %u\n", EngineList->Type.Port.PortData.MiscControls.LinkSafeMode); + IDS_HDT_CONSOLE (PCIE_MISC, " Misc Control, SB Link - %u\n", EngineList->Type.Port.PortData.MiscControls.SbLink); + IDS_HDT_CONSOLE (PCIE_MISC, " Misc Control, CLK PM Support - %u\n", EngineList->Type.Port.PortData.MiscControls.ClkPmSupport); IDS_HDT_CONSOLE (PCIE_MISC, " Native PCI Dev Number - %d\n", EngineList->Type.Port.NativeDevNumber); IDS_HDT_CONSOLE (PCIE_MISC, " Native PCI Func Number - %d\n", EngineList->Type.Port.NativeFunNumber); IDS_HDT_CONSOLE (PCIE_MISC, " Hotplug - %s\n", @@ -737,7 +740,7 @@ PcieUserDescriptorConfigDump ( EngineDescriptor->EngineData.EndLane ); if (EngineDescriptor->EngineData.EngineType == PciePortEngine) { - IDS_HDT_CONSOLE (PCIE_MISC, " PortPresent - %d\n ChannelType - %d\n DeviceNumber - %d\n FunctionNumber - %d\n LinkSpeedCapability - %d\n LinkAspm - %d\n LinkHotplug - %d\n ResetId - %d\n SB link - %d\n MiscControls - 0x%02x\n" , + IDS_HDT_CONSOLE (PCIE_MISC, " PortPresent - %d\n ChannelType - %d\n DeviceNumber - %d\n FunctionNumber - %d\n LinkSpeedCapability - %d\n LinkAspm - %d\n LinkHotplug - %d\n ResetId - %d\n Compliance Mode - %d\n Safe Mode - %d\n SB link - %d\n CLK PM Support - %d\n" , ((PCIe_PORT_DESCRIPTOR *) EngineDescriptor)->Port.PortPresent, ((PCIe_PORT_DESCRIPTOR *) EngineDescriptor)->Port.ChannelType, ((PCIe_PORT_DESCRIPTOR *) EngineDescriptor)->Port.DeviceNumber, @@ -746,8 +749,10 @@ PcieUserDescriptorConfigDump ( ((PCIe_PORT_DESCRIPTOR *) EngineDescriptor)->Port.LinkAspm, ((PCIe_PORT_DESCRIPTOR *) EngineDescriptor)->Port.LinkHotplug, ((PCIe_PORT_DESCRIPTOR *) EngineDescriptor)->Port.ResetId, + ((PCIe_PORT_DESCRIPTOR *) EngineDescriptor)->Port.MiscControls.LinkComplianceMode, + ((PCIe_PORT_DESCRIPTOR *) EngineDescriptor)->Port.MiscControls.LinkSafeMode, ((PCIe_PORT_DESCRIPTOR *) EngineDescriptor)->Port.MiscControls.SbLink, - ((PCIe_PORT_DESCRIPTOR *) EngineDescriptor)->Port.MiscControls + ((PCIe_PORT_DESCRIPTOR *) EngineDescriptor)->Port.MiscControls.ClkPmSupport ); } if (EngineDescriptor->EngineData.EngineType == PcieDdiEngine) { @@ -785,7 +790,7 @@ PcieUserConfigConfigDump ( for (ComplexIndex = 0; ComplexIndex < NumberOfComplexes; ++ComplexIndex) { CurrentComplexDescriptor = PcieInputParserGetComplexDescriptor (ComplexDescriptor, ComplexIndex); NumberOfEngines = PcieInputParserGetNumberOfEngines (CurrentComplexDescriptor); - IDS_HDT_CONSOLE (PCIE_MISC, " ComplexDescriptor SocketId - %d\n NumberOfEngines - %d\n", + IDS_HDT_CONSOLE (PCIE_MISC, " ComplexDescriptor SocketId - %d\n NumberOfEngines - %ld\n", ComplexDescriptor->SocketId, NumberOfEngines ); diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieInitLibV1/PciePowerMgmt.c b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieInitLibV1/PciePowerMgmt.c index 2a40c0900512..98731541fa1c 100644 --- a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieInitLibV1/PciePowerMgmt.c +++ b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieInitLibV1/PciePowerMgmt.c @@ -167,7 +167,7 @@ PcieLanesToPowerDownPllInL1 ( for (Index = 0; Index < 4; Index++) { if ((ActiveLanesBitmap & (0xF << (Index * 4))) != 0) { if (LaneGroupExitLatency [Index] > LinkLatencyInfo.MaxL1ExitLatency) { - IDS_HDT_CONSOLE (GNB_TRACE, " Index %d Latency %d\n", Index, LinkLatencyInfo.MaxL1ExitLatency); + IDS_HDT_CONSOLE (GNB_TRACE, " Index %ld Latency %d\n", Index, LinkLatencyInfo.MaxL1ExitLatency); LaneGroupExitLatency [Index] = LinkLatencyInfo.MaxL1ExitLatency; } } @@ -177,7 +177,7 @@ PcieLanesToPowerDownPllInL1 ( } LaneBitmapForPllOffInL1 = 0; for (Index = 0; Index < 4; Index++) { - IDS_HDT_CONSOLE (GNB_TRACE, " Index %d Final Latency %d\n", Index, LaneGroupExitLatency[Index]); + IDS_HDT_CONSOLE (GNB_TRACE, " Index %ld Final Latency %d\n", Index, LaneGroupExitLatency[Index]); if (LaneGroupExitLatency[Index] > PllPowerUpLatency) { LaneBitmapForPllOffInL1 |= (0xF << (Index * 4)); } |