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-rw-r--r--src/vendorcode/amd/opensil/genoa_poc/opensil.h5
-rw-r--r--src/vendorcode/amd/opensil/genoa_poc/ramstage.c17
2 files changed, 19 insertions, 3 deletions
diff --git a/src/vendorcode/amd/opensil/genoa_poc/opensil.h b/src/vendorcode/amd/opensil/genoa_poc/opensil.h
index e22552233bed..334903ff2e7e 100644
--- a/src/vendorcode/amd/opensil/genoa_poc/opensil.h
+++ b/src/vendorcode/amd/opensil/genoa_poc/opensil.h
@@ -4,7 +4,6 @@
#define _OPENSIL_H_
#include <acpi/acpi.h>
-#include <xSIM-api.h>
void SIL_STATUS_report(const char *function, const int status);
// Add the memory map to dev, starting at index idx, returns last use idx
@@ -15,6 +14,8 @@ void opensil_fill_fadt_io_ports(acpi_fadt_t *fadt);
void configure_mpio(void);
void setup_opensil(void);
-void opensil_entry(SIL_TIMEPOINT timepoint);
+void opensil_xSIM_timepoint_1(void);
+void opensil_xSIM_timepoint_2(void);
+void opensil_xSIM_timepoint_3(void);
#endif
diff --git a/src/vendorcode/amd/opensil/genoa_poc/ramstage.c b/src/vendorcode/amd/opensil/genoa_poc/ramstage.c
index 11289bb81b27..758b2841fdcf 100644
--- a/src/vendorcode/amd/opensil/genoa_poc/ramstage.c
+++ b/src/vendorcode/amd/opensil/genoa_poc/ramstage.c
@@ -129,7 +129,7 @@ void setup_opensil(void)
configure_mpio();
}
-void opensil_entry(SIL_TIMEPOINT timepoint)
+static void opensil_entry(SIL_TIMEPOINT timepoint)
{
SIL_STATUS ret;
SIL_TIMEPOINT tp = (uintptr_t)timepoint;
@@ -160,4 +160,19 @@ void opensil_entry(SIL_TIMEPOINT timepoint)
}
}
+void opensil_xSIM_timepoint_1(void)
+{
+ opensil_entry(SIL_TP1);
+}
+
+void opensil_xSIM_timepoint_2(void)
+{
+ opensil_entry(SIL_TP2);
+}
+
+void opensil_xSIM_timepoint_3(void)
+{
+ opensil_entry(SIL_TP3);
+}
+
/* TODO: also call timepoints 2 and 3 from coreboot. Are they NOOP? */