diff options
Diffstat (limited to 'src/vendorcode/mediatek/mt8192/include')
31 files changed, 26117 insertions, 0 deletions
diff --git a/src/vendorcode/mediatek/mt8192/include/Margaux_Register_DDRPHY_AO.h b/src/vendorcode/mediatek/mt8192/include/Margaux_Register_DDRPHY_AO.h new file mode 100644 index 000000000000..773c3e41bce4 --- /dev/null +++ b/src/vendorcode/mediatek/mt8192/include/Margaux_Register_DDRPHY_AO.h @@ -0,0 +1,3597 @@ +/* SPDX-License-Identifier: BSD-3-Clause */ + +#ifndef __DDRPHY_AO_REGS_H__ +#define __DDRPHY_AO_REGS_H__ + +#define Channel_A_DDRPHY_AO_BASE_ADDRESS 0x10238000 +#define Channel_B_DDRPHY_AO_BASE_ADDRESS 0x10248000 + +#define DDRPHY_AO_BASE_ADDRESS Channel_A_DDRPHY_AO_BASE_VIRTUAL + +#define DDRPHY_REG_PHYPLL0 (DDRPHY_AO_BASE_ADDRESS + 0x0000) + #define PHYPLL0_RG_RPHYPLL_SDM_SSC_EN Fld(1, 2) //[2:2] + #define PHYPLL0_RG_RPHYPLL_EN Fld(1, 31) //[31:31] + +#define DDRPHY_REG_PHYPLL1 (DDRPHY_AO_BASE_ADDRESS + 0x0004) + #define PHYPLL1_RG_RPHYPLL_TSTOP_EN Fld(1, 0) //[0:0] + #define PHYPLL1_RG_RPHYPLL_TSTOD_EN Fld(1, 1) //[1:1] + #define PHYPLL1_RG_RPHYPLL_TSTFM_EN Fld(1, 2) //[2:2] + #define PHYPLL1_RG_RPHYPLL_TSTCK_EN Fld(1, 3) //[3:3] + #define PHYPLL1_RG_RPHYPLL_TST_EN Fld(1, 4) //[4:4] + #define PHYPLL1_RG_RPHYPLL_TSTLVROD_EN Fld(1, 5) //[5:5] + #define PHYPLL1_RG_RPHYPLL_TST_SEL Fld(4, 8) //[11:8] + +#define DDRPHY_REG_PHYPLL2 (DDRPHY_AO_BASE_ADDRESS + 0x0008) + #define PHYPLL2_RG_RPHYPLL_RESETB Fld(1, 16) //[16:16] + #define PHYPLL2_RG_RPHYPLL_ATPG_EN Fld(1, 17) //[17:17] + #define PHYPLL2_RG_RPHYPLL_AD_MCK8X_EN Fld(1, 21) //[21:21] + #define PHYPLL2_RG_RPHYPLL_ADA_MCK8X_EN Fld(1, 22) //[22:22] + +#define DDRPHY_REG_CLRPLL0 (DDRPHY_AO_BASE_ADDRESS + 0x0020) + #define CLRPLL0_RG_RCLRPLL_SDM_SSC_EN Fld(1, 2) //[2:2] + #define CLRPLL0_RG_RCLRPLL_EN Fld(1, 31) //[31:31] + +#define DDRPHY_REG_RK_B0_RXDVS0 (DDRPHY_AO_BASE_ADDRESS + 0x0060) + #define RK_B0_RXDVS0_R_RK0_B0_DVS_LEAD_LAG_CNT_CLR Fld(1, 26) //[26:26] + #define RK_B0_RXDVS0_R_RK0_B0_DVS_SW_CNT_CLR Fld(1, 27) //[27:27] + #define RK_B0_RXDVS0_R_RK0_B0_DVS_SW_CNT_ENA Fld(1, 31) //[31:31] + +#define DDRPHY_REG_RK_B0_RXDVS1 (DDRPHY_AO_BASE_ADDRESS + 0x0064) + #define RK_B0_RXDVS1_R_RK0_B0_DVS_TH_LAG Fld(16, 0) //[15:0] + #define RK_B0_RXDVS1_R_RK0_B0_DVS_TH_LEAD Fld(16, 16) //[31:16] + +#define DDRPHY_REG_RK_B0_RXDVS2 (DDRPHY_AO_BASE_ADDRESS + 0x0068) + #define RK_B0_RXDVS2_R_RK0_RX_DLY_FAL_DQS_SCALE_B0 Fld(2, 16) //[17:16] + #define RK_B0_RXDVS2_R_RK0_RX_DLY_FAL_DQ_SCALE_B0 Fld(2, 18) //[19:18] + #define RK_B0_RXDVS2_R_RK0_RX_DLY_FAL_TRACK_GATE_ENA_B0 Fld(1, 23) //[23:23] + #define RK_B0_RXDVS2_R_RK0_RX_DLY_RIS_DQS_SCALE_B0 Fld(2, 24) //[25:24] + #define RK_B0_RXDVS2_R_RK0_RX_DLY_RIS_DQ_SCALE_B0 Fld(2, 26) //[27:26] + #define RK_B0_RXDVS2_R_RK0_RX_DLY_RIS_TRACK_GATE_ENA_B0 Fld(1, 28) //[28:28] + #define RK_B0_RXDVS2_R_RK0_DVS_FDLY_MODE_B0 Fld(1, 29) //[29:29] + #define RK_B0_RXDVS2_R_RK0_DVS_MODE_B0 Fld(2, 30) //[31:30] + +#define DDRPHY_REG_RK_B0_RXDVS3 (DDRPHY_AO_BASE_ADDRESS + 0x006C) + #define RK_B0_RXDVS3_RG_RK0_ARDQ_MIN_DLY_B0 Fld(8, 0) //[7:0] + #define RK_B0_RXDVS3_RG_RK0_ARDQ_MAX_DLY_B0 Fld(8, 8) //[15:8] + +#define DDRPHY_REG_RK_B0_RXDVS4 (DDRPHY_AO_BASE_ADDRESS + 0x0070) + #define RK_B0_RXDVS4_RG_RK0_ARDQS0_MIN_DLY_B0 Fld(9, 0) //[8:0] + #define RK_B0_RXDVS4_RG_RK0_ARDQS0_MAX_DLY_B0 Fld(9, 16) //[24:16] + +#define DDRPHY_REG_B0_LP_CTRL0 (DDRPHY_AO_BASE_ADDRESS + 0x0160) + #define B0_LP_CTRL0_RG_ARDMSUS_10_B0 Fld(1, 0) //[0:0] + #define B0_LP_CTRL0_RESERVED_B0_LP_CTRL0_3_1 Fld(3, 1) //[3:1] + #define B0_LP_CTRL0_RG_ARDMSUS_10_B0_LP_SEL Fld(1, 4) //[4:4] + #define B0_LP_CTRL0_RG_DA_PICG_B0_CTRL_LOW_BY_LPC Fld(1, 5) //[5:5] + #define B0_LP_CTRL0_RESERVED_B0_LP_CTRL0_6_6 Fld(1, 6) //[6:6] + #define B0_LP_CTRL0_RG_TX_ARDQ_RESETB_B0_LP_SEL Fld(1, 7) //[7:7] + #define B0_LP_CTRL0_RG_ARDQ_RESETB_B0_LP_SEL Fld(1, 8) //[8:8] + #define B0_LP_CTRL0_RG_ARPI_RESETB_B0_LP_SEL Fld(1, 9) //[9:9] + #define B0_LP_CTRL0_RESERVED_B0_LP_CTRL0_11_10 Fld(2, 10) //[11:10] + #define B0_LP_CTRL0_RG_B0_MS_SLV_LP_SEL Fld(1, 12) //[12:12] + #define B0_LP_CTRL0_RG_ARDLL_PHDET_EN_B0_LP_SEL Fld(1, 13) //[13:13] + #define B0_LP_CTRL0_RG_B0_DLL_EN_OP_SEQ_LP_SEL Fld(1, 14) //[14:14] + #define B0_LP_CTRL0_RESERVED_B0_LP_CTRL0_15 Fld(1, 15) //[15:15] + #define B0_LP_CTRL0_RG_RX_ARDQ_BIAS_EN_B0_LP_SEL Fld(1, 16) //[16:16] + #define B0_LP_CTRL0_DA_ARPI_CG_MCK_B0_LP_SEL Fld(1, 17) //[17:17] + #define B0_LP_CTRL0_DA_ARPI_CG_MCK_FB2DLL_B0_LP_SEL Fld(1, 18) //[18:18] + #define B0_LP_CTRL0_DA_ARPI_CG_MCTL_B0_LP_SEL Fld(1, 19) //[19:19] + #define B0_LP_CTRL0_DA_ARPI_CG_FB_B0_LP_SEL Fld(1, 20) //[20:20] + #define B0_LP_CTRL0_DA_ARPI_CG_DQ_B0_LP_SEL Fld(1, 21) //[21:21] + #define B0_LP_CTRL0_DA_ARPI_CG_DQM_B0_LP_SEL Fld(1, 22) //[22:22] + #define B0_LP_CTRL0_DA_ARPI_CG_DQS_B0_LP_SEL Fld(1, 23) //[23:23] + #define B0_LP_CTRL0_DA_ARPI_CG_DQSIEN_B0_LP_SEL Fld(1, 24) //[24:24] + #define B0_LP_CTRL0_DA_ARPI_MPDIV_CG_B0_LP_SEL Fld(1, 25) //[25:25] + #define B0_LP_CTRL0_RG_RX_ARDQ_VREF_EN_B0_LP_SEL Fld(1, 26) //[26:26] + #define B0_LP_CTRL0_DA_ARPI_MIDPI_EN_B0_LP_SEL Fld(1, 27) //[27:27] + #define B0_LP_CTRL0_DA_ARPI_MIDPI_CKDIV4_EN_B0_LP_SEL Fld(1, 28) //[28:28] + #define B0_LP_CTRL0_RG_ARPI_DDR400_EN_B0_LP_SEL Fld(1, 29) //[29:29] + #define B0_LP_CTRL0_RG_MIDPI_EN_B0_OP_LP_SEL Fld(1, 30) //[30:30] + #define B0_LP_CTRL0_RG_MIDPI_CKDIV4_EN_B0_OP_LP_SEL Fld(1, 31) //[31:31] + +#define DDRPHY_REG_B0_RXDVS0 (DDRPHY_AO_BASE_ADDRESS + 0x0164) + #define B0_RXDVS0_R_RX_RANKINSEL_B0 Fld(1, 0) //[0:0] + #define B0_RXDVS0_B0_RXDVS0_RFU Fld(3, 1) //[3:1] + #define B0_RXDVS0_R_RX_RANKINCTL_B0 Fld(4, 4) //[7:4] + #define B0_RXDVS0_R_DVS_SW_UP_B0 Fld(1, 8) //[8:8] + #define B0_RXDVS0_R_DMRXDVS_DQIENPRE_OPT_B0 Fld(1, 9) //[9:9] + #define B0_RXDVS0_R_DMRXDVS_PBYTESTUCK_RST_B0 Fld(1, 10) //[10:10] + #define B0_RXDVS0_R_DMRXDVS_PBYTESTUCK_IG_B0 Fld(1, 11) //[11:11] + #define B0_RXDVS0_R_DMRXDVS_DQIENPOST_OPT_B0 Fld(2, 12) //[13:12] + #define B0_RXDVS0_R_RX_DLY_RANK_ERR_ST_CLR_B0 Fld(3, 16) //[18:16] + #define B0_RXDVS0_R_DMRXDVS_CNTCMP_OPT_B0 Fld(1, 19) //[19:19] + #define B0_RXDVS0_R_RX_DLY_RK_OPT_B0 Fld(2, 20) //[21:20] + #define B0_RXDVS0_R_HWRESTORE_ENA_B0 Fld(1, 22) //[22:22] + #define B0_RXDVS0_R_HWSAVE_MODE_ENA_B0 Fld(1, 24) //[24:24] + #define B0_RXDVS0_R_RX_DLY_DVS_MODE_SYNC_DIS_B0 Fld(1, 26) //[26:26] + #define B0_RXDVS0_R_RX_DLY_TRACK_BYPASS_MODESYNC_B0 Fld(1, 27) //[27:27] + #define B0_RXDVS0_R_RX_DLY_TRACK_CG_EN_B0 Fld(1, 28) //[28:28] + #define B0_RXDVS0_R_RX_DLY_TRACK_SPM_CTRL_B0 Fld(1, 29) //[29:29] + #define B0_RXDVS0_R_RX_DLY_TRACK_CLR_B0 Fld(1, 30) //[30:30] + #define B0_RXDVS0_R_RX_DLY_TRACK_ENA_B0 Fld(1, 31) //[31:31] + +#define DDRPHY_REG_B0_RXDVS1 (DDRPHY_AO_BASE_ADDRESS + 0x0168) + #define B0_RXDVS1_B0_RXDVS1_RFU Fld(15, 0) //[14:0] + #define B0_RXDVS1_F_LEADLAG_TRACK_B0 Fld(1, 15) //[15:15] + #define B0_RXDVS1_R_DMRXDVS_UPD_CLR_ACK_B0 Fld(1, 16) //[16:16] + #define B0_RXDVS1_R_DMRXDVS_UPD_CLR_NORD_B0 Fld(1, 17) //[17:17] + +#define DDRPHY_REG_B0_DLL_ARPI0 (DDRPHY_AO_BASE_ADDRESS + 0x016C) + #define B0_DLL_ARPI0_RG_ARMCTLPLL_CK_SEL_B0 Fld(1, 1) //[1:1] + #define B0_DLL_ARPI0_RG_ARPI_RESETB_B0 Fld(1, 3) //[3:3] + #define B0_DLL_ARPI0_RG_ARPI_LS_EN_B0 Fld(1, 4) //[4:4] + #define B0_DLL_ARPI0_RG_ARPI_LS_SEL_B0 Fld(1, 5) //[5:5] + #define B0_DLL_ARPI0_RG_ARPI_MCK8X_SEL_B0 Fld(1, 6) //[6:6] + +#define DDRPHY_REG_B0_DLL_ARPI1 (DDRPHY_AO_BASE_ADDRESS + 0x0170) + #define B0_DLL_ARPI1_RG_ARPI_DQSIEN_JUMP_EN_B0 Fld(1, 11) //[11:11] + #define B0_DLL_ARPI1_RG_ARPI_DQ_JUMP_EN_B0 Fld(1, 13) //[13:13] + #define B0_DLL_ARPI1_RG_ARPI_DQM_JUMP_EN_B0 Fld(1, 14) //[14:14] + #define B0_DLL_ARPI1_RG_ARPI_DQS_JUMP_EN_B0 Fld(1, 15) //[15:15] + #define B0_DLL_ARPI1_RG_ARPI_FB_JUMP_EN_B0 Fld(1, 17) //[17:17] + #define B0_DLL_ARPI1_RG_ARPI_MCTL_JUMP_EN_B0 Fld(1, 19) //[19:19] + #define B0_DLL_ARPI1_RG_ARPISM_MCK_SEL_B0_REG_OPT Fld(1, 20) //[20:20] + #define B0_DLL_ARPI1_RG_ARPISM_MCK_SEL_B0 Fld(1, 21) //[21:21] + #define B0_DLL_ARPI1_RG_ARPI_SET_UPDN_B0 Fld(3, 28) //[30:28] + +#define DDRPHY_REG_B0_DLL_ARPI4 (DDRPHY_AO_BASE_ADDRESS + 0x0174) + #define B0_DLL_ARPI4_RG_ARPI_BYPASS_SR_DQ_B0 Fld(1, 8) //[8:8] + #define B0_DLL_ARPI4_RG_ARPI_BYPASS_SR_DQS_B0 Fld(1, 9) //[9:9] + #define B0_DLL_ARPI4_RG_ARPI_BYPASS_DQSIEN_B0 Fld(1, 11) //[11:11] + #define B0_DLL_ARPI4_RG_ARPI_BYPASS_DQ_B0 Fld(1, 13) //[13:13] + #define B0_DLL_ARPI4_RG_ARPI_BYPASS_DQM_B0 Fld(1, 14) //[14:14] + #define B0_DLL_ARPI4_RG_ARPI_BYPASS_DQS_B0 Fld(1, 15) //[15:15] + #define B0_DLL_ARPI4_RG_ARPI_BYPASS_FB_B0 Fld(1, 17) //[17:17] + #define B0_DLL_ARPI4_RG_ARPI_BYPASS_MCTL_B0 Fld(1, 19) //[19:19] + +#define DDRPHY_REG_B0_DLL_ARPI5 (DDRPHY_AO_BASE_ADDRESS + 0x0178) + #define B0_DLL_ARPI5_RG_ARDLL_MON_SEL_B0 Fld(4, 4) //[7:4] + #define B0_DLL_ARPI5_RG_ARDLL_DIV_DEC_B0 Fld(1, 8) //[8:8] + #define B0_DLL_ARPI5_RG_ARDLL_FJ_OUT_MODE_SEL_B0 Fld(1, 25) //[25:25] + #define B0_DLL_ARPI5_RG_ARDLL_FJ_OUT_MODE_B0 Fld(1, 26) //[26:26] + #define B0_DLL_ARPI5_RG_ARDLL_IDLE_EN_B0 Fld(1, 28) //[28:28] + #define B0_DLL_ARPI5_RG_ARDLL_PD_ZONE_B0 Fld(3, 29) //[31:29] + +#define DDRPHY_REG_B0_DQ2 (DDRPHY_AO_BASE_ADDRESS + 0x017C) + #define B0_DQ2_RG_TX_ARDQS0_ODTEN_DIS_B0 Fld(1, 0) //[0:0] + #define B0_DQ2_RG_TX_ARDQS0_OE_DIS_B0 Fld(1, 1) //[1:1] + #define B0_DQ2_RG_TX_ARDQS_OE_TIE_SEL_B0 Fld(1, 2) //[2:2] + #define B0_DQ2_RG_TX_ARDQS_OE_TIE_EN_B0 Fld(1, 3) //[3:3] + #define B0_DQ2_RG_TX_ARWCK_OE_TIE_SEL_B0 Fld(1, 8) //[8:8] + #define B0_DQ2_RG_TX_ARWCK_OE_TIE_EN_B0 Fld(1, 9) //[9:9] + #define B0_DQ2_RG_TX_ARWCKB_OE_TIE_SEL_B0 Fld(1, 10) //[10:10] + #define B0_DQ2_RG_TX_ARWCKB_OE_TIE_EN_B0 Fld(1, 11) //[11:11] + #define B0_DQ2_RG_TX_ARDQM0_ODTEN_DIS_B0 Fld(1, 12) //[12:12] + #define B0_DQ2_RG_TX_ARDQM0_OE_DIS_B0 Fld(1, 13) //[13:13] + #define B0_DQ2_RG_TX_ARDQM_OE_TIE_SEL_B0 Fld(1, 14) //[14:14] + #define B0_DQ2_RG_TX_ARDQM_OE_TIE_EN_B0 Fld(1, 15) //[15:15] + #define B0_DQ2_RG_TX_ARDQ_ODTEN_DIS_B0 Fld(1, 20) //[20:20] + #define B0_DQ2_RG_TX_ARDQ_OE_DIS_B0 Fld(1, 21) //[21:21] + #define B0_DQ2_RG_TX_ARDQ_OE_TIE_SEL_B0 Fld(1, 22) //[22:22] + #define B0_DQ2_RG_TX_ARDQ_OE_TIE_EN_B0 Fld(8, 24) //[31:24] + +#define DDRPHY_REG_B0_DQ3 (DDRPHY_AO_BASE_ADDRESS + 0x0180) + #define B0_DQ3_RG_ARDQ_ATPG_EN_B0 Fld(1, 0) //[0:0] + #define B0_DQ3_RG_RX_ARDQ_SMT_EN_B0 Fld(1, 1) //[1:1] + #define B0_DQ3_RG_TX_ARDQ_EN_B0 Fld(1, 2) //[2:2] + #define B0_DQ3_RG_ARDQ_RESETB_B0 Fld(1, 3) //[3:3] + #define B0_DQ3_RG_RX_ARDQS0_IN_BUFF_EN_B0 Fld(1, 5) //[5:5] + #define B0_DQ3_RG_RX_ARDQM0_IN_BUFF_EN_B0 Fld(1, 6) //[6:6] + #define B0_DQ3_RG_RX_ARDQ_IN_BUFF_EN_B0 Fld(1, 7) //[7:7] + #define B0_DQ3_RG_RX_ARDQ_STBENCMP_EN_B0 Fld(1, 10) //[10:10] + #define B0_DQ3_RG_RX_ARDQ_OFFC_EN_B0 Fld(1, 11) //[11:11] + #define B0_DQ3_RG_RX_ARDQS0_SWAP_EN_B0 Fld(1, 15) //[15:15] + #define B0_DQ3_RG_ARPI_ASYNC_EN_B0 Fld(1, 23) //[23:23] + #define B0_DQ3_RG_ARPI_LAT_EN_B0 Fld(1, 24) //[24:24] + #define B0_DQ3_RG_ARPI_MCK_FB_SEL_B0 Fld(2, 26) //[27:26] + +#define DDRPHY_REG_B0_DQ4 (DDRPHY_AO_BASE_ADDRESS + 0x0184) + #define B0_DQ4_RG_RX_ARDQS_EYE_R_DLY_B0 Fld(7, 0) //[6:0] + #define B0_DQ4_RG_RX_ARDQS_EYE_F_DLY_B0 Fld(7, 8) //[14:8] + #define B0_DQ4_RG_RX_ARDQ_EYE_R_DLY_B0 Fld(6, 16) //[21:16] + #define B0_DQ4_RG_RX_ARDQ_EYE_F_DLY_B0 Fld(6, 24) //[29:24] + +#define DDRPHY_REG_B0_DQ5 (DDRPHY_AO_BASE_ADDRESS + 0x0188) + #define B0_DQ5_RG_RX_ARDQ_EYE_VREF_SEL_B0 Fld(6, 8) //[13:8] + #define B0_DQ5_RG_RX_ARDQ_VREF_EN_B0 Fld(1, 16) //[16:16] + #define B0_DQ5_RG_RX_ARDQ_EYE_VREF_EN_B0 Fld(1, 17) //[17:17] + #define B0_DQ5_RG_RX_ARDQ_EYE_SEL_B0 Fld(4, 20) //[23:20] + #define B0_DQ5_RG_RX_ARDQ_EYE_EN_B0 Fld(1, 24) //[24:24] + #define B0_DQ5_RG_RX_ARDQ_EYE_STBEN_RESETB_B0 Fld(1, 25) //[25:25] + #define B0_DQ5_RG_RX_ARDQS0_DVS_EN_B0 Fld(1, 31) //[31:31] + +#define DDRPHY_REG_B0_DQ6 (DDRPHY_AO_BASE_ADDRESS + 0x018C) + #define B0_DQ6_RG_RX_ARDQ_BIAS_PS_B0 Fld(2, 0) //[1:0] + #define B0_DQ6_RG_TX_ARDQ_OE_EXT_DIS_B0 Fld(1, 2) //[2:2] + #define B0_DQ6_RG_TX_ARDQ_ODTEN_EXT_DIS_B0 Fld(1, 3) //[3:3] + #define B0_DQ6_RG_RX_ARDQ_RPRE_TOG_EN_B0 Fld(1, 5) //[5:5] + #define B0_DQ6_RG_RX_ARDQ_RES_BIAS_EN_B0 Fld(1, 6) //[6:6] + #define B0_DQ6_RG_RX_ARDQ_OP_BIAS_SW_EN_B0 Fld(1, 7) //[7:7] + #define B0_DQ6_RG_RX_ARDQ_LPBK_EN_B0 Fld(1, 8) //[8:8] + #define B0_DQ6_RG_RX_ARDQ_O1_SEL_B0 Fld(1, 9) //[9:9] + #define B0_DQ6_RG_RX_ARDQ_JM_SEL_B0 Fld(1, 11) //[11:11] + #define B0_DQ6_RG_RX_ARDQ_BIAS_EN_B0 Fld(1, 12) //[12:12] + #define B0_DQ6_RG_RX_ARDQ_BIAS_VREF_SEL_B0 Fld(2, 14) //[15:14] + #define B0_DQ6_RG_RX_ARDQ_DDR4_SEL_B0 Fld(1, 16) //[16:16] + #define B0_DQ6_RG_TX_ARDQ_DDR4_SEL_B0 Fld(1, 17) //[17:17] + #define B0_DQ6_RG_RX_ARDQ_DDR3_SEL_B0 Fld(1, 18) //[18:18] + #define B0_DQ6_RG_TX_ARDQ_DDR3_SEL_B0 Fld(1, 19) //[19:19] + #define B0_DQ6_RG_TX_ARDQ_LP5_SEL_B0 Fld(1, 20) //[20:20] + #define B0_DQ6_RG_TX_ARDQ_LP4_SEL_B0 Fld(1, 21) //[21:21] + #define B0_DQ6_RG_TX_ARDQ_CAP_EN_B0 Fld(1, 24) //[24:24] + #define B0_DQ6_RG_TX_ARDQ_DATA_SWAP_EN_B0 Fld(1, 25) //[25:25] + #define B0_DQ6_RG_TX_ARDQ_DATA_SWAP_B0 Fld(2, 26) //[27:26] + #define B0_DQ6_RG_RX_ARDQ_EYE_DLY_DQS_BYPASS_B0 Fld(1, 28) //[28:28] + #define B0_DQ6_RG_RX_ARDQ_EYE_OE_GATE_EN_B0 Fld(1, 29) //[29:29] + #define B0_DQ6_RG_RX_ARDQ_DMRANK_OUTSEL_B0 Fld(1, 31) //[31:31] + +#define DDRPHY_REG_B0_DQ7 (DDRPHY_AO_BASE_ADDRESS + 0x0190) + #define B0_DQ7_RG_TX_ARDQS0B_PULL_DN_B0 Fld(1, 0) //[0:0] + #define B0_DQ7_RG_TX_ARDQS0B_PULL_UP_B0 Fld(1, 1) //[1:1] + #define B0_DQ7_RG_TX_ARDQS0_PULL_DN_B0 Fld(1, 2) //[2:2] + #define B0_DQ7_RG_TX_ARDQS0_PULL_UP_B0 Fld(1, 3) //[3:3] + #define B0_DQ7_RG_TX_ARDQM0_PULL_DN_B0 Fld(1, 4) //[4:4] + #define B0_DQ7_RG_TX_ARDQM0_PULL_UP_B0 Fld(1, 5) //[5:5] + #define B0_DQ7_RG_TX_ARDQ_PULL_DN_B0 Fld(1, 6) //[6:6] + #define B0_DQ7_RG_TX_ARDQ_PULL_UP_B0 Fld(1, 7) //[7:7] + #define B0_DQ7_RG_TX_ARWCKB_PULL_DN_B0 Fld(1, 8) //[8:8] + #define B0_DQ7_RG_TX_ARWCKB_PULL_UP_B0 Fld(1, 9) //[9:9] + #define B0_DQ7_RG_TX_ARWCK_PULL_DN_B0 Fld(1, 10) //[10:10] + #define B0_DQ7_RG_TX_ARWCK_PULL_UP_B0 Fld(1, 11) //[11:11] + #define B0_DQ7_RG_TX_ARDQS0B_PULL_DN_B0_LP4Y Fld(1, 16) //[16:16] + +#define DDRPHY_REG_B0_DQ8 (DDRPHY_AO_BASE_ADDRESS + 0x0194) + #define B0_DQ8_RG_TX_ARDQ_EN_LP4P_B0 Fld(1, 0) //[0:0] + #define B0_DQ8_RG_TX_ARDQ_EN_CAP_LP4P_B0 Fld(1, 1) //[1:1] + #define B0_DQ8_RG_TX_ARDQ_CAP_DET_B0 Fld(1, 2) //[2:2] + #define B0_DQ8_RG_TX_ARDQ_CKE_MCK4X_SEL_B0 Fld(2, 3) //[4:3] + #define B0_DQ8_RG_RX_ARDQS_BURST_E1_EN_B0 Fld(1, 8) //[8:8] + #define B0_DQ8_RG_RX_ARDQS_BURST_E2_EN_B0 Fld(1, 9) //[9:9] + #define B0_DQ8_RG_RX_ARDQS_GATE_EN_MODE_B0 Fld(1, 12) //[12:12] + #define B0_DQ8_RG_RX_ARDQS_SER_RST_MODE_B0 Fld(1, 13) //[13:13] + #define B0_DQ8_RG_ARDLL_RESETB_B0 Fld(1, 15) //[15:15] + +#define DDRPHY_REG_B0_DQ9 (DDRPHY_AO_BASE_ADDRESS + 0x0198) + #define B0_DQ9_RG_RX_ARDQ_STBEN_RESETB_B0 Fld(1, 0) //[0:0] + #define B0_DQ9_RG_RX_ARDQS0_STBEN_RESETB_B0 Fld(1, 4) //[4:4] + #define B0_DQ9_RG_RX_ARDQS0_DQSIENMODE_B0 Fld(1, 5) //[5:5] + #define B0_DQ9_R_DMRXDVS_R_F_DLY_RK_OPT_B0 Fld(1, 6) //[6:6] + #define B0_DQ9_R_DMRXFIFO_STBENCMP_EN_B0 Fld(1, 7) //[7:7] + #define B0_DQ9_R_IN_GATE_EN_LOW_OPT_B0 Fld(8, 8) //[15:8] + #define B0_DQ9_R_DMDQSIEN_VALID_LAT_B0 Fld(3, 16) //[18:16] + #define B0_DQ9_R_DMDQSIEN_RDSEL_LAT_B0 Fld(3, 20) //[22:20] + #define B0_DQ9_R_DMRXDVS_VALID_LAT_B0 Fld(3, 24) //[26:24] + #define B0_DQ9_R_DMRXDVS_RDSEL_LAT_B0 Fld(3, 28) //[30:28] + +#define DDRPHY_REG_B0_DQ10 (DDRPHY_AO_BASE_ADDRESS + 0x019C) + #define B0_DQ10_ARPI_CG_RK1_SRC_SEL_B0 Fld(1, 0) //[0:0] + +#define DDRPHY_REG_B0_DQ11 (DDRPHY_AO_BASE_ADDRESS + 0x01A0) + #define B0_DQ11_DMY_DQ11_B0 Fld(1, 0) //[0:0] + +#define DDRPHY_REG_B0_PHY2 (DDRPHY_AO_BASE_ADDRESS + 0x01A4) + #define B0_PHY2_RG_RX_ARDQS_SE_SWAP_EN_B0 Fld(1, 0) //[0:0] + #define B0_PHY2_RG_RX_ARDQS_JM_SEL_B0 Fld(4, 4) //[7:4] + #define B0_PHY2_RG_RX_ARDQS_JM_EN_B0 Fld(1, 8) //[8:8] + #define B0_PHY2_RG_RX_ARDQS_JM_DLY_B0 Fld(9, 16) //[24:16] + #define B0_PHY2_RG_RX_ARDQS_DQSIEN_UI_LEAD_LAG_EN_B0 Fld(1, 28) //[28:28] + #define B0_PHY2_RG_RX_ARDQS_DQSIEN_TIE_GATE_EN_B0 Fld(1, 29) //[29:29] + #define B0_PHY2_RG_RX_ARDQSB_SE_SWAP_EN_B0 Fld(1, 30) //[30:30] + +#define DDRPHY_REG_B0_PHY3 (DDRPHY_AO_BASE_ADDRESS + 0x01A8) + #define B0_PHY3_RG_RX_ARDQ_DUTY_VCAL_VREF_SEL_B0 Fld(7, 8) //[14:8] + #define B0_PHY3_RG_RX_ARDQ_DUTY_VCAL_OFFSETC_B0 Fld(4, 16) //[19:16] + #define B0_PHY3_RG_RX_ARDQ_DUTY_VCAL_EN_B0 Fld(1, 20) //[20:20] + #define B0_PHY3_RG_RX_ARDQ_DUTY_VCAL_CLK_SEL_B0 Fld(2, 24) //[25:24] + #define B0_PHY3_RG_RX_ARDQ_DUTY_VCAL_CLK_RC_SEL_B0 Fld(2, 26) //[27:26] + #define B0_PHY3_RG_RX_ARDQ_BUFF_EN_SEL_B0 Fld(1, 28) //[28:28] + +#define DDRPHY_REG_B0_TX_MCK (DDRPHY_AO_BASE_ADDRESS + 0x01AC) + #define B0_TX_MCK_DMY_TX_MCK_B0 Fld(1, 0) //[0:0] + +#define DDRPHY_REG_RK_B1_RXDVS0 (DDRPHY_AO_BASE_ADDRESS + 0x01E0) + #define RK_B1_RXDVS0_R_RK0_B1_DVS_LEAD_LAG_CNT_CLR Fld(1, 26) //[26:26] + #define RK_B1_RXDVS0_R_RK0_B1_DVS_SW_CNT_CLR Fld(1, 27) //[27:27] + #define RK_B1_RXDVS0_R_RK0_B1_DVS_SW_CNT_ENA Fld(1, 31) //[31:31] + +#define DDRPHY_REG_RK_B1_RXDVS1 (DDRPHY_AO_BASE_ADDRESS + 0x01E4) + #define RK_B1_RXDVS1_R_RK0_B1_DVS_TH_LAG Fld(16, 0) //[15:0] + #define RK_B1_RXDVS1_R_RK0_B1_DVS_TH_LEAD Fld(16, 16) //[31:16] + +#define DDRPHY_REG_RK_B1_RXDVS2 (DDRPHY_AO_BASE_ADDRESS + 0x01E8) + #define RK_B1_RXDVS2_R_RK0_RX_DLY_FAL_DQS_SCALE_B1 Fld(2, 16) //[17:16] + #define RK_B1_RXDVS2_R_RK0_RX_DLY_FAL_DQ_SCALE_B1 Fld(2, 18) //[19:18] + #define RK_B1_RXDVS2_R_RK0_RX_DLY_FAL_TRACK_GATE_ENA_B1 Fld(1, 23) //[23:23] + #define RK_B1_RXDVS2_R_RK0_RX_DLY_RIS_DQS_SCALE_B1 Fld(2, 24) //[25:24] + #define RK_B1_RXDVS2_R_RK0_RX_DLY_RIS_DQ_SCALE_B1 Fld(2, 26) //[27:26] + #define RK_B1_RXDVS2_R_RK0_RX_DLY_RIS_TRACK_GATE_ENA_B1 Fld(1, 28) //[28:28] + #define RK_B1_RXDVS2_R_RK0_DVS_FDLY_MODE_B1 Fld(1, 29) //[29:29] + #define RK_B1_RXDVS2_R_RK0_DVS_MODE_B1 Fld(2, 30) //[31:30] + +#define DDRPHY_REG_RK_B1_RXDVS3 (DDRPHY_AO_BASE_ADDRESS + 0x01EC) + #define RK_B1_RXDVS3_RG_RK0_ARDQ_MIN_DLY_B1 Fld(8, 0) //[7:0] + #define RK_B1_RXDVS3_RG_RK0_ARDQ_MAX_DLY_B1 Fld(8, 8) //[15:8] + +#define DDRPHY_REG_RK_B1_RXDVS4 (DDRPHY_AO_BASE_ADDRESS + 0x01F0) + #define RK_B1_RXDVS4_RG_RK0_ARDQS0_MIN_DLY_B1 Fld(9, 0) //[8:0] + #define RK_B1_RXDVS4_RG_RK0_ARDQS0_MAX_DLY_B1 Fld(9, 16) //[24:16] + +#define DDRPHY_REG_B1_LP_CTRL0 (DDRPHY_AO_BASE_ADDRESS + 0x02E0) + #define B1_LP_CTRL0_RG_ARDMSUS_10_B1 Fld(1, 0) //[0:0] + #define B1_LP_CTRL0_RESERVED_B1_LP_CTRL0_3_1 Fld(3, 1) //[3:1] + #define B1_LP_CTRL0_RG_ARDMSUS_10_B1_LP_SEL Fld(1, 4) //[4:4] + #define B1_LP_CTRL0_RG_DA_PICG_B1_CTRL_LOW_BY_LPC Fld(1, 5) //[5:5] + #define B1_LP_CTRL0_RESERVED_B1_LP_CTRL0_6_6 Fld(1, 6) //[6:6] + #define B1_LP_CTRL0_RG_TX_ARDQ_RESETB_B1_LP_SEL Fld(1, 7) //[7:7] + #define B1_LP_CTRL0_RG_ARDQ_RESETB_B1_LP_SEL Fld(1, 8) //[8:8] + #define B1_LP_CTRL0_RG_ARPI_RESETB_B1_LP_SEL Fld(1, 9) //[9:9] + #define B1_LP_CTRL0_RESERVED_B1_LP_CTRL0_11_10 Fld(2, 10) //[11:10] + #define B1_LP_CTRL0_RG_B1_MS_SLV_LP_SEL Fld(1, 12) //[12:12] + #define B1_LP_CTRL0_RG_ARDLL_PHDET_EN_B1_LP_SEL Fld(1, 13) //[13:13] + #define B1_LP_CTRL0_RG_B1_DLL_EN_OP_SEQ_LP_SEL Fld(1, 14) //[14:14] + #define B1_LP_CTRL0_RESERVED_B1_LP_CTRL0_15 Fld(1, 15) //[15:15] + #define B1_LP_CTRL0_RG_RX_ARDQ_BIAS_EN_B1_LP_SEL Fld(1, 16) //[16:16] + #define B1_LP_CTRL0_DA_ARPI_CG_MCK_B1_LP_SEL Fld(1, 17) //[17:17] + #define B1_LP_CTRL0_DA_ARPI_CG_MCK_FB2DLL_B1_LP_SEL Fld(1, 18) //[18:18] + #define B1_LP_CTRL0_DA_ARPI_CG_MCTL_B1_LP_SEL Fld(1, 19) //[19:19] + #define B1_LP_CTRL0_DA_ARPI_CG_FB_B1_LP_SEL Fld(1, 20) //[20:20] + #define B1_LP_CTRL0_DA_ARPI_CG_DQ_B1_LP_SEL Fld(1, 21) //[21:21] + #define B1_LP_CTRL0_DA_ARPI_CG_DQM_B1_LP_SEL Fld(1, 22) //[22:22] + #define B1_LP_CTRL0_DA_ARPI_CG_DQS_B1_LP_SEL Fld(1, 23) //[23:23] + #define B1_LP_CTRL0_DA_ARPI_CG_DQSIEN_B1_LP_SEL Fld(1, 24) //[24:24] + #define B1_LP_CTRL0_DA_ARPI_MPDIV_CG_B1_LP_SEL Fld(1, 25) //[25:25] + #define B1_LP_CTRL0_RG_RX_ARDQ_VREF_EN_B1_LP_SEL Fld(1, 26) //[26:26] + #define B1_LP_CTRL0_DA_ARPI_MIDPI_EN_B1_LP_SEL Fld(1, 27) //[27:27] + #define B1_LP_CTRL0_DA_ARPI_MIDPI_CKDIV4_EN_B1_LP_SEL Fld(1, 28) //[28:28] + #define B1_LP_CTRL0_RG_ARPI_DDR400_EN_B1_LP_SEL Fld(1, 29) //[29:29] + #define B1_LP_CTRL0_RG_MIDPI_EN_B1_OP_LP_SEL Fld(1, 30) //[30:30] + #define B1_LP_CTRL0_RG_MIDPI_CKDIV4_EN_B1_OP_LP_SEL Fld(1, 31) //[31:31] + +#define DDRPHY_REG_B1_RXDVS0 (DDRPHY_AO_BASE_ADDRESS + 0x02E4) + #define B1_RXDVS0_R_RX_RANKINSEL_B1 Fld(1, 0) //[0:0] + #define B1_RXDVS0_B1_RXDVS0_RFU Fld(3, 1) //[3:1] + #define B1_RXDVS0_R_RX_RANKINCTL_B1 Fld(4, 4) //[7:4] + #define B1_RXDVS0_R_DVS_SW_UP_B1 Fld(1, 8) //[8:8] + #define B1_RXDVS0_R_DMRXDVS_DQIENPRE_OPT_B1 Fld(1, 9) //[9:9] + #define B1_RXDVS0_R_DMRXDVS_PBYTESTUCK_RST_B1 Fld(1, 10) //[10:10] + #define B1_RXDVS0_R_DMRXDVS_PBYTESTUCK_IG_B1 Fld(1, 11) //[11:11] + #define B1_RXDVS0_R_DMRXDVS_DQIENPOST_OPT_B1 Fld(2, 12) //[13:12] + #define B1_RXDVS0_R_RX_DLY_RANK_ERR_ST_CLR_B1 Fld(3, 16) //[18:16] + #define B1_RXDVS0_R_DMRXDVS_CNTCMP_OPT_B1 Fld(1, 19) //[19:19] + #define B1_RXDVS0_R_RX_DLY_RK_OPT_B1 Fld(2, 20) //[21:20] + #define B1_RXDVS0_R_HWRESTORE_ENA_B1 Fld(1, 22) //[22:22] + #define B1_RXDVS0_R_HWSAVE_MODE_ENA_B1 Fld(1, 24) //[24:24] + #define B1_RXDVS0_R_RX_DLY_DVS_MODE_SYNC_DIS_B1 Fld(1, 26) //[26:26] + #define B1_RXDVS0_R_RX_DLY_TRACK_BYPASS_MODESYNC_B1 Fld(1, 27) //[27:27] + #define B1_RXDVS0_R_RX_DLY_TRACK_CG_EN_B1 Fld(1, 28) //[28:28] + #define B1_RXDVS0_R_RX_DLY_TRACK_SPM_CTRL_B1 Fld(1, 29) //[29:29] + #define B1_RXDVS0_R_RX_DLY_TRACK_CLR_B1 Fld(1, 30) //[30:30] + #define B1_RXDVS0_R_RX_DLY_TRACK_ENA_B1 Fld(1, 31) //[31:31] + +#define DDRPHY_REG_B1_RXDVS1 (DDRPHY_AO_BASE_ADDRESS + 0x02E8) + #define B1_RXDVS1_B1_RXDVS1_RFU Fld(15, 0) //[14:0] + #define B1_RXDVS1_F_LEADLAG_TRACK_B1 Fld(1, 15) //[15:15] + #define B1_RXDVS1_R_DMRXDVS_UPD_CLR_ACK_B1 Fld(1, 16) //[16:16] + #define B1_RXDVS1_R_DMRXDVS_UPD_CLR_NORD_B1 Fld(1, 17) //[17:17] + +#define DDRPHY_REG_B1_DLL_ARPI0 (DDRPHY_AO_BASE_ADDRESS + 0x02EC) + #define B1_DLL_ARPI0_RG_ARMCTLPLL_CK_SEL_B1 Fld(1, 1) //[1:1] + #define B1_DLL_ARPI0_RG_ARPI_RESETB_B1 Fld(1, 3) //[3:3] + #define B1_DLL_ARPI0_RG_ARPI_LS_EN_B1 Fld(1, 4) //[4:4] + #define B1_DLL_ARPI0_RG_ARPI_LS_SEL_B1 Fld(1, 5) //[5:5] + #define B1_DLL_ARPI0_RG_ARPI_MCK8X_SEL_B1 Fld(1, 6) //[6:6] + +#define DDRPHY_REG_B1_DLL_ARPI1 (DDRPHY_AO_BASE_ADDRESS + 0x02F0) + #define B1_DLL_ARPI1_RG_ARPI_DQSIEN_JUMP_EN_B1 Fld(1, 11) //[11:11] + #define B1_DLL_ARPI1_RG_ARPI_DQ_JUMP_EN_B1 Fld(1, 13) //[13:13] + #define B1_DLL_ARPI1_RG_ARPI_DQM_JUMP_EN_B1 Fld(1, 14) //[14:14] + #define B1_DLL_ARPI1_RG_ARPI_DQS_JUMP_EN_B1 Fld(1, 15) //[15:15] + #define B1_DLL_ARPI1_RG_ARPI_FB_JUMP_EN_B1 Fld(1, 17) //[17:17] + #define B1_DLL_ARPI1_RG_ARPI_MCTL_JUMP_EN_B1 Fld(1, 19) //[19:19] + #define B1_DLL_ARPI1_RG_ARPISM_MCK_SEL_B1_REG_OPT Fld(1, 20) //[20:20] + #define B1_DLL_ARPI1_RG_ARPISM_MCK_SEL_B1 Fld(1, 21) //[21:21] + #define B1_DLL_ARPI1_RG_ARPI_SET_UPDN_B1 Fld(3, 28) //[30:28] + +#define DDRPHY_REG_B1_DLL_ARPI4 (DDRPHY_AO_BASE_ADDRESS + 0x02F4) + #define B1_DLL_ARPI4_RG_ARPI_BYPASS_SR_DQ_B1 Fld(1, 8) //[8:8] + #define B1_DLL_ARPI4_RG_ARPI_BYPASS_SR_DQS_B1 Fld(1, 9) //[9:9] + #define B1_DLL_ARPI4_RG_ARPI_BYPASS_DQSIEN_B1 Fld(1, 11) //[11:11] + #define B1_DLL_ARPI4_RG_ARPI_BYPASS_DQ_B1 Fld(1, 13) //[13:13] + #define B1_DLL_ARPI4_RG_ARPI_BYPASS_DQM_B1 Fld(1, 14) //[14:14] + #define B1_DLL_ARPI4_RG_ARPI_BYPASS_DQS_B1 Fld(1, 15) //[15:15] + #define B1_DLL_ARPI4_RG_ARPI_BYPASS_FB_B1 Fld(1, 17) //[17:17] + #define B1_DLL_ARPI4_RG_ARPI_BYPASS_MCTL_B1 Fld(1, 19) //[19:19] + +#define DDRPHY_REG_B1_DLL_ARPI5 (DDRPHY_AO_BASE_ADDRESS + 0x02F8) + #define B1_DLL_ARPI5_RG_ARDLL_MON_SEL_B1 Fld(4, 4) //[7:4] + #define B1_DLL_ARPI5_RG_ARDLL_DIV_DEC_B1 Fld(1, 8) //[8:8] + #define B1_DLL_ARPI5_RG_ARDLL_FJ_OUT_MODE_SEL_B1 Fld(1, 25) //[25:25] + #define B1_DLL_ARPI5_RG_ARDLL_FJ_OUT_MODE_B1 Fld(1, 26) //[26:26] + #define B1_DLL_ARPI5_RG_ARDLL_IDLE_EN_B1 Fld(1, 28) //[28:28] + #define B1_DLL_ARPI5_RG_ARDLL_PD_ZONE_B1 Fld(3, 29) //[31:29] + +#define DDRPHY_REG_B1_DQ2 (DDRPHY_AO_BASE_ADDRESS + 0x02FC) + #define B1_DQ2_RG_TX_ARDQS0_ODTEN_DIS_B1 Fld(1, 0) //[0:0] + #define B1_DQ2_RG_TX_ARDQS0_OE_DIS_B1 Fld(1, 1) //[1:1] + #define B1_DQ2_RG_TX_ARDQS_OE_TIE_SEL_B1 Fld(1, 2) //[2:2] + #define B1_DQ2_RG_TX_ARDQS_OE_TIE_EN_B1 Fld(1, 3) //[3:3] + #define B1_DQ2_RG_TX_ARWCK_OE_TIE_SEL_B1 Fld(1, 8) //[8:8] + #define B1_DQ2_RG_TX_ARWCK_OE_TIE_EN_B1 Fld(1, 9) //[9:9] + #define B1_DQ2_RG_TX_ARWCKB_OE_TIE_SEL_B1 Fld(1, 10) //[10:10] + #define B1_DQ2_RG_TX_ARWCKB_OE_TIE_EN_B1 Fld(1, 11) //[11:11] + #define B1_DQ2_RG_TX_ARDQM0_ODTEN_DIS_B1 Fld(1, 12) //[12:12] + #define B1_DQ2_RG_TX_ARDQM0_OE_DIS_B1 Fld(1, 13) //[13:13] + #define B1_DQ2_RG_TX_ARDQM_OE_TIE_SEL_B1 Fld(1, 14) //[14:14] + #define B1_DQ2_RG_TX_ARDQM_OE_TIE_EN_B1 Fld(1, 15) //[15:15] + #define B1_DQ2_RG_TX_ARDQ_ODTEN_DIS_B1 Fld(1, 20) //[20:20] + #define B1_DQ2_RG_TX_ARDQ_OE_DIS_B1 Fld(1, 21) //[21:21] + #define B1_DQ2_RG_TX_ARDQ_OE_TIE_SEL_B1 Fld(1, 22) //[22:22] + #define B1_DQ2_RG_TX_ARDQ_OE_TIE_EN_B1 Fld(8, 24) //[31:24] + +#define DDRPHY_REG_B1_DQ3 (DDRPHY_AO_BASE_ADDRESS + 0x0300) + #define B1_DQ3_RG_ARDQ_ATPG_EN_B1 Fld(1, 0) //[0:0] + #define B1_DQ3_RG_RX_ARDQ_SMT_EN_B1 Fld(1, 1) //[1:1] + #define B1_DQ3_RG_TX_ARDQ_EN_B1 Fld(1, 2) //[2:2] + #define B1_DQ3_RG_ARDQ_RESETB_B1 Fld(1, 3) //[3:3] + #define B1_DQ3_RG_RX_ARDQS0_IN_BUFF_EN_B1 Fld(1, 5) //[5:5] + #define B1_DQ3_RG_RX_ARDQM0_IN_BUFF_EN_B1 Fld(1, 6) //[6:6] + #define B1_DQ3_RG_RX_ARDQ_IN_BUFF_EN_B1 Fld(1, 7) //[7:7] + #define B1_DQ3_RG_RX_ARDQ_STBENCMP_EN_B1 Fld(1, 10) //[10:10] + #define B1_DQ3_RG_RX_ARDQ_OFFC_EN_B1 Fld(1, 11) //[11:11] + #define B1_DQ3_RG_RX_ARDQS0_SWAP_EN_B1 Fld(1, 15) //[15:15] + #define B1_DQ3_RG_ARPI_ASYNC_EN_B1 Fld(1, 23) //[23:23] + #define B1_DQ3_RG_ARPI_LAT_EN_B1 Fld(1, 24) //[24:24] + #define B1_DQ3_RG_ARPI_MCK_FB_SEL_B1 Fld(2, 26) //[27:26] + +#define DDRPHY_REG_B1_DQ4 (DDRPHY_AO_BASE_ADDRESS + 0x0304) + #define B1_DQ4_RG_RX_ARDQS_EYE_R_DLY_B1 Fld(7, 0) //[6:0] + #define B1_DQ4_RG_RX_ARDQS_EYE_F_DLY_B1 Fld(7, 8) //[14:8] + #define B1_DQ4_RG_RX_ARDQ_EYE_R_DLY_B1 Fld(6, 16) //[21:16] + #define B1_DQ4_RG_RX_ARDQ_EYE_F_DLY_B1 Fld(6, 24) //[29:24] + +#define DDRPHY_REG_B1_DQ5 (DDRPHY_AO_BASE_ADDRESS + 0x0308) + #define B1_DQ5_RG_RX_ARDQ_EYE_VREF_SEL_B1 Fld(6, 8) //[13:8] + #define B1_DQ5_RG_RX_ARDQ_VREF_EN_B1 Fld(1, 16) //[16:16] + #define B1_DQ5_RG_RX_ARDQ_EYE_VREF_EN_B1 Fld(1, 17) //[17:17] + #define B1_DQ5_RG_RX_ARDQ_EYE_SEL_B1 Fld(4, 20) //[23:20] + #define B1_DQ5_RG_RX_ARDQ_EYE_EN_B1 Fld(1, 24) //[24:24] + #define B1_DQ5_RG_RX_ARDQ_EYE_STBEN_RESETB_B1 Fld(1, 25) //[25:25] + #define B1_DQ5_RG_RX_ARDQS0_DVS_EN_B1 Fld(1, 31) //[31:31] + +#define DDRPHY_REG_B1_DQ6 (DDRPHY_AO_BASE_ADDRESS + 0x030C) + #define B1_DQ6_RG_RX_ARDQ_BIAS_PS_B1 Fld(2, 0) //[1:0] + #define B1_DQ6_RG_TX_ARDQ_OE_EXT_DIS_B1 Fld(1, 2) //[2:2] + #define B1_DQ6_RG_TX_ARDQ_ODTEN_EXT_DIS_B1 Fld(1, 3) //[3:3] + #define B1_DQ6_RG_RX_ARDQ_RPRE_TOG_EN_B1 Fld(1, 5) //[5:5] + #define B1_DQ6_RG_RX_ARDQ_RES_BIAS_EN_B1 Fld(1, 6) //[6:6] + #define B1_DQ6_RG_RX_ARDQ_OP_BIAS_SW_EN_B1 Fld(1, 7) //[7:7] + #define B1_DQ6_RG_RX_ARDQ_LPBK_EN_B1 Fld(1, 8) //[8:8] + #define B1_DQ6_RG_RX_ARDQ_O1_SEL_B1 Fld(1, 9) //[9:9] + #define B1_DQ6_RG_RX_ARDQ_JM_SEL_B1 Fld(1, 11) //[11:11] + #define B1_DQ6_RG_RX_ARDQ_BIAS_EN_B1 Fld(1, 12) //[12:12] + #define B1_DQ6_RG_RX_ARDQ_BIAS_VREF_SEL_B1 Fld(2, 14) //[15:14] + #define B1_DQ6_RG_RX_ARDQ_DDR4_SEL_B1 Fld(1, 16) //[16:16] + #define B1_DQ6_RG_TX_ARDQ_DDR4_SEL_B1 Fld(1, 17) //[17:17] + #define B1_DQ6_RG_RX_ARDQ_DDR3_SEL_B1 Fld(1, 18) //[18:18] + #define B1_DQ6_RG_TX_ARDQ_DDR3_SEL_B1 Fld(1, 19) //[19:19] + #define B1_DQ6_RG_TX_ARDQ_LP5_SEL_B1 Fld(1, 20) //[20:20] + #define B1_DQ6_RG_TX_ARDQ_LP4_SEL_B1 Fld(1, 21) //[21:21] + #define B1_DQ6_RG_TX_ARDQ_CAP_EN_B1 Fld(1, 24) //[24:24] + #define B1_DQ6_RG_TX_ARDQ_DATA_SWAP_EN_B1 Fld(1, 25) //[25:25] + #define B1_DQ6_RG_TX_ARDQ_DATA_SWAP_B1 Fld(2, 26) //[27:26] + #define B1_DQ6_RG_RX_ARDQ_EYE_DLY_DQS_BYPASS_B1 Fld(1, 28) //[28:28] + #define B1_DQ6_RG_RX_ARDQ_EYE_OE_GATE_EN_B1 Fld(1, 29) //[29:29] + #define B1_DQ6_RG_RX_ARDQ_DMRANK_OUTSEL_B1 Fld(1, 31) //[31:31] + +#define DDRPHY_REG_B1_DQ7 (DDRPHY_AO_BASE_ADDRESS + 0x0310) + #define B1_DQ7_RG_TX_ARDQS0B_PULL_DN_B1 Fld(1, 0) //[0:0] + #define B1_DQ7_RG_TX_ARDQS0B_PULL_UP_B1 Fld(1, 1) //[1:1] + #define B1_DQ7_RG_TX_ARDQS0_PULL_DN_B1 Fld(1, 2) //[2:2] + #define B1_DQ7_RG_TX_ARDQS0_PULL_UP_B1 Fld(1, 3) //[3:3] + #define B1_DQ7_RG_TX_ARDQM0_PULL_DN_B1 Fld(1, 4) //[4:4] + #define B1_DQ7_RG_TX_ARDQM0_PULL_UP_B1 Fld(1, 5) //[5:5] + #define B1_DQ7_RG_TX_ARDQ_PULL_DN_B1 Fld(1, 6) //[6:6] + #define B1_DQ7_RG_TX_ARDQ_PULL_UP_B1 Fld(1, 7) //[7:7] + #define B1_DQ7_RG_TX_ARWCKB_PULL_DN_B1 Fld(1, 8) //[8:8] + #define B1_DQ7_RG_TX_ARWCKB_PULL_UP_B1 Fld(1, 9) //[9:9] + #define B1_DQ7_RG_TX_ARWCK_PULL_DN_B1 Fld(1, 10) //[10:10] + #define B1_DQ7_RG_TX_ARWCK_PULL_UP_B1 Fld(1, 11) //[11:11] + #define B1_DQ7_RG_TX_ARDQS0B_PULL_DN_B1_LP4Y Fld(1, 16) //[16:16] + +#define DDRPHY_REG_B1_DQ8 (DDRPHY_AO_BASE_ADDRESS + 0x0314) + #define B1_DQ8_RG_TX_ARDQ_EN_LP4P_B1 Fld(1, 0) //[0:0] + #define B1_DQ8_RG_TX_ARDQ_EN_CAP_LP4P_B1 Fld(1, 1) //[1:1] + #define B1_DQ8_RG_TX_ARDQ_CAP_DET_B1 Fld(1, 2) //[2:2] + #define B1_DQ8_RG_TX_ARDQ_CKE_MCK4X_SEL_B1 Fld(2, 3) //[4:3] + #define B1_DQ8_RG_RX_ARDQS_BURST_E1_EN_B1 Fld(1, 8) //[8:8] + #define B1_DQ8_RG_RX_ARDQS_BURST_E2_EN_B1 Fld(1, 9) //[9:9] + #define B1_DQ8_RG_RX_ARDQS_GATE_EN_MODE_B1 Fld(1, 12) //[12:12] + #define B1_DQ8_RG_RX_ARDQS_SER_RST_MODE_B1 Fld(1, 13) //[13:13] + #define B1_DQ8_RG_ARDLL_RESETB_B1 Fld(1, 15) //[15:15] + +#define DDRPHY_REG_B1_DQ9 (DDRPHY_AO_BASE_ADDRESS + 0x0318) + #define B1_DQ9_RG_RX_ARDQ_STBEN_RESETB_B1 Fld(1, 0) //[0:0] + #define B1_DQ9_RG_RX_ARDQS0_STBEN_RESETB_B1 Fld(1, 4) //[4:4] + #define B1_DQ9_RG_RX_ARDQS0_DQSIENMODE_B1 Fld(1, 5) //[5:5] + #define B1_DQ9_R_DMRXDVS_R_F_DLY_RK_OPT_B1 Fld(1, 6) //[6:6] + #define B1_DQ9_R_DMRXFIFO_STBENCMP_EN_B1 Fld(1, 7) //[7:7] + #define B1_DQ9_R_IN_GATE_EN_LOW_OPT_B1 Fld(8, 8) //[15:8] + #define B1_DQ9_R_DMDQSIEN_VALID_LAT_B1 Fld(3, 16) //[18:16] + #define B1_DQ9_R_DMDQSIEN_RDSEL_LAT_B1 Fld(3, 20) //[22:20] + #define B1_DQ9_R_DMRXDVS_VALID_LAT_B1 Fld(3, 24) //[26:24] + #define B1_DQ9_R_DMRXDVS_RDSEL_LAT_B1 Fld(3, 28) //[30:28] + +#define DDRPHY_REG_B1_DQ10 (DDRPHY_AO_BASE_ADDRESS + 0x031C) + #define B1_DQ10_ARPI_CG_RK1_SRC_SEL_B1 Fld(1, 0) //[0:0] + +#define DDRPHY_REG_B1_DQ11 (DDRPHY_AO_BASE_ADDRESS + 0x0320) + #define B1_DQ11_DMY_DQ11_B1 Fld(1, 0) //[0:0] + +#define DDRPHY_REG_B1_PHY2 (DDRPHY_AO_BASE_ADDRESS + 0x0324) + #define B1_PHY2_RG_RX_ARDQS_SE_SWAP_EN_B1 Fld(1, 0) //[0:0] + #define B1_PHY2_RG_RX_ARDQS_JM_SEL_B1 Fld(4, 4) //[7:4] + #define B1_PHY2_RG_RX_ARDQS_JM_EN_B1 Fld(1, 8) //[8:8] + #define B1_PHY2_RG_RX_ARDQS_JM_DLY_B1 Fld(9, 16) //[24:16] + #define B1_PHY2_RG_RX_ARDQS_DQSIEN_UI_LEAD_LAG_EN_B1 Fld(1, 28) //[28:28] + #define B1_PHY2_RG_RX_ARDQS_DQSIEN_TIE_GATE_EN_B1 Fld(1, 29) //[29:29] + #define B1_PHY2_RG_RX_ARDQSB_SE_SWAP_EN_B1 Fld(1, 30) //[30:30] + +#define DDRPHY_REG_B1_PHY3 (DDRPHY_AO_BASE_ADDRESS + 0x0328) + #define B1_PHY3_RG_RX_ARDQ_DUTY_VCAL_VREF_SEL_B1 Fld(7, 8) //[14:8] + #define B1_PHY3_RG_RX_ARDQ_DUTY_VCAL_OFFSETC_B1 Fld(4, 16) //[19:16] + #define B1_PHY3_RG_RX_ARDQ_DUTY_VCAL_EN_B1 Fld(1, 20) //[20:20] + #define B1_PHY3_RG_RX_ARDQ_DUTY_VCAL_CLK_SEL_B1 Fld(2, 24) //[25:24] + #define B1_PHY3_RG_RX_ARDQ_DUTY_VCAL_CLK_RC_SEL_B1 Fld(2, 26) //[27:26] + #define B1_PHY3_RG_RX_ARDQ_BUFF_EN_SEL_B1 Fld(1, 28) //[28:28] + +#define DDRPHY_REG_B1_TX_MCK (DDRPHY_AO_BASE_ADDRESS + 0x032C) + #define B1_TX_MCK_DMY_TX_MCK_B1 Fld(1, 0) //[0:0] + +#define DDRPHY_REG_RK_CA_RXDVS0 (DDRPHY_AO_BASE_ADDRESS + 0x0360) + #define RK_CA_RXDVS0_R_RK0_CA_DVS_LEAD_LAG_CNT_CLR Fld(1, 26) //[26:26] + #define RK_CA_RXDVS0_R_RK0_CA_DVS_SW_CNT_CLR Fld(1, 27) //[27:27] + #define RK_CA_RXDVS0_R_RK0_CA_DVS_SW_CNT_ENA Fld(1, 31) //[31:31] + +#define DDRPHY_REG_RK_CA_RXDVS1 (DDRPHY_AO_BASE_ADDRESS + 0x0364) + #define RK_CA_RXDVS1_R_RK0_CA_DVS_TH_LAG Fld(16, 0) //[15:0] + #define RK_CA_RXDVS1_R_RK0_CA_DVS_TH_LEAD Fld(16, 16) //[31:16] + +#define DDRPHY_REG_RK_CA_RXDVS2 (DDRPHY_AO_BASE_ADDRESS + 0x0368) + #define RK_CA_RXDVS2_R_RK0_RX_DLY_FAL_DQS_SCALE_CA Fld(2, 16) //[17:16] + #define RK_CA_RXDVS2_R_RK0_RX_DLY_FAL_DQ_SCALE_CA Fld(2, 18) //[19:18] + #define RK_CA_RXDVS2_R_RK0_RX_DLY_FAL_TRACK_GATE_ENA_CA Fld(1, 23) //[23:23] + #define RK_CA_RXDVS2_R_RK0_RX_DLY_RIS_DQS_SCALE_CA Fld(2, 24) //[25:24] + #define RK_CA_RXDVS2_R_RK0_RX_DLY_RIS_DQ_SCALE_CA Fld(2, 26) //[27:26] + #define RK_CA_RXDVS2_R_RK0_RX_DLY_RIS_TRACK_GATE_ENA_CA Fld(1, 28) //[28:28] + #define RK_CA_RXDVS2_R_RK0_DVS_FDLY_MODE_CA Fld(1, 29) //[29:29] + #define RK_CA_RXDVS2_R_RK0_DVS_MODE_CA Fld(2, 30) //[31:30] + +#define DDRPHY_REG_RK_CA_RXDVS3 (DDRPHY_AO_BASE_ADDRESS + 0x036C) + #define RK_CA_RXDVS3_RG_RK0_ARCMD_MIN_DLY Fld(6, 0) //[5:0] + #define RK_CA_RXDVS3_RG_RK0_ARCMD_MIN_DLY_RFU Fld(2, 6) //[7:6] + #define RK_CA_RXDVS3_RG_RK0_ARCMD_MAX_DLY Fld(6, 8) //[13:8] + #define RK_CA_RXDVS3_RG_RK0_ARCMD_MAX_DLY_RFU Fld(2, 14) //[15:14] + +#define DDRPHY_REG_RK_CA_RXDVS4 (DDRPHY_AO_BASE_ADDRESS + 0x0370) + #define RK_CA_RXDVS4_RG_RK0_ARCLK_MIN_DLY Fld(7, 0) //[6:0] + #define RK_CA_RXDVS4_RG_RK0_ARCLK_MIN_DLY_RFU Fld(1, 7) //[7:7] + #define RK_CA_RXDVS4_RG_RK0_ARCLK_MAX_DLY Fld(7, 8) //[14:8] + #define RK_CA_RXDVS4_RG_RK0_ARCLK_MAX_DLY_RFU Fld(1, 15) //[15:15] + +#define DDRPHY_REG_CA_LP_CTRL0 (DDRPHY_AO_BASE_ADDRESS + 0x0460) + #define CA_LP_CTRL0_RG_ARDMSUS_10_CA Fld(1, 0) //[0:0] + #define CA_LP_CTRL0_RG_TX_ARCA_PULL_DN_LP_SEL Fld(1, 1) //[1:1] + #define CA_LP_CTRL0_RG_TX_ARCA_PULL_UP_LP_SEL Fld(1, 2) //[2:2] + #define CA_LP_CTRL0_RG_TX_ARCS_PULL_DN_LP_SEL Fld(1, 3) //[3:3] + #define CA_LP_CTRL0_RG_ARDMSUS_10_CA_LP_SEL Fld(1, 4) //[4:4] + #define CA_LP_CTRL0_RG_DA_PICG_CA_CTRL_LOW_BY_LPC Fld(1, 5) //[5:5] + #define CA_LP_CTRL0_RESERVED_CA_LP_CTRL0_6_6 Fld(1, 6) //[6:6] + #define CA_LP_CTRL0_RG_TX_ARCMD_RESETB_LP_SEL Fld(1, 7) //[7:7] + #define CA_LP_CTRL0_RG_ARCMD_RESETB_LP_SEL Fld(1, 8) //[8:8] + #define CA_LP_CTRL0_RG_ARPI_RESETB_CA_LP_SEL Fld(1, 9) //[9:9] + #define CA_LP_CTRL0_RESERVED_CA_LP_CTRL0_11_10 Fld(2, 10) //[11:10] + #define CA_LP_CTRL0_RG_CA_MS_SLV_LP_SEL Fld(1, 12) //[12:12] + #define CA_LP_CTRL0_RG_ARDLL_PHDET_EN_CA_LP_SEL Fld(1, 13) //[13:13] + #define CA_LP_CTRL0_RG_CA_DLL_EN_OP_SEQ_LP_SEL Fld(1, 14) //[14:14] + #define CA_LP_CTRL0_RG_TX_ARCS_PULL_UP_LP_SEL Fld(1, 15) //[15:15] + #define CA_LP_CTRL0_RG_RX_ARCMD_BIAS_EN_LP_SEL Fld(1, 16) //[16:16] + #define CA_LP_CTRL0_DA_ARPI_CG_MCK_CA_LP_SEL Fld(1, 17) //[17:17] + #define CA_LP_CTRL0_DA_ARPI_CG_MCK_FB2DLL_CA_LP_SEL Fld(1, 18) //[18:18] + #define CA_LP_CTRL0_DA_ARPI_CG_MCTL_CA_LP_SEL Fld(1, 19) //[19:19] + #define CA_LP_CTRL0_DA_ARPI_CG_FB_CA_LP_SEL Fld(1, 20) //[20:20] + #define CA_LP_CTRL0_DA_ARPI_CG_CS_LP_SEL Fld(1, 21) //[21:21] + #define CA_LP_CTRL0_DA_ARPI_CG_CLK_LP_SEL Fld(1, 22) //[22:22] + #define CA_LP_CTRL0_DA_ARPI_CG_CMD_LP_SEL Fld(1, 23) //[23:23] + #define CA_LP_CTRL0_DA_ARPI_CG_CLKIEN_LP_SEL Fld(1, 24) //[24:24] + #define CA_LP_CTRL0_DA_ARPI_MPDIV_CG_CA_LP_SEL Fld(1, 25) //[25:25] + #define CA_LP_CTRL0_RG_RX_ARCMD_VREF_EN_LP_SEL Fld(1, 26) //[26:26] + #define CA_LP_CTRL0_DA_ARPI_MIDPI_EN_CA_LP_SEL Fld(1, 27) //[27:27] + #define CA_LP_CTRL0_DA_ARPI_MIDPI_CKDIV4_EN_CA_LP_SEL Fld(1, 28) //[28:28] + #define CA_LP_CTRL0_RG_ARPI_DDR400_EN_CA_LP_SEL Fld(1, 29) //[29:29] + #define CA_LP_CTRL0_RG_MIDPI_EN_CA_OP_LP_SEL Fld(1, 30) //[30:30] + #define CA_LP_CTRL0_RG_MIDPI_CKDIV4_EN_CA_OP_LP_SEL Fld(1, 31) //[31:31] + +#define DDRPHY_REG_CA_RXDVS0 (DDRPHY_AO_BASE_ADDRESS + 0x0464) + #define CA_RXDVS0_R_RX_RANKINSEL_CA Fld(1, 0) //[0:0] + #define CA_RXDVS0_CA_RXDVS0_RFU Fld(3, 1) //[3:1] + #define CA_RXDVS0_R_RX_RANKINCTL_CA Fld(4, 4) //[7:4] + #define CA_RXDVS0_R_DVS_SW_UP_CA Fld(1, 8) //[8:8] + #define CA_RXDVS0_R_DMRXDVS_DQIENPRE_OPT_CA Fld(1, 9) //[9:9] + #define CA_RXDVS0_R_DMRXDVS_PBYTESTUCK_RST_CA Fld(1, 10) //[10:10] + #define CA_RXDVS0_R_DMRXDVS_PBYTESTUCK_IG_CA Fld(1, 11) //[11:11] + #define CA_RXDVS0_R_DMRXDVS_DQIENPOST_OPT_CA Fld(2, 12) //[13:12] + #define CA_RXDVS0_R_RX_DLY_RANK_ERR_ST_CLR_CA Fld(3, 16) //[18:16] + #define CA_RXDVS0_R_DMRXDVS_CNTCMP_OPT_CA Fld(1, 19) //[19:19] + #define CA_RXDVS0_R_RX_DLY_RK_OPT_CA Fld(2, 20) //[21:20] + #define CA_RXDVS0_R_HWRESTORE_ENA_CA Fld(1, 22) //[22:22] + #define CA_RXDVS0_R_HWSAVE_MODE_ENA_CA Fld(1, 24) //[24:24] + #define CA_RXDVS0_R_RX_DLY_DVS_MODE_SYNC_DIS_CA Fld(1, 26) //[26:26] + #define CA_RXDVS0_R_RX_DLY_TRACK_BYPASS_MODESYNC_CA Fld(1, 27) //[27:27] + #define CA_RXDVS0_R_RX_DLY_TRACK_CG_EN_CA Fld(1, 28) //[28:28] + #define CA_RXDVS0_R_RX_DLY_TRACK_SPM_CTRL_CA Fld(1, 29) //[29:29] + #define CA_RXDVS0_R_RX_DLY_TRACK_CLR_CA Fld(1, 30) //[30:30] + #define CA_RXDVS0_R_RX_DLY_TRACK_ENA_CA Fld(1, 31) //[31:31] + +#define DDRPHY_REG_CA_RXDVS1 (DDRPHY_AO_BASE_ADDRESS + 0x0468) + #define CA_RXDVS1_CA_RXDVS1_RFU Fld(16, 0) //[15:0] + #define CA_RXDVS1_R_DMRXDVS_UPD_CLR_ACK_CA Fld(1, 16) //[16:16] + #define CA_RXDVS1_R_DMRXDVS_UPD_CLR_NORD_CA Fld(1, 17) //[17:17] + +#define DDRPHY_REG_CA_DLL_ARPI0 (DDRPHY_AO_BASE_ADDRESS + 0x046C) + #define CA_DLL_ARPI0_RG_ARMCTLPLL_CK_SEL_CA Fld(1, 1) //[1:1] + #define CA_DLL_ARPI0_RG_ARPI_RESETB_CA Fld(1, 3) //[3:3] + #define CA_DLL_ARPI0_RG_ARPI_LS_EN_CA Fld(1, 4) //[4:4] + #define CA_DLL_ARPI0_RG_ARPI_LS_SEL_CA Fld(1, 5) //[5:5] + #define CA_DLL_ARPI0_RG_ARPI_MCK8X_SEL_CA Fld(1, 6) //[6:6] + +#define DDRPHY_REG_CA_DLL_ARPI1 (DDRPHY_AO_BASE_ADDRESS + 0x0470) + #define CA_DLL_ARPI1_RG_ARPI_CLKIEN_JUMP_EN Fld(1, 11) //[11:11] + #define CA_DLL_ARPI1_RG_ARPI_CMD_JUMP_EN Fld(1, 13) //[13:13] + #define CA_DLL_ARPI1_RG_ARPI_CLK_JUMP_EN Fld(1, 15) //[15:15] + #define CA_DLL_ARPI1_RG_ARPI_CS_JUMP_EN Fld(1, 16) //[16:16] + #define CA_DLL_ARPI1_RG_ARPI_FB_JUMP_EN_CA Fld(1, 17) //[17:17] + #define CA_DLL_ARPI1_RG_ARPI_MCTL_JUMP_EN_CA Fld(1, 19) //[19:19] + #define CA_DLL_ARPI1_RG_ARPISM_MCK_SEL_CA_REG_OPT Fld(1, 20) //[20:20] + #define CA_DLL_ARPI1_RG_ARPISM_MCK_SEL_CA Fld(1, 21) //[21:21] + #define CA_DLL_ARPI1_RG_ARPI_SET_UPDN_CA Fld(3, 28) //[30:28] + +#define DDRPHY_REG_CA_DLL_ARPI4 (DDRPHY_AO_BASE_ADDRESS + 0x0474) + #define CA_DLL_ARPI4_RG_ARPI_BYPASS_SR_CA_CA Fld(1, 8) //[8:8] + #define CA_DLL_ARPI4_RG_ARPI_BYPASS_SR_CLK_CA Fld(1, 9) //[9:9] + #define CA_DLL_ARPI4_RG_ARPI_BYPASS_CLKIEN Fld(1, 11) //[11:11] + #define CA_DLL_ARPI4_RG_ARPI_BYPASS_CMD Fld(1, 13) //[13:13] + #define CA_DLL_ARPI4_RG_ARPI_BYPASS_CLK Fld(1, 15) //[15:15] + #define CA_DLL_ARPI4_RG_ARPI_BYPASS_CS Fld(1, 16) //[16:16] + #define CA_DLL_ARPI4_RG_ARPI_BYPASS_FB_CA Fld(1, 17) //[17:17] + #define CA_DLL_ARPI4_RG_ARPI_BYPASS_MCTL_CA Fld(1, 19) //[19:19] + +#define DDRPHY_REG_CA_DLL_ARPI5 (DDRPHY_AO_BASE_ADDRESS + 0x0478) + #define CA_DLL_ARPI5_RG_ARDLL_MON_SEL_CA Fld(4, 4) //[7:4] + #define CA_DLL_ARPI5_RG_ARDLL_DIV_DEC_CA Fld(1, 8) //[8:8] + #define CA_DLL_ARPI5_RG_ARDLL_FJ_OUT_MODE_SEL_CA Fld(1, 25) //[25:25] + #define CA_DLL_ARPI5_RG_ARDLL_FJ_OUT_MODE_CA Fld(1, 26) //[26:26] + #define CA_DLL_ARPI5_RG_ARDLL_IDLE_EN_CA Fld(1, 28) //[28:28] + #define CA_DLL_ARPI5_RG_ARDLL_PD_ZONE_CA Fld(3, 29) //[31:29] + +#define DDRPHY_REG_CA_CMD2 (DDRPHY_AO_BASE_ADDRESS + 0x047C) + #define CA_CMD2_RG_TX_ARCLK_ODTEN_DIS_CA Fld(1, 0) //[0:0] + #define CA_CMD2_RG_TX_ARCLK_OE_DIS_CA Fld(1, 1) //[1:1] + #define CA_CMD2_RG_TX_ARCLK_OE_TIE_SEL_CA Fld(1, 2) //[2:2] + #define CA_CMD2_RG_TX_ARCLK_OE_TIE_EN_CA Fld(1, 3) //[3:3] + #define CA_CMD2_RG_TX_ARCS_OE_TIE_SEL_CA Fld(1, 14) //[14:14] + #define CA_CMD2_RG_TX_ARCS_OE_TIE_EN_CA Fld(1, 15) //[15:15] + #define CA_CMD2_RG_TX_ARCMD_ODTEN_DIS_CA Fld(1, 20) //[20:20] + #define CA_CMD2_RG_TX_ARCMD_OE_DIS_CA Fld(1, 21) //[21:21] + #define CA_CMD2_RG_TX_ARCA_OE_TIE_SEL_CA Fld(1, 22) //[22:22] + #define CA_CMD2_RG_TX_ARCA_OE_TIE_EN_CA Fld(8, 24) //[31:24] + +#define DDRPHY_REG_CA_CMD3 (DDRPHY_AO_BASE_ADDRESS + 0x0480) + #define CA_CMD3_RG_ARCMD_ATPG_EN Fld(1, 0) //[0:0] + #define CA_CMD3_RG_RX_ARCMD_SMT_EN Fld(1, 1) //[1:1] + #define CA_CMD3_RG_TX_ARCMD_EN Fld(1, 2) //[2:2] + #define CA_CMD3_RG_ARCMD_RESETB Fld(1, 3) //[3:3] + #define CA_CMD3_RG_RX_ARCLK_IN_BUFF_EN Fld(1, 5) //[5:5] + #define CA_CMD3_RG_RX_ARCMD_IN_BUFF_EN Fld(1, 7) //[7:7] + #define CA_CMD3_RG_RX_ARCMD_STBENCMP_EN Fld(1, 10) //[10:10] + #define CA_CMD3_RG_RX_ARCMD_OFFC_EN Fld(1, 11) //[11:11] + #define CA_CMD3_RG_RX_ARCLK_SWAP_EN Fld(1, 15) //[15:15] + #define CA_CMD3_RG_ARPI_ASYNC_EN_CA Fld(1, 23) //[23:23] + #define CA_CMD3_RG_ARPI_LAT_EN_CA Fld(1, 24) //[24:24] + #define CA_CMD3_RG_ARPI_MCK_FB_SEL_CA Fld(2, 26) //[27:26] + +#define DDRPHY_REG_CA_CMD4 (DDRPHY_AO_BASE_ADDRESS + 0x0484) + #define CA_CMD4_RG_RX_ARCLK_EYE_R_DLY Fld(7, 0) //[6:0] + #define CA_CMD4_RG_RX_ARCLK_EYE_F_DLY Fld(7, 8) //[14:8] + #define CA_CMD4_RG_RX_ARCMD_EYE_R_DLY Fld(6, 16) //[21:16] + #define CA_CMD4_RG_RX_ARCMD_EYE_F_DLY Fld(6, 24) //[29:24] + +#define DDRPHY_REG_CA_CMD5 (DDRPHY_AO_BASE_ADDRESS + 0x0488) + #define CA_CMD5_RG_RX_ARCMD_EYE_VREF_SEL Fld(6, 8) //[13:8] + #define CA_CMD5_RG_RX_ARCMD_VREF_EN Fld(1, 16) //[16:16] + #define CA_CMD5_RG_RX_ARCMD_EYE_VREF_EN Fld(1, 17) //[17:17] + #define CA_CMD5_RG_RX_ARCMD_EYE_SEL Fld(4, 20) //[23:20] + #define CA_CMD5_RG_RX_ARCMD_EYE_EN Fld(1, 24) //[24:24] + #define CA_CMD5_RG_RX_ARCMD_EYE_STBEN_RESETB Fld(1, 25) //[25:25] + #define CA_CMD5_RG_RX_ARCLK_DVS_EN Fld(1, 31) //[31:31] + +#define DDRPHY_REG_CA_CMD6 (DDRPHY_AO_BASE_ADDRESS + 0x048C) + #define CA_CMD6_RG_RX_ARCMD_BIAS_PS Fld(2, 0) //[1:0] + #define CA_CMD6_RG_TX_ARCMD_OE_EXT_DIS Fld(1, 2) //[2:2] + #define CA_CMD6_RG_TX_ARCMD_ODTEN_EXT_DIS Fld(1, 3) //[3:3] + #define CA_CMD6_RG_RX_ARCMD_RPRE_TOG_EN Fld(1, 5) //[5:5] + #define CA_CMD6_RG_RX_ARCMD_RES_BIAS_EN Fld(1, 6) //[6:6] + #define CA_CMD6_RG_RX_ARCMD_OP_BIAS_SW_EN Fld(1, 7) //[7:7] + #define CA_CMD6_RG_RX_ARCMD_LPBK_EN Fld(1, 8) //[8:8] + #define CA_CMD6_RG_RX_ARCMD_O1_SEL Fld(1, 9) //[9:9] + #define CA_CMD6_RG_RX_ARCMD_JM_SEL Fld(1, 11) //[11:11] + #define CA_CMD6_RG_RX_ARCMD_BIAS_EN Fld(1, 12) //[12:12] + #define CA_CMD6_RG_RX_ARCMD_BIAS_VREF_SEL Fld(2, 14) //[15:14] + #define CA_CMD6_RG_RX_ARCMD_DDR4_SEL Fld(1, 16) //[16:16] + #define CA_CMD6_RG_TX_ARCMD_DDR4_SEL Fld(1, 17) //[17:17] + #define CA_CMD6_RG_RX_ARCMD_DDR3_SEL Fld(1, 18) //[18:18] + #define CA_CMD6_RG_TX_ARCMD_DDR3_SEL Fld(1, 19) //[19:19] + #define CA_CMD6_RG_TX_ARCMD_LP5_SEL Fld(1, 20) //[20:20] + #define CA_CMD6_RG_TX_ARCMD_LP4_SEL Fld(1, 21) //[21:21] + #define CA_CMD6_RG_TX_ARCMD_CAP_EN Fld(1, 24) //[24:24] + #define CA_CMD6_RG_TX_ARCMD_DATA_SWAP_EN Fld(1, 25) //[25:25] + #define CA_CMD6_RG_TX_ARCMD_DATA_SWAP Fld(2, 26) //[27:26] + #define CA_CMD6_RG_RX_ARCMD_EYE_DLY_DQS_BYPASS Fld(1, 28) //[28:28] + #define CA_CMD6_RG_RX_ARCMD_EYE_OE_GATE_EN Fld(1, 29) //[29:29] + #define CA_CMD6_RG_RX_ARCMD_DMRANK_OUTSEL Fld(1, 31) //[31:31] + +#define DDRPHY_REG_CA_CMD7 (DDRPHY_AO_BASE_ADDRESS + 0x0490) + #define CA_CMD7_RG_TX_ARCLKB_PULL_DN Fld(1, 0) //[0:0] + #define CA_CMD7_RG_TX_ARCLKB_PULL_UP Fld(1, 1) //[1:1] + #define CA_CMD7_RG_TX_ARCLK_PULL_DN Fld(1, 2) //[2:2] + #define CA_CMD7_RG_TX_ARCLK_PULL_UP Fld(1, 3) //[3:3] + #define CA_CMD7_RG_TX_ARCS0_PULL_DN Fld(1, 4) //[4:4] + #define CA_CMD7_RG_TX_ARCS0_PULL_UP Fld(1, 5) //[5:5] + #define CA_CMD7_RG_TX_ARCMD_PULL_DN Fld(1, 6) //[6:6] + #define CA_CMD7_RG_TX_ARCMD_PULL_UP Fld(1, 7) //[7:7] + #define CA_CMD7_RG_TX_ARCS1_PULL_DN Fld(1, 8) //[8:8] + #define CA_CMD7_RG_TX_ARCS1_PULL_UP Fld(1, 9) //[9:9] + #define CA_CMD7_RG_TX_ARCLKB_PULL_DN_LP4Y Fld(1, 16) //[16:16] + +#define DDRPHY_REG_CA_CMD8 (DDRPHY_AO_BASE_ADDRESS + 0x0494) + #define CA_CMD8_RG_TX_ARCMD_EN_LP4P Fld(1, 0) //[0:0] + #define CA_CMD8_RG_TX_ARCMD_EN_CAP_LP4P Fld(1, 1) //[1:1] + #define CA_CMD8_RG_TX_ARCMD_CAP_DET Fld(1, 2) //[2:2] + #define CA_CMD8_RG_TX_ARCMD_CKE_MCK4X_SEL Fld(2, 3) //[4:3] + #define CA_CMD8_RG_RX_ARCLK_DQSIEN_BURST_E1_EN Fld(1, 8) //[8:8] + #define CA_CMD8_RG_RX_ARCLK_DQSIEN_BURST_E2_EN Fld(1, 9) //[9:9] + #define CA_CMD8_RG_RX_ARCLK_GATE_EN_MODE Fld(1, 12) //[12:12] + #define CA_CMD8_RG_RX_ARCLK_SER_RST_MODE Fld(1, 13) //[13:13] + #define CA_CMD8_RG_ARDLL_RESETB_CA Fld(1, 15) //[15:15] + #define CA_CMD8_RG_TX_ARCMD_LP3_CKE_SEL Fld(1, 16) //[16:16] + #define CA_CMD8_RG_TX_ARCMD_LP4_CKE_SEL Fld(1, 17) //[17:17] + #define CA_CMD8_RG_TX_ARCMD_LP4X_CKE_SEL Fld(1, 18) //[18:18] + #define CA_CMD8_RG_TX_ARCMD_LSH_DQM_CG_EN Fld(1, 20) //[20:20] + #define CA_CMD8_RG_TX_ARCMD_LSH_DQS_CG_EN Fld(1, 21) //[21:21] + #define CA_CMD8_RG_TX_ARCMD_LSH_DQ_CG_EN Fld(1, 22) //[22:22] + #define CA_CMD8_RG_TX_ARCMD_OE_SUS_EN Fld(1, 24) //[24:24] + #define CA_CMD8_RG_TX_ARCMD_ODTEN_OE_SUS_EN Fld(1, 25) //[25:25] + +#define DDRPHY_REG_CA_CMD9 (DDRPHY_AO_BASE_ADDRESS + 0x0498) + #define CA_CMD9_RG_RX_ARCMD_STBEN_RESETB Fld(1, 0) //[0:0] + #define CA_CMD9_RG_RX_ARCLK_STBEN_RESETB Fld(1, 4) //[4:4] + #define CA_CMD9_RG_RX_ARCLK_DQSIENMODE Fld(1, 5) //[5:5] + #define CA_CMD9_R_DMRXDVS_R_F_DLY_RK_OPT Fld(1, 6) //[6:6] + #define CA_CMD9_R_DMRXFIFO_STBENCMP_EN_CA Fld(1, 7) //[7:7] + #define CA_CMD9_R_IN_GATE_EN_LOW_OPT_CA Fld(8, 8) //[15:8] + #define CA_CMD9_R_DMDQSIEN_VALID_LAT_CA Fld(3, 16) //[18:16] + #define CA_CMD9_R_DMDQSIEN_RDSEL_LAT_CA Fld(3, 20) //[22:20] + #define CA_CMD9_R_DMRXDVS_VALID_LAT_CA Fld(3, 24) //[26:24] + #define CA_CMD9_R_DMRXDVS_RDSEL_LAT_CA Fld(3, 28) //[30:28] + +#define DDRPHY_REG_CA_CMD10 (DDRPHY_AO_BASE_ADDRESS + 0x049C) + #define CA_CMD10_ARPI_CG_RK1_SRC_SEL_CA Fld(1, 0) //[0:0] + +#define DDRPHY_REG_CA_CMD11 (DDRPHY_AO_BASE_ADDRESS + 0x04A0) + #define CA_CMD11_RG_RRESETB_DRVP Fld(5, 0) //[4:0] + #define CA_CMD11_RG_RRESETB_DRVN Fld(5, 8) //[12:8] + #define CA_CMD11_RG_RX_RRESETB_SMT_EN Fld(1, 16) //[16:16] + #define CA_CMD11_RG_TX_RRESETB_SCAN_IN_EN Fld(1, 17) //[17:17] + #define CA_CMD11_RG_TX_RRESETB_DDR4_SEL Fld(1, 18) //[18:18] + #define CA_CMD11_RG_TX_RRESETB_DDR3_SEL Fld(1, 19) //[19:19] + #define CA_CMD11_RG_TX_RRESETB_PULL_DN Fld(1, 20) //[20:20] + #define CA_CMD11_RG_TX_RRESETB_PULL_UP Fld(1, 21) //[21:21] + #define CA_CMD11_RG_RRESETB_OPEN_DRAIN_EN Fld(1, 22) //[22:22] + +#define DDRPHY_REG_CA_PHY2 (DDRPHY_AO_BASE_ADDRESS + 0x04A4) + #define CA_PHY2_RG_RX_ARCLK_SE_SWAP_EN_CA Fld(1, 0) //[0:0] + #define CA_PHY2_RG_RX_ARCLK_JM_SEL_CA Fld(4, 4) //[7:4] + #define CA_PHY2_RG_RX_ARCLK_JM_EN_CA Fld(1, 8) //[8:8] + #define CA_PHY2_RG_RX_ARCLK_JM_DLY_CA Fld(9, 16) //[24:16] + #define CA_PHY2_RG_RX_ARCLK_DQSIEN_UI_LEAD_LAG_EN_CA Fld(1, 28) //[28:28] + #define CA_PHY2_RG_RX_ARCLK_DQSIEN_TIE_GATE_EN_CA Fld(1, 29) //[29:29] + #define CA_PHY2_RG_RX_ARCLKB_SE_SWAP_EN_CA Fld(1, 30) //[30:30] + +#define DDRPHY_REG_CA_PHY3 (DDRPHY_AO_BASE_ADDRESS + 0x04A8) + #define CA_PHY3_RG_RX_ARCA_DUTY_VCAL_VREF_SEL_CA Fld(7, 8) //[14:8] + #define CA_PHY3_RG_RX_ARCA_DUTY_VCAL_OFFSETC_CA Fld(4, 16) //[19:16] + #define CA_PHY3_RG_RX_ARCA_DUTY_VCAL_EN_CA Fld(1, 20) //[20:20] + #define CA_PHY3_RG_RX_ARCA_DUTY_VCAL_CLK_SEL_CA Fld(2, 24) //[25:24] + #define CA_PHY3_RG_RX_ARCA_DUTY_VCAL_CLK_RC_SEL_CA Fld(2, 26) //[27:26] + #define CA_PHY3_RG_RX_ARCA_BUFF_EN_SEL_CA Fld(1, 28) //[28:28] + +#define DDRPHY_REG_CA_TX_MCK (DDRPHY_AO_BASE_ADDRESS + 0x04AC) + #define CA_TX_MCK_R_DMRESETB_DRVP_FRPHY Fld(5, 21) //[25:21] + #define CA_TX_MCK_R_DMRESETB_DRVN_FRPHY Fld(5, 26) //[30:26] + #define CA_TX_MCK_R_DMRESET_FRPHY_OPT Fld(1, 31) //[31:31] + +#define DDRPHY_REG_MISC_STBCAL (DDRPHY_AO_BASE_ADDRESS + 0x04E0) + #define MISC_STBCAL_PIMASK_RKCHG_OPT Fld(1, 0) //[0:0] + #define MISC_STBCAL_PIMASK_RKCHG_EXT Fld(3, 1) //[3:1] + #define MISC_STBCAL_STBDLELAST_OPT Fld(1, 4) //[4:4] + #define MISC_STBCAL_STBDLELAST_PULSE Fld(4, 8) //[11:8] + #define MISC_STBCAL_STBDLELAST_FILTER Fld(1, 12) //[12:12] + #define MISC_STBCAL_STBUPDSTOP Fld(1, 13) //[13:13] + #define MISC_STBCAL_CG_RKEN Fld(1, 14) //[14:14] + #define MISC_STBCAL_STBSTATE_OPT Fld(1, 15) //[15:15] + #define MISC_STBCAL_PHYVALID_IG Fld(1, 16) //[16:16] + #define MISC_STBCAL_SREF_DQSGUPD Fld(1, 17) //[17:17] + #define MISC_STBCAL_RKCHGMASKDIS Fld(1, 19) //[19:19] + #define MISC_STBCAL_PICGEN Fld(1, 20) //[20:20] + #define MISC_STBCAL_REFUICHG Fld(1, 21) //[21:21] + #define MISC_STBCAL_STBCAL2R Fld(1, 23) //[23:23] + #define MISC_STBCAL_STBDLYOUT_OPT Fld(1, 25) //[25:25] + #define MISC_STBCAL_PICHGBLOCK_NORD Fld(1, 26) //[26:26] + #define MISC_STBCAL_STB_DQIEN_IG Fld(1, 27) //[27:27] + #define MISC_STBCAL_DQSIENCG_CHG_EN Fld(1, 28) //[28:28] + #define MISC_STBCAL_DQSIENCG_NORMAL_EN Fld(1, 29) //[29:29] + #define MISC_STBCAL_DQSIENMODE Fld(1, 31) //[31:31] + +#define DDRPHY_REG_MISC_STBCAL1 (DDRPHY_AO_BASE_ADDRESS + 0x04E4) + #define MISC_STBCAL1_STBCNT_SHU_RST_EN Fld(1, 0) //[0:0] + #define MISC_STBCAL1_RKUICHG_EN Fld(1, 1) //[1:1] + #define MISC_STBCAL1_DIS_PI_TRACK_AS_NOT_RD Fld(1, 2) //[2:2] + #define MISC_STBCAL1_STBCNT_MODESEL Fld(1, 4) //[4:4] + #define MISC_STBCAL1_DQSIEN_7UI_EN Fld(1, 5) //[5:5] + #define MISC_STBCAL1_STB_SHIFT_DTCOUT_IG Fld(1, 6) //[6:6] + #define MISC_STBCAL1_STB_FLAGCLR_OPT Fld(1, 8) //[8:8] + #define MISC_STBCAL1_STB_DLLFRZ_IG Fld(1, 9) //[9:9] + #define MISC_STBCAL1_STBCNT_SW_RST Fld(1, 15) //[15:15] + #define MISC_STBCAL1_STBCAL_FILTER Fld(16, 16) //[31:16] + +#define DDRPHY_REG_MISC_STBCAL2 (DDRPHY_AO_BASE_ADDRESS + 0x04E8) + #define MISC_STBCAL2_STB_PIDLYCG_IG Fld(1, 0) //[0:0] + #define MISC_STBCAL2_STB_UIDLYCG_IG Fld(1, 1) //[1:1] + #define MISC_STBCAL2_STBENCMPEN Fld(1, 2) //[2:2] + #define MISC_STBCAL2_STB_DBG_EN Fld(4, 4) //[7:4] + #define MISC_STBCAL2_STB_DBG_CG_AO Fld(1, 8) //[8:8] + #define MISC_STBCAL2_STB_DBG_UIPI_UPD_OPT Fld(1, 9) //[9:9] + #define MISC_STBCAL2_DQSGCNT_BYP_REF Fld(1, 10) //[10:10] + #define MISC_STBCAL2_STB_DRS_MASK_HW_SAVE Fld(1, 12) //[12:12] + #define MISC_STBCAL2_STB_DRS_RK1_FLAG_SYNC_RK0_EN Fld(1, 13) //[13:13] + #define MISC_STBCAL2_STB_PICG_EARLY_1T_EN Fld(1, 16) //[16:16] + #define MISC_STBCAL2_STB_STBENRST_EARLY_1T_EN Fld(1, 17) //[17:17] + #define MISC_STBCAL2_STB_IG_XRANK_CG_RST Fld(1, 18) //[18:18] + #define MISC_STBCAL2_STB_RST_BY_RANK Fld(1, 19) //[19:19] + #define MISC_STBCAL2_DQSIEN_SELPH_BY_RANK_EN Fld(1, 20) //[20:20] + #define MISC_STBCAL2_DQSG_CNT_EN Fld(1, 21) //[21:21] + #define MISC_STBCAL2_DQSG_CNT_RST Fld(1, 22) //[22:22] + #define MISC_STBCAL2_STB_DBG_STATUS Fld(4, 24) //[27:24] + #define MISC_STBCAL2_STB_GERRSTOP Fld(1, 28) //[28:28] + #define MISC_STBCAL2_STB_GERR_RST Fld(1, 29) //[29:29] + #define MISC_STBCAL2_STB_GERR_B01 Fld(1, 30) //[30:30] + #define MISC_STBCAL2_STB_GERR_B23 Fld(1, 31) //[31:31] + +#define DDRPHY_REG_MISC_CG_CTRL0 (DDRPHY_AO_BASE_ADDRESS + 0x04EC) + #define MISC_CG_CTRL0_W_CHG_MEM Fld(1, 0) //[0:0] + #define MISC_CG_CTRL0_RESERVED_MISC_CG_CTRL0_BIT3_1 Fld(3, 1) //[3:1] + #define MISC_CG_CTRL0_CLK_MEM_SEL Fld(2, 4) //[5:4] + #define MISC_CG_CTRL0_CLK_MEM_INV Fld(1, 6) //[6:6] + #define MISC_CG_CTRL0_RESERVED_MISC_CG_CTRL0_BIT7 Fld(1, 7) //[7:7] + #define MISC_CG_CTRL0_RG_CG_EMI_OFF_DISABLE Fld(1, 8) //[8:8] + #define MISC_CG_CTRL0_RG_CG_DRAMC_OFF_DISABLE Fld(1, 9) //[9:9] + #define MISC_CG_CTRL0_RG_CG_PHY_OFF_DIABLE Fld(1, 10) //[10:10] + #define MISC_CG_CTRL0_RG_CG_COMB_OFF_DISABLE Fld(1, 11) //[11:11] + #define MISC_CG_CTRL0_RG_CG_CMD_OFF_DISABLE Fld(1, 12) //[12:12] + #define MISC_CG_CTRL0_RG_CG_COMB0_OFF_DISABLE Fld(1, 13) //[13:13] + #define MISC_CG_CTRL0_RG_CG_COMB1_OFF_DISABLE Fld(1, 14) //[14:14] + #define MISC_CG_CTRL0_RG_CG_RX_CMD_OFF_DISABLE Fld(1, 15) //[15:15] + #define MISC_CG_CTRL0_RG_CG_RX_COMB0_OFF_DISABLE Fld(1, 16) //[16:16] + #define MISC_CG_CTRL0_RG_CG_RX_COMB1_OFF_DISABLE Fld(1, 17) //[17:17] + #define MISC_CG_CTRL0_RG_CG_IDLE_SYNC_EN Fld(1, 18) //[18:18] + #define MISC_CG_CTRL0_RG_CG_INFRA_OFF_DISABLE Fld(1, 19) //[19:19] + #define MISC_CG_CTRL0_RG_CG_DRAMC_CK_OFF Fld(1, 20) //[20:20] + #define MISC_CG_CTRL0_RESERVED_MISC_CG_CTRL0_BIT21 Fld(1, 21) //[21:21] + #define MISC_CG_CTRL0_RG_CG_NAO_FORCE_OFF Fld(1, 22) //[22:22] + #define MISC_CG_CTRL0_RG_DBG_OUT_SEL Fld(2, 23) //[24:23] + #define MISC_CG_CTRL0_RESERVED_MISC_CG_CTRL0_BIT27_25 Fld(3, 25) //[27:25] + #define MISC_CG_CTRL0_RG_DA_RREF_CK_SEL Fld(1, 28) //[28:28] + #define MISC_CG_CTRL0_RG_FREERUN_MCK_CG Fld(1, 29) //[29:29] + #define MISC_CG_CTRL0_RG_FREERUN_MCK_SEL Fld(1, 30) //[30:30] + #define MISC_CG_CTRL0_RESERVED_MISC_CG_CTRL0_BIT31 Fld(1, 31) //[31:31] + +#define DDRPHY_REG_MISC_CG_CTRL1 (DDRPHY_AO_BASE_ADDRESS + 0x04F0) + #define MISC_CG_CTRL1_R_DVS_DIV4_CG_CTRL Fld(32, 0) //[31:0] + +#define DDRPHY_REG_MISC_CG_CTRL2 (DDRPHY_AO_BASE_ADDRESS + 0x04F4) + #define MISC_CG_CTRL2_RG_MEM_DCM_APB_TOG Fld(1, 0) //[0:0] + #define MISC_CG_CTRL2_RG_MEM_DCM_APB_SEL Fld(5, 1) //[5:1] + #define MISC_CG_CTRL2_RG_MEM_DCM_FORCE_ON Fld(1, 6) //[6:6] + #define MISC_CG_CTRL2_RG_MEM_DCM_DCM_EN Fld(1, 7) //[7:7] + #define MISC_CG_CTRL2_RG_MEM_DCM_DBC_EN Fld(1, 8) //[8:8] + #define MISC_CG_CTRL2_RG_MEM_DCM_DBC_CNT Fld(7, 9) //[15:9] + #define MISC_CG_CTRL2_RG_MEM_DCM_FSEL Fld(5, 16) //[20:16] + #define MISC_CG_CTRL2_RG_MEM_DCM_IDLE_FSEL Fld(5, 21) //[25:21] + #define MISC_CG_CTRL2_RG_MEM_DCM_FORCE_OFF Fld(1, 26) //[26:26] + #define MISC_CG_CTRL2_RESERVED_MISC_CG_CTRL2_BIT27 Fld(1, 27) //[27:27] + #define MISC_CG_CTRL2_RG_PHY_CG_OFF_DISABLE Fld(1, 28) //[28:28] + #define MISC_CG_CTRL2_RG_PIPE0_CG_OFF_DISABLE Fld(1, 29) //[29:29] + #define MISC_CG_CTRL2_RESERVED_MISC_CG_CTRL2_BIT30 Fld(1, 30) //[30:30] + #define MISC_CG_CTRL2_RG_MEM_DCM_CG_OFF_DISABLE Fld(1, 31) //[31:31] + +#define DDRPHY_REG_MISC_CG_CTRL3 (DDRPHY_AO_BASE_ADDRESS + 0x04F8) + #define MISC_CG_CTRL3_R_LBK_CG_CTRL Fld(32, 0) //[31:0] + +#define DDRPHY_REG_MISC_CG_CTRL5 (DDRPHY_AO_BASE_ADDRESS + 0x0500) + #define MISC_CG_CTRL5_RESERVE Fld(16, 0) //[15:0] + #define MISC_CG_CTRL5_R_DQ1_DLY_DCM_EN Fld(1, 16) //[16:16] + #define MISC_CG_CTRL5_R_DQ0_DLY_DCM_EN Fld(1, 17) //[17:17] + #define MISC_CG_CTRL5_R_CA_DLY_DCM_EN Fld(1, 18) //[18:18] + #define MISC_CG_CTRL5_R_DQ1_PI_DCM_EN Fld(1, 20) //[20:20] + #define MISC_CG_CTRL5_R_DQ0_PI_DCM_EN Fld(1, 21) //[21:21] + #define MISC_CG_CTRL5_R_CA_PI_DCM_EN Fld(1, 22) //[22:22] + #define MISC_CG_CTRL5_R_PICG_MON_CLR Fld(1, 23) //[23:23] + #define MISC_CG_CTRL5_R_PICG_MON_EN Fld(1, 24) //[24:24] + +#define DDRPHY_REG_MISC_CG_CTRL7 (DDRPHY_AO_BASE_ADDRESS + 0x0504) + #define MISC_CG_CTRL7_RESERVED_MISC_CG_CTRL7_BIT3_0 Fld(4, 0) //[3:0] + #define MISC_CG_CTRL7_FMEM_CK_CG_PINMUX Fld(2, 4) //[5:4] + #define MISC_CG_CTRL7_RESERVED_MISC_CG_CTRL7_BIT10_6 Fld(5, 6) //[10:6] + #define MISC_CG_CTRL7_CK_BFE_DCM_EN Fld(1, 11) //[11:11] + #define MISC_CG_CTRL7_RESERVED_MISC_CG_CTRL7_BIT15_12 Fld(4, 12) //[15:12] + #define MISC_CG_CTRL7_ARMCTL_CK_OUT_CG_SEL Fld(1, 16) //[16:16] + #define MISC_CG_CTRL7_RESERVED_MISC_CG_CTRL7_BIT31_17 Fld(15, 17) //[31:17] + +#define DDRPHY_REG_MISC_CG_CTRL9 (DDRPHY_AO_BASE_ADDRESS + 0x0508) + #define MISC_CG_CTRL9_RESERVED_MISC_CG_CTRL9_BIT3_0 Fld(4, 0) //[3:0] + #define MISC_CG_CTRL9_RG_M_CK_OPENLOOP_MODE_EN Fld(1, 4) //[4:4] + #define MISC_CG_CTRL9_RESERVED_MISC_CG_CTRL9_BIT7_5 Fld(3, 5) //[7:5] + #define MISC_CG_CTRL9_RG_MCK4X_I_OPENLOOP_MODE_EN Fld(1, 8) //[8:8] + #define MISC_CG_CTRL9_RG_CG_DDR400_MCK4X_I_OFF Fld(1, 9) //[9:9] + #define MISC_CG_CTRL9_RG_DDR400_MCK4X_I_FORCE_ON Fld(1, 10) //[10:10] + #define MISC_CG_CTRL9_RG_MCK4X_I_FB_CK_CG_OFF Fld(1, 11) //[11:11] + #define MISC_CG_CTRL9_RG_MCK4X_Q_OPENLOOP_MODE_EN Fld(1, 12) //[12:12] + #define MISC_CG_CTRL9_RG_CG_DDR400_MCK4X_Q_OFF Fld(1, 13) //[13:13] + #define MISC_CG_CTRL9_RG_DDR400_MCK4X_Q_FORCE_ON Fld(1, 14) //[14:14] + #define MISC_CG_CTRL9_RG_MCK4X_Q_FB_CK_CG_OFF Fld(1, 15) //[15:15] + #define MISC_CG_CTRL9_RG_MCK4X_O_OPENLOOP_MODE_EN Fld(1, 16) //[16:16] + #define MISC_CG_CTRL9_RG_CG_DDR400_MCK4X_O_OFF Fld(1, 17) //[17:17] + #define MISC_CG_CTRL9_RG_DDR400_MCK4X_O_FORCE_ON Fld(1, 18) //[18:18] + #define MISC_CG_CTRL9_RG_MCK4X_O_FB_CK_CG_OFF Fld(1, 19) //[19:19] + #define MISC_CG_CTRL9_RESERVED_MISC_CG_CTRL9_BIT31_20 Fld(12, 20) //[31:20] + +#define DDRPHY_REG_MISC_CG_CTRL10 (DDRPHY_AO_BASE_ADDRESS + 0x050C) + #define MISC_CG_CTRL10_RESERVED_MISC_CG_CTRL10_BIT31_0 Fld(32, 0) //[31:0] + +#define DDRPHY_REG_MISC_DVFSCTL (DDRPHY_AO_BASE_ADDRESS + 0x0510) + #define MISC_DVFSCTL_R_DVFS_PICG_MARGIN_NEW Fld(4, 0) //[3:0] + #define MISC_DVFSCTL_R_DVFS_PICG_MARGIN2_NEW Fld(4, 4) //[7:4] + #define MISC_DVFSCTL_R_DVFS_PICG_MARGIN3_NEW Fld(4, 8) //[11:8] + #define MISC_DVFSCTL_R_DVFS_PICG_MARGIN4_NEW Fld(4, 12) //[15:12] + #define MISC_DVFSCTL_R_DVFS_MCK_CG_EN_FT_EN Fld(1, 16) //[16:16] + #define MISC_DVFSCTL_R_DVFS_MCK_CG_EN_FT_IN Fld(1, 17) //[17:17] + #define MISC_DVFSCTL_R_DMSHUFFLE_CHANGE_FREQ_OPT Fld(1, 18) //[18:18] + #define MISC_DVFSCTL_R_NEW_SHU_MUX_SPM Fld(1, 19) //[19:19] + #define MISC_DVFSCTL_R_MPDIV_SHU_GP Fld(3, 20) //[22:20] + #define MISC_DVFSCTL_R_OTHER_SHU_GP Fld(2, 24) //[25:24] + #define MISC_DVFSCTL_R_SHUFFLE_PI_RESET_ENABLE Fld(1, 26) //[26:26] + #define MISC_DVFSCTL_R_DVFS_PICG_POSTPONE Fld(1, 27) //[27:27] + #define MISC_DVFSCTL_R_DVFS_MCK8X_MARGIN Fld(4, 28) //[31:28] + +#define DDRPHY_REG_MISC_DVFSCTL2 (DDRPHY_AO_BASE_ADDRESS + 0x0514) + #define MISC_DVFSCTL2_DLL_LOCK_SHU_EN Fld(1, 0) //[0:0] + #define MISC_DVFSCTL2_RG_IGNORE_PHY_SH_CHG_CLK_RDY_CHA Fld(1, 1) //[1:1] + #define MISC_DVFSCTL2_RG_IGNORE_PHY_SH_CHG_CLK_RDY_CHB Fld(1, 2) //[2:2] + #define MISC_DVFSCTL2_RG_TOPCK_FMEM_CK_BLOCK_DURING_DFS Fld(1, 3) //[3:3] + #define MISC_DVFSCTL2_RG_DLL_SHUFFLE Fld(1, 4) //[4:4] + #define MISC_DVFSCTL2_RG_ADA_MCK8X_EN_SHUFFLE Fld(1, 5) //[5:5] + #define MISC_DVFSCTL2_R_DVFS_DDRPHY_FSM_CLR Fld(1, 7) //[7:7] + #define MISC_DVFSCTL2_RG_MRW_AFTER_DFS Fld(1, 8) //[8:8] + #define MISC_DVFSCTL2_R_DVFS_CDC_OPTION Fld(1, 9) //[9:9] + #define MISC_DVFSCTL2_R_DVFS_PICG_MARGIN Fld(2, 10) //[11:10] + #define MISC_DVFSCTL2_R_DVFS_DLL_CHA Fld(1, 12) //[12:12] + #define MISC_DVFSCTL2_R_CDC_MUX_SEL_OPTION Fld(1, 13) //[13:13] + #define MISC_DVFSCTL2_R_DVFS_PARK_N Fld(1, 14) //[14:14] + #define MISC_DVFSCTL2_R_DVFS_OPTION Fld(1, 15) //[15:15] + #define MISC_DVFSCTL2_RG_PHY_ST_DELAY_BYPASS_CK_CHG_TO_MCLK Fld(1, 16) //[16:16] + #define MISC_DVFSCTL2_RG_PHY_ST_DELAY_BYPASS_CK_CHG_TO_BCLK Fld(1, 17) //[17:17] + #define MISC_DVFSCTL2_RG_PS_CLK_FREERUN Fld(1, 18) //[18:18] + #define MISC_DVFSCTL2_DVFS_SYNC_MASK_FOR_PHY Fld(1, 19) //[19:19] + #define MISC_DVFSCTL2_GT_SYNC_MASK_FOR_PHY Fld(1, 20) //[20:20] + #define MISC_DVFSCTL2_GTDMW_SYNC_MASK_FOR_PHY Fld(1, 21) //[21:21] + #define MISC_DVFSCTL2_R_DVFS_RG_CDC_TX_SEL Fld(1, 26) //[26:26] + #define MISC_DVFSCTL2_R_DVFS_RG_CDC_SYNC_ENABLE Fld(1, 27) //[27:27] + #define MISC_DVFSCTL2_R_SHU_RESTORE Fld(1, 28) //[28:28] + #define MISC_DVFSCTL2_R_DVFS_CLK_CHG_OK_SEL Fld(1, 29) //[29:29] + #define MISC_DVFSCTL2_R_DVFS_SYNC_MODULE_RST_SEL Fld(1, 31) //[31:31] + +#define DDRPHY_REG_MISC_DVFSCTL3 (DDRPHY_AO_BASE_ADDRESS + 0x0518) + #define MISC_DVFSCTL3_RG_DFS_BEF_PHY_SHU_DBG_EN Fld(1, 0) //[0:0] + #define MISC_DVFSCTL3_RG_DFS_AFT_PHY_SHU_DBG_EN Fld(1, 1) //[1:1] + #define MISC_DVFSCTL3_RG_PHY_ST_CHG_TO_MCLK_BY_LPC_EN Fld(1, 2) //[2:2] + #define MISC_DVFSCTL3_RG_PHY_ST_CHG_TO_BCLK_BY_LPC_EN Fld(1, 3) //[3:3] + #define MISC_DVFSCTL3_RG_PHY_ST_DELAY_AFT_CHG_TO_MCLK Fld(1, 4) //[4:4] + #define MISC_DVFSCTL3_RG_PHY_ST_DELAY_BEF_CHG_TO_MCLK Fld(1, 5) //[5:5] + #define MISC_DVFSCTL3_RG_PHY_ST_DELAY_AFT_CHG_TO_BCLK Fld(1, 6) //[6:6] + #define MISC_DVFSCTL3_RG_PHY_ST_DELAY_BEF_CHG_TO_BCLK Fld(1, 7) //[7:7] + #define MISC_DVFSCTL3_RG_DVFS_MEM_CK_SEL_DESTI Fld(2, 8) //[9:8] + #define MISC_DVFSCTL3_RG_DVFS_MEM_CK_SEL_SOURCE Fld(2, 10) //[11:10] + #define MISC_DVFSCTL3_RG_CNT_PHY_ST_DELAY_AFT_CHG_TO_MCLK Fld(6, 12) //[17:12] + #define MISC_DVFSCTL3_RG_CNT_PHY_ST_DELAY_BEF_CHG_TO_MCLK Fld(4, 18) //[21:18] + #define MISC_DVFSCTL3_RG_CNT_PHY_ST_DELAY_AFT_CHG_TO_BCLK Fld(6, 22) //[27:22] + #define MISC_DVFSCTL3_RG_CNT_PHY_ST_DELAY_BEF_CHG_TO_BCLK Fld(4, 28) //[31:28] + +#define DDRPHY_REG_MISC_CKMUX_SEL (DDRPHY_AO_BASE_ADDRESS + 0x051C) + #define MISC_CKMUX_SEL_R_PHYCTRLMUX Fld(1, 0) //[0:0] + #define MISC_CKMUX_SEL_R_PHYCTRLDCM Fld(1, 1) //[1:1] + #define MISC_CKMUX_SEL_R_DMMCTLPLL_CKSEL Fld(2, 4) //[5:4] + #define MISC_CKMUX_SEL_BCLK_SHU_SEL Fld(1, 8) //[8:8] + #define MISC_CKMUX_SEL_RG_52M_104M_SEL Fld(1, 12) //[12:12] + #define MISC_CKMUX_SEL_RG_104M_208M_SEL Fld(1, 13) //[13:13] + #define MISC_CKMUX_SEL_RG_FMEM_CK_OCC_FRC_EN Fld(1, 14) //[14:14] + #define MISC_CKMUX_SEL_RG_MEM_CLKMUX_REFCLK_SEL Fld(1, 15) //[15:15] + #define MISC_CKMUX_SEL_FB_CK_MUX Fld(2, 16) //[17:16] + #define MISC_CKMUX_SEL_FMEM_CK_MUX Fld(2, 18) //[19:18] + +#define DDRPHY_REG_MISC_CLK_CTRL (DDRPHY_AO_BASE_ADDRESS + 0x0520) + #define MISC_CLK_CTRL_DVFS_MEM_CK_MUX_UPDATE_EN Fld(1, 0) //[0:0] + #define MISC_CLK_CTRL_DVFS_CLK_MEM_SEL Fld(1, 1) //[1:1] + #define MISC_CLK_CTRL_DVFS_MEM_CK_MUX_UPDATE Fld(1, 8) //[8:8] + #define MISC_CLK_CTRL_DVFS_MEM_CK_MUX_SEL Fld(2, 9) //[10:9] + #define MISC_CLK_CTRL_DVFS_MEM_CK_MUX_SEL_MODE Fld(2, 12) //[13:12] + #define MISC_CLK_CTRL_RESERVED_MISC_CLK_CTRL_BIT31_4 Fld(18, 14) //[31:14] + +#define DDRPHY_REG_MISC_DQSG_RETRY1 (DDRPHY_AO_BASE_ADDRESS + 0x0524) + #define MISC_DQSG_RETRY1_R_RETRY_SAV_MSK Fld(1, 24) //[24:24] + #define MISC_DQSG_RETRY1_RETRY_DEBUG_RANK_SEL Fld(2, 28) //[29:28] + #define MISC_DQSG_RETRY1_RETRY_DEBUG_BYTE_SEL Fld(2, 30) //[31:30] + +#define DDRPHY_REG_MISC_RDSEL_TRACK (DDRPHY_AO_BASE_ADDRESS + 0x0528) + #define MISC_RDSEL_TRACK_RDSEL_SW_RST Fld(1, 0) //[0:0] + +#define DDRPHY_REG_MISC_PRE_TDQSCK1 (DDRPHY_AO_BASE_ADDRESS + 0x052C) + #define MISC_PRE_TDQSCK1_TDQSCK_HW_SW_UP_SEL Fld(1, 22) //[22:22] + #define MISC_PRE_TDQSCK1_TDQSCK_SW_UP_CASE Fld(1, 23) //[23:23] + #define MISC_PRE_TDQSCK1_TDQSCK_SW_SAVE Fld(1, 24) //[24:24] + #define MISC_PRE_TDQSCK1_TDQSCK_REG_DVFS Fld(1, 25) //[25:25] + #define MISC_PRE_TDQSCK1_TDQSCK_PRECAL_HW Fld(1, 26) //[26:26] + #define MISC_PRE_TDQSCK1_TDQSCK_PRECAL_START Fld(1, 27) //[27:27] + +#define DDRPHY_REG_MISC_CDC_CTRL (DDRPHY_AO_BASE_ADDRESS + 0x0530) + #define MISC_CDC_CTRL_RESERVED_MISC_CDC_CTRL_30_0 Fld(31, 0) //[30:0] + #define MISC_CDC_CTRL_REG_CDC_BYPASS_DBG Fld(1, 31) //[31:31] + +#define DDRPHY_REG_MISC_LP_CTRL (DDRPHY_AO_BASE_ADDRESS + 0x0534) + #define MISC_LP_CTRL_RG_ARDMSUS_10 Fld(1, 0) //[0:0] + #define MISC_LP_CTRL_RG_ARDMSUS_10_LP_SEL Fld(1, 1) //[1:1] + #define MISC_LP_CTRL_RG_RIMP_DMSUS_10 Fld(1, 2) //[2:2] + #define MISC_LP_CTRL_RG_RIMP_DMSUS_10_LP_SEL Fld(1, 3) //[3:3] + #define MISC_LP_CTRL_RG_RRESETB_LP_SEL Fld(1, 4) //[4:4] + #define MISC_LP_CTRL_RG_RPHYPLL_RESETB_LP_SEL Fld(1, 5) //[5:5] + #define MISC_LP_CTRL_RG_RPHYPLL_EN_LP_SEL Fld(1, 6) //[6:6] + #define MISC_LP_CTRL_RG_RCLRPLL_EN_LP_SEL Fld(1, 7) //[7:7] + #define MISC_LP_CTRL_RG_RPHYPLL_ADA_MCK8X_EN_LP_SEL Fld(1, 8) //[8:8] + #define MISC_LP_CTRL_RG_RPHYPLL_AD_MCK8X_EN_LP_SEL Fld(1, 9) //[9:9] + #define MISC_LP_CTRL_RG_RPHYPLL_TOP_REV_0_LP_SEL Fld(1, 10) //[10:10] + #define MISC_LP_CTRL_RG_SC_ARPI_RESETB_8X_SEQ_LP_SEL Fld(1, 11) //[11:11] + #define MISC_LP_CTRL_RG_ADA_MCK8X_8X_SEQ_LP_SEL Fld(1, 12) //[12:12] + #define MISC_LP_CTRL_RG_AD_MCK8X_8X_SEQ_LP_SEL Fld(1, 13) //[13:13] + #define MISC_LP_CTRL_RG_ADA_MCK8X_OP_LP_SEL Fld(1, 14) //[14:14] + #define MISC_LP_CTRL_RG_AD_MCK8X_OP_LP_SEL Fld(1, 15) //[15:15] + #define MISC_LP_CTRL_RG_RPHYPLL_DDR400_EN_LP_SEL Fld(1, 16) //[16:16] + #define MISC_LP_CTRL_RG_MIDPI_EN_8X_SEQ_LP_SEL Fld(1, 17) //[17:17] + #define MISC_LP_CTRL_RG_MIDPI_CKDIV4_EN_8X_SEQ_LP_SEL Fld(1, 18) //[18:18] + #define MISC_LP_CTRL_RG_MCK8X_CG_SRC_LP_SEL Fld(1, 19) //[19:19] + #define MISC_LP_CTRL_RG_MCK8X_CG_SRC_AND_LP_SEL Fld(1, 20) //[20:20] + #define MISC_LP_CTRL_RG_TX_RESETB_CTRL_OPT Fld(1, 21) //[21:21] + #define MISC_LP_CTRL_RESERVED_MISC_LP_CTRL_31_20 Fld(10, 22) //[31:22] + +#define DDRPHY_REG_MISC_RG_DFS_CTRL (DDRPHY_AO_BASE_ADDRESS + 0x0538) + #define MISC_RG_DFS_CTRL_SPM_DVFS_CONTROL_SEL Fld(1, 0) //[0:0] + #define MISC_RG_DFS_CTRL_RG_TX_TRACKING_DIS Fld(1, 1) //[1:1] + #define MISC_RG_DFS_CTRL_RG_DPY_RXDLY_TRACK_EN Fld(1, 2) //[2:2] + #define MISC_RG_DFS_CTRL_RG_DPY_PRECAL_UP Fld(1, 3) //[3:3] + #define MISC_RG_DFS_CTRL_RG_DR_SHU_LEVEL_SRAM Fld(4, 4) //[7:4] + #define MISC_RG_DFS_CTRL_RG_DR_SRAM_RESTORE Fld(1, 8) //[8:8] + #define MISC_RG_DFS_CTRL_RG_DR_SHU_LEVEL_SRAM_LATCH Fld(1, 9) //[9:9] + #define MISC_RG_DFS_CTRL_RG_DR_SRAM_LOAD Fld(1, 10) //[10:10] + #define MISC_RG_DFS_CTRL_RESERVED_MISC_RG_DFS_CTRL_11_11 Fld(1, 11) //[11:11] + #define MISC_RG_DFS_CTRL_RG_DPHY_RESERVED Fld(4, 12) //[15:12] + #define MISC_RG_DFS_CTRL_RG_DR_SHU_LEVEL Fld(2, 16) //[17:16] + #define MISC_RG_DFS_CTRL_RG_PHYPLL_SHU_EN Fld(1, 18) //[18:18] + #define MISC_RG_DFS_CTRL_RG_PHYPLL2_SHU_EN Fld(1, 19) //[19:19] + #define MISC_RG_DFS_CTRL_RG_PHYPLL_MODE_SW Fld(1, 20) //[20:20] + #define MISC_RG_DFS_CTRL_RG_PHYPLL2_MODE_SW Fld(1, 21) //[21:21] + #define MISC_RG_DFS_CTRL_RG_DR_SHORT_QUEUE Fld(1, 22) //[22:22] + #define MISC_RG_DFS_CTRL_RG_DR_SHU_EN Fld(1, 23) //[23:23] + #define MISC_RG_DFS_CTRL_RG_DDRPHY_FB_CK_EN Fld(1, 24) //[24:24] + #define MISC_RG_DFS_CTRL_RG_TX_TRACKING_RETRY_EN Fld(1, 25) //[25:25] + #define MISC_RG_DFS_CTRL_RG_RX_GATING_RETRY_EN Fld(1, 26) //[26:26] + #define MISC_RG_DFS_CTRL_RESERVED_MISC_RG_DFS_CTRL_31_27 Fld(5, 27) //[31:27] + +#define DDRPHY_REG_MISC_DDR_RESERVE (DDRPHY_AO_BASE_ADDRESS + 0x053C) + #define MISC_DDR_RESERVE_WDT_CONF_ISO_CNT Fld(8, 0) //[7:0] + #define MISC_DDR_RESERVE_WDT_ISO_CNT Fld(8, 8) //[15:8] + #define MISC_DDR_RESERVE_WDT_SREF_CNT Fld(8, 16) //[23:16] + #define MISC_DDR_RESERVE_WDT_SM_CLR Fld(1, 24) //[24:24] + #define MISC_DDR_RESERVE_WDT_LITE_EN Fld(1, 25) //[25:25] + +#define DDRPHY_REG_MISC_IMP_CTRL1 (DDRPHY_AO_BASE_ADDRESS + 0x0540) + #define MISC_IMP_CTRL1_RG_IMP_OCD_PUCMP_EN Fld(1, 0) //[0:0] + #define MISC_IMP_CTRL1_RG_IMP_EN Fld(1, 1) //[1:1] + #define MISC_IMP_CTRL1_RG_RIMP_DDR4_SEL Fld(1, 2) //[2:2] + #define MISC_IMP_CTRL1_RG_RIMP_DDR3_SEL Fld(1, 3) //[3:3] + #define MISC_IMP_CTRL1_RG_RIMP_BIAS_EN Fld(1, 4) //[4:4] + #define MISC_IMP_CTRL1_RG_RIMP_ODT_EN Fld(1, 5) //[5:5] + #define MISC_IMP_CTRL1_RG_RIMP_PRE_EN Fld(1, 6) //[6:6] + #define MISC_IMP_CTRL1_RG_RIMP_VREF_EN Fld(1, 7) //[7:7] + #define MISC_IMP_CTRL1_IMP_DIFF_THD Fld(5, 8) //[12:8] + #define MISC_IMP_CTRL1_IMP_ABN_LAT_CLR Fld(1, 14) //[14:14] + #define MISC_IMP_CTRL1_IMP_ABN_LAT_EN Fld(1, 15) //[15:15] + #define MISC_IMP_CTRL1_IMP_ABN_PRD Fld(12, 16) //[27:16] + #define MISC_IMP_CTRL1_IMP_CG_EN Fld(1, 30) //[30:30] + #define MISC_IMP_CTRL1_RG_RIMP_SUS_ECO_OPT Fld(1, 31) //[31:31] + +#define DDRPHY_REG_MISC_IMPCAL (DDRPHY_AO_BASE_ADDRESS + 0x0544) + #define MISC_IMPCAL_DRVCGWREF Fld(1, 2) //[2:2] + #define MISC_IMPCAL_DQDRVSWUPD Fld(1, 3) //[3:3] + #define MISC_IMPCAL_IMPSRCEXT Fld(1, 4) //[4:4] + #define MISC_IMPCAL_IMPBINARY Fld(1, 5) //[5:5] + #define MISC_IMPCAL_DRV_ECO_OPT Fld(1, 10) //[10:10] + #define MISC_IMPCAL_IMPCAL_CHGDRV_ECO_OPT Fld(1, 11) //[11:11] + #define MISC_IMPCAL_IMPCAL_SM_ECO_OPT Fld(1, 12) //[12:12] + #define MISC_IMPCAL_IMPCAL_ECO_OPT Fld(1, 13) //[13:13] + #define MISC_IMPCAL_DIS_SUS_CH1_DRV Fld(1, 14) //[14:14] + #define MISC_IMPCAL_DIS_SUS_CH0_DRV Fld(1, 15) //[15:15] + #define MISC_IMPCAL_DIS_SHU_DRV Fld(1, 16) //[16:16] + #define MISC_IMPCAL_IMPCAL_DRVUPDOPT Fld(1, 17) //[17:17] + #define MISC_IMPCAL_IMPCAL_USING_SYNC Fld(1, 18) //[18:18] + #define MISC_IMPCAL_IMPCAL_BYPASS_UP_CA_DRV Fld(1, 19) //[19:19] + #define MISC_IMPCAL_IMPCAL_HWSAVE_EN Fld(1, 20) //[20:20] + #define MISC_IMPCAL_IMPCAL_CALI_ENN Fld(1, 21) //[21:21] + #define MISC_IMPCAL_IMPCAL_CALI_ENP Fld(1, 22) //[22:22] + #define MISC_IMPCAL_IMPCAL_CALI_EN Fld(1, 23) //[23:23] + #define MISC_IMPCAL_IMPCAL_IMPPDN Fld(1, 24) //[24:24] + #define MISC_IMPCAL_IMPCAL_IMPPDP Fld(1, 25) //[25:25] + #define MISC_IMPCAL_IMPCAL_NEW_OLD_SL Fld(1, 26) //[26:26] + #define MISC_IMPCAL_IMPCAL_CMP_DIREC Fld(2, 27) //[28:27] + #define MISC_IMPCAL_IMPCAL_SWVALUE_EN Fld(1, 29) //[29:29] + #define MISC_IMPCAL_IMPCAL_EN Fld(1, 30) //[30:30] + #define MISC_IMPCAL_IMPCAL_HW Fld(1, 31) //[31:31] + +#define DDRPHY_REG_MISC_IMPCAL1 (DDRPHY_AO_BASE_ADDRESS + 0x0548) + #define MISC_IMPCAL1_IMPCAL_RSV Fld(32, 0) //[31:0] + +#define DDRPHY_REG_MISC_IMPEDAMCE_CTRL1 (DDRPHY_AO_BASE_ADDRESS + 0x054C) + #define MISC_IMPEDAMCE_CTRL1_DQS1_OFF Fld(10, 0) //[9:0] + #define MISC_IMPEDAMCE_CTRL1_DOS2_OFF Fld(10, 10) //[19:10] + #define MISC_IMPEDAMCE_CTRL1_DQS1_OFF_SUB Fld(2, 28) //[29:28] + #define MISC_IMPEDAMCE_CTRL1_DQS2_OFF_SUB Fld(2, 30) //[31:30] + +#define DDRPHY_REG_MISC_IMPEDAMCE_CTRL2 (DDRPHY_AO_BASE_ADDRESS + 0x0550) + #define MISC_IMPEDAMCE_CTRL2_DQ1_OFF Fld(10, 0) //[9:0] + #define MISC_IMPEDAMCE_CTRL2_DQ2_OFF Fld(10, 10) //[19:10] + #define MISC_IMPEDAMCE_CTRL2_DQ1_OFF_SUB Fld(2, 28) //[29:28] + #define MISC_IMPEDAMCE_CTRL2_DQ2_OFF_SUB Fld(2, 30) //[31:30] + +#define DDRPHY_REG_MISC_IMPEDAMCE_CTRL3 (DDRPHY_AO_BASE_ADDRESS + 0x0554) + #define MISC_IMPEDAMCE_CTRL3_CMD1_OFF Fld(10, 0) //[9:0] + #define MISC_IMPEDAMCE_CTRL3_CMD2_OFF Fld(10, 10) //[19:10] + #define MISC_IMPEDAMCE_CTRL3_CMD1_OFF_SUB Fld(2, 28) //[29:28] + #define MISC_IMPEDAMCE_CTRL3_CMD2_OFF_SUB Fld(2, 30) //[31:30] + +#define DDRPHY_REG_MISC_IMPEDAMCE_CTRL4 (DDRPHY_AO_BASE_ADDRESS + 0x0558) + #define MISC_IMPEDAMCE_CTRL4_DQC1_OFF Fld(10, 0) //[9:0] + #define MISC_IMPEDAMCE_CTRL4_DQC2_OFF Fld(10, 10) //[19:10] + #define MISC_IMPEDAMCE_CTRL4_DQC1_OFF_SUB Fld(2, 28) //[29:28] + #define MISC_IMPEDAMCE_CTRL4_DQC2_OFF_SUB Fld(2, 30) //[31:30] + +#define DDRPHY_REG_MISC_PERIPHER_CTRL2 (DDRPHY_AO_BASE_ADDRESS + 0x055C) + #define MISC_PERIPHER_CTRL2_APB_WRITE_MASK_EN Fld(1, 0) //[0:0] + #define MISC_PERIPHER_CTRL2_R_SW_RXFIFO_RDSEL_BUS Fld(4, 27) //[30:27] + #define MISC_PERIPHER_CTRL2_R_SW_RXFIFO_RDSEL_EN Fld(1, 31) //[31:31] + +#define DDRPHY_REG_MISC_APB (DDRPHY_AO_BASE_ADDRESS + 0x0560) + #define MISC_APB_APB_ARB_SW_KEEP Fld(1, 30) //[30:30] + #define MISC_APB_SRAM_ARB_SW_KEEP Fld(1, 31) //[31:31] + +#define DDRPHY_REG_MISC_EXTLB0 (DDRPHY_AO_BASE_ADDRESS + 0x0564) + #define MISC_EXTLB0_EXTLB_LFSR_INI_1 Fld(16, 16) //[31:16] + #define MISC_EXTLB0_EXTLB_LFSR_INI_0 Fld(16, 0) //[15:0] + +#define DDRPHY_REG_MISC_EXTLB1 (DDRPHY_AO_BASE_ADDRESS + 0x0568) + #define MISC_EXTLB1_EXTLB_LFSR_INI_3 Fld(16, 16) //[31:16] + #define MISC_EXTLB1_EXTLB_LFSR_INI_2 Fld(16, 0) //[15:0] + +#define DDRPHY_REG_MISC_EXTLB2 (DDRPHY_AO_BASE_ADDRESS + 0x056C) + #define MISC_EXTLB2_EXTLB_LFSR_INI_5 Fld(16, 16) //[31:16] + #define MISC_EXTLB2_EXTLB_LFSR_INI_4 Fld(16, 0) //[15:0] + +#define DDRPHY_REG_MISC_EXTLB3 (DDRPHY_AO_BASE_ADDRESS + 0x0570) + #define MISC_EXTLB3_EXTLB_LFSR_INI_7 Fld(16, 16) //[31:16] + #define MISC_EXTLB3_EXTLB_LFSR_INI_6 Fld(16, 0) //[15:0] + +#define DDRPHY_REG_MISC_EXTLB4 (DDRPHY_AO_BASE_ADDRESS + 0x0574) + #define MISC_EXTLB4_EXTLB_LFSR_INI_9 Fld(16, 16) //[31:16] + #define MISC_EXTLB4_EXTLB_LFSR_INI_8 Fld(16, 0) //[15:0] + +#define DDRPHY_REG_MISC_EXTLB5 (DDRPHY_AO_BASE_ADDRESS + 0x0578) + #define MISC_EXTLB5_EXTLB_LFSR_INI_11 Fld(16, 16) //[31:16] + #define MISC_EXTLB5_EXTLB_LFSR_INI_10 Fld(16, 0) //[15:0] + +#define DDRPHY_REG_MISC_EXTLB6 (DDRPHY_AO_BASE_ADDRESS + 0x057C) + #define MISC_EXTLB6_EXTLB_LFSR_INI_13 Fld(16, 16) //[31:16] + #define MISC_EXTLB6_EXTLB_LFSR_INI_12 Fld(16, 0) //[15:0] + +#define DDRPHY_REG_MISC_EXTLB7 (DDRPHY_AO_BASE_ADDRESS + 0x0580) + #define MISC_EXTLB7_EXTLB_LFSR_INI_15 Fld(16, 16) //[31:16] + #define MISC_EXTLB7_EXTLB_LFSR_INI_14 Fld(16, 0) //[15:0] + +#define DDRPHY_REG_MISC_EXTLB8 (DDRPHY_AO_BASE_ADDRESS + 0x0584) + #define MISC_EXTLB8_EXTLB_LFSR_INI_17 Fld(16, 16) //[31:16] + #define MISC_EXTLB8_EXTLB_LFSR_INI_16 Fld(16, 0) //[15:0] + +#define DDRPHY_REG_MISC_EXTLB9 (DDRPHY_AO_BASE_ADDRESS + 0x0588) + #define MISC_EXTLB9_EXTLB_LFSR_INI_19 Fld(16, 16) //[31:16] + #define MISC_EXTLB9_EXTLB_LFSR_INI_18 Fld(16, 0) //[15:0] + +#define DDRPHY_REG_MISC_EXTLB10 (DDRPHY_AO_BASE_ADDRESS + 0x058C) + #define MISC_EXTLB10_EXTLB_LFSR_INI_21 Fld(16, 16) //[31:16] + #define MISC_EXTLB10_EXTLB_LFSR_INI_20 Fld(16, 0) //[15:0] + +#define DDRPHY_REG_MISC_EXTLB11 (DDRPHY_AO_BASE_ADDRESS + 0x0590) + #define MISC_EXTLB11_EXTLB_LFSR_INI_23 Fld(16, 16) //[31:16] + #define MISC_EXTLB11_EXTLB_LFSR_INI_22 Fld(16, 0) //[15:0] + +#define DDRPHY_REG_MISC_EXTLB12 (DDRPHY_AO_BASE_ADDRESS + 0x0594) + #define MISC_EXTLB12_EXTLB_LFSR_INI_25 Fld(16, 16) //[31:16] + #define MISC_EXTLB12_EXTLB_LFSR_INI_24 Fld(16, 0) //[15:0] + +#define DDRPHY_REG_MISC_EXTLB13 (DDRPHY_AO_BASE_ADDRESS + 0x0598) + #define MISC_EXTLB13_EXTLB_LFSR_INI_27 Fld(16, 16) //[31:16] + #define MISC_EXTLB13_EXTLB_LFSR_INI_26 Fld(16, 0) //[15:0] + +#define DDRPHY_REG_MISC_EXTLB14 (DDRPHY_AO_BASE_ADDRESS + 0x059C) + #define MISC_EXTLB14_EXTLB_LFSR_INI_29 Fld(16, 16) //[31:16] + #define MISC_EXTLB14_EXTLB_LFSR_INI_28 Fld(16, 0) //[15:0] + +#define DDRPHY_REG_MISC_EXTLB15 (DDRPHY_AO_BASE_ADDRESS + 0x05A0) + #define MISC_EXTLB15_EXTLB_LFSR_INI_30 Fld(16, 0) //[15:0] + #define MISC_EXTLB15_EXTLB_LFSR_INI_31 Fld(16, 16) //[31:16] + +#define DDRPHY_REG_MISC_EXTLB16 (DDRPHY_AO_BASE_ADDRESS + 0x05A4) + #define MISC_EXTLB16_EXTLB_ODTEN_DQS1_ON Fld(1, 27) //[27:27] + #define MISC_EXTLB16_EXTLB_ODTEN_DQM1_ON Fld(1, 26) //[26:26] + #define MISC_EXTLB16_EXTLB_ODTEN_DQB1_ON Fld(1, 25) //[25:25] + #define MISC_EXTLB16_EXTLB_ODTEN_DQS0_ON Fld(1, 24) //[24:24] + #define MISC_EXTLB16_EXTLB_ODTEN_DQM0_ON Fld(1, 23) //[23:23] + #define MISC_EXTLB16_EXTLB_ODTEN_DQB0_ON Fld(1, 22) //[22:22] + #define MISC_EXTLB16_EXTLB_OE_DQS1_ON Fld(1, 21) //[21:21] + #define MISC_EXTLB16_EXTLB_OE_DQM1_ON Fld(1, 20) //[20:20] + #define MISC_EXTLB16_EXTLB_OE_DQB1_ON Fld(1, 19) //[19:19] + #define MISC_EXTLB16_EXTLB_OE_DQS0_ON Fld(1, 18) //[18:18] + #define MISC_EXTLB16_EXTLB_OE_DQM0_ON Fld(1, 17) //[17:17] + #define MISC_EXTLB16_EXTLB_OE_DQB0_ON Fld(1, 16) //[16:16] + #define MISC_EXTLB16_EXTLB_LFSR_TAP Fld(16, 0) //[15:0] + +#define DDRPHY_REG_MISC_EXTLB17 (DDRPHY_AO_BASE_ADDRESS + 0x05A8) + #define MISC_EXTLB17_EXTLB_RX_LENGTH_M1 Fld(24, 8) //[31:8] + #define MISC_EXTLB17_EXTLB_TX_PRE_ON Fld(1, 7) //[7:7] + #define MISC_EXTLB17_INTLB_DRDF_CA_MUXSEL Fld(1, 5) //[5:5] + #define MISC_EXTLB17_INTLB_ARCLK_MUXSEL Fld(1, 4) //[4:4] + #define MISC_EXTLB17_EXTLB_TX_EN_OTHERCH_SEL Fld(1, 3) //[3:3] + #define MISC_EXTLB17_EXTLB_TX_EN Fld(1, 2) //[2:2] + #define MISC_EXTLB17_EXTLB_RX_SWRST Fld(1, 1) //[1:1] + #define MISC_EXTLB17_EXTLB Fld(1, 0) //[0:0] + +#define DDRPHY_REG_MISC_EXTLB18 (DDRPHY_AO_BASE_ADDRESS + 0x05AC) + #define MISC_EXTLB18_TX_EN_SRC_SEL Fld(1, 0) //[0:0] + #define MISC_EXTLB18_OTH_TX_EN_SRC_SEL Fld(1, 1) //[1:1] + #define MISC_EXTLB18_LPBK_DQ_MODE_FOCA Fld(1, 3) //[3:3] + #define MISC_EXTLB18_LPBK_DQ_TX_MODE Fld(1, 4) //[4:4] + #define MISC_EXTLB18_LPBK_CA_TX_MODE Fld(1, 5) //[5:5] + #define MISC_EXTLB18_LPBK_DQ_RX_MODE Fld(1, 8) //[8:8] + #define MISC_EXTLB18_LPBK_CA_RX_MODE Fld(1, 9) //[9:9] + #define MISC_EXTLB18_TX_TRIG_SRC_SEL Fld(4, 16) //[19:16] + #define MISC_EXTLB18_OTH_TX_TRIG_SRC_SEL Fld(4, 20) //[23:20] + +#define DDRPHY_REG_MISC_EXTLB19 (DDRPHY_AO_BASE_ADDRESS + 0x05B0) + #define MISC_EXTLB19_EXTLB_LFSR_ENABLE Fld(1, 0) //[0:0] + #define MISC_EXTLB19_EXTLB_SSO_ENABLE Fld(1, 1) //[1:1] + #define MISC_EXTLB19_EXTLB_XTALK_ENABLE Fld(1, 2) //[2:2] + #define MISC_EXTLB19_EXTLB_LEADLAG_DBG_ENABLE Fld(1, 3) //[3:3] + #define MISC_EXTLB19_EXTLB_DBG_SEL Fld(5, 16) //[20:16] + #define MISC_EXTLB19_EXTLB_LFSR_EXTEND_INV Fld(1, 21) //[21:21] + #define MISC_EXTLB19_LPBK_DC_TOG_MODE Fld(1, 23) //[23:23] + #define MISC_EXTLB19_LPBK_DC_TOG_TIMER Fld(8, 24) //[31:24] + +#define DDRPHY_REG_MISC_EXTLB20 (DDRPHY_AO_BASE_ADDRESS + 0x05B4) + #define MISC_EXTLB20_XTALK_TX_00_TOG_CYCLE Fld(4, 0) //[3:0] + #define MISC_EXTLB20_XTALK_TX_01_TOG_CYCLE Fld(4, 4) //[7:4] + #define MISC_EXTLB20_XTALK_TX_02_TOG_CYCLE Fld(4, 8) //[11:8] + #define MISC_EXTLB20_XTALK_TX_03_TOG_CYCLE Fld(4, 12) //[15:12] + #define MISC_EXTLB20_XTALK_TX_04_TOG_CYCLE Fld(4, 16) //[19:16] + #define MISC_EXTLB20_XTALK_TX_05_TOG_CYCLE Fld(4, 20) //[23:20] + #define MISC_EXTLB20_XTALK_TX_06_TOG_CYCLE Fld(4, 24) //[27:24] + #define MISC_EXTLB20_XTALK_TX_07_TOG_CYCLE Fld(4, 28) //[31:28] + +#define DDRPHY_REG_MISC_EXTLB21 (DDRPHY_AO_BASE_ADDRESS + 0x05B8) + #define MISC_EXTLB21_XTALK_TX_08_TOG_CYCLE Fld(4, 0) //[3:0] + #define MISC_EXTLB21_XTALK_TX_09_TOG_CYCLE Fld(4, 4) //[7:4] + #define MISC_EXTLB21_XTALK_TX_10_TOG_CYCLE Fld(4, 8) //[11:8] + #define MISC_EXTLB21_XTALK_TX_11_TOG_CYCLE Fld(4, 12) //[15:12] + #define MISC_EXTLB21_XTALK_TX_12_TOG_CYCLE Fld(4, 16) //[19:16] + #define MISC_EXTLB21_XTALK_TX_13_TOG_CYCLE Fld(4, 20) //[23:20] + #define MISC_EXTLB21_XTALK_TX_14_TOG_CYCLE Fld(4, 24) //[27:24] + #define MISC_EXTLB21_XTALK_TX_15_TOG_CYCLE Fld(4, 28) //[31:28] + +#define DDRPHY_REG_MISC_EXTLB22 (DDRPHY_AO_BASE_ADDRESS + 0x05BC) + #define MISC_EXTLB22_XTALK_TX_16_TOG_CYCLE Fld(4, 0) //[3:0] + #define MISC_EXTLB22_XTALK_TX_17_TOG_CYCLE Fld(4, 4) //[7:4] + #define MISC_EXTLB22_XTALK_TX_18_TOG_CYCLE Fld(4, 8) //[11:8] + #define MISC_EXTLB22_XTALK_TX_19_TOG_CYCLE Fld(4, 12) //[15:12] + #define MISC_EXTLB22_XTALK_TX_20_TOG_CYCLE Fld(4, 16) //[19:16] + #define MISC_EXTLB22_XTALK_TX_21_TOG_CYCLE Fld(4, 20) //[23:20] + #define MISC_EXTLB22_XTALK_TX_22_TOG_CYCLE Fld(4, 24) //[27:24] + #define MISC_EXTLB22_XTALK_TX_23_TOG_CYCLE Fld(4, 28) //[31:28] + +#define DDRPHY_REG_MISC_EXTLB23 (DDRPHY_AO_BASE_ADDRESS + 0x05C0) + #define MISC_EXTLB23_XTALK_TX_24_TOG_CYCLE Fld(4, 0) //[3:0] + #define MISC_EXTLB23_XTALK_TX_25_TOG_CYCLE Fld(4, 4) //[7:4] + #define MISC_EXTLB23_XTALK_TX_26_TOG_CYCLE Fld(4, 8) //[11:8] + #define MISC_EXTLB23_XTALK_TX_27_TOG_CYCLE Fld(4, 12) //[15:12] + #define MISC_EXTLB23_XTALK_TX_28_TOG_CYCLE Fld(4, 16) //[19:16] + #define MISC_EXTLB23_XTALK_TX_29_TOG_CYCLE Fld(4, 20) //[23:20] + #define MISC_EXTLB23_XTALK_TX_30_TOG_CYCLE Fld(4, 24) //[27:24] + #define MISC_EXTLB23_XTALK_TX_31_TOG_CYCLE Fld(4, 28) //[31:28] + +#define DDRPHY_REG_MISC_EXTLB_RX0 (DDRPHY_AO_BASE_ADDRESS + 0x05C4) + #define MISC_EXTLB_RX0_EXTLB_LFSR_RX_INI_1 Fld(16, 16) //[31:16] + #define MISC_EXTLB_RX0_EXTLB_LFSR_RX_INI_0 Fld(16, 0) //[15:0] + +#define DDRPHY_REG_MISC_EXTLB_RX1 (DDRPHY_AO_BASE_ADDRESS + 0x05C8) + #define MISC_EXTLB_RX1_EXTLB_LFSR_RX_INI_3 Fld(16, 16) //[31:16] + #define MISC_EXTLB_RX1_EXTLB_LFSR_RX_INI_2 Fld(16, 0) //[15:0] + +#define DDRPHY_REG_MISC_EXTLB_RX2 (DDRPHY_AO_BASE_ADDRESS + 0x05CC) + #define MISC_EXTLB_RX2_EXTLB_LFSR_RX_INI_5 Fld(16, 16) //[31:16] + #define MISC_EXTLB_RX2_EXTLB_LFSR_RX_INI_4 Fld(16, 0) //[15:0] + +#define DDRPHY_REG_MISC_EXTLB_RX3 (DDRPHY_AO_BASE_ADDRESS + 0x05D0) + #define MISC_EXTLB_RX3_EXTLB_LFSR_RX_INI_7 Fld(16, 16) //[31:16] + #define MISC_EXTLB_RX3_EXTLB_LFSR_RX_INI_6 Fld(16, 0) //[15:0] + +#define DDRPHY_REG_MISC_EXTLB_RX4 (DDRPHY_AO_BASE_ADDRESS + 0x05D4) + #define MISC_EXTLB_RX4_EXTLB_LFSR_RX_INI_9 Fld(16, 16) //[31:16] + #define MISC_EXTLB_RX4_EXTLB_LFSR_RX_INI_8 Fld(16, 0) //[15:0] + +#define DDRPHY_REG_MISC_EXTLB_RX5 (DDRPHY_AO_BASE_ADDRESS + 0x05D8) + #define MISC_EXTLB_RX5_EXTLB_LFSR_RX_INI_11 Fld(16, 16) //[31:16] + #define MISC_EXTLB_RX5_EXTLB_LFSR_RX_INI_10 Fld(16, 0) //[15:0] + +#define DDRPHY_REG_MISC_EXTLB_RX6 (DDRPHY_AO_BASE_ADDRESS + 0x05DC) + #define MISC_EXTLB_RX6_EXTLB_LFSR_RX_INI_13 Fld(16, 16) //[31:16] + #define MISC_EXTLB_RX6_EXTLB_LFSR_RX_INI_12 Fld(16, 0) //[15:0] + +#define DDRPHY_REG_MISC_EXTLB_RX7 (DDRPHY_AO_BASE_ADDRESS + 0x05E0) + #define MISC_EXTLB_RX7_EXTLB_LFSR_RX_INI_15 Fld(16, 16) //[31:16] + #define MISC_EXTLB_RX7_EXTLB_LFSR_RX_INI_14 Fld(16, 0) //[15:0] + +#define DDRPHY_REG_MISC_EXTLB_RX8 (DDRPHY_AO_BASE_ADDRESS + 0x05E4) + #define MISC_EXTLB_RX8_EXTLB_LFSR_RX_INI_17 Fld(16, 16) //[31:16] + #define MISC_EXTLB_RX8_EXTLB_LFSR_RX_INI_16 Fld(16, 0) //[15:0] + +#define DDRPHY_REG_MISC_EXTLB_RX9 (DDRPHY_AO_BASE_ADDRESS + 0x05E8) + #define MISC_EXTLB_RX9_EXTLB_LFSR_RX_INI_19 Fld(16, 16) //[31:16] + #define MISC_EXTLB_RX9_EXTLB_LFSR_RX_INI_18 Fld(16, 0) //[15:0] + +#define DDRPHY_REG_MISC_EXTLB_RX10 (DDRPHY_AO_BASE_ADDRESS + 0x05EC) + #define MISC_EXTLB_RX10_EXTLB_LFSR_RX_INI_21 Fld(16, 16) //[31:16] + #define MISC_EXTLB_RX10_EXTLB_LFSR_RX_INI_20 Fld(16, 0) //[15:0] + +#define DDRPHY_REG_MISC_EXTLB_RX11 (DDRPHY_AO_BASE_ADDRESS + 0x05F0) + #define MISC_EXTLB_RX11_EXTLB_LFSR_RX_INI_23 Fld(16, 16) //[31:16] + #define MISC_EXTLB_RX11_EXTLB_LFSR_RX_INI_22 Fld(16, 0) //[15:0] + +#define DDRPHY_REG_MISC_EXTLB_RX12 (DDRPHY_AO_BASE_ADDRESS + 0x05F4) + #define MISC_EXTLB_RX12_EXTLB_LFSR_RX_INI_25 Fld(16, 16) //[31:16] + #define MISC_EXTLB_RX12_EXTLB_LFSR_RX_INI_24 Fld(16, 0) //[15:0] + +#define DDRPHY_REG_MISC_EXTLB_RX13 (DDRPHY_AO_BASE_ADDRESS + 0x05F8) + #define MISC_EXTLB_RX13_EXTLB_LFSR_RX_INI_27 Fld(16, 16) //[31:16] + #define MISC_EXTLB_RX13_EXTLB_LFSR_RX_INI_26 Fld(16, 0) //[15:0] + +#define DDRPHY_REG_MISC_EXTLB_RX14 (DDRPHY_AO_BASE_ADDRESS + 0x05FC) + #define MISC_EXTLB_RX14_EXTLB_LFSR_RX_INI_29 Fld(16, 16) //[31:16] + #define MISC_EXTLB_RX14_EXTLB_LFSR_RX_INI_28 Fld(16, 0) //[15:0] + +#define DDRPHY_REG_MISC_EXTLB_RX15 (DDRPHY_AO_BASE_ADDRESS + 0x0600) + #define MISC_EXTLB_RX15_EXTLB_LFSR_RX_INI_30 Fld(16, 0) //[15:0] + #define MISC_EXTLB_RX15_EXTLB_LFSR_RX_INI_31 Fld(16, 16) //[31:16] + +#define DDRPHY_REG_MISC_EXTLB_RX16 (DDRPHY_AO_BASE_ADDRESS + 0x0604) + #define MISC_EXTLB_RX16_EXTLB_RX_GATE_DELSEL_DQB0 Fld(7, 0) //[6:0] + #define MISC_EXTLB_RX16_EXTLB_RX_GATE_DELSEL_DQB1 Fld(7, 8) //[14:8] + #define MISC_EXTLB_RX16_EXTLB_RX_GATE_DELSEL_CA Fld(7, 16) //[22:16] + +#define DDRPHY_REG_MISC_EXTLB_RX17 (DDRPHY_AO_BASE_ADDRESS + 0x0608) + #define MISC_EXTLB_RX17_XTALK_RX_00_TOG_CYCLE Fld(4, 0) //[3:0] + #define MISC_EXTLB_RX17_XTALK_RX_01_TOG_CYCLE Fld(4, 4) //[7:4] + #define MISC_EXTLB_RX17_XTALK_RX_02_TOG_CYCLE Fld(4, 8) //[11:8] + #define MISC_EXTLB_RX17_XTALK_RX_03_TOG_CYCLE Fld(4, 12) //[15:12] + #define MISC_EXTLB_RX17_XTALK_RX_04_TOG_CYCLE Fld(4, 16) //[19:16] + #define MISC_EXTLB_RX17_XTALK_RX_05_TOG_CYCLE Fld(4, 20) //[23:20] + #define MISC_EXTLB_RX17_XTALK_RX_06_TOG_CYCLE Fld(4, 24) //[27:24] + #define MISC_EXTLB_RX17_XTALK_RX_07_TOG_CYCLE Fld(4, 28) //[31:28] + +#define DDRPHY_REG_MISC_EXTLB_RX18 (DDRPHY_AO_BASE_ADDRESS + 0x060C) + #define MISC_EXTLB_RX18_XTALK_RX_08_TOG_CYCLE Fld(4, 0) //[3:0] + #define MISC_EXTLB_RX18_XTALK_RX_09_TOG_CYCLE Fld(4, 4) //[7:4] + #define MISC_EXTLB_RX18_XTALK_RX_10_TOG_CYCLE Fld(4, 8) //[11:8] + #define MISC_EXTLB_RX18_XTALK_RX_11_TOG_CYCLE Fld(4, 12) //[15:12] + #define MISC_EXTLB_RX18_XTALK_RX_12_TOG_CYCLE Fld(4, 16) //[19:16] + #define MISC_EXTLB_RX18_XTALK_RX_13_TOG_CYCLE Fld(4, 20) //[23:20] + #define MISC_EXTLB_RX18_XTALK_RX_14_TOG_CYCLE Fld(4, 24) //[27:24] + #define MISC_EXTLB_RX18_XTALK_RX_15_TOG_CYCLE Fld(4, 28) //[31:28] + +#define DDRPHY_REG_MISC_EXTLB_RX19 (DDRPHY_AO_BASE_ADDRESS + 0x0610) + #define MISC_EXTLB_RX19_XTALK_RX_16_TOG_CYCLE Fld(4, 0) //[3:0] + #define MISC_EXTLB_RX19_XTALK_RX_17_TOG_CYCLE Fld(4, 4) //[7:4] + #define MISC_EXTLB_RX19_XTALK_RX_18_TOG_CYCLE Fld(4, 8) //[11:8] + #define MISC_EXTLB_RX19_XTALK_RX_19_TOG_CYCLE Fld(4, 12) //[15:12] + #define MISC_EXTLB_RX19_XTALK_RX_20_TOG_CYCLE Fld(4, 16) //[19:16] + #define MISC_EXTLB_RX19_XTALK_RX_21_TOG_CYCLE Fld(4, 20) //[23:20] + #define MISC_EXTLB_RX19_XTALK_RX_22_TOG_CYCLE Fld(4, 24) //[27:24] + #define MISC_EXTLB_RX19_XTALK_RX_23_TOG_CYCLE Fld(4, 28) //[31:28] + +#define DDRPHY_REG_MISC_EXTLB_RX20 (DDRPHY_AO_BASE_ADDRESS + 0x0614) + #define MISC_EXTLB_RX20_XTALK_RX_24_TOG_CYCLE Fld(4, 0) //[3:0] + #define MISC_EXTLB_RX20_XTALK_RX_25_TOG_CYCLE Fld(4, 4) //[7:4] + #define MISC_EXTLB_RX20_XTALK_RX_26_TOG_CYCLE Fld(4, 8) //[11:8] + #define MISC_EXTLB_RX20_XTALK_RX_27_TOG_CYCLE Fld(4, 12) //[15:12] + #define MISC_EXTLB_RX20_XTALK_RX_28_TOG_CYCLE Fld(4, 16) //[19:16] + #define MISC_EXTLB_RX20_XTALK_RX_29_TOG_CYCLE Fld(4, 20) //[23:20] + #define MISC_EXTLB_RX20_XTALK_RX_30_TOG_CYCLE Fld(4, 24) //[27:24] + #define MISC_EXTLB_RX20_XTALK_RX_31_TOG_CYCLE Fld(4, 28) //[31:28] + +#define DDRPHY_REG_MISC_SRAM_DMA0 (DDRPHY_AO_BASE_ADDRESS + 0x0618) + #define MISC_SRAM_DMA0_SW_DMA_FIRE Fld(1, 0) //[0:0] + #define MISC_SRAM_DMA0_SW_MODE Fld(1, 1) //[1:1] + #define MISC_SRAM_DMA0_APB_WR_MODE Fld(1, 2) //[2:2] + #define MISC_SRAM_DMA0_SRAM_WR_MODE Fld(1, 3) //[3:3] + #define MISC_SRAM_DMA0_SW_SHU_LEVEL_SRAM Fld(4, 4) //[7:4] + #define MISC_SRAM_DMA0_SW_SHU_LEVEL_APB Fld(4, 8) //[11:8] + #define MISC_SRAM_DMA0_PENABLE_LAT_RD Fld(2, 12) //[13:12] + #define MISC_SRAM_DMA0_PENABLE_LAT_WR Fld(2, 14) //[15:14] + #define MISC_SRAM_DMA0_KEEP_SRAM_ARB_ENA Fld(1, 16) //[16:16] + #define MISC_SRAM_DMA0_KEEP_APB_ARB_ENA Fld(1, 17) //[17:17] + #define MISC_SRAM_DMA0_DMA_TIMER_EN Fld(1, 18) //[18:18] + #define MISC_SRAM_DMA0_EARLY_ACK_ENA Fld(1, 20) //[20:20] + #define MISC_SRAM_DMA0_SPM_CTR_APB_LEVEL Fld(1, 21) //[21:21] + #define MISC_SRAM_DMA0_SPM_CTR_RESTORE Fld(1, 22) //[22:22] + #define MISC_SRAM_DMA0_SW_STEP_EN_MODE Fld(1, 23) //[23:23] + #define MISC_SRAM_DMA0_DMA_CLK_FORCE_ON Fld(1, 24) //[24:24] + #define MISC_SRAM_DMA0_DMA_CLK_FORCE_OFF Fld(1, 25) //[25:25] + #define MISC_SRAM_DMA0_APB_SLV_SEL Fld(2, 28) //[29:28] + +#define DDRPHY_REG_MISC_SRAM_DMA1 (DDRPHY_AO_BASE_ADDRESS + 0x061C) + #define MISC_SRAM_DMA1_SPM_RESTORE_STEP_EN Fld(17, 0) //[16:0] + #define MISC_SRAM_DMA1_R_APB_DMA_DBG_ACCESS Fld(1, 19) //[19:19] + #define MISC_SRAM_DMA1_R_APB_DMA_DBG_LEVEL Fld(4, 20) //[23:20] + #define MISC_SRAM_DMA1_PLL_REG_LENGTH Fld(7, 24) //[30:24] + +#define DDRPHY_REG_MISC_SRAM_DMA2 (DDRPHY_AO_BASE_ADDRESS + 0x0620) + #define MISC_SRAM_DMA2_SW_DMA_STEP_EN Fld(17, 0) //[16:0] + +#define DDRPHY_REG_MISC_DUTYSCAN1 (DDRPHY_AO_BASE_ADDRESS + 0x0624) + #define MISC_DUTYSCAN1_REG_SW_RST Fld(1, 0) //[0:0] + #define MISC_DUTYSCAN1_RX_EYE_SCAN_EN Fld(1, 1) //[1:1] + #define MISC_DUTYSCAN1_RX_MIOCK_JIT_EN Fld(1, 2) //[2:2] + #define MISC_DUTYSCAN1_RX_EYE_SCAN_CG_EN Fld(1, 3) //[3:3] + #define MISC_DUTYSCAN1_EYESCAN_RD_SEL_OPT Fld(1, 4) //[4:4] + #define MISC_DUTYSCAN1_DMDQ4BMUX Fld(1, 5) //[5:5] + #define MISC_DUTYSCAN1_EYESCAN_CHK_OPT Fld(1, 6) //[6:6] + #define MISC_DUTYSCAN1_EYESCAN_TOG_OPT Fld(1, 7) //[7:7] + #define MISC_DUTYSCAN1_EYESCAN_DQ_SYNC_EN Fld(1, 8) //[8:8] + #define MISC_DUTYSCAN1_EYESCAN_NEW_DQ_SYNC_EN Fld(1, 9) //[9:9] + #define MISC_DUTYSCAN1_EYESCAN_DQS_SYNC_EN Fld(1, 10) //[10:10] + #define MISC_DUTYSCAN1_EYESCAN_DQS_OPT Fld(1, 11) //[11:11] + #define MISC_DUTYSCAN1_DCBLNCEN Fld(1, 12) //[12:12] + #define MISC_DUTYSCAN1_DCBLNCINS Fld(1, 13) //[13:13] + #define MISC_DUTYSCAN1_DQSERRCNT_DIS Fld(1, 14) //[14:14] + #define MISC_DUTYSCAN1_RX_DQ_EYE_SEL Fld(4, 16) //[19:16] + #define MISC_DUTYSCAN1_RX_DQ_EYE_SEL_B1 Fld(4, 20) //[23:20] + #define MISC_DUTYSCAN1_RX_DQ_EYE_SEL_B2 Fld(4, 24) //[27:24] + #define MISC_DUTYSCAN1_RX_DQ_EYE_SEL_B3 Fld(4, 28) //[31:28] + +#define DDRPHY_REG_MISC_MIOCK_JIT_MTR (DDRPHY_AO_BASE_ADDRESS + 0x0628) + #define MISC_MIOCK_JIT_MTR_RX_MIOCK_JIT_LIMIT Fld(32, 0) //[31:0] + +#define DDRPHY_REG_MISC_JMETER (DDRPHY_AO_BASE_ADDRESS + 0x062C) + #define MISC_JMETER_JMTR_EN Fld(1, 0) //[0:0] + #define MISC_JMETER_JMTRCNT Fld(16, 16) //[31:16] + +#define DDRPHY_REG_MISC_DVFS_EMI_CLK (DDRPHY_AO_BASE_ADDRESS + 0x0630) + #define MISC_DVFS_EMI_CLK_RG_DLL_SHUFFLE_DDRPHY Fld(1, 24) //[24:24] + #define MISC_DVFS_EMI_CLK_GATING_EMI_NEW Fld(2, 30) //[31:30] + +#define DDRPHY_REG_MISC_RX_IN_GATE_EN_CTRL (DDRPHY_AO_BASE_ADDRESS + 0x0634) + #define MISC_RX_IN_GATE_EN_CTRL_RX_IN_GATE_EN_OPT Fld(1, 0) //[0:0] + #define MISC_RX_IN_GATE_EN_CTRL_RX_IN_GATE_EN_4BYTE_EN Fld(1, 1) //[1:1] + #define MISC_RX_IN_GATE_EN_CTRL_FIX_IN_GATE_EN Fld(4, 8) //[11:8] + #define MISC_RX_IN_GATE_EN_CTRL_DIS_IN_GATE_EN Fld(4, 12) //[15:12] + +#define DDRPHY_REG_MISC_RX_IN_BUFF_EN_CTRL (DDRPHY_AO_BASE_ADDRESS + 0x0638) + #define MISC_RX_IN_BUFF_EN_CTRL_RX_IN_BUFF_EN_OPT Fld(1, 0) //[0:0] + #define MISC_RX_IN_BUFF_EN_CTRL_RX_IN_BUFF_EN_4BYTE_EN Fld(1, 1) //[1:1] + #define MISC_RX_IN_BUFF_EN_CTRL_FIX_IN_BUFF_EN Fld(4, 8) //[11:8] + #define MISC_RX_IN_BUFF_EN_CTRL_DIS_IN_BUFF_EN Fld(4, 12) //[15:12] + +#define DDRPHY_REG_MISC_CTRL0 (DDRPHY_AO_BASE_ADDRESS + 0x063C) + #define MISC_CTRL0_R_DMDQSIEN_FIFO_EN Fld(1, 0) //[0:0] + #define MISC_CTRL0_R_DMDQSIEN_DEPTH_HALF Fld(1, 1) //[1:1] + #define MISC_CTRL0_R_DMSTBEN_SYNCOPT Fld(1, 2) //[2:2] + #define MISC_CTRL0_R_DMVALID_DLY_OPT Fld(1, 4) //[4:4] + #define MISC_CTRL0_R_DMVALID_NARROW_IG Fld(1, 5) //[5:5] + #define MISC_CTRL0_R_DMVALID_DLY Fld(3, 8) //[10:8] + #define MISC_CTRL0_IMPCAL_CHAB_EN Fld(1, 12) //[12:12] + #define MISC_CTRL0_IMPCAL_TRACK_DISABLE Fld(1, 13) //[13:13] + #define MISC_CTRL0_IMPCAL_LP_ECO_OPT Fld(1, 18) //[18:18] + #define MISC_CTRL0_IMPCAL_CDC_ECO_OPT Fld(1, 19) //[19:19] + #define MISC_CTRL0_IDLE_DCM_CHB_CDC_ECO_OPT Fld(1, 20) //[20:20] + #define MISC_CTRL0_R_DMSHU_PHYDCM_FORCEOFF Fld(1, 27) //[27:27] + #define MISC_CTRL0_R_DQS0IEN_DIV4_CK_CG_CTRL Fld(1, 28) //[28:28] + #define MISC_CTRL0_R_DQS1IEN_DIV4_CK_CG_CTRL Fld(1, 29) //[29:29] + #define MISC_CTRL0_R_CLKIEN_DIV4_CK_CG_CTRL Fld(1, 30) //[30:30] + #define MISC_CTRL0_R_STBENCMP_DIV4CK_EN Fld(1, 31) //[31:31] + +#define DDRPHY_REG_MISC_CTRL1 (DDRPHY_AO_BASE_ADDRESS + 0x0640) + #define MISC_CTRL1_R_RK_PINMUXSWAP_EN Fld(1, 0) //[0:0] + #define MISC_CTRL1_R_DMPHYRST Fld(1, 1) //[1:1] + #define MISC_CTRL1_R_DM_TX_ARCLK_OE Fld(1, 2) //[2:2] + #define MISC_CTRL1_R_DM_TX_ARCMD_OE Fld(1, 3) //[3:3] + #define MISC_CTRL1_R_DMMUXCA Fld(1, 6) //[6:6] + #define MISC_CTRL1_R_DMARPIDQ_SW Fld(1, 7) //[7:7] + #define MISC_CTRL1_R_DMPINMUX Fld(2, 8) //[9:8] + #define MISC_CTRL1_R_DMARPICA_SW_UPDX Fld(1, 10) //[10:10] + #define MISC_CTRL1_R_DMRRESETB_I_OPT Fld(1, 12) //[12:12] + #define MISC_CTRL1_R_DMDA_RRESETB_I Fld(1, 13) //[13:13] + #define MISC_CTRL1_R_DQ2DM_SWAP Fld(1, 15) //[15:15] + #define MISC_CTRL1_R_DMDRAMCLKEN0 Fld(4, 16) //[19:16] + #define MISC_CTRL1_R_DMDRAMCLKEN1 Fld(4, 20) //[23:20] + #define MISC_CTRL1_R_DMDQSIENCG_EN Fld(1, 24) //[24:24] + #define MISC_CTRL1_R_DMSTBENCMP_RK_OPT Fld(1, 25) //[25:25] + #define MISC_CTRL1_R_WL_DOWNSP Fld(1, 26) //[26:26] + #define MISC_CTRL1_R_DMODTDISOE_A Fld(1, 27) //[27:27] + #define MISC_CTRL1_R_DMODTDISOE_B Fld(1, 28) //[28:28] + #define MISC_CTRL1_R_DMODTDISOE_C Fld(1, 29) //[29:29] + #define MISC_CTRL1_R_DMDA_RRESETB_E Fld(1, 31) //[31:31] + +#define DDRPHY_REG_MISC_CTRL2 (DDRPHY_AO_BASE_ADDRESS + 0x0644) + #define MISC_CTRL2_CLRPLL_SHU_GP Fld(2, 0) //[1:0] + #define MISC_CTRL2_PHYPLL_SHU_GP Fld(2, 2) //[3:2] + +#define DDRPHY_REG_MISC_CTRL3 (DDRPHY_AO_BASE_ADDRESS + 0x0648) + #define MISC_CTRL3_ARPI_CG_CMD_OPT Fld(2, 0) //[1:0] + #define MISC_CTRL3_ARPI_CG_CLK_OPT Fld(2, 2) //[3:2] + #define MISC_CTRL3_ARPI_MPDIV_CG_CA_OPT Fld(1, 4) //[4:4] + #define MISC_CTRL3_ARPI_CG_MCK_CA_OPT Fld(1, 5) //[5:5] + #define MISC_CTRL3_ARPI_CG_MCTL_CA_OPT Fld(1, 6) //[6:6] + #define MISC_CTRL3_DDRPHY_MCK_MPDIV_CG_CA_SEL Fld(2, 8) //[9:8] + #define MISC_CTRL3_DRAM_CLK_NEW_CA_EN_SEL Fld(4, 12) //[15:12] + #define MISC_CTRL3_ARPI_CG_DQ_OPT Fld(2, 16) //[17:16] + #define MISC_CTRL3_ARPI_CG_DQS_OPT Fld(2, 18) //[19:18] + #define MISC_CTRL3_ARPI_MPDIV_CG_DQ_OPT Fld(1, 20) //[20:20] + #define MISC_CTRL3_ARPI_CG_MCK_DQ_OPT Fld(1, 21) //[21:21] + #define MISC_CTRL3_ARPI_CG_MCTL_DQ_OPT Fld(1, 22) //[22:22] + #define MISC_CTRL3_DDRPHY_MCK_MPDIV_CG_DQ_SEL Fld(2, 24) //[25:24] + #define MISC_CTRL3_R_DDRPHY_COMB_CG_IG Fld(1, 26) //[26:26] + #define MISC_CTRL3_R_DDRPHY_RX_PIPE_CG_IG Fld(1, 27) //[27:27] + #define MISC_CTRL3_DRAM_CLK_NEW_DQ_EN_SEL Fld(4, 28) //[31:28] + +#define DDRPHY_REG_MISC_CTRL4 (DDRPHY_AO_BASE_ADDRESS + 0x064C) + #define MISC_CTRL4_R_OPT2_MPDIV_CG Fld(1, 0) //[0:0] + #define MISC_CTRL4_R_OPT2_CG_MCK Fld(1, 1) //[1:1] + #define MISC_CTRL4_R_OPT2_CG_DQM Fld(1, 2) //[2:2] + #define MISC_CTRL4_R_OPT2_CG_DQS Fld(1, 3) //[3:3] + #define MISC_CTRL4_R_OPT2_CG_DQ Fld(1, 4) //[4:4] + #define MISC_CTRL4_R_OPT2_CG_DQSIEN Fld(1, 5) //[5:5] + #define MISC_CTRL4_R_OPT2_CG_CMD Fld(1, 6) //[6:6] + #define MISC_CTRL4_R_OPT2_CG_CLK Fld(1, 7) //[7:7] + #define MISC_CTRL4_R_OPT2_CG_CS Fld(1, 8) //[8:8] + +#define DDRPHY_REG_MISC_CTRL5 (DDRPHY_AO_BASE_ADDRESS + 0x0650) + #define MISC_CTRL5_R_SRAM_DELSEL Fld(10, 0) //[9:0] + #define MISC_CTRL5_R_MBIST_RPREG_LOAD Fld(1, 10) //[10:10] + #define MISC_CTRL5_R_MBIST_RPREG_SEL Fld(1, 11) //[11:11] + #define MISC_CTRL5_R_MBIST_RPRSTB Fld(1, 12) //[12:12] + #define MISC_CTRL5_R_MBIST_MODE Fld(1, 13) //[13:13] + #define MISC_CTRL5_R_MBIST_BACKGROUND Fld(3, 14) //[16:14] + #define MISC_CTRL5_R_SLEEP_W Fld(1, 17) //[17:17] + #define MISC_CTRL5_R_SLEEP_R Fld(1, 18) //[18:18] + #define MISC_CTRL5_R_SLEEP_INV Fld(1, 19) //[19:19] + #define MISC_CTRL5_R_SLEEP_TEST Fld(1, 20) //[20:20] + #define MISC_CTRL5_R_MBIST_HOLDB Fld(1, 21) //[21:21] + #define MISC_CTRL5_R_CS_MARK Fld(1, 22) //[22:22] + #define MISC_CTRL5_MBIST_RSTB Fld(1, 23) //[23:23] + #define MISC_CTRL5_R_SPM_SRAM_SLP_MSK Fld(1, 24) //[24:24] + #define MISC_CTRL5_R_SRAM_HDEN Fld(1, 25) //[25:25] + #define MISC_CTRL5_R_SRAM_ISOINTB Fld(1, 26) //[26:26] + #define MISC_CTRL5_R_SRAM_SLEEPB Fld(1, 27) //[27:27] + +#define DDRPHY_REG_MISC_CTRL6 (DDRPHY_AO_BASE_ADDRESS + 0x0654) + #define MISC_CTRL6_RG_PHDET_EN_SHU_OPT Fld(1, 0) //[0:0] + #define MISC_CTRL6_RG_ADA_MCK8X_EN_SHU_OPT Fld(1, 1) //[1:1] + #define MISC_CTRL6_R_SRAM_DELSEL_1 Fld(10, 16) //[25:16] + +#define DDRPHY_REG_MISC_VREF_CTRL (DDRPHY_AO_BASE_ADDRESS + 0x0658) + #define MISC_VREF_CTRL_VREF_CTRL_RFU Fld(15, 16) //[30:16] + #define MISC_VREF_CTRL_RG_RVREF_VREF_EN Fld(1, 31) //[31:31] + +#define DDRPHY_REG_MISC_SHU_OPT (DDRPHY_AO_BASE_ADDRESS + 0x065C) + #define MISC_SHU_OPT_R_DQB0_SHU_PHY_GATING_RESETB_SPM_EN Fld(1, 0) //[0:0] + #define MISC_SHU_OPT_R_DQB0_SHU_PHDET_SPM_EN Fld(2, 2) //[3:2] + #define MISC_SHU_OPT_R_DQB1_SHU_PHY_GATING_RESETB_SPM_EN Fld(1, 8) //[8:8] + #define MISC_SHU_OPT_R_DQB1_SHU_PHDET_SPM_EN Fld(2, 10) //[11:10] + #define MISC_SHU_OPT_R_CA_SHU_PHY_GATING_RESETB_SPM_EN Fld(1, 16) //[16:16] + #define MISC_SHU_OPT_R_CA_SHU_PHDET_SPM_EN Fld(2, 18) //[19:18] + +#define DDRPHY_REG_MISC_RXDVS0 (DDRPHY_AO_BASE_ADDRESS + 0x0660) + #define MISC_RXDVS0_R_RX_DLY_TRACK_RO_SEL Fld(3, 0) //[2:0] + #define MISC_RXDVS0_R_DA_DQX_R_DLY_RO_SEL Fld(4, 8) //[11:8] + #define MISC_RXDVS0_R_DA_CAX_R_DLY_RO_SEL Fld(4, 12) //[15:12] + +#define DDRPHY_REG_MISC_RXDVS2 (DDRPHY_AO_BASE_ADDRESS + 0x0664) + #define MISC_RXDVS2_R_DMRXDVS_DEPTH_HALF Fld(1, 0) //[0:0] + #define MISC_RXDVS2_R_DMRXDVS_SHUFFLE_CTRL_CG_IG Fld(1, 8) //[8:8] + #define MISC_RXDVS2_R_DMRXDVS_DBG_MON_EN Fld(1, 16) //[16:16] + #define MISC_RXDVS2_R_DMRXDVS_DBG_MON_CLR Fld(1, 17) //[17:17] + #define MISC_RXDVS2_R_DMRXDVS_DBG_PAUSE_EN Fld(1, 18) //[18:18] + +#define DDRPHY_REG_MISC_DQSIEN_AUTOK_CFG0 (DDRPHY_AO_BASE_ADDRESS + 0x0668) + #define MISC_DQSIEN_AUTOK_CFG0_DQSIEN_AUTOK_GO Fld(1, 0) //[0:0] + #define MISC_DQSIEN_AUTOK_CFG0_DQSIEN_AUTOK_B0_EN Fld(1, 1) //[1:1] + #define MISC_DQSIEN_AUTOK_CFG0_DQSIEN_AUTOK_B1_EN Fld(1, 2) //[2:2] + #define MISC_DQSIEN_AUTOK_CFG0_DQSIEN_AUTOK_CA_EN Fld(1, 3) //[3:3] + #define MISC_DQSIEN_AUTOK_CFG0_DQSIEN_AUTOK_DEBUG_MODE_EN Fld(1, 4) //[4:4] + #define MISC_DQSIEN_AUTOK_CFG0_DQSIEN_AUTOK_EARLY_BREAK_EN Fld(1, 5) //[5:5] + #define MISC_DQSIEN_AUTOK_CFG0_DQSIEN_AUTOK_CUR_RANK Fld(1, 6) //[6:6] + #define MISC_DQSIEN_AUTOK_CFG0_DQSIEN_AUTOK_PI_OFFSET Fld(2, 8) //[9:8] + #define MISC_DQSIEN_AUTOK_CFG0_DQSIEN_AUTOK_BURST_LENGTH Fld(2, 10) //[11:10] + #define MISC_DQSIEN_AUTOK_CFG0_DQSIEN_AUTOK_SW_RST Fld(1, 12) //[12:12] + #define MISC_DQSIEN_AUTOK_CFG0_DQSIEN_AUTOK_RK0_SW_RST Fld(1, 13) //[13:13] + #define MISC_DQSIEN_AUTOK_CFG0_DQSIEN_AUTOK_RK1_SW_RST Fld(1, 14) //[14:14] + #define MISC_DQSIEN_AUTOK_CFG0_DQSIEN_AUTOK_END__UI Fld(4, 16) //[19:16] + #define MISC_DQSIEN_AUTOK_CFG0_DQSIEN_AUTOK_END_MCK Fld(4, 20) //[23:20] + #define MISC_DQSIEN_AUTOK_CFG0_DQSIEN_AUTOK_INI__UI Fld(4, 24) //[27:24] + #define MISC_DQSIEN_AUTOK_CFG0_DQSIEN_AUTOK_INI_MCK Fld(4, 28) //[31:28] + +#define DDRPHY_REG_MISC_DLINE_MON_CFG (DDRPHY_AO_BASE_ADDRESS + 0x066C) + #define MISC_DLINE_MON_CFG_DLINE_MON_TRACK_EN Fld(1, 0) //[0:0] + #define MISC_DLINE_MON_CFG_FORCE_DLINE_MON_EN Fld(1, 1) //[1:1] + #define MISC_DLINE_MON_CFG_FORCE_UDP_DLY_VAL Fld(1, 2) //[2:2] + #define MISC_DLINE_MON_CFG_MON_DLY_OUT Fld(4, 4) //[7:4] + #define MISC_DLINE_MON_CFG_RX_UDP_EN Fld(1, 8) //[8:8] + #define MISC_DLINE_MON_CFG_TX_UDP_EN Fld(1, 9) //[9:9] + #define MISC_DLINE_MON_CFG_DLINE_MON_TRACK_CG_EN Fld(1, 10) //[10:10] + +#define DDRPHY_REG_MISC_RX_AUTOK_CFG0 (DDRPHY_AO_BASE_ADDRESS + 0x0670) + #define MISC_RX_AUTOK_CFG0_RX_CAL_START Fld(1, 0) //[0:0] + #define MISC_RX_AUTOK_CFG0_RX_CAL_BREAK Fld(1, 1) //[1:1] + #define MISC_RX_AUTOK_CFG0_RX_CAL_CLEAR Fld(1, 2) //[2:2] + #define MISC_RX_AUTOK_CFG0_RX_CAL_CG_EN Fld(1, 3) //[3:3] + #define MISC_RX_AUTOK_CFG0_RX_CAL_BEGIN Fld(11, 4) //[14:4] + #define MISC_RX_AUTOK_CFG0_RX_CAL_LEN Fld(10, 16) //[25:16] + #define MISC_RX_AUTOK_CFG0_RX_CAL_STEP Fld(4, 28) //[31:28] + +#define DDRPHY_REG_MISC_RX_AUTOK_CFG1 (DDRPHY_AO_BASE_ADDRESS + 0x0674) + #define MISC_RX_AUTOK_CFG1_RX_CAL_OUT_DBG_EN Fld(1, 0) //[0:0] + #define MISC_RX_AUTOK_CFG1_RX_CAL_OUT_DBG_SEL Fld(4, 4) //[7:4] + +#define DDRPHY_REG_MISC_DBG_IRQ_CTRL0 (DDRPHY_AO_BASE_ADDRESS + 0x0680) + #define MISC_DBG_IRQ_CTRL0_DBG_DB_SW_RST Fld(1, 0) //[0:0] + #define MISC_DBG_IRQ_CTRL0_DBG_DB_IRQ_RST_EN Fld(1, 1) //[1:1] + #define MISC_DBG_IRQ_CTRL0_IRQ_CK_FRUN Fld(1, 4) //[4:4] + +#define DDRPHY_REG_MISC_DBG_IRQ_CTRL1 (DDRPHY_AO_BASE_ADDRESS + 0x0684) + #define MISC_DBG_IRQ_CTRL1_REFRATE_EN Fld(1, 0) //[0:0] + #define MISC_DBG_IRQ_CTRL1_REFPENDING_EN Fld(1, 1) //[1:1] + #define MISC_DBG_IRQ_CTRL1_PRE_REFRATE_EN Fld(1, 2) //[2:2] + #define MISC_DBG_IRQ_CTRL1_RTMRW_ABNORMAL_STOP_EN Fld(1, 3) //[3:3] + #define MISC_DBG_IRQ_CTRL1_SREF_REQ_NO_ACK_EN Fld(1, 6) //[6:6] + #define MISC_DBG_IRQ_CTRL1_SREF_REQ_SHORT_EN Fld(1, 7) //[7:7] + #define MISC_DBG_IRQ_CTRL1_SREF_REQ_DTRIG_EN Fld(1, 8) //[8:8] + #define MISC_DBG_IRQ_CTRL1_RTSWCMD_NONVALIDCMD_EN Fld(1, 12) //[12:12] + #define MISC_DBG_IRQ_CTRL1_TX_TRACKING1_EN Fld(1, 16) //[16:16] + #define MISC_DBG_IRQ_CTRL1_TX_TRACKING2_EN Fld(1, 17) //[17:17] + +#define DDRPHY_REG_MISC_DBG_IRQ_CTRL2 (DDRPHY_AO_BASE_ADDRESS + 0x0688) + #define MISC_DBG_IRQ_CTRL2_REFRATE_POL Fld(1, 0) //[0:0] + #define MISC_DBG_IRQ_CTRL2_REFPENDING_POL Fld(1, 1) //[1:1] + #define MISC_DBG_IRQ_CTRL2_PRE_REFRATE_POL Fld(1, 2) //[2:2] + #define MISC_DBG_IRQ_CTRL2_RTMRW_ABNORMAL_STOP_POL Fld(1, 3) //[3:3] + #define MISC_DBG_IRQ_CTRL2_SREF_REQ_NO_ACK_POL Fld(1, 6) //[6:6] + #define MISC_DBG_IRQ_CTRL2_SREF_REQ_SHORT_POL Fld(1, 7) //[7:7] + #define MISC_DBG_IRQ_CTRL2_SREF_REQ_DTRIG_POL Fld(1, 8) //[8:8] + #define MISC_DBG_IRQ_CTRL2_RTSWCMD_NONVALIDCMD_POL Fld(1, 12) //[12:12] + #define MISC_DBG_IRQ_CTRL2_TX_TRACKING1_POL Fld(1, 16) //[16:16] + #define MISC_DBG_IRQ_CTRL2_TX_TRACKING2_POL Fld(1, 17) //[17:17] + +#define DDRPHY_REG_MISC_DBG_IRQ_CTRL3 (DDRPHY_AO_BASE_ADDRESS + 0x068C) + #define MISC_DBG_IRQ_CTRL3_REFRATE_CLEAN Fld(1, 0) //[0:0] + #define MISC_DBG_IRQ_CTRL3_REFPENDING_CLEAN Fld(1, 1) //[1:1] + #define MISC_DBG_IRQ_CTRL3_PRE_REFRATE_CLEAN Fld(1, 2) //[2:2] + #define MISC_DBG_IRQ_CTRL3_RTMRW_ABNORMAL_STOP_CLEAN Fld(1, 3) //[3:3] + #define MISC_DBG_IRQ_CTRL3_SREF_REQ_NO_ACK_CLEAN Fld(1, 6) //[6:6] + #define MISC_DBG_IRQ_CTRL3_SREF_REQ_SHORT_CLEAN Fld(1, 7) //[7:7] + #define MISC_DBG_IRQ_CTRL3_SREF_REQ_DTRIG_CLEAN Fld(1, 8) //[8:8] + #define MISC_DBG_IRQ_CTRL3_RTSWCMD_NONVALIDCMD_CLEAN Fld(1, 12) //[12:12] + #define MISC_DBG_IRQ_CTRL3_TX_TRACKING1_CLEAN Fld(1, 16) //[16:16] + #define MISC_DBG_IRQ_CTRL3_TX_TRACKING2_CLEAN Fld(1, 17) //[17:17] + +#define DDRPHY_REG_MISC_DBG_IRQ_CTRL4 (DDRPHY_AO_BASE_ADDRESS + 0x0690) + #define MISC_DBG_IRQ_CTRL4_DBG_DRAMC_IRQ_EN_1 Fld(32, 0) //[31:0] + +#define DDRPHY_REG_MISC_DBG_IRQ_CTRL5 (DDRPHY_AO_BASE_ADDRESS + 0x0694) + #define MISC_DBG_IRQ_CTRL5_DBG_DRAMC_IRQ_POL_1 Fld(32, 0) //[31:0] + +#define DDRPHY_REG_MISC_DBG_IRQ_CTRL6 (DDRPHY_AO_BASE_ADDRESS + 0x0698) + #define MISC_DBG_IRQ_CTRL6_DBG_DRAMC_IRQ_CLEAN_1 Fld(32, 0) //[31:0] + +#define DDRPHY_REG_MISC_DBG_IRQ_CTRL7 (DDRPHY_AO_BASE_ADDRESS + 0x069C) + #define MISC_DBG_IRQ_CTRL7_PI_TRACKING_WAR_RK1_B0_EN Fld(1, 0) //[0:0] + #define MISC_DBG_IRQ_CTRL7_PI_TRACKING_WAR_RK0_B0_EN Fld(1, 1) //[1:1] + #define MISC_DBG_IRQ_CTRL7_PI_TRACKING_WAR_RK1_B1_EN Fld(1, 2) //[2:2] + #define MISC_DBG_IRQ_CTRL7_PI_TRACKING_WAR_RK0_B1_EN Fld(1, 3) //[3:3] + #define MISC_DBG_IRQ_CTRL7_PI_TRACKING_WAR_RK1_CA_EN Fld(1, 4) //[4:4] + #define MISC_DBG_IRQ_CTRL7_PI_TRACKING_WAR_RK0_CA_EN Fld(1, 5) //[5:5] + #define MISC_DBG_IRQ_CTRL7_STB_GATTING_ERR_EN Fld(1, 7) //[7:7] + #define MISC_DBG_IRQ_CTRL7_RX_ARDQ0_FIFO_STBEN_ERR_B0_EN Fld(1, 8) //[8:8] + #define MISC_DBG_IRQ_CTRL7_RX_ARDQ4_FIFO_STBEN_ERR_B0_EN Fld(1, 9) //[9:9] + #define MISC_DBG_IRQ_CTRL7_RX_ARDQ0_FIFO_STBEN_ERR_B1_EN Fld(1, 10) //[10:10] + #define MISC_DBG_IRQ_CTRL7_RX_ARDQ4_FIFO_STBEN_ERR_B1_EN Fld(1, 11) //[11:11] + #define MISC_DBG_IRQ_CTRL7_TRACKING_STATUS_ERR_RISING_R1_B1_EN Fld(1, 12) //[12:12] + #define MISC_DBG_IRQ_CTRL7_TRACKING_STATUS_ERR_RISING_R1_B0_EN Fld(1, 13) //[13:13] + #define MISC_DBG_IRQ_CTRL7_TRACKING_STATUS_ERR_RISING_R0_B1_EN Fld(1, 14) //[14:14] + #define MISC_DBG_IRQ_CTRL7_TRACKING_STATUS_ERR_RISING_R0_B0_EN Fld(1, 15) //[15:15] + #define MISC_DBG_IRQ_CTRL7_IMP_CLK_ERR_EN Fld(1, 24) //[24:24] + #define MISC_DBG_IRQ_CTRL7_IMP_CMD_ERR_EN Fld(1, 25) //[25:25] + #define MISC_DBG_IRQ_CTRL7_IMP_DQ1_ERR_EN Fld(1, 26) //[26:26] + #define MISC_DBG_IRQ_CTRL7_IMP_DQ0_ERR_EN Fld(1, 27) //[27:27] + #define MISC_DBG_IRQ_CTRL7_IMP_DQS_ERR_EN Fld(1, 28) //[28:28] + #define MISC_DBG_IRQ_CTRL7_IMP_ODTN_ERR_EN Fld(1, 29) //[29:29] + #define MISC_DBG_IRQ_CTRL7_IMP_DRVN_ERR_EN Fld(1, 30) //[30:30] + #define MISC_DBG_IRQ_CTRL7_IMP_DRVP_ERR_EN Fld(1, 31) //[31:31] + +#define DDRPHY_REG_MISC_DBG_IRQ_CTRL8 (DDRPHY_AO_BASE_ADDRESS + 0x06A0) + #define MISC_DBG_IRQ_CTRL8_PI_TRACKING_WAR_RK1_B0_POL Fld(1, 0) //[0:0] + #define MISC_DBG_IRQ_CTRL8_PI_TRACKING_WAR_RK0_B0_POL Fld(1, 1) //[1:1] + #define MISC_DBG_IRQ_CTRL8_PI_TRACKING_WAR_RK1_B1_POL Fld(1, 2) //[2:2] + #define MISC_DBG_IRQ_CTRL8_PI_TRACKING_WAR_RK0_B1_POL Fld(1, 3) //[3:3] + #define MISC_DBG_IRQ_CTRL8_PI_TRACKING_WAR_RK1_CA_POL Fld(1, 4) //[4:4] + #define MISC_DBG_IRQ_CTRL8_PI_TRACKING_WAR_RK0_CA_POL Fld(1, 5) //[5:5] + #define MISC_DBG_IRQ_CTRL8_STB_GATTING_ERR_POL Fld(1, 7) //[7:7] + #define MISC_DBG_IRQ_CTRL8_RX_ARDQ0_FIFO_STBEN_ERR_B0_POL Fld(1, 8) //[8:8] + #define MISC_DBG_IRQ_CTRL8_RX_ARDQ4_FIFO_STBEN_ERR_B0_POL Fld(1, 9) //[9:9] + #define MISC_DBG_IRQ_CTRL8_RX_ARDQ0_FIFO_STBEN_ERR_B1_POL Fld(1, 10) //[10:10] + #define MISC_DBG_IRQ_CTRL8_RX_ARDQ4_FIFO_STBEN_ERR_B1_POL Fld(1, 11) //[11:11] + #define MISC_DBG_IRQ_CTRL8_TRACKING_STATUS_ERR_RISING_R1_B1_POL Fld(1, 12) //[12:12] + #define MISC_DBG_IRQ_CTRL8_TRACKING_STATUS_ERR_RISING_R1_B0_POL Fld(1, 13) //[13:13] + #define MISC_DBG_IRQ_CTRL8_TRACKING_STATUS_ERR_RISING_R0_B1_POL Fld(1, 14) //[14:14] + #define MISC_DBG_IRQ_CTRL8_TRACKING_STATUS_ERR_RISING_R0_B0_POL Fld(1, 15) //[15:15] + #define MISC_DBG_IRQ_CTRL8_IMP_CLK_ERR_POL Fld(1, 24) //[24:24] + #define MISC_DBG_IRQ_CTRL8_IMP_CMD_ERR_POL Fld(1, 25) //[25:25] + #define MISC_DBG_IRQ_CTRL8_IMP_DQ1_ERR_POL Fld(1, 26) //[26:26] + #define MISC_DBG_IRQ_CTRL8_IMP_DQ0_ERR_POL Fld(1, 27) //[27:27] + #define MISC_DBG_IRQ_CTRL8_IMP_DQS_ERR_POL Fld(1, 28) //[28:28] + #define MISC_DBG_IRQ_CTRL8_IMP_ODTN_ERR_POL Fld(1, 29) //[29:29] + #define MISC_DBG_IRQ_CTRL8_IMP_DRVN_ERR_POL Fld(1, 30) //[30:30] + #define MISC_DBG_IRQ_CTRL8_IMP_DRVP_ERR_POL Fld(1, 31) //[31:31] + +#define DDRPHY_REG_MISC_DBG_IRQ_CTRL9 (DDRPHY_AO_BASE_ADDRESS + 0x06A4) + #define MISC_DBG_IRQ_CTRL9_PI_TRACKING_WAR_RK1_B0_CLEAN Fld(1, 0) //[0:0] + #define MISC_DBG_IRQ_CTRL9_PI_TRACKING_WAR_RK0_B0_CLEAN Fld(1, 1) //[1:1] + #define MISC_DBG_IRQ_CTRL9_PI_TRACKING_WAR_RK1_B1_CLEAN Fld(1, 2) //[2:2] + #define MISC_DBG_IRQ_CTRL9_PI_TRACKING_WAR_RK0_B1_CLEAN Fld(1, 3) //[3:3] + #define MISC_DBG_IRQ_CTRL9_PI_TRACKING_WAR_RK1_CA_CLEAN Fld(1, 4) //[4:4] + #define MISC_DBG_IRQ_CTRL9_PI_TRACKING_WAR_RK0_CA_CLEAN Fld(1, 5) //[5:5] + #define MISC_DBG_IRQ_CTRL9_STB_GATTING_ERR_CLEAN Fld(1, 7) //[7:7] + #define MISC_DBG_IRQ_CTRL9_RX_ARDQ0_FIFO_STBEN_ERR_B0_CLEAN Fld(1, 8) //[8:8] + #define MISC_DBG_IRQ_CTRL9_RX_ARDQ4_FIFO_STBEN_ERR_B0_CLEAN Fld(1, 9) //[9:9] + #define MISC_DBG_IRQ_CTRL9_RX_ARDQ0_FIFO_STBEN_ERR_B1_CLEAN Fld(1, 10) //[10:10] + #define MISC_DBG_IRQ_CTRL9_RX_ARDQ4_FIFO_STBEN_ERR_B1_CLEAN Fld(1, 11) //[11:11] + #define MISC_DBG_IRQ_CTRL9_TRACKING_STATUS_ERR_RISING_R1_B1_CLEAN Fld(1, 12) //[12:12] + #define MISC_DBG_IRQ_CTRL9_TRACKING_STATUS_ERR_RISING_R1_B0_CLEAN Fld(1, 13) //[13:13] + #define MISC_DBG_IRQ_CTRL9_TRACKING_STATUS_ERR_RISING_R0_B1_CLEAN Fld(1, 14) //[14:14] + #define MISC_DBG_IRQ_CTRL9_TRACKING_STATUS_ERR_RISING_R0_B0_CLEAN Fld(1, 15) //[15:15] + #define MISC_DBG_IRQ_CTRL9_IMP_CLK_ERR_CLEAN Fld(1, 24) //[24:24] + #define MISC_DBG_IRQ_CTRL9_IMP_CMD_ERR_CLEAN Fld(1, 25) //[25:25] + #define MISC_DBG_IRQ_CTRL9_IMP_DQ1_ERR_CLEAN Fld(1, 26) //[26:26] + #define MISC_DBG_IRQ_CTRL9_IMP_DQ0_ERR_CLEAN Fld(1, 27) //[27:27] + #define MISC_DBG_IRQ_CTRL9_IMP_DQS_ERR_CLEAN Fld(1, 28) //[28:28] + #define MISC_DBG_IRQ_CTRL9_IMP_ODTN_ERR_CLEAN Fld(1, 29) //[29:29] + #define MISC_DBG_IRQ_CTRL9_IMP_DRVN_ERR_CLEAN Fld(1, 30) //[30:30] + #define MISC_DBG_IRQ_CTRL9_IMP_DRVP_ERR_CLEAN Fld(1, 31) //[31:31] + +#define DDRPHY_REG_MISC_DQ_SE_PINMUX_CTRL0 (DDRPHY_AO_BASE_ADDRESS + 0x06B0) + #define MISC_DQ_SE_PINMUX_CTRL0_DQ_PINMUX_SEL_DQ0 Fld(4, 0) //[3:0] + #define MISC_DQ_SE_PINMUX_CTRL0_DQ_PINMUX_SEL_DQ1 Fld(4, 4) //[7:4] + #define MISC_DQ_SE_PINMUX_CTRL0_DQ_PINMUX_SEL_DQ2 Fld(4, 8) //[11:8] + #define MISC_DQ_SE_PINMUX_CTRL0_DQ_PINMUX_SEL_DQ3 Fld(4, 12) //[15:12] + #define MISC_DQ_SE_PINMUX_CTRL0_DQ_PINMUX_SEL_DQ4 Fld(4, 16) //[19:16] + #define MISC_DQ_SE_PINMUX_CTRL0_DQ_PINMUX_SEL_DQ5 Fld(4, 20) //[23:20] + #define MISC_DQ_SE_PINMUX_CTRL0_DQ_PINMUX_SEL_DQ6 Fld(4, 24) //[27:24] + #define MISC_DQ_SE_PINMUX_CTRL0_DQ_PINMUX_SEL_DQ7 Fld(4, 28) //[31:28] + +#define DDRPHY_REG_MISC_DQ_SE_PINMUX_CTRL1 (DDRPHY_AO_BASE_ADDRESS + 0x06B4) + #define MISC_DQ_SE_PINMUX_CTRL1_DQ_PINMUX_SEL_DQ8 Fld(4, 0) //[3:0] + #define MISC_DQ_SE_PINMUX_CTRL1_DQ_PINMUX_SEL_DQ9 Fld(4, 4) //[7:4] + #define MISC_DQ_SE_PINMUX_CTRL1_DQ_PINMUX_SEL_DQ10 Fld(4, 8) //[11:8] + #define MISC_DQ_SE_PINMUX_CTRL1_DQ_PINMUX_SEL_DQ11 Fld(4, 12) //[15:12] + #define MISC_DQ_SE_PINMUX_CTRL1_DQ_PINMUX_SEL_DQ12 Fld(4, 16) //[19:16] + #define MISC_DQ_SE_PINMUX_CTRL1_DQ_PINMUX_SEL_DQ13 Fld(4, 20) //[23:20] + #define MISC_DQ_SE_PINMUX_CTRL1_DQ_PINMUX_SEL_DQ14 Fld(4, 24) //[27:24] + #define MISC_DQ_SE_PINMUX_CTRL1_DQ_PINMUX_SEL_DQ15 Fld(4, 28) //[31:28] + +#define DDRPHY_REG_MISC_BIST_LPBK_CTRL0 (DDRPHY_AO_BASE_ADDRESS + 0x06C0) + #define MISC_BIST_LPBK_CTRL0_BIST_EN Fld(1, 0) //[0:0] + #define MISC_BIST_LPBK_CTRL0_BIST_TA2_LPBK_MODE Fld(1, 1) //[1:1] + #define MISC_BIST_LPBK_CTRL0_BIST_RX_LPBK_MODE Fld(1, 2) //[2:2] + #define MISC_BIST_LPBK_CTRL0_BIST_DSEL_MODE Fld(1, 3) //[3:3] + #define MISC_BIST_LPBK_CTRL0_BIST_TX_DQSINCTL Fld(4, 12) //[15:12] + #define MISC_BIST_LPBK_CTRL0_BIST_SEDA_LPBK_DSEL_RW Fld(5, 16) //[20:16] + #define MISC_BIST_LPBK_CTRL0_BIST_SEDA_LPBK_DLE_RW Fld(5, 24) //[28:24] + +#define DDRPHY_REG_SHU_PHYPLL0 (DDRPHY_AO_BASE_ADDRESS + 0x0700) + #define SHU_PHYPLL0_RG_RPHYPLL_RESERVED Fld(16, 0) //[15:0] + #define SHU_PHYPLL0_RG_RPHYPLL_FS Fld(2, 18) //[19:18] + #define SHU_PHYPLL0_RG_RPHYPLL_BW Fld(3, 20) //[22:20] + #define SHU_PHYPLL0_RG_RPHYPLL_ICHP Fld(2, 24) //[25:24] + #define SHU_PHYPLL0_RG_RPHYPLL_IBIAS Fld(2, 26) //[27:26] + #define SHU_PHYPLL0_RG_RPHYPLL_BLP Fld(1, 29) //[29:29] + #define SHU_PHYPLL0_RG_RPHYPLL_BR Fld(1, 30) //[30:30] + #define SHU_PHYPLL0_RG_RPHYPLL_BP Fld(1, 31) //[31:31] + +#define DDRPHY_REG_SHU_PHYPLL1 (DDRPHY_AO_BASE_ADDRESS + 0x0704) + #define SHU_PHYPLL1_RG_RPHYPLL_SDM_FRA_EN Fld(1, 0) //[0:0] + #define SHU_PHYPLL1_RG_RPHYPLL_SDM_PCW_CHG Fld(1, 1) //[1:1] + #define SHU_PHYPLL1_RG_RPHYPLL_SDM_PCW Fld(16, 16) //[31:16] + +#define DDRPHY_REG_SHU_PHYPLL2 (DDRPHY_AO_BASE_ADDRESS + 0x0708) + #define SHU_PHYPLL2_RG_RPHYPLL_POSDIV Fld(3, 0) //[2:0] + #define SHU_PHYPLL2_RG_RPHYPLL_PREDIV Fld(2, 18) //[19:18] + +#define DDRPHY_REG_SHU_PHYPLL3 (DDRPHY_AO_BASE_ADDRESS + 0x070C) + #define SHU_PHYPLL3_RG_RPHYPLL_DIV_CK_SEL Fld(1, 0) //[0:0] + #define SHU_PHYPLL3_RG_RPHYPLL_GLITCH_FREE_EN Fld(1, 1) //[1:1] + #define SHU_PHYPLL3_RG_RPHYPLL_LVR_REFSEL Fld(2, 2) //[3:2] + #define SHU_PHYPLL3_RG_RPHYPLL_DIV3_EN Fld(1, 4) //[4:4] + #define SHU_PHYPLL3_RG_RPHYPLL_FS_EN Fld(1, 5) //[5:5] + #define SHU_PHYPLL3_RG_RPHYPLL_FBKSEL Fld(1, 6) //[6:6] + #define SHU_PHYPLL3_RG_RPHYPLL_RST_DLY Fld(2, 8) //[9:8] + #define SHU_PHYPLL3_RG_RPHYPLL_LVROD_EN Fld(1, 12) //[12:12] + #define SHU_PHYPLL3_RG_RPHYPLL_MONREF_EN Fld(1, 13) //[13:13] + #define SHU_PHYPLL3_RG_RPHYPLL_MONVC_EN Fld(2, 14) //[15:14] + #define SHU_PHYPLL3_RG_RPHYPLL_MONCK_EN Fld(1, 16) //[16:16] + +#define DDRPHY_REG_SHU_PHYPLL4 (DDRPHY_AO_BASE_ADDRESS + 0x0710) + #define SHU_PHYPLL4_RG_RPHYPLL_EXT_FBDIV Fld(6, 0) //[5:0] + #define SHU_PHYPLL4_RG_RPHYPLL_EXTFBDIV_EN Fld(1, 8) //[8:8] + +#define DDRPHY_REG_SHU_PHYPLL5 (DDRPHY_AO_BASE_ADDRESS + 0x0714) + #define SHU_PHYPLL5_RG_RPHYPLL_FB_DL Fld(6, 0) //[5:0] + #define SHU_PHYPLL5_RG_RPHYPLL_REF_DL Fld(6, 8) //[13:8] + +#define DDRPHY_REG_SHU_PHYPLL6 (DDRPHY_AO_BASE_ADDRESS + 0x0718) + #define SHU_PHYPLL6_RG_RPHYPLL_SDM_HREN Fld(1, 0) //[0:0] + #define SHU_PHYPLL6_RG_RPHYPLL_SDM_SSC_PH_INIT Fld(1, 1) //[1:1] + #define SHU_PHYPLL6_RG_RPHYPLL_SDM_SSC_PRD Fld(16, 16) //[31:16] + +#define DDRPHY_REG_SHU_PHYPLL7 (DDRPHY_AO_BASE_ADDRESS + 0x071C) + #define SHU_PHYPLL7_RG_RPHYPLL_SDM_SSC_DELTA Fld(16, 0) //[15:0] + #define SHU_PHYPLL7_RG_RPHYPLL_SDM_SSC_DELTA1 Fld(16, 16) //[31:16] + +#define DDRPHY_REG_SHU_CLRPLL0 (DDRPHY_AO_BASE_ADDRESS + 0x0720) + #define SHU_CLRPLL0_RG_RCLRPLL_RESERVED Fld(16, 0) //[15:0] + #define SHU_CLRPLL0_RG_RCLRPLL_FS Fld(2, 18) //[19:18] + #define SHU_CLRPLL0_RG_RCLRPLL_BW Fld(3, 20) //[22:20] + #define SHU_CLRPLL0_RG_RCLRPLL_ICHP Fld(2, 24) //[25:24] + #define SHU_CLRPLL0_RG_RCLRPLL_IBIAS Fld(2, 26) //[27:26] + #define SHU_CLRPLL0_RG_RCLRPLL_BLP Fld(1, 29) //[29:29] + #define SHU_CLRPLL0_RG_RCLRPLL_BR Fld(1, 30) //[30:30] + #define SHU_CLRPLL0_RG_RCLRPLL_BP Fld(1, 31) //[31:31] + +#define DDRPHY_REG_SHU_CLRPLL1 (DDRPHY_AO_BASE_ADDRESS + 0x0724) + #define SHU_CLRPLL1_RG_RCLRPLL_SDM_FRA_EN Fld(1, 0) //[0:0] + #define SHU_CLRPLL1_RG_RCLRPLL_SDM_PCW_CHG Fld(1, 1) //[1:1] + #define SHU_CLRPLL1_RG_RCLRPLL_SDM_PCW Fld(16, 16) //[31:16] + +#define DDRPHY_REG_SHU_CLRPLL2 (DDRPHY_AO_BASE_ADDRESS + 0x0728) + #define SHU_CLRPLL2_RG_RCLRPLL_POSDIV Fld(3, 0) //[2:0] + #define SHU_CLRPLL2_RG_RCLRPLL_PREDIV Fld(2, 18) //[19:18] + +#define DDRPHY_REG_SHU_CLRPLL3 (DDRPHY_AO_BASE_ADDRESS + 0x072C) + #define SHU_CLRPLL3_RG_RCLRPLL_DIV_CK_SEL Fld(1, 0) //[0:0] + #define SHU_CLRPLL3_RG_RCLRPLL_GLITCH_FREE_EN Fld(1, 1) //[1:1] + #define SHU_CLRPLL3_RG_RCLRPLL_LVR_REFSEL Fld(2, 2) //[3:2] + #define SHU_CLRPLL3_RG_RCLRPLL_DIV3_EN Fld(1, 4) //[4:4] + #define SHU_CLRPLL3_RG_RCLRPLL_FS_EN Fld(1, 5) //[5:5] + #define SHU_CLRPLL3_RG_RCLRPLL_FBKSEL Fld(1, 6) //[6:6] + #define SHU_CLRPLL3_RG_RCLRPLL_RST_DLY Fld(2, 8) //[9:8] + #define SHU_CLRPLL3_RG_RCLRPLL_LVROD_EN Fld(1, 12) //[12:12] + #define SHU_CLRPLL3_RG_RCLRPLL_MONREF_EN Fld(1, 13) //[13:13] + #define SHU_CLRPLL3_RG_RCLRPLL_MONVC_EN Fld(2, 14) //[15:14] + #define SHU_CLRPLL3_RG_RCLRPLL_MONCK_EN Fld(1, 16) //[16:16] + +#define DDRPHY_REG_SHU_CLRPLL4 (DDRPHY_AO_BASE_ADDRESS + 0x0730) + #define SHU_CLRPLL4_RG_RCLRPLL_EXT_PODIV Fld(6, 0) //[5:0] + #define SHU_CLRPLL4_RG_RCLRPLL_BYPASS Fld(1, 8) //[8:8] + #define SHU_CLRPLL4_RG_RCLRPLL_EXTPODIV_EN Fld(1, 12) //[12:12] + #define SHU_CLRPLL4_RG_RCLRPLL_EXT_FBDIV Fld(6, 16) //[21:16] + #define SHU_CLRPLL4_RG_RCLRPLL_EXTFBDIV_EN Fld(1, 24) //[24:24] + +#define DDRPHY_REG_SHU_CLRPLL5 (DDRPHY_AO_BASE_ADDRESS + 0x0734) + #define SHU_CLRPLL5_RG_RCLRPLL_FB_DL Fld(6, 0) //[5:0] + #define SHU_CLRPLL5_RG_RCLRPLL_REF_DL Fld(6, 8) //[13:8] + +#define DDRPHY_REG_SHU_CLRPLL6 (DDRPHY_AO_BASE_ADDRESS + 0x0738) + #define SHU_CLRPLL6_RG_RCLRPLL_SDM_HREN Fld(1, 0) //[0:0] + #define SHU_CLRPLL6_RG_RCLRPLL_SDM_SSC_PH_INIT Fld(1, 1) //[1:1] + #define SHU_CLRPLL6_RG_RCLRPLL_SDM_SSC_PRD Fld(16, 16) //[31:16] + +#define DDRPHY_REG_SHU_CLRPLL7 (DDRPHY_AO_BASE_ADDRESS + 0x073C) + #define SHU_CLRPLL7_RG_RCLRPLL_SDM_SSC_DELTA Fld(16, 0) //[15:0] + #define SHU_CLRPLL7_RG_RCLRPLL_SDM_SSC_DELTA1 Fld(16, 16) //[31:16] + +#define DDRPHY_REG_SHU_PLL0 (DDRPHY_AO_BASE_ADDRESS + 0x0740) + #define SHU_PLL0_RG_RPHYPLL_TOP_REV Fld(16, 0) //[15:0] + #define SHU_PLL0_RG_RPLLGP_SOPEN_SER_MODE Fld(1, 16) //[16:16] + #define SHU_PLL0_RG_RPLLGP_SOPEN_PREDIV_EN Fld(1, 17) //[17:17] + #define SHU_PLL0_RG_RPLLGP_SOPEN_EN Fld(1, 18) //[18:18] + #define SHU_PLL0_RG_RPLLGP_DLINE_MON_TSHIFT Fld(2, 20) //[21:20] + #define SHU_PLL0_RG_RPLLGP_DLINE_MON_DIV Fld(2, 22) //[23:22] + #define SHU_PLL0_RG_RPLLGP_DLINE_MON_DLY Fld(7, 24) //[30:24] + #define SHU_PLL0_RG_RPLLGP_DLINE_MON_EN Fld(1, 31) //[31:31] + +#define DDRPHY_REG_SHU_PLL1 (DDRPHY_AO_BASE_ADDRESS + 0x0744) + #define SHU_PLL1_RG_RPHYPLLGP_CK_SEL Fld(1, 0) //[0:0] + #define SHU_PLL1_RG_RPLLGP_PLLCK_VSEL Fld(1, 1) //[1:1] + #define SHU_PLL1_R_SHU_AUTO_PLL_MUX Fld(1, 4) //[4:4] + #define SHU_PLL1_RG_RPHYPLL_DDR400_EN Fld(1, 8) //[8:8] + +#define DDRPHY_REG_SHU_PLL2 (DDRPHY_AO_BASE_ADDRESS + 0x0748) + #define SHU_PLL2_RG_RPHYPLL_ADA_MCK8X_EN_SHU Fld(1, 0) //[0:0] + +#define DDRPHY_REG_SHU_R0_B0_TXDLY0 (DDRPHY_AO_BASE_ADDRESS + 0x0760) + #define SHU_R0_B0_TXDLY0_TX_ARDQ0_DLY_B0 Fld(8, 0) //[7:0] + #define SHU_R0_B0_TXDLY0_TX_ARDQ1_DLY_B0 Fld(8, 8) //[15:8] + #define SHU_R0_B0_TXDLY0_TX_ARDQ2_DLY_B0 Fld(8, 16) //[23:16] + #define SHU_R0_B0_TXDLY0_TX_ARDQ3_DLY_B0 Fld(8, 24) //[31:24] + +#define DDRPHY_REG_SHU_R0_B0_TXDLY1 (DDRPHY_AO_BASE_ADDRESS + 0x0764) + #define SHU_R0_B0_TXDLY1_TX_ARDQ4_DLY_B0 Fld(8, 0) //[7:0] + #define SHU_R0_B0_TXDLY1_TX_ARDQ5_DLY_B0 Fld(8, 8) //[15:8] + #define SHU_R0_B0_TXDLY1_TX_ARDQ6_DLY_B0 Fld(8, 16) //[23:16] + #define SHU_R0_B0_TXDLY1_TX_ARDQ7_DLY_B0 Fld(8, 24) //[31:24] + +#define DDRPHY_REG_SHU_R0_B0_TXDLY2 (DDRPHY_AO_BASE_ADDRESS + 0x0768) + #define SHU_R0_B0_TXDLY2_TX_ARDQS0_DLYB_B0 Fld(8, 0) //[7:0] + #define SHU_R0_B0_TXDLY2_TX_ARDQS0B_DLYB_B0 Fld(8, 8) //[15:8] + #define SHU_R0_B0_TXDLY2_TX_ARDQS0_DLY_B0 Fld(8, 16) //[23:16] + #define SHU_R0_B0_TXDLY2_TX_ARDQS0B_DLY_B0 Fld(8, 24) //[31:24] + +#define DDRPHY_REG_SHU_R0_B0_TXDLY3 (DDRPHY_AO_BASE_ADDRESS + 0x076C) + #define SHU_R0_B0_TXDLY3_TX_ARDQM0_DLY_B0 Fld(8, 0) //[7:0] + #define SHU_R0_B0_TXDLY3_TX_ARWCK_DLY_B0 Fld(8, 16) //[23:16] + #define SHU_R0_B0_TXDLY3_TX_ARWCKB_DLY_B0 Fld(8, 24) //[31:24] + +#define DDRPHY_REG_SHU_R0_B0_TXDLY4 (DDRPHY_AO_BASE_ADDRESS + 0x0770) + #define SHU_R0_B0_TXDLY4_DMY_TXDLY4_B0 Fld(1, 0) //[0:0] + +#define DDRPHY_REG_SHU_R0_B0_RXDLY0 (DDRPHY_AO_BASE_ADDRESS + 0x0774) + #define SHU_R0_B0_RXDLY0_RX_ARDQ0_R_DLY_B0 Fld(8, 0) //[7:0] + #define SHU_R0_B0_RXDLY0_RX_ARDQ0_F_DLY_B0 Fld(8, 8) //[15:8] + #define SHU_R0_B0_RXDLY0_RX_ARDQ1_R_DLY_B0 Fld(8, 16) //[23:16] + #define SHU_R0_B0_RXDLY0_RX_ARDQ1_F_DLY_B0 Fld(8, 24) //[31:24] + +#define DDRPHY_REG_SHU_R0_B0_RXDLY1 (DDRPHY_AO_BASE_ADDRESS + 0x0778) + #define SHU_R0_B0_RXDLY1_RX_ARDQ2_R_DLY_B0 Fld(8, 0) //[7:0] + #define SHU_R0_B0_RXDLY1_RX_ARDQ2_F_DLY_B0 Fld(8, 8) //[15:8] + #define SHU_R0_B0_RXDLY1_RX_ARDQ3_R_DLY_B0 Fld(8, 16) //[23:16] + #define SHU_R0_B0_RXDLY1_RX_ARDQ3_F_DLY_B0 Fld(8, 24) //[31:24] + +#define DDRPHY_REG_SHU_R0_B0_RXDLY2 (DDRPHY_AO_BASE_ADDRESS + 0x077C) + #define SHU_R0_B0_RXDLY2_RX_ARDQ4_R_DLY_B0 Fld(8, 0) //[7:0] + #define SHU_R0_B0_RXDLY2_RX_ARDQ4_F_DLY_B0 Fld(8, 8) //[15:8] + #define SHU_R0_B0_RXDLY2_RX_ARDQ5_R_DLY_B0 Fld(8, 16) //[23:16] + #define SHU_R0_B0_RXDLY2_RX_ARDQ5_F_DLY_B0 Fld(8, 24) //[31:24] + +#define DDRPHY_REG_SHU_R0_B0_RXDLY3 (DDRPHY_AO_BASE_ADDRESS + 0x0780) + #define SHU_R0_B0_RXDLY3_RX_ARDQ6_R_DLY_B0 Fld(8, 0) //[7:0] + #define SHU_R0_B0_RXDLY3_RX_ARDQ6_F_DLY_B0 Fld(8, 8) //[15:8] + #define SHU_R0_B0_RXDLY3_RX_ARDQ7_R_DLY_B0 Fld(8, 16) //[23:16] + #define SHU_R0_B0_RXDLY3_RX_ARDQ7_F_DLY_B0 Fld(8, 24) //[31:24] + +#define DDRPHY_REG_SHU_R0_B0_RXDLY4 (DDRPHY_AO_BASE_ADDRESS + 0x0784) + #define SHU_R0_B0_RXDLY4_RX_ARDQM0_R_DLY_B0 Fld(8, 0) //[7:0] + #define SHU_R0_B0_RXDLY4_RX_ARDQM0_F_DLY_B0 Fld(8, 8) //[15:8] + +#define DDRPHY_REG_SHU_R0_B0_RXDLY5 (DDRPHY_AO_BASE_ADDRESS + 0x0788) + #define SHU_R0_B0_RXDLY5_RX_ARDQS0_R_DLY_B0 Fld(9, 0) //[8:0] + #define SHU_R0_B0_RXDLY5_RX_ARDQS0_F_DLY_B0 Fld(9, 16) //[24:16] + +#if 0 +#define DDRPHY_REG_SHU_R0_B0_RXDLY6 (DDRPHY_AO_BASE_ADDRESS + 0x078C) + #define SHU_R0_B0_RXDLY6_DMY_RXDLY6_B0 Fld(1, 0) //[0:0] + +#define DDRPHY_REG_SHU_R0_B0_RXDLY7 (DDRPHY_AO_BASE_ADDRESS + 0x0790) + #define SHU_R0_B0_RXDLY7_DMY_RXDLY7_B0 Fld(1, 0) //[0:0] +#else +#define DDRPHY_REG_SHU_RK_B0_DQ1 (DDRPHY_AO_BASE_ADDRESS + 0x078C) + #define SHU_RK_B0_DQ1_RG_RX_ARDQM0_OFFC_B0 Fld(4, 0) //[3:0] + +#define DDRPHY_REG_SHU_B0_PHY_VREF_SEL (DDRPHY_AO_BASE_ADDRESS + 0x0790) + #define SHU_B0_PHY_VREF_SEL_RG_RX_ARDQ_VREF_SEL_LB_B0 Fld(7, 0) //[6:0] + #define SHU_B0_PHY_VREF_SEL_RG_RX_ARDQ_VREF_SEL_UB_B0 Fld(7, 8) //[14:8] +#endif + +#define DDRPHY_REG_SHU_R0_B0_DQ0 (DDRPHY_AO_BASE_ADDRESS + 0x0794) + #define SHU_R0_B0_DQ0_RG_RX_ARDQS0_R_DLY_DUTY Fld(3, 0) //[2:0] + #define SHU_R0_B0_DQ0_RG_RX_ARDQS0_F_DLY_DUTY Fld(3, 4) //[6:4] + #define SHU_R0_B0_DQ0_SW_ARPI_DQ_B0 Fld(6, 8) //[13:8] + #define SHU_R0_B0_DQ0_SW_ARPI_DQM_B0 Fld(6, 16) //[21:16] + #define SHU_R0_B0_DQ0_ARPI_PBYTE_B0 Fld(6, 24) //[29:24] + #define SHU_R0_B0_DQ0_DA_ARPI_DDR400_0D5UI_RK0_B0 Fld(1, 30) //[30:30] + #define SHU_R0_B0_DQ0_DA_RX_ARDQSIEN_0D5UI_RK0_B0 Fld(1, 31) //[31:31] + +#define DDRPHY_REG_SHU_R0_B0_INI_UIPI (DDRPHY_AO_BASE_ADDRESS + 0x0798) + #define SHU_R0_B0_INI_UIPI_CURR_INI_PI_B0 Fld(7, 0) //[6:0] + #define SHU_R0_B0_INI_UIPI_CURR_INI_UI_B0 Fld(8, 8) //[15:8] + +#define DDRPHY_REG_SHU_R0_B0_NEXT_INI_UIPI (DDRPHY_AO_BASE_ADDRESS + 0x079C) + #define SHU_R0_B0_NEXT_INI_UIPI_NEXT_INI_PI_B0 Fld(7, 0) //[6:0] + #define SHU_R0_B0_NEXT_INI_UIPI_NEXT_INI_UI_B0 Fld(8, 8) //[15:8] + #define SHU_R0_B0_NEXT_INI_UIPI_NEXT_INI_UI_P1_B0 Fld(8, 24) //[31:24] + +#define DDRPHY_REG_SHU_RK_B0_DQSIEN_MCK_UI_DLY (DDRPHY_AO_BASE_ADDRESS + 0x07A0) + #define SHU_RK_B0_DQSIEN_MCK_UI_DLY_DQSIEN_UI_P0_B0 Fld(4, 0) //[3:0] + #define SHU_RK_B0_DQSIEN_MCK_UI_DLY_DQSIEN_UI_P1_B0 Fld(4, 4) //[7:4] + #define SHU_RK_B0_DQSIEN_MCK_UI_DLY_DQSIEN_MCK_P0_B0 Fld(4, 16) //[19:16] + #define SHU_RK_B0_DQSIEN_MCK_UI_DLY_DQSIEN_MCK_P1_B0 Fld(4, 20) //[23:20] + +#define DDRPHY_REG_SHU_RK_B0_DQSIEN_PI_DLY (DDRPHY_AO_BASE_ADDRESS + 0x07A4) + #define SHU_RK_B0_DQSIEN_PI_DLY_DQSIEN_PI_B0 Fld(7, 0) //[6:0] + +#define DDRPHY_REG_SHU_RK_B0_RODTEN_MCK_UI_DLY (DDRPHY_AO_BASE_ADDRESS + 0x07A8) + #define SHU_RK_B0_RODTEN_MCK_UI_DLY_RODTEN_UI_P0_B0 Fld(3, 0) //[2:0] + #define SHU_RK_B0_RODTEN_MCK_UI_DLY_RODTEN_UI_P1_B0 Fld(3, 4) //[6:4] + #define SHU_RK_B0_RODTEN_MCK_UI_DLY_RODTEN_MCK_P0_B0 Fld(3, 16) //[18:16] + #define SHU_RK_B0_RODTEN_MCK_UI_DLY_RODTEN_MCK_P1_B0 Fld(3, 20) //[22:20] + +#define DDRPHY_REG_SHU_RK_B0_DQ0 (DDRPHY_AO_BASE_ADDRESS + 0x07AC) + #define SHU_RK_B0_DQ0_RG_RX_ARDQ0_OFFC_B0 Fld(4, 0) //[3:0] + #define SHU_RK_B0_DQ0_RG_RX_ARDQ1_OFFC_B0 Fld(4, 4) //[7:4] + #define SHU_RK_B0_DQ0_RG_RX_ARDQ2_OFFC_B0 Fld(4, 8) //[11:8] + #define SHU_RK_B0_DQ0_RG_RX_ARDQ3_OFFC_B0 Fld(4, 12) //[15:12] + #define SHU_RK_B0_DQ0_RG_RX_ARDQ4_OFFC_B0 Fld(4, 16) //[19:16] + #define SHU_RK_B0_DQ0_RG_RX_ARDQ5_OFFC_B0 Fld(4, 20) //[23:20] + #define SHU_RK_B0_DQ0_RG_RX_ARDQ6_OFFC_B0 Fld(4, 24) //[27:24] + #define SHU_RK_B0_DQ0_RG_RX_ARDQ7_OFFC_B0 Fld(4, 28) //[31:28] + +#if 0 +#define DDRPHY_REG_SHU_RK_B0_DQ1 (DDRPHY_AO_BASE_ADDRESS + 0x07B0) + #define SHU_RK_B0_DQ1_RG_RX_ARDQM0_OFFC_B0 Fld(4, 0) //[3:0] + +#define DDRPHY_REG_SHU_B0_PHY_VREF_SEL (DDRPHY_AO_BASE_ADDRESS + 0x07B4) + #define SHU_B0_PHY_VREF_SEL_RG_RX_ARDQ_VREF_SEL_LB_B0 Fld(7, 0) //[6:0] + #define SHU_B0_PHY_VREF_SEL_RG_RX_ARDQ_VREF_SEL_UB_B0 Fld(7, 8) //[14:8] +#endif + +#define DDRPHY_REG_SHU_RK_B0_BIST_CTRL (DDRPHY_AO_BASE_ADDRESS + 0x07C0) + #define SHU_RK_B0_BIST_CTRL_BIST_TX_DQS_UI_DLY_B0 Fld(8, 0) //[7:0] + +#define DDRPHY_REG_SHU_B0_DQ0 (DDRPHY_AO_BASE_ADDRESS + 0x0860) + #define SHU_B0_DQ0_RG_TX_ARDQS0_PRE_EN_B0 Fld(1, 4) //[4:4] + #define SHU_B0_DQ0_RG_TX_ARDQS0_DRVP_PRE_B0 Fld(3, 8) //[10:8] + #define SHU_B0_DQ0_RG_TX_ARDQS0_DRVN_PRE_B0 Fld(3, 12) //[14:12] + #define SHU_B0_DQ0_RG_TX_ARDQ_PRE_EN_B0 Fld(1, 20) //[20:20] + #define SHU_B0_DQ0_RG_TX_ARDQ_DRVP_PRE_B0 Fld(3, 24) //[26:24] + #define SHU_B0_DQ0_RG_TX_ARDQ_DRVN_PRE_B0 Fld(3, 28) //[30:28] + #define SHU_B0_DQ0_R_LP4Y_WDN_MODE_DQS0 Fld(1, 31) //[31:31] + +#define DDRPHY_REG_SHU_B0_DQ3 (DDRPHY_AO_BASE_ADDRESS + 0x0864) + #define SHU_B0_DQ3_RG_TX_ARDQS0_PU_B0 Fld(2, 0) //[1:0] + #define SHU_B0_DQ3_RG_TX_ARDQS0_PU_PRE_B0 Fld(2, 2) //[3:2] + #define SHU_B0_DQ3_RG_TX_ARDQS0_PDB_B0 Fld(2, 4) //[5:4] + #define SHU_B0_DQ3_RG_TX_ARDQS0_PDB_PRE_B0 Fld(2, 6) //[7:6] + #define SHU_B0_DQ3_RG_TX_ARDQ_PU_B0 Fld(2, 8) //[9:8] + #define SHU_B0_DQ3_RG_TX_ARDQ_PU_PRE_B0 Fld(2, 10) //[11:10] + #define SHU_B0_DQ3_RG_TX_ARDQ_PDB_B0 Fld(2, 12) //[13:12] + #define SHU_B0_DQ3_RG_TX_ARDQ_PDB_PRE_B0 Fld(2, 14) //[15:14] + #define SHU_B0_DQ3_RG_ARDQ_DUTYREV_B0 Fld(9, 23) //[31:23] + +#define DDRPHY_REG_SHU_B0_DQ4 (DDRPHY_AO_BASE_ADDRESS + 0x0868) + #define SHU_B0_DQ4_RG_ARPI_AA_MCK_DL_B0 Fld(6, 0) //[5:0] + #define SHU_B0_DQ4_RG_ARPI_AA_MCK_FB_DL_B0 Fld(6, 8) //[13:8] + #define SHU_B0_DQ4_RG_ARPI_DA_MCK_FB_DL_B0 Fld(6, 16) //[21:16] + +#define DDRPHY_REG_SHU_B0_DQ5 (DDRPHY_AO_BASE_ADDRESS + 0x086C) + #define SHU_B0_DQ5_RG_RX_ARDQ_VREF_SEL_B0 Fld(6, 0) //[5:0] + #define SHU_B0_DQ5_RG_RX_ARDQ_VREF_BYPASS_B0 Fld(1, 6) //[6:6] + #define SHU_B0_DQ5_RG_ARPI_FB_B0 Fld(6, 8) //[13:8] + #define SHU_B0_DQ5_RG_RX_ARDQS0_DQSIEN_DLY_B0 Fld(3, 16) //[18:16] + #define SHU_B0_DQ5_RG_RX_ARDQS_DQSIEN_RB_DLY_B0 Fld(1, 19) //[19:19] + #define SHU_B0_DQ5_RG_RX_ARDQS0_DVS_DLY_B0 Fld(4, 20) //[23:20] + #define SHU_B0_DQ5_RG_RX_ARDQ_FIFO_DQSI_DLY_B0 Fld(3, 29) //[31:29] + +#define DDRPHY_REG_SHU_B0_DQ6 (DDRPHY_AO_BASE_ADDRESS + 0x0870) + #define SHU_B0_DQ6_RG_ARPI_OFFSET_DQSIEN_B0 Fld(6, 0) //[5:0] + #define SHU_B0_DQ6_RG_ARPI_OFFSET_MCTL_B0 Fld(6, 6) //[11:6] + #define SHU_B0_DQ6_RG_ARPI_CAP_SEL_B0 Fld(7, 12) //[18:12] + #define SHU_B0_DQ6_RG_ARPI_SOPEN_EN_B0 Fld(1, 20) //[20:20] + #define SHU_B0_DQ6_RG_ARPI_OPEN_EN_B0 Fld(1, 21) //[21:21] + #define SHU_B0_DQ6_RG_ARPI_HYST_SEL_B0 Fld(2, 22) //[23:22] + #define SHU_B0_DQ6_RG_ARPI_BUFGP_XLATCH_FORCE_DQ_B0 Fld(1, 24) //[24:24] + #define SHU_B0_DQ6_RG_ARPI_BUFGP_XLATCH_FORCE_DQS_B0 Fld(1, 25) //[25:25] + #define SHU_B0_DQ6_RG_ARPI_SOPEN_CKGEN_EN_B0 Fld(1, 26) //[26:26] + #define SHU_B0_DQ6_RG_ARPI_SOPEN_CKGEN_DIV_B0 Fld(1, 27) //[27:27] + #define SHU_B0_DQ6_RG_ARPI_DDR400_EN_B0 Fld(1, 28) //[28:28] + #define SHU_B0_DQ6_RG_RX_ARDQ_RANK_SEL_SER_MODE_B0 Fld(1, 29) //[29:29] + +#define DDRPHY_REG_SHU_B0_DQ1 (DDRPHY_AO_BASE_ADDRESS + 0x0874) + #define SHU_B0_DQ1_RG_ARPI_MIDPI_EN_B0 Fld(1, 0) //[0:0] + #define SHU_B0_DQ1_RG_ARPI_MIDPI_CKDIV4_PREDIV_EN_B0 Fld(1, 1) //[1:1] + #define SHU_B0_DQ1_RG_ARPI_MIDPI_CKDIV4_EN_B0 Fld(1, 2) //[2:2] + #define SHU_B0_DQ1_RG_ARPI_MIDPI_8PH_DLY_B0 Fld(5, 8) //[12:8] + #define SHU_B0_DQ1_RG_ARPI_MIDPI_LDO_VREF_SEL_B0 Fld(2, 16) //[17:16] + #define SHU_B0_DQ1_RG_ARPI_MIDPI_CAP_SEL_B0 Fld(2, 22) //[23:22] + #define SHU_B0_DQ1_RG_ARPI_MIDPI_VTH_SEL_B0 Fld(2, 24) //[25:24] + #define SHU_B0_DQ1_RG_ARPI_8PHASE_XLATCH_FORCE_B0 Fld(1, 26) //[26:26] + #define SHU_B0_DQ1_RG_ARPI_MIDPI_DUMMY_EN_B0 Fld(1, 27) //[27:27] + #define SHU_B0_DQ1_RG_ARPI_MIDPI_BYPASS_EN_B0 Fld(1, 31) //[31:31] + +#define DDRPHY_REG_SHU_B0_DQ2 (DDRPHY_AO_BASE_ADDRESS + 0x0878) + #define SHU_B0_DQ2_RG_ARPI_TX_CG_SYNC_DIS_B0 Fld(1, 0) //[0:0] + #define SHU_B0_DQ2_RG_ARPI_TX_CG_DQ_EN_B0 Fld(1, 4) //[4:4] + #define SHU_B0_DQ2_RG_ARPI_TX_CG_DQS_EN_B0 Fld(1, 5) //[5:5] + #define SHU_B0_DQ2_RG_ARPI_TX_CG_DQM_EN_B0 Fld(1, 6) //[6:6] + #define SHU_B0_DQ2_RG_ARPI_SMT_XLATCH_FORCE_DQS_B0 Fld(1, 8) //[8:8] + #define SHU_B0_DQ2_RG_ARPI_SMT_XLATCH_DQ_FORCE_B0 Fld(1, 9) //[9:9] + #define SHU_B0_DQ2_RG_ARPI_PSMUX_XLATCH_FORCE_DQ_B0 Fld(1, 10) //[10:10] + #define SHU_B0_DQ2_RG_ARPI_PSMUX_XLATCH_FORCE_DQS_B0 Fld(1, 11) //[11:11] + #define SHU_B0_DQ2_RG_ARPISM_MCK_SEL_B0_SHU Fld(1, 12) //[12:12] + #define SHU_B0_DQ2_RG_ARPI_PD_MCTL_SEL_B0 Fld(1, 13) //[13:13] + #define SHU_B0_DQ2_RG_ARPI_OFFSET_LAT_EN_B0 Fld(1, 16) //[16:16] + #define SHU_B0_DQ2_RG_ARPI_OFFSET_ASYNC_EN_B0 Fld(1, 17) //[17:17] + +#define DDRPHY_REG_SHU_B0_DQ10 (DDRPHY_AO_BASE_ADDRESS + 0x087C) + #define SHU_B0_DQ10_RG_RX_ARDQS_SE_EN_B0 Fld(1, 0) //[0:0] + #define SHU_B0_DQ10_RG_RX_ARDQS_DQSSTB_CG_EN_B0 Fld(1, 1) //[1:1] + #define SHU_B0_DQ10_RG_RX_ARDQS_DQSIEN_RANK_SEL_LAT_EN_B0 Fld(1, 2) //[2:2] + #define SHU_B0_DQ10_RG_RX_ARDQS_RANK_SEL_LAT_EN_B0 Fld(1, 3) //[3:3] + #define SHU_B0_DQ10_RG_RX_ARDQS_DQSSTB_RPST_HS_EN_B0 Fld(1, 4) //[4:4] + #define SHU_B0_DQ10_RG_RX_ARDQS_DQSIEN_MODE_B0 Fld(3, 8) //[10:8] + #define SHU_B0_DQ10_RG_RX_ARDQS_DLY_LAT_EN_B0 Fld(1, 15) //[15:15] + #define SHU_B0_DQ10_RG_RX_ARDQS_DIFF_SWAP_EN_B0 Fld(1, 16) //[16:16] + #define SHU_B0_DQ10_RG_RX_ARDQS_BW_SEL_B0 Fld(2, 18) //[19:18] + +#define DDRPHY_REG_SHU_B0_DQ11 (DDRPHY_AO_BASE_ADDRESS + 0x0880) + #define SHU_B0_DQ11_RG_RX_ARDQ_RANK_SEL_SER_EN_B0 Fld(1, 0) //[0:0] + #define SHU_B0_DQ11_RG_RX_ARDQ_RANK_SEL_LAT_EN_B0 Fld(1, 1) //[1:1] + #define SHU_B0_DQ11_RG_RX_ARDQ_OFFSETC_LAT_EN_B0 Fld(1, 2) //[2:2] + #define SHU_B0_DQ11_RG_RX_ARDQ_OFFSETC_EN_B0 Fld(1, 3) //[3:3] + #define SHU_B0_DQ11_RG_RX_ARDQ_OFFSETC_BIAS_EN_B0 Fld(1, 4) //[4:4] + #define SHU_B0_DQ11_RG_RX_ARDQ_FRATE_EN_B0 Fld(1, 5) //[5:5] + #define SHU_B0_DQ11_RG_RX_ARDQ_CDR_EN_B0 Fld(1, 6) //[6:6] + #define SHU_B0_DQ11_RG_RX_ARDQ_DVS_EN_B0 Fld(1, 7) //[7:7] + #define SHU_B0_DQ11_RG_RX_ARDQ_DVS_DLY_B0 Fld(4, 8) //[11:8] + #define SHU_B0_DQ11_RG_RX_ARDQ_DES_MODE_B0 Fld(2, 16) //[17:16] + #define SHU_B0_DQ11_RG_RX_ARDQ_BW_SEL_B0 Fld(2, 18) //[19:18] + +#define DDRPHY_REG_SHU_B0_DQ7 (DDRPHY_AO_BASE_ADDRESS + 0x0884) + #define SHU_B0_DQ7_R_DMRANKRXDVS_B0 Fld(4, 0) //[3:0] + #define SHU_B0_DQ7_R_DMDQMDBI_EYE_SHU_B0 Fld(1, 6) //[6:6] + #define SHU_B0_DQ7_R_DMDQMDBI_SHU_B0 Fld(1, 7) //[7:7] + #define SHU_B0_DQ7_R_DMRXDVS_DQM_FLAGSEL_B0 Fld(4, 8) //[11:8] + #define SHU_B0_DQ7_R_DMRXDVS_PBYTE_FLAG_OPT_B0 Fld(1, 12) //[12:12] + #define SHU_B0_DQ7_R_DMRXDVS_PBYTE_DQM_EN_B0 Fld(1, 13) //[13:13] + #define SHU_B0_DQ7_R_DMRXTRACK_DQM_EN_B0 Fld(1, 14) //[14:14] + #define SHU_B0_DQ7_R_DMRODTEN_B0 Fld(1, 15) //[15:15] + #define SHU_B0_DQ7_R_DMARPI_CG_FB2DLL_DCM_EN_B0 Fld(1, 16) //[16:16] + #define SHU_B0_DQ7_R_DMTX_ARPI_CG_DQ_NEW_B0 Fld(1, 17) //[17:17] + #define SHU_B0_DQ7_R_DMTX_ARPI_CG_DQS_NEW_B0 Fld(1, 18) //[18:18] + #define SHU_B0_DQ7_R_DMTX_ARPI_CG_DQM_NEW_B0 Fld(1, 19) //[19:19] + #define SHU_B0_DQ7_R_LP4Y_SDN_MODE_DQS0 Fld(1, 20) //[20:20] + #define SHU_B0_DQ7_R_DMRXRANK_DQ_EN_B0 Fld(1, 24) //[24:24] + #define SHU_B0_DQ7_R_DMRXRANK_DQ_LAT_B0 Fld(3, 25) //[27:25] + #define SHU_B0_DQ7_R_DMRXRANK_DQS_EN_B0 Fld(1, 28) //[28:28] + #define SHU_B0_DQ7_R_DMRXRANK_DQS_LAT_B0 Fld(3, 29) //[31:29] + +#define DDRPHY_REG_SHU_B0_DQ8 (DDRPHY_AO_BASE_ADDRESS + 0x0888) + #define SHU_B0_DQ8_R_DMRXDVS_UPD_FORCE_CYC_B0 Fld(15, 0) //[14:0] + #define SHU_B0_DQ8_R_DMRXDVS_UPD_FORCE_EN_B0 Fld(1, 15) //[15:15] + #define SHU_B0_DQ8_R_DMRANK_RXDLY_PIPE_CG_IG_B0 Fld(1, 19) //[19:19] + #define SHU_B0_DQ8_R_RMRODTEN_CG_IG_B0 Fld(1, 20) //[20:20] + #define SHU_B0_DQ8_R_RMRX_TOPHY_CG_IG_B0 Fld(1, 21) //[21:21] + #define SHU_B0_DQ8_R_DMRXDVS_RDSEL_PIPE_CG_IG_B0 Fld(1, 22) //[22:22] + #define SHU_B0_DQ8_R_DMRXDVS_RDSEL_TOG_PIPE_CG_IG_B0 Fld(1, 23) //[23:23] + #define SHU_B0_DQ8_R_DMRXDLY_CG_IG_B0 Fld(1, 24) //[24:24] + #define SHU_B0_DQ8_R_DMDQSIEN_FLAG_SYNC_CG_IG_B0 Fld(1, 26) //[26:26] + #define SHU_B0_DQ8_R_DMDQSIEN_FLAG_PIPE_CG_IG_B0 Fld(1, 27) //[27:27] + #define SHU_B0_DQ8_R_DMDQSIEN_RDSEL_PIPE_CG_IG_B0 Fld(1, 28) //[28:28] + #define SHU_B0_DQ8_R_DMDQSIEN_RDSEL_TOG_PIPE_CG_IG_B0 Fld(1, 29) //[29:29] + #define SHU_B0_DQ8_R_DMRANK_PIPE_CG_IG_B0 Fld(1, 30) //[30:30] + #define SHU_B0_DQ8_R_DMRANK_CHG_PIPE_CG_IG_B0 Fld(1, 31) //[31:31] + +#define DDRPHY_REG_SHU_B0_DQ9 (DDRPHY_AO_BASE_ADDRESS + 0x088C) + #define SHU_B0_DQ9_RG_ARPI_RESERVE_B0 Fld(32, 0) //[31:0] + +#define DDRPHY_REG_SHU_B0_DQ12 (DDRPHY_AO_BASE_ADDRESS + 0x0890) + #define SHU_B0_DQ12_DMY_DQ12_B0 Fld(1, 0) //[0:0] + +#define DDRPHY_REG_SHU_B0_DLL0 (DDRPHY_AO_BASE_ADDRESS + 0x0894) + #define SHU_B0_DLL0_RG_ARDLL_LCK_DET_LV2_DLY_B0 Fld(3, 0) //[2:0] + #define SHU_B0_DLL0_RG_ARDLL_LCK_DET_LV1_DLY_B0 Fld(3, 4) //[6:4] + #define SHU_B0_DLL0_RG_ARDLL_LCK_DET_EN_B0 Fld(1, 8) //[8:8] + #define SHU_B0_DLL0_RG_ARDLL_IDLECNT_B0 Fld(4, 12) //[15:12] + #define SHU_B0_DLL0_RG_ARDLL_HOLD_ON_LOCK_EN_B0 Fld(1, 16) //[16:16] + #define SHU_B0_DLL0_RG_ARDLL_GAIN_BOOST_B0 Fld(3, 17) //[19:17] + #define SHU_B0_DLL0_RG_ARDLL_GAIN_B0 Fld(4, 20) //[23:20] + #define SHU_B0_DLL0_RG_ARDLL_FAST_DIV_EN_B0 Fld(1, 24) //[24:24] + #define SHU_B0_DLL0_RG_ARDLL_FAST_PSJP_B0 Fld(1, 25) //[25:25] + #define SHU_B0_DLL0_RG_ARDLL_FASTPJ_CK_SEL_B0 Fld(1, 26) //[26:26] + #define SHU_B0_DLL0_RG_ARDLL_GEAR2_PSJP_B0 Fld(1, 27) //[27:27] + +#define DDRPHY_REG_SHU_B0_DLL1 (DDRPHY_AO_BASE_ADDRESS + 0x0898) + #define SHU_B0_DLL1_RG_ARDLL_AD_ARFB_CK_EN_B0 Fld(1, 0) //[0:0] + #define SHU_B0_DLL1_RG_ARDLL_DIV_MODE_B0 Fld(2, 2) //[3:2] + #define SHU_B0_DLL1_RG_ARDLL_UDIV_EN_B0 Fld(1, 4) //[4:4] + #define SHU_B0_DLL1_RG_ARDLL_UPDATE_ON_IDLE_EN_B0 Fld(1, 5) //[5:5] + #define SHU_B0_DLL1_RG_ARDLL_TRACKING_CA_EN_B0 Fld(1, 6) //[6:6] + #define SHU_B0_DLL1_RG_ARDLL_UPDATE_ON_IDLE_MODE_B0 Fld(1, 7) //[7:7] + #define SHU_B0_DLL1_RG_ARDLL_SER_MODE_B0 Fld(2, 8) //[9:8] + #define SHU_B0_DLL1_RG_ARDLL_PS_EN_B0 Fld(1, 10) //[10:10] + #define SHU_B0_DLL1_RG_ARDLL_PSJP_EN_B0 Fld(1, 11) //[11:11] + #define SHU_B0_DLL1_RG_ARDLL_PHDIV_B0 Fld(1, 12) //[12:12] + #define SHU_B0_DLL1_RG_ARDLL_PHDET_OUT_SEL_B0 Fld(1, 13) //[13:13] + #define SHU_B0_DLL1_RG_ARDLL_PHDET_IN_SWAP_B0 Fld(1, 14) //[14:14] + #define SHU_B0_DLL1_RG_ARDLL_PHDET_EN_B0 Fld(1, 16) //[16:16] + #define SHU_B0_DLL1_RG_ARDLL_DIV_MCTL_B0 Fld(2, 18) //[19:18] + #define SHU_B0_DLL1_RG_ARDLL_PGAIN_B0 Fld(4, 20) //[23:20] + #define SHU_B0_DLL1_RG_ARDLL_PD_CK_SEL_B0 Fld(1, 24) //[24:24] + +#define DDRPHY_REG_SHU_B0_DLL2 (DDRPHY_AO_BASE_ADDRESS + 0x089C) + #define SHU_B0_DLL2_RG_ARDQ_REV_B0 Fld(32, 0) //[31:0] + +#define DDRPHY_REG_SHU_B0_RANK_SELPH_UI_DLY (DDRPHY_AO_BASE_ADDRESS + 0x08A0) + #define SHU_B0_RANK_SELPH_UI_DLY_RANKSEL_UI_DLY_P0_B0 Fld(3, 0) //[2:0] + #define SHU_B0_RANK_SELPH_UI_DLY_RANKSEL_UI_DLY_P1_B0 Fld(3, 4) //[6:4] + #define SHU_B0_RANK_SELPH_UI_DLY_RANKSEL_MCK_DLY_P0_B0 Fld(3, 16) //[18:16] + #define SHU_B0_RANK_SELPH_UI_DLY_RANKSEL_MCK_DLY_P1_B0 Fld(3, 20) //[22:20] + +#define DDRPHY_REG_SHU_B0_DLL_ARPI2 (DDRPHY_AO_BASE_ADDRESS + 0x08A4) + #define SHU_B0_DLL_ARPI2_RG_ARPI_MPDIV_CG_B0 Fld(1, 10) //[10:10] + #define SHU_B0_DLL_ARPI2_RG_ARPI_CG_DQSIEN_B0 Fld(1, 11) //[11:11] + #define SHU_B0_DLL_ARPI2_RG_ARPI_CG_DQ_B0 Fld(1, 13) //[13:13] + #define SHU_B0_DLL_ARPI2_RG_ARPI_CG_DQM_B0 Fld(1, 14) //[14:14] + #define SHU_B0_DLL_ARPI2_RG_ARPI_CG_DQS_B0 Fld(1, 15) //[15:15] + #define SHU_B0_DLL_ARPI2_RG_ARPI_CG_FB_B0 Fld(1, 17) //[17:17] + #define SHU_B0_DLL_ARPI2_RG_ARPI_CG_MCTL_B0 Fld(1, 19) //[19:19] + #define SHU_B0_DLL_ARPI2_RG_ARPI_CG_MCK_FB2DLL_B0 Fld(1, 27) //[27:27] + #define SHU_B0_DLL_ARPI2_RG_ARPI_CG_MCK_B0 Fld(1, 31) //[31:31] + +#define DDRPHY_REG_SHU_B0_DLL_ARPI3 (DDRPHY_AO_BASE_ADDRESS + 0x08A8) + #define SHU_B0_DLL_ARPI3_RG_ARPI_DQSIEN_EN_B0 Fld(1, 11) //[11:11] + #define SHU_B0_DLL_ARPI3_RG_ARPI_DQ_EN_B0 Fld(1, 13) //[13:13] + #define SHU_B0_DLL_ARPI3_RG_ARPI_DQM_EN_B0 Fld(1, 14) //[14:14] + #define SHU_B0_DLL_ARPI3_RG_ARPI_DQS_EN_B0 Fld(1, 15) //[15:15] + #define SHU_B0_DLL_ARPI3_RG_ARPI_FB_EN_B0 Fld(1, 17) //[17:17] + #define SHU_B0_DLL_ARPI3_RG_ARPI_MCTL_EN_B0 Fld(1, 19) //[19:19] + +#define DDRPHY_REG_SHU_B0_TXDUTY (DDRPHY_AO_BASE_ADDRESS + 0x08AC) + #define SHU_B0_TXDUTY_DA_TX_ARDQ_DUTY_DLY_B0 Fld(6, 0) //[5:0] + #define SHU_B0_TXDUTY_DA_TX_ARDQS_DUTY_DLY_B0 Fld(6, 8) //[13:8] + #define SHU_B0_TXDUTY_DA_TX_ARDQM_DUTY_DLY_B0 Fld(6, 16) //[21:16] + #define SHU_B0_TXDUTY_DA_TX_ARWCK_DUTY_DLY_B0 Fld(6, 24) //[29:24] + +#define DDRPHY_REG_SHU_B0_VREF (DDRPHY_AO_BASE_ADDRESS + 0x08B0) + #define SHU_B0_VREF_RG_RX_ARDQ_VREF_SEL_DQS_B0 Fld(7, 0) //[6:0] + #define SHU_B0_VREF_RG_RX_ARDQ_VREF_RANK_SEL_EN_B0 Fld(1, 16) //[16:16] + #define SHU_B0_VREF_RG_RX_ARDQ_VREF_EN_UB_RK1_B0 Fld(1, 17) //[17:17] + #define SHU_B0_VREF_RG_RX_ARDQ_VREF_EN_UB_RK0_B0 Fld(1, 18) //[18:18] + #define SHU_B0_VREF_RG_RX_ARDQ_VREF_EN_LB_RK1_B0 Fld(1, 19) //[19:19] + #define SHU_B0_VREF_RG_RX_ARDQ_VREF_EN_LB_RK0_B0 Fld(1, 20) //[20:20] + #define SHU_B0_VREF_RG_RX_ARDQ_VREF_EN_DQS_B0 Fld(1, 21) //[21:21] + #define SHU_B0_VREF_RG_RX_ARDQ_VREF_UNTERM_EN_B0 Fld(1, 22) //[22:22] + +#define DDRPHY_REG_SHU_B0_DQ13 (DDRPHY_AO_BASE_ADDRESS + 0x08B4) + #define SHU_B0_DQ13_RG_TX_ARDQ_IO_ODT_DIS_B0 Fld(1, 0) //[0:0] + #define SHU_B0_DQ13_RG_TX_ARDQ_FRATE_EN_B0 Fld(1, 1) //[1:1] + #define SHU_B0_DQ13_RG_TX_ARDQ_DLY_LAT_EN_B0 Fld(1, 2) //[2:2] + #define SHU_B0_DQ13_RG_TX_ARDQS_READ_BASE_EN_B0 Fld(1, 3) //[3:3] + #define SHU_B0_DQ13_RG_TX_ARDQS_PRE_DATA_SEL_B0 Fld(1, 5) //[5:5] + #define SHU_B0_DQ13_RG_TX_ARDQS_OE_ODTEN_SWAP_B0 Fld(1, 6) //[6:6] + #define SHU_B0_DQ13_RG_TX_ARDQS_OE_ODTEN_CG_EN_B0 Fld(1, 7) //[7:7] + #define SHU_B0_DQ13_RG_TX_ARDQS_MCKIO_CG_B0 Fld(1, 8) //[8:8] + #define SHU_B0_DQ13_RG_TX_ARDQS_MCKIO_SEL_B0 Fld(2, 12) //[13:12] + #define SHU_B0_DQ13_RG_TX_ARDQM_MCKIO_SEL_B0 Fld(1, 14) //[14:14] + #define SHU_B0_DQ13_RG_TX_ARDQSB_READ_BASE_EN_B0 Fld(1, 15) //[15:15] + #define SHU_B0_DQ13_RG_TX_ARDQM_OE_ODTEN_CG_EN_B0 Fld(1, 16) //[16:16] + #define SHU_B0_DQ13_RG_TX_ARDQSB_READ_BASE_DATA_TIE_EN_B0 Fld(1, 17) //[17:17] + #define SHU_B0_DQ13_RG_TX_ARDQS_READ_BASE_DATA_TIE_EN_B0 Fld(1, 18) //[18:18] + #define SHU_B0_DQ13_RG_TX_ARDQ_READ_BASE_EN_B0 Fld(1, 19) //[19:19] + #define SHU_B0_DQ13_RG_TX_ARDQ_READ_BASE_DATA_TIE_EN_B0 Fld(1, 20) //[20:20] + #define SHU_B0_DQ13_RG_TX_ARDQSB_OE_TIE_SEL_B0 Fld(1, 24) //[24:24] + #define SHU_B0_DQ13_RG_TX_ARDQSB_OE_TIE_EN_B0 Fld(1, 25) //[25:25] + +#define DDRPHY_REG_SHU_B0_DQ14 (DDRPHY_AO_BASE_ADDRESS + 0x08B8) + #define SHU_B0_DQ14_RG_TX_ARWCK_PRE_EN_B0 Fld(1, 0) //[0:0] + #define SHU_B0_DQ14_RG_TX_ARWCK_PRE_DATA_SEL_B0 Fld(1, 1) //[1:1] + #define SHU_B0_DQ14_RG_TX_ARWCK_MCKIO_SEL_B0 Fld(1, 2) //[2:2] + #define SHU_B0_DQ14_RG_TX_ARDQ_SER_MODE_B0 Fld(2, 4) //[5:4] + #define SHU_B0_DQ14_RG_TX_ARDQ_AUX_SER_MODE_B0 Fld(1, 6) //[6:6] + #define SHU_B0_DQ14_RG_TX_ARDQ_PRE_DATA_SEL_B0 Fld(1, 9) //[9:9] + #define SHU_B0_DQ14_RG_TX_ARDQ_OE_ODTEN_SWAP_B0 Fld(1, 10) //[10:10] + #define SHU_B0_DQ14_RG_TX_ARDQ_OE_ODTEN_CG_EN_B0 Fld(1, 11) //[11:11] + #define SHU_B0_DQ14_RG_TX_ARDQ_MCKIO_SEL_B0 Fld(8, 16) //[23:16] + +#define DDRPHY_REG_B0_SHU_MIDPI_CTRL (DDRPHY_AO_BASE_ADDRESS + 0x08BC) + #define B0_SHU_MIDPI_CTRL_MIDPI_ENABLE_B0 Fld(1, 0) //[0:0] + #define B0_SHU_MIDPI_CTRL_MIDPI_DIV4_ENABLE_B0 Fld(1, 1) //[1:1] + +#define DDRPHY_REG_SHU_R0_B1_TXDLY0 (DDRPHY_AO_BASE_ADDRESS + 0x08E0) + #define SHU_R0_B1_TXDLY0_TX_ARDQ0_DLY_B1 Fld(8, 0) //[7:0] + #define SHU_R0_B1_TXDLY0_TX_ARDQ1_DLY_B1 Fld(8, 8) //[15:8] + #define SHU_R0_B1_TXDLY0_TX_ARDQ2_DLY_B1 Fld(8, 16) //[23:16] + #define SHU_R0_B1_TXDLY0_TX_ARDQ3_DLY_B1 Fld(8, 24) //[31:24] + +#define DDRPHY_REG_SHU_R0_B1_TXDLY1 (DDRPHY_AO_BASE_ADDRESS + 0x08E4) + #define SHU_R0_B1_TXDLY1_TX_ARDQ4_DLY_B1 Fld(8, 0) //[7:0] + #define SHU_R0_B1_TXDLY1_TX_ARDQ5_DLY_B1 Fld(8, 8) //[15:8] + #define SHU_R0_B1_TXDLY1_TX_ARDQ6_DLY_B1 Fld(8, 16) //[23:16] + #define SHU_R0_B1_TXDLY1_TX_ARDQ7_DLY_B1 Fld(8, 24) //[31:24] + +#define DDRPHY_REG_SHU_R0_B1_TXDLY2 (DDRPHY_AO_BASE_ADDRESS + 0x08E8) + #define SHU_R0_B1_TXDLY2_TX_ARDQS0_DLYB_B1 Fld(8, 0) //[7:0] + #define SHU_R0_B1_TXDLY2_TX_ARDQS0B_DLYB_B1 Fld(8, 8) //[15:8] + #define SHU_R0_B1_TXDLY2_TX_ARDQS0_DLY_B1 Fld(8, 16) //[23:16] + #define SHU_R0_B1_TXDLY2_TX_ARDQS0B_DLY_B1 Fld(8, 24) //[31:24] + +#define DDRPHY_REG_SHU_R0_B1_TXDLY3 (DDRPHY_AO_BASE_ADDRESS + 0x08EC) + #define SHU_R0_B1_TXDLY3_TX_ARDQM0_DLY_B1 Fld(8, 0) //[7:0] + #define SHU_R0_B1_TXDLY3_TX_ARWCK_DLY_B1 Fld(8, 16) //[23:16] + #define SHU_R0_B1_TXDLY3_TX_ARWCKB_DLY_B1 Fld(8, 24) //[31:24] + +#define DDRPHY_REG_SHU_R0_B1_TXDLY4 (DDRPHY_AO_BASE_ADDRESS + 0x08F0) + #define SHU_R0_B1_TXDLY4_DMY_TXDLY4_B1 Fld(1, 0) //[0:0] + +#define DDRPHY_REG_SHU_R0_B1_RXDLY0 (DDRPHY_AO_BASE_ADDRESS + 0x08F4) + #define SHU_R0_B1_RXDLY0_RX_ARDQ0_R_DLY_B1 Fld(8, 0) //[7:0] + #define SHU_R0_B1_RXDLY0_RX_ARDQ0_F_DLY_B1 Fld(8, 8) //[15:8] + #define SHU_R0_B1_RXDLY0_RX_ARDQ1_R_DLY_B1 Fld(8, 16) //[23:16] + #define SHU_R0_B1_RXDLY0_RX_ARDQ1_F_DLY_B1 Fld(8, 24) //[31:24] + +#define DDRPHY_REG_SHU_R0_B1_RXDLY1 (DDRPHY_AO_BASE_ADDRESS + 0x08F8) + #define SHU_R0_B1_RXDLY1_RX_ARDQ2_R_DLY_B1 Fld(8, 0) //[7:0] + #define SHU_R0_B1_RXDLY1_RX_ARDQ2_F_DLY_B1 Fld(8, 8) //[15:8] + #define SHU_R0_B1_RXDLY1_RX_ARDQ3_R_DLY_B1 Fld(8, 16) //[23:16] + #define SHU_R0_B1_RXDLY1_RX_ARDQ3_F_DLY_B1 Fld(8, 24) //[31:24] + +#define DDRPHY_REG_SHU_R0_B1_RXDLY2 (DDRPHY_AO_BASE_ADDRESS + 0x08FC) + #define SHU_R0_B1_RXDLY2_RX_ARDQ4_R_DLY_B1 Fld(8, 0) //[7:0] + #define SHU_R0_B1_RXDLY2_RX_ARDQ4_F_DLY_B1 Fld(8, 8) //[15:8] + #define SHU_R0_B1_RXDLY2_RX_ARDQ5_R_DLY_B1 Fld(8, 16) //[23:16] + #define SHU_R0_B1_RXDLY2_RX_ARDQ5_F_DLY_B1 Fld(8, 24) //[31:24] + +#define DDRPHY_REG_SHU_R0_B1_RXDLY3 (DDRPHY_AO_BASE_ADDRESS + 0x0900) + #define SHU_R0_B1_RXDLY3_RX_ARDQ6_R_DLY_B1 Fld(8, 0) //[7:0] + #define SHU_R0_B1_RXDLY3_RX_ARDQ6_F_DLY_B1 Fld(8, 8) //[15:8] + #define SHU_R0_B1_RXDLY3_RX_ARDQ7_R_DLY_B1 Fld(8, 16) //[23:16] + #define SHU_R0_B1_RXDLY3_RX_ARDQ7_F_DLY_B1 Fld(8, 24) //[31:24] + +#define DDRPHY_REG_SHU_R0_B1_RXDLY4 (DDRPHY_AO_BASE_ADDRESS + 0x0904) + #define SHU_R0_B1_RXDLY4_RX_ARDQM0_R_DLY_B1 Fld(8, 0) //[7:0] + #define SHU_R0_B1_RXDLY4_RX_ARDQM0_F_DLY_B1 Fld(8, 8) //[15:8] + +#define DDRPHY_REG_SHU_R0_B1_RXDLY5 (DDRPHY_AO_BASE_ADDRESS + 0x0908) + #define SHU_R0_B1_RXDLY5_RX_ARDQS0_R_DLY_B1 Fld(9, 0) //[8:0] + #define SHU_R0_B1_RXDLY5_RX_ARDQS0_F_DLY_B1 Fld(9, 16) //[24:16] + +#if 0 +#define DDRPHY_REG_SHU_R0_B1_RXDLY6 (DDRPHY_AO_BASE_ADDRESS + 0x090C) + #define SHU_R0_B1_RXDLY6_DMY_RXDLY6_B1 Fld(1, 0) //[0:0] + +#define DDRPHY_REG_SHU_R0_B1_RXDLY7 (DDRPHY_AO_BASE_ADDRESS + 0x0910) + #define SHU_R0_B1_RXDLY7_DMY_RXDLY7_B1 Fld(1, 0) //[0:0] +#else +#define DDRPHY_REG_SHU_RK_B1_DQ1 (DDRPHY_AO_BASE_ADDRESS + 0x090C) + #define SHU_RK_B1_DQ1_RG_RX_ARDQM0_OFFC_B1 Fld(4, 0) //[3:0] + +#define DDRPHY_REG_SHU_B1_PHY_VREF_SEL (DDRPHY_AO_BASE_ADDRESS + 0x0910) + #define SHU_B1_PHY_VREF_SEL_RG_RX_ARDQ_VREF_SEL_LB_B1 Fld(7, 0) //[6:0] + #define SHU_B1_PHY_VREF_SEL_RG_RX_ARDQ_VREF_SEL_UB_B1 Fld(7, 8) //[14:8] +#endif + +#define DDRPHY_REG_SHU_R0_B1_DQ0 (DDRPHY_AO_BASE_ADDRESS + 0x0914) + #define SHU_R0_B1_DQ0_RG_RX_ARDQS1_R_DLY_DUTY Fld(3, 0) //[2:0] + #define SHU_R0_B1_DQ0_RG_RX_ARDQS1_F_DLY_DUTY Fld(3, 4) //[6:4] + #define SHU_R0_B1_DQ0_SW_ARPI_DQ_B1 Fld(6, 8) //[13:8] + #define SHU_R0_B1_DQ0_SW_ARPI_DQM_B1 Fld(6, 16) //[21:16] + #define SHU_R0_B1_DQ0_ARPI_PBYTE_B1 Fld(6, 24) //[29:24] + #define SHU_R0_B1_DQ0_DA_ARPI_DDR400_0D5UI_RK0_B1 Fld(1, 30) //[30:30] + #define SHU_R0_B1_DQ0_DA_RX_ARDQSIEN_0D5UI_RK0_B1 Fld(1, 31) //[31:31] + +#define DDRPHY_REG_SHU_R0_B1_INI_UIPI (DDRPHY_AO_BASE_ADDRESS + 0x0918) + #define SHU_R0_B1_INI_UIPI_CURR_INI_PI_B1 Fld(7, 0) //[6:0] + #define SHU_R0_B1_INI_UIPI_CURR_INI_UI_B1 Fld(8, 8) //[15:8] + +#define DDRPHY_REG_SHU_R0_B1_NEXT_INI_UIPI (DDRPHY_AO_BASE_ADDRESS + 0x091C) + #define SHU_R0_B1_NEXT_INI_UIPI_NEXT_INI_PI_B1 Fld(7, 0) //[6:0] + #define SHU_R0_B1_NEXT_INI_UIPI_NEXT_INI_UI_B1 Fld(8, 8) //[15:8] + #define SHU_R0_B1_NEXT_INI_UIPI_NEXT_INI_UI_P1_B1 Fld(8, 24) //[31:24] + +#define DDRPHY_REG_SHU_RK_B1_DQSIEN_MCK_UI_DLY (DDRPHY_AO_BASE_ADDRESS + 0x0920) + #define SHU_RK_B1_DQSIEN_MCK_UI_DLY_DQSIEN_UI_P0_B1 Fld(4, 0) //[3:0] + #define SHU_RK_B1_DQSIEN_MCK_UI_DLY_DQSIEN_UI_P1_B1 Fld(4, 4) //[7:4] + #define SHU_RK_B1_DQSIEN_MCK_UI_DLY_DQSIEN_MCK_P0_B1 Fld(4, 16) //[19:16] + #define SHU_RK_B1_DQSIEN_MCK_UI_DLY_DQSIEN_MCK_P1_B1 Fld(4, 20) //[23:20] + +#define DDRPHY_REG_SHU_RK_B1_DQSIEN_PI_DLY (DDRPHY_AO_BASE_ADDRESS + 0x0924) + #define SHU_RK_B1_DQSIEN_PI_DLY_DQSIEN_PI_B1 Fld(7, 0) //[6:0] + +#define DDRPHY_REG_SHU_RK_B1_RODTEN_MCK_UI_DLY (DDRPHY_AO_BASE_ADDRESS + 0x0928) + #define SHU_RK_B1_RODTEN_MCK_UI_DLY_RODTEN_UI_P0_B1 Fld(3, 0) //[2:0] + #define SHU_RK_B1_RODTEN_MCK_UI_DLY_RODTEN_UI_P1_B1 Fld(3, 4) //[6:4] + #define SHU_RK_B1_RODTEN_MCK_UI_DLY_RODTEN_MCK_P0_B1 Fld(3, 16) //[18:16] + #define SHU_RK_B1_RODTEN_MCK_UI_DLY_RODTEN_MCK_P1_B1 Fld(3, 20) //[22:20] + +#define DDRPHY_REG_SHU_RK_B1_DQ0 (DDRPHY_AO_BASE_ADDRESS + 0x092C) + #define SHU_RK_B1_DQ0_RG_RX_ARDQ0_OFFC_B1 Fld(4, 0) //[3:0] + #define SHU_RK_B1_DQ0_RG_RX_ARDQ1_OFFC_B1 Fld(4, 4) //[7:4] + #define SHU_RK_B1_DQ0_RG_RX_ARDQ2_OFFC_B1 Fld(4, 8) //[11:8] + #define SHU_RK_B1_DQ0_RG_RX_ARDQ3_OFFC_B1 Fld(4, 12) //[15:12] + #define SHU_RK_B1_DQ0_RG_RX_ARDQ4_OFFC_B1 Fld(4, 16) //[19:16] + #define SHU_RK_B1_DQ0_RG_RX_ARDQ5_OFFC_B1 Fld(4, 20) //[23:20] + #define SHU_RK_B1_DQ0_RG_RX_ARDQ6_OFFC_B1 Fld(4, 24) //[27:24] + #define SHU_RK_B1_DQ0_RG_RX_ARDQ7_OFFC_B1 Fld(4, 28) //[31:28] + +#if 0 +#define DDRPHY_REG_SHU_RK_B1_DQ1 (DDRPHY_AO_BASE_ADDRESS + 0x0930) + #define SHU_RK_B1_DQ1_RG_RX_ARDQM0_OFFC_B1 Fld(4, 0) //[3:0] + +#define DDRPHY_REG_SHU_B1_PHY_VREF_SEL (DDRPHY_AO_BASE_ADDRESS + 0x0934) + #define SHU_B1_PHY_VREF_SEL_RG_RX_ARDQ_VREF_SEL_LB_B1 Fld(7, 0) //[6:0] + #define SHU_B1_PHY_VREF_SEL_RG_RX_ARDQ_VREF_SEL_UB_B1 Fld(7, 8) //[14:8] +#endif + +#define DDRPHY_REG_SHU_RK_B1_BIST_CTRL (DDRPHY_AO_BASE_ADDRESS + 0x0940) + #define SHU_RK_B1_BIST_CTRL_BIST_TX_DQS_UI_DLY_B1 Fld(8, 0) //[7:0] + +#define DDRPHY_REG_SHU_B1_DQ0 (DDRPHY_AO_BASE_ADDRESS + 0x09E0) + #define SHU_B1_DQ0_RG_TX_ARDQS0_PRE_EN_B1 Fld(1, 4) //[4:4] + #define SHU_B1_DQ0_RG_TX_ARDQS0_DRVP_PRE_B1 Fld(3, 8) //[10:8] + #define SHU_B1_DQ0_RG_TX_ARDQS0_DRVN_PRE_B1 Fld(3, 12) //[14:12] + #define SHU_B1_DQ0_RG_TX_ARDQ_PRE_EN_B1 Fld(1, 20) //[20:20] + #define SHU_B1_DQ0_RG_TX_ARDQ_DRVP_PRE_B1 Fld(3, 24) //[26:24] + #define SHU_B1_DQ0_RG_TX_ARDQ_DRVN_PRE_B1 Fld(3, 28) //[30:28] + #define SHU_B1_DQ0_R_LP4Y_WDN_MODE_DQS1 Fld(1, 31) //[31:31] + +#define DDRPHY_REG_SHU_B1_DQ3 (DDRPHY_AO_BASE_ADDRESS + 0x09E4) + #define SHU_B1_DQ3_RG_TX_ARDQS0_PU_B1 Fld(2, 0) //[1:0] + #define SHU_B1_DQ3_RG_TX_ARDQS0_PU_PRE_B1 Fld(2, 2) //[3:2] + #define SHU_B1_DQ3_RG_TX_ARDQS0_PDB_B1 Fld(2, 4) //[5:4] + #define SHU_B1_DQ3_RG_TX_ARDQS0_PDB_PRE_B1 Fld(2, 6) //[7:6] + #define SHU_B1_DQ3_RG_TX_ARDQ_PU_B1 Fld(2, 8) //[9:8] + #define SHU_B1_DQ3_RG_TX_ARDQ_PU_PRE_B1 Fld(2, 10) //[11:10] + #define SHU_B1_DQ3_RG_TX_ARDQ_PDB_B1 Fld(2, 12) //[13:12] + #define SHU_B1_DQ3_RG_TX_ARDQ_PDB_PRE_B1 Fld(2, 14) //[15:14] + #define SHU_B1_DQ3_RG_ARDQ_DUTYREV_B1 Fld(9, 23) //[31:23] + +#define DDRPHY_REG_SHU_B1_DQ4 (DDRPHY_AO_BASE_ADDRESS + 0x09E8) + #define SHU_B1_DQ4_RG_ARPI_AA_MCK_DL_B1 Fld(6, 0) //[5:0] + #define SHU_B1_DQ4_RG_ARPI_AA_MCK_FB_DL_B1 Fld(6, 8) //[13:8] + #define SHU_B1_DQ4_RG_ARPI_DA_MCK_FB_DL_B1 Fld(6, 16) //[21:16] + +#define DDRPHY_REG_SHU_B1_DQ5 (DDRPHY_AO_BASE_ADDRESS + 0x09EC) + #define SHU_B1_DQ5_RG_RX_ARDQ_VREF_SEL_B1 Fld(6, 0) //[5:0] + #define SHU_B1_DQ5_RG_RX_ARDQ_VREF_BYPASS_B1 Fld(1, 6) //[6:6] + #define SHU_B1_DQ5_RG_ARPI_FB_B1 Fld(6, 8) //[13:8] + #define SHU_B1_DQ5_RG_RX_ARDQS0_DQSIEN_DLY_B1 Fld(3, 16) //[18:16] + #define SHU_B1_DQ5_RG_RX_ARDQS_DQSIEN_RB_DLY_B1 Fld(1, 19) //[19:19] + #define SHU_B1_DQ5_RG_RX_ARDQS0_DVS_DLY_B1 Fld(4, 20) //[23:20] + #define SHU_B1_DQ5_RG_RX_ARDQ_FIFO_DQSI_DLY_B1 Fld(3, 29) //[31:29] + +#define DDRPHY_REG_SHU_B1_DQ6 (DDRPHY_AO_BASE_ADDRESS + 0x09F0) + #define SHU_B1_DQ6_RG_ARPI_OFFSET_DQSIEN_B1 Fld(6, 0) //[5:0] + #define SHU_B1_DQ6_RG_ARPI_OFFSET_MCTL_B1 Fld(6, 6) //[11:6] + #define SHU_B1_DQ6_RG_ARPI_CAP_SEL_B1 Fld(7, 12) //[18:12] + #define SHU_B1_DQ6_RG_ARPI_SOPEN_EN_B1 Fld(1, 20) //[20:20] + #define SHU_B1_DQ6_RG_ARPI_OPEN_EN_B1 Fld(1, 21) //[21:21] + #define SHU_B1_DQ6_RG_ARPI_HYST_SEL_B1 Fld(2, 22) //[23:22] + #define SHU_B1_DQ6_RG_ARPI_BUFGP_XLATCH_FORCE_DQ_B1 Fld(1, 24) //[24:24] + #define SHU_B1_DQ6_RG_ARPI_BUFGP_XLATCH_FORCE_DQS_B1 Fld(1, 25) //[25:25] + #define SHU_B1_DQ6_RG_ARPI_SOPEN_CKGEN_EN_B1 Fld(1, 26) //[26:26] + #define SHU_B1_DQ6_RG_ARPI_SOPEN_CKGEN_DIV_B1 Fld(1, 27) //[27:27] + #define SHU_B1_DQ6_RG_ARPI_DDR400_EN_B1 Fld(1, 28) //[28:28] + #define SHU_B1_DQ6_RG_RX_ARDQ_RANK_SEL_SER_MODE_B1 Fld(1, 29) //[29:29] + +#define DDRPHY_REG_SHU_B1_DQ1 (DDRPHY_AO_BASE_ADDRESS + 0x09F4) + #define SHU_B1_DQ1_RG_ARPI_MIDPI_EN_B1 Fld(1, 0) //[0:0] + #define SHU_B1_DQ1_RG_ARPI_MIDPI_CKDIV4_PREDIV_EN_B1 Fld(1, 1) //[1:1] + #define SHU_B1_DQ1_RG_ARPI_MIDPI_CKDIV4_EN_B1 Fld(1, 2) //[2:2] + #define SHU_B1_DQ1_RG_ARPI_MIDPI_8PH_DLY_B1 Fld(5, 8) //[12:8] + #define SHU_B1_DQ1_RG_ARPI_MIDPI_LDO_VREF_SEL_B1 Fld(2, 16) //[17:16] + #define SHU_B1_DQ1_RG_ARPI_MIDPI_CAP_SEL_B1 Fld(2, 22) //[23:22] + #define SHU_B1_DQ1_RG_ARPI_MIDPI_VTH_SEL_B1 Fld(2, 24) //[25:24] + #define SHU_B1_DQ1_RG_ARPI_8PHASE_XLATCH_FORCE_B1 Fld(1, 26) //[26:26] + #define SHU_B1_DQ1_RG_ARPI_MIDPI_DUMMY_EN_B1 Fld(1, 27) //[27:27] + #define SHU_B1_DQ1_RG_ARPI_MIDPI_BYPASS_EN_B1 Fld(1, 31) //[31:31] + +#define DDRPHY_REG_SHU_B1_DQ2 (DDRPHY_AO_BASE_ADDRESS + 0x09F8) + #define SHU_B1_DQ2_RG_ARPI_TX_CG_SYNC_DIS_B1 Fld(1, 0) //[0:0] + #define SHU_B1_DQ2_RG_ARPI_TX_CG_DQ_EN_B1 Fld(1, 4) //[4:4] + #define SHU_B1_DQ2_RG_ARPI_TX_CG_DQS_EN_B1 Fld(1, 5) //[5:5] + #define SHU_B1_DQ2_RG_ARPI_TX_CG_DQM_EN_B1 Fld(1, 6) //[6:6] + #define SHU_B1_DQ2_RG_ARPI_SMT_XLATCH_FORCE_DQS_B1 Fld(1, 8) //[8:8] + #define SHU_B1_DQ2_RG_ARPI_SMT_XLATCH_DQ_FORCE_B1 Fld(1, 9) //[9:9] + #define SHU_B1_DQ2_RG_ARPI_PSMUX_XLATCH_FORCE_DQ_B1 Fld(1, 10) //[10:10] + #define SHU_B1_DQ2_RG_ARPI_PSMUX_XLATCH_FORCE_DQS_B1 Fld(1, 11) //[11:11] + #define SHU_B1_DQ2_RG_ARPISM_MCK_SEL_B1_SHU Fld(1, 12) //[12:12] + #define SHU_B1_DQ2_RG_ARPI_PD_MCTL_SEL_B1 Fld(1, 13) //[13:13] + #define SHU_B1_DQ2_RG_ARPI_OFFSET_LAT_EN_B1 Fld(1, 16) //[16:16] + #define SHU_B1_DQ2_RG_ARPI_OFFSET_ASYNC_EN_B1 Fld(1, 17) //[17:17] + +#define DDRPHY_REG_SHU_B1_DQ10 (DDRPHY_AO_BASE_ADDRESS + 0x09FC) + #define SHU_B1_DQ10_RG_RX_ARDQS_SE_EN_B1 Fld(1, 0) //[0:0] + #define SHU_B1_DQ10_RG_RX_ARDQS_DQSSTB_CG_EN_B1 Fld(1, 1) //[1:1] + #define SHU_B1_DQ10_RG_RX_ARDQS_DQSIEN_RANK_SEL_LAT_EN_B1 Fld(1, 2) //[2:2] + #define SHU_B1_DQ10_RG_RX_ARDQS_RANK_SEL_LAT_EN_B1 Fld(1, 3) //[3:3] + #define SHU_B1_DQ10_RG_RX_ARDQS_DQSSTB_RPST_HS_EN_B1 Fld(1, 4) //[4:4] + #define SHU_B1_DQ10_RG_RX_ARDQS_DQSIEN_MODE_B1 Fld(3, 8) //[10:8] + #define SHU_B1_DQ10_RG_RX_ARDQS_DLY_LAT_EN_B1 Fld(1, 15) //[15:15] + #define SHU_B1_DQ10_RG_RX_ARDQS_DIFF_SWAP_EN_B1 Fld(1, 16) //[16:16] + #define SHU_B1_DQ10_RG_RX_ARDQS_BW_SEL_B1 Fld(2, 18) //[19:18] + +#define DDRPHY_REG_SHU_B1_DQ11 (DDRPHY_AO_BASE_ADDRESS + 0x0A00) + #define SHU_B1_DQ11_RG_RX_ARDQ_RANK_SEL_SER_EN_B1 Fld(1, 0) //[0:0] + #define SHU_B1_DQ11_RG_RX_ARDQ_RANK_SEL_LAT_EN_B1 Fld(1, 1) //[1:1] + #define SHU_B1_DQ11_RG_RX_ARDQ_OFFSETC_LAT_EN_B1 Fld(1, 2) //[2:2] + #define SHU_B1_DQ11_RG_RX_ARDQ_OFFSETC_EN_B1 Fld(1, 3) //[3:3] + #define SHU_B1_DQ11_RG_RX_ARDQ_OFFSETC_BIAS_EN_B1 Fld(1, 4) //[4:4] + #define SHU_B1_DQ11_RG_RX_ARDQ_FRATE_EN_B1 Fld(1, 5) //[5:5] + #define SHU_B1_DQ11_RG_RX_ARDQ_CDR_EN_B1 Fld(1, 6) //[6:6] + #define SHU_B1_DQ11_RG_RX_ARDQ_DVS_EN_B1 Fld(1, 7) //[7:7] + #define SHU_B1_DQ11_RG_RX_ARDQ_DVS_DLY_B1 Fld(4, 8) //[11:8] + #define SHU_B1_DQ11_RG_RX_ARDQ_DES_MODE_B1 Fld(2, 16) //[17:16] + #define SHU_B1_DQ11_RG_RX_ARDQ_BW_SEL_B1 Fld(2, 18) //[19:18] + +#define DDRPHY_REG_SHU_B1_DQ7 (DDRPHY_AO_BASE_ADDRESS + 0x0A04) + #define SHU_B1_DQ7_R_DMRANKRXDVS_B1 Fld(4, 0) //[3:0] + #define SHU_B1_DQ7_R_DMDQMDBI_EYE_SHU_B1 Fld(1, 6) //[6:6] + #define SHU_B1_DQ7_R_DMDQMDBI_SHU_B1 Fld(1, 7) //[7:7] + #define SHU_B1_DQ7_R_DMRXDVS_DQM_FLAGSEL_B1 Fld(4, 8) //[11:8] + #define SHU_B1_DQ7_R_DMRXDVS_PBYTE_FLAG_OPT_B1 Fld(1, 12) //[12:12] + #define SHU_B1_DQ7_R_DMRXDVS_PBYTE_DQM_EN_B1 Fld(1, 13) //[13:13] + #define SHU_B1_DQ7_R_DMRXTRACK_DQM_EN_B1 Fld(1, 14) //[14:14] + #define SHU_B1_DQ7_R_DMRODTEN_B1 Fld(1, 15) //[15:15] + #define SHU_B1_DQ7_R_DMARPI_CG_FB2DLL_DCM_EN_B1 Fld(1, 16) //[16:16] + #define SHU_B1_DQ7_R_DMTX_ARPI_CG_DQ_NEW_B1 Fld(1, 17) //[17:17] + #define SHU_B1_DQ7_R_DMTX_ARPI_CG_DQS_NEW_B1 Fld(1, 18) //[18:18] + #define SHU_B1_DQ7_R_DMTX_ARPI_CG_DQM_NEW_B1 Fld(1, 19) //[19:19] + #define SHU_B1_DQ7_R_LP4Y_SDN_MODE_DQS1 Fld(1, 20) //[20:20] + #define SHU_B1_DQ7_R_DMRXRANK_DQ_EN_B1 Fld(1, 24) //[24:24] + #define SHU_B1_DQ7_R_DMRXRANK_DQ_LAT_B1 Fld(3, 25) //[27:25] + #define SHU_B1_DQ7_R_DMRXRANK_DQS_EN_B1 Fld(1, 28) //[28:28] + #define SHU_B1_DQ7_R_DMRXRANK_DQS_LAT_B1 Fld(3, 29) //[31:29] + +#define DDRPHY_REG_SHU_B1_DQ8 (DDRPHY_AO_BASE_ADDRESS + 0x0A08) + #define SHU_B1_DQ8_R_DMRXDVS_UPD_FORCE_CYC_B1 Fld(15, 0) //[14:0] + #define SHU_B1_DQ8_R_DMRXDVS_UPD_FORCE_EN_B1 Fld(1, 15) //[15:15] + #define SHU_B1_DQ8_R_DMRANK_RXDLY_PIPE_CG_IG_B1 Fld(1, 19) //[19:19] + #define SHU_B1_DQ8_R_RMRODTEN_CG_IG_B1 Fld(1, 20) //[20:20] + #define SHU_B1_DQ8_R_RMRX_TOPHY_CG_IG_B1 Fld(1, 21) //[21:21] + #define SHU_B1_DQ8_R_DMRXDVS_RDSEL_PIPE_CG_IG_B1 Fld(1, 22) //[22:22] + #define SHU_B1_DQ8_R_DMRXDVS_RDSEL_TOG_PIPE_CG_IG_B1 Fld(1, 23) //[23:23] + #define SHU_B1_DQ8_R_DMRXDLY_CG_IG_B1 Fld(1, 24) //[24:24] + #define SHU_B1_DQ8_R_DMDQSIEN_FLAG_SYNC_CG_IG_B1 Fld(1, 26) //[26:26] + #define SHU_B1_DQ8_R_DMDQSIEN_FLAG_PIPE_CG_IG_B1 Fld(1, 27) //[27:27] + #define SHU_B1_DQ8_R_DMDQSIEN_RDSEL_PIPE_CG_IG_B1 Fld(1, 28) //[28:28] + #define SHU_B1_DQ8_R_DMDQSIEN_RDSEL_TOG_PIPE_CG_IG_B1 Fld(1, 29) //[29:29] + #define SHU_B1_DQ8_R_DMRANK_PIPE_CG_IG_B1 Fld(1, 30) //[30:30] + #define SHU_B1_DQ8_R_DMRANK_CHG_PIPE_CG_IG_B1 Fld(1, 31) //[31:31] + +#define DDRPHY_REG_SHU_B1_DQ9 (DDRPHY_AO_BASE_ADDRESS + 0x0A0C) + #define SHU_B1_DQ9_RG_ARPI_RESERVE_B1 Fld(32, 0) //[31:0] + +#define DDRPHY_REG_SHU_B1_DQ12 (DDRPHY_AO_BASE_ADDRESS + 0x0A10) + #define SHU_B1_DQ12_DMY_DQ12_B1 Fld(1, 0) //[0:0] + +#define DDRPHY_REG_SHU_B1_DLL0 (DDRPHY_AO_BASE_ADDRESS + 0x0A14) + #define SHU_B1_DLL0_RG_ARDLL_LCK_DET_LV2_DLY_B1 Fld(3, 0) //[2:0] + #define SHU_B1_DLL0_RG_ARDLL_LCK_DET_LV1_DLY_B1 Fld(3, 4) //[6:4] + #define SHU_B1_DLL0_RG_ARDLL_LCK_DET_EN_B1 Fld(1, 8) //[8:8] + #define SHU_B1_DLL0_RG_ARDLL_IDLECNT_B1 Fld(4, 12) //[15:12] + #define SHU_B1_DLL0_RG_ARDLL_HOLD_ON_LOCK_EN_B1 Fld(1, 16) //[16:16] + #define SHU_B1_DLL0_RG_ARDLL_GAIN_BOOST_B1 Fld(3, 17) //[19:17] + #define SHU_B1_DLL0_RG_ARDLL_GAIN_B1 Fld(4, 20) //[23:20] + #define SHU_B1_DLL0_RG_ARDLL_FAST_DIV_EN_B1 Fld(1, 24) //[24:24] + #define SHU_B1_DLL0_RG_ARDLL_FAST_PSJP_B1 Fld(1, 25) //[25:25] + #define SHU_B1_DLL0_RG_ARDLL_FASTPJ_CK_SEL_B1 Fld(1, 26) //[26:26] + #define SHU_B1_DLL0_RG_ARDLL_GEAR2_PSJP_B1 Fld(1, 27) //[27:27] + +#define DDRPHY_REG_SHU_B1_DLL1 (DDRPHY_AO_BASE_ADDRESS + 0x0A18) + #define SHU_B1_DLL1_RG_ARDLL_AD_ARFB_CK_EN_B1 Fld(1, 0) //[0:0] + #define SHU_B1_DLL1_RG_ARDLL_DIV_MODE_B1 Fld(2, 2) //[3:2] + #define SHU_B1_DLL1_RG_ARDLL_UDIV_EN_B1 Fld(1, 4) //[4:4] + #define SHU_B1_DLL1_RG_ARDLL_UPDATE_ON_IDLE_EN_B1 Fld(1, 5) //[5:5] + #define SHU_B1_DLL1_RG_ARDLL_TRACKING_CA_EN_B1 Fld(1, 6) //[6:6] + #define SHU_B1_DLL1_RG_ARDLL_UPDATE_ON_IDLE_MODE_B1 Fld(1, 7) //[7:7] + #define SHU_B1_DLL1_RG_ARDLL_SER_MODE_B1 Fld(2, 8) //[9:8] + #define SHU_B1_DLL1_RG_ARDLL_PS_EN_B1 Fld(1, 10) //[10:10] + #define SHU_B1_DLL1_RG_ARDLL_PSJP_EN_B1 Fld(1, 11) //[11:11] + #define SHU_B1_DLL1_RG_ARDLL_PHDIV_B1 Fld(1, 12) //[12:12] + #define SHU_B1_DLL1_RG_ARDLL_PHDET_OUT_SEL_B1 Fld(1, 13) //[13:13] + #define SHU_B1_DLL1_RG_ARDLL_PHDET_IN_SWAP_B1 Fld(1, 14) //[14:14] + #define SHU_B1_DLL1_RG_ARDLL_PHDET_EN_B1 Fld(1, 16) //[16:16] + #define SHU_B1_DLL1_RG_ARDLL_DIV_MCTL_B1 Fld(2, 18) //[19:18] + #define SHU_B1_DLL1_RG_ARDLL_PGAIN_B1 Fld(4, 20) //[23:20] + #define SHU_B1_DLL1_RG_ARDLL_PD_CK_SEL_B1 Fld(1, 24) //[24:24] + +#define DDRPHY_REG_SHU_B1_DLL2 (DDRPHY_AO_BASE_ADDRESS + 0x0A1C) + #define SHU_B1_DLL2_RG_ARDQ_REV_B1 Fld(32, 0) //[31:0] + +#define DDRPHY_REG_SHU_B1_RANK_SELPH_UI_DLY (DDRPHY_AO_BASE_ADDRESS + 0x0A20) + #define SHU_B1_RANK_SELPH_UI_DLY_RANKSEL_UI_DLY_P0_B1 Fld(3, 0) //[2:0] + #define SHU_B1_RANK_SELPH_UI_DLY_RANKSEL_UI_DLY_P1_B1 Fld(3, 4) //[6:4] + #define SHU_B1_RANK_SELPH_UI_DLY_RANKSEL_MCK_DLY_P0_B1 Fld(3, 16) //[18:16] + #define SHU_B1_RANK_SELPH_UI_DLY_RANKSEL_MCK_DLY_P1_B1 Fld(3, 20) //[22:20] + +#define DDRPHY_REG_SHU_B1_DLL_ARPI2 (DDRPHY_AO_BASE_ADDRESS + 0x0A24) + #define SHU_B1_DLL_ARPI2_RG_ARPI_MPDIV_CG_B1 Fld(1, 10) //[10:10] + #define SHU_B1_DLL_ARPI2_RG_ARPI_CG_DQSIEN_B1 Fld(1, 11) //[11:11] + #define SHU_B1_DLL_ARPI2_RG_ARPI_CG_DQ_B1 Fld(1, 13) //[13:13] + #define SHU_B1_DLL_ARPI2_RG_ARPI_CG_DQM_B1 Fld(1, 14) //[14:14] + #define SHU_B1_DLL_ARPI2_RG_ARPI_CG_DQS_B1 Fld(1, 15) //[15:15] + #define SHU_B1_DLL_ARPI2_RG_ARPI_CG_FB_B1 Fld(1, 17) //[17:17] + #define SHU_B1_DLL_ARPI2_RG_ARPI_CG_MCTL_B1 Fld(1, 19) //[19:19] + #define SHU_B1_DLL_ARPI2_RG_ARPI_CG_MCK_FB2DLL_B1 Fld(1, 27) //[27:27] + #define SHU_B1_DLL_ARPI2_RG_ARPI_CG_MCK_B1 Fld(1, 31) //[31:31] + +#define DDRPHY_REG_SHU_B1_DLL_ARPI3 (DDRPHY_AO_BASE_ADDRESS + 0x0A28) + #define SHU_B1_DLL_ARPI3_RG_ARPI_DQSIEN_EN_B1 Fld(1, 11) //[11:11] + #define SHU_B1_DLL_ARPI3_RG_ARPI_DQ_EN_B1 Fld(1, 13) //[13:13] + #define SHU_B1_DLL_ARPI3_RG_ARPI_DQM_EN_B1 Fld(1, 14) //[14:14] + #define SHU_B1_DLL_ARPI3_RG_ARPI_DQS_EN_B1 Fld(1, 15) //[15:15] + #define SHU_B1_DLL_ARPI3_RG_ARPI_FB_EN_B1 Fld(1, 17) //[17:17] + #define SHU_B1_DLL_ARPI3_RG_ARPI_MCTL_EN_B1 Fld(1, 19) //[19:19] + +#define DDRPHY_REG_SHU_B1_TXDUTY (DDRPHY_AO_BASE_ADDRESS + 0x0A2C) + #define SHU_B1_TXDUTY_DA_TX_ARDQ_DUTY_DLY_B1 Fld(6, 0) //[5:0] + #define SHU_B1_TXDUTY_DA_TX_ARDQS_DUTY_DLY_B1 Fld(6, 8) //[13:8] + #define SHU_B1_TXDUTY_DA_TX_ARDQM_DUTY_DLY_B1 Fld(6, 16) //[21:16] + #define SHU_B1_TXDUTY_DA_TX_ARWCK_DUTY_DLY_B1 Fld(6, 24) //[29:24] + +#define DDRPHY_REG_SHU_B1_VREF (DDRPHY_AO_BASE_ADDRESS + 0x0A30) + #define SHU_B1_VREF_RG_RX_ARDQ_VREF_SEL_DQS_B1 Fld(7, 0) //[6:0] + #define SHU_B1_VREF_RG_RX_ARDQ_VREF_RANK_SEL_EN_B1 Fld(1, 16) //[16:16] + #define SHU_B1_VREF_RG_RX_ARDQ_VREF_EN_UB_RK1_B1 Fld(1, 17) //[17:17] + #define SHU_B1_VREF_RG_RX_ARDQ_VREF_EN_UB_RK0_B1 Fld(1, 18) //[18:18] + #define SHU_B1_VREF_RG_RX_ARDQ_VREF_EN_LB_RK1_B1 Fld(1, 19) //[19:19] + #define SHU_B1_VREF_RG_RX_ARDQ_VREF_EN_LB_RK0_B1 Fld(1, 20) //[20:20] + #define SHU_B1_VREF_RG_RX_ARDQ_VREF_EN_DQS_B1 Fld(1, 21) //[21:21] + #define SHU_B1_VREF_RG_RX_ARDQ_VREF_UNTERM_EN_B1 Fld(1, 22) //[22:22] + +#define DDRPHY_REG_SHU_B1_DQ13 (DDRPHY_AO_BASE_ADDRESS + 0x0A34) + #define SHU_B1_DQ13_RG_TX_ARDQ_IO_ODT_DIS_B1 Fld(1, 0) //[0:0] + #define SHU_B1_DQ13_RG_TX_ARDQ_FRATE_EN_B1 Fld(1, 1) //[1:1] + #define SHU_B1_DQ13_RG_TX_ARDQ_DLY_LAT_EN_B1 Fld(1, 2) //[2:2] + #define SHU_B1_DQ13_RG_TX_ARDQS_READ_BASE_EN_B1 Fld(1, 3) //[3:3] + #define SHU_B1_DQ13_RG_TX_ARDQS_PRE_DATA_SEL_B1 Fld(1, 5) //[5:5] + #define SHU_B1_DQ13_RG_TX_ARDQS_OE_ODTEN_SWAP_B1 Fld(1, 6) //[6:6] + #define SHU_B1_DQ13_RG_TX_ARDQS_OE_ODTEN_CG_EN_B1 Fld(1, 7) //[7:7] + #define SHU_B1_DQ13_RG_TX_ARDQS_MCKIO_CG_B1 Fld(1, 8) //[8:8] + #define SHU_B1_DQ13_RG_TX_ARDQS_MCKIO_SEL_B1 Fld(2, 12) //[13:12] + #define SHU_B1_DQ13_RG_TX_ARDQM_MCKIO_SEL_B1 Fld(1, 14) //[14:14] + #define SHU_B1_DQ13_RG_TX_ARDQSB_READ_BASE_EN_B1 Fld(1, 15) //[15:15] + #define SHU_B1_DQ13_RG_TX_ARDQM_OE_ODTEN_CG_EN_B1 Fld(1, 16) //[16:16] + #define SHU_B1_DQ13_RG_TX_ARDQSB_READ_BASE_DATA_TIE_EN_B1 Fld(1, 17) //[17:17] + #define SHU_B1_DQ13_RG_TX_ARDQS_READ_BASE_DATA_TIE_EN_B1 Fld(1, 18) //[18:18] + #define SHU_B1_DQ13_RG_TX_ARDQ_READ_BASE_EN_B1 Fld(1, 19) //[19:19] + #define SHU_B1_DQ13_RG_TX_ARDQ_READ_BASE_DATA_TIE_EN_B1 Fld(1, 20) //[20:20] + #define SHU_B1_DQ13_RG_TX_ARDQSB_OE_TIE_SEL_B1 Fld(1, 24) //[24:24] + #define SHU_B1_DQ13_RG_TX_ARDQSB_OE_TIE_EN_B1 Fld(1, 25) //[25:25] + +#define DDRPHY_REG_SHU_B1_DQ14 (DDRPHY_AO_BASE_ADDRESS + 0x0A38) + #define SHU_B1_DQ14_RG_TX_ARWCK_PRE_EN_B1 Fld(1, 0) //[0:0] + #define SHU_B1_DQ14_RG_TX_ARWCK_PRE_DATA_SEL_B1 Fld(1, 1) //[1:1] + #define SHU_B1_DQ14_RG_TX_ARWCK_MCKIO_SEL_B1 Fld(1, 2) //[2:2] + #define SHU_B1_DQ14_RG_TX_ARDQ_SER_MODE_B1 Fld(2, 4) //[5:4] + #define SHU_B1_DQ14_RG_TX_ARDQ_AUX_SER_MODE_B1 Fld(1, 6) //[6:6] + #define SHU_B1_DQ14_RG_TX_ARDQ_PRE_DATA_SEL_B1 Fld(1, 9) //[9:9] + #define SHU_B1_DQ14_RG_TX_ARDQ_OE_ODTEN_SWAP_B1 Fld(1, 10) //[10:10] + #define SHU_B1_DQ14_RG_TX_ARDQ_OE_ODTEN_CG_EN_B1 Fld(1, 11) //[11:11] + #define SHU_B1_DQ14_RG_TX_ARDQ_MCKIO_SEL_B1 Fld(8, 16) //[23:16] + +#define DDRPHY_REG_B1_SHU_MIDPI_CTRL (DDRPHY_AO_BASE_ADDRESS + 0x0A3C) + #define B1_SHU_MIDPI_CTRL_MIDPI_ENABLE_B1 Fld(1, 0) //[0:0] + #define B1_SHU_MIDPI_CTRL_MIDPI_DIV4_ENABLE_B1 Fld(1, 1) //[1:1] + +#define DDRPHY_REG_SHU_R0_CA_TXDLY0 (DDRPHY_AO_BASE_ADDRESS + 0x0A60) + #define SHU_R0_CA_TXDLY0_TX_ARCA0_DLY Fld(8, 0) //[7:0] + #define SHU_R0_CA_TXDLY0_TX_ARCA1_DLY Fld(8, 8) //[15:8] + #define SHU_R0_CA_TXDLY0_TX_ARCA2_DLY Fld(8, 16) //[23:16] + #define SHU_R0_CA_TXDLY0_TX_ARCA3_DLY Fld(8, 24) //[31:24] + +#define DDRPHY_REG_SHU_R0_CA_TXDLY1 (DDRPHY_AO_BASE_ADDRESS + 0x0A64) + #define SHU_R0_CA_TXDLY1_TX_ARCA4_DLY Fld(8, 0) //[7:0] + #define SHU_R0_CA_TXDLY1_TX_ARCA5_DLY Fld(8, 8) //[15:8] + #define SHU_R0_CA_TXDLY1_TX_ARCA6_DLY Fld(8, 16) //[23:16] + #define SHU_R0_CA_TXDLY1_TX_ARCA7_DLY Fld(8, 24) //[31:24] + +#define DDRPHY_REG_SHU_R0_CA_TXDLY2 (DDRPHY_AO_BASE_ADDRESS + 0x0A68) + #define SHU_R0_CA_TXDLY2_TX_ARCKE0_DLY Fld(8, 0) //[7:0] + #define SHU_R0_CA_TXDLY2_TX_ARCKE1_DLY Fld(8, 8) //[15:8] + #define SHU_R0_CA_TXDLY2_TX_ARCKE2_DLY Fld(8, 16) //[23:16] + #define SHU_R0_CA_TXDLY2_TX_ARCS0_DLY Fld(8, 24) //[31:24] + +#define DDRPHY_REG_SHU_R0_CA_TXDLY3 (DDRPHY_AO_BASE_ADDRESS + 0x0A6C) + #define SHU_R0_CA_TXDLY3_TX_ARCS1_DLY Fld(8, 0) //[7:0] + #define SHU_R0_CA_TXDLY3_TX_ARCS2_DLY Fld(8, 8) //[15:8] + #define SHU_R0_CA_TXDLY3_TX_ARCLK_DLY Fld(8, 16) //[23:16] + #define SHU_R0_CA_TXDLY3_TX_ARCLKB_DLY Fld(8, 24) //[31:24] + +#define DDRPHY_REG_SHU_R0_CA_TXDLY4 (DDRPHY_AO_BASE_ADDRESS + 0x0A70) + #define SHU_R0_CA_TXDLY4_TX_ARCLK_DLYB Fld(8, 0) //[7:0] + #define SHU_R0_CA_TXDLY4_TX_ARCLKB_DLYB Fld(8, 8) //[15:8] + +#define DDRPHY_REG_SHU_R0_CA_RXDLY0 (DDRPHY_AO_BASE_ADDRESS + 0x0A74) + #define SHU_R0_CA_RXDLY0_RG_RX_ARCA0_R_DLY Fld(8, 0) //[7:0] + #define SHU_R0_CA_RXDLY0_RG_RX_ARCA0_F_DLY Fld(8, 8) //[15:8] + #define SHU_R0_CA_RXDLY0_RG_RX_ARCA1_R_DLY Fld(8, 16) //[23:16] + #define SHU_R0_CA_RXDLY0_RG_RX_ARCA1_F_DLY Fld(8, 24) //[31:24] + +#define DDRPHY_REG_SHU_R0_CA_RXDLY1 (DDRPHY_AO_BASE_ADDRESS + 0x0A78) + #define SHU_R0_CA_RXDLY1_RG_RX_ARCA2_R_DLY Fld(8, 0) //[7:0] + #define SHU_R0_CA_RXDLY1_RG_RX_ARCA2_F_DLY Fld(8, 8) //[15:8] + #define SHU_R0_CA_RXDLY1_RG_RX_ARCA3_R_DLY Fld(8, 16) //[23:16] + #define SHU_R0_CA_RXDLY1_RG_RX_ARCA3_F_DLY Fld(8, 24) //[31:24] + +#define DDRPHY_REG_SHU_R0_CA_RXDLY2 (DDRPHY_AO_BASE_ADDRESS + 0x0A7C) + #define SHU_R0_CA_RXDLY2_RG_RX_ARCA4_R_DLY Fld(8, 0) //[7:0] + #define SHU_R0_CA_RXDLY2_RG_RX_ARCA4_F_DLY Fld(8, 8) //[15:8] + #define SHU_R0_CA_RXDLY2_RG_RX_ARCA5_R_DLY Fld(8, 16) //[23:16] + #define SHU_R0_CA_RXDLY2_RG_RX_ARCA5_F_DLY Fld(8, 24) //[31:24] + +#define DDRPHY_REG_SHU_R0_CA_RXDLY6 (DDRPHY_AO_BASE_ADDRESS + 0x0A80) + #define SHU_R0_CA_RXDLY6_RG_RX_ARCA6_R_DLY Fld(8, 0) //[7:0] + #define SHU_R0_CA_RXDLY6_RG_RX_ARCA6_F_DLY Fld(8, 8) //[15:8] + #define SHU_R0_CA_RXDLY6_RG_RX_ARCA7_R_DLY Fld(8, 16) //[23:16] + #define SHU_R0_CA_RXDLY6_RG_RX_ARCA7_F_DLY Fld(8, 24) //[31:24] + +#define DDRPHY_REG_SHU_R0_CA_RXDLY3 (DDRPHY_AO_BASE_ADDRESS + 0x0A84) + #define SHU_R0_CA_RXDLY3_RG_RX_ARCKE0_R_DLY Fld(8, 0) //[7:0] + #define SHU_R0_CA_RXDLY3_RG_RX_ARCKE0_F_DLY Fld(8, 8) //[15:8] + #define SHU_R0_CA_RXDLY3_RG_RX_ARCKE1_R_DLY Fld(8, 16) //[23:16] + #define SHU_R0_CA_RXDLY3_RG_RX_ARCKE1_F_DLY Fld(8, 24) //[31:24] + +#define DDRPHY_REG_SHU_R0_CA_RXDLY4 (DDRPHY_AO_BASE_ADDRESS + 0x0A88) + #define SHU_R0_CA_RXDLY4_RG_RX_ARCKE2_R_DLY Fld(8, 0) //[7:0] + #define SHU_R0_CA_RXDLY4_RG_RX_ARCKE2_F_DLY Fld(8, 8) //[15:8] + #define SHU_R0_CA_RXDLY4_RG_RX_ARCS0_R_DLY Fld(8, 16) //[23:16] + #define SHU_R0_CA_RXDLY4_RG_RX_ARCS0_F_DLY Fld(8, 24) //[31:24] + +#define DDRPHY_REG_SHU_R0_CA_RXDLY5 (DDRPHY_AO_BASE_ADDRESS + 0x0A8C) + #define SHU_R0_CA_RXDLY5_RG_RX_ARCS1_R_DLY Fld(8, 0) //[7:0] + #define SHU_R0_CA_RXDLY5_RG_RX_ARCS1_F_DLY Fld(8, 8) //[15:8] + #define SHU_R0_CA_RXDLY5_RG_RX_ARCS2_R_DLY Fld(8, 16) //[23:16] + #define SHU_R0_CA_RXDLY5_RG_RX_ARCS2_F_DLY Fld(8, 24) //[31:24] + +#define DDRPHY_REG_SHU_R0_CA_RXDLY7 (DDRPHY_AO_BASE_ADDRESS + 0x0A90) + #define SHU_R0_CA_RXDLY7_RG_RX_ARCLK_R_DLY Fld(9, 0) //[8:0] + #define SHU_R0_CA_RXDLY7_RG_RX_ARCLK_F_DLY Fld(9, 16) //[24:16] + +#define DDRPHY_REG_SHU_R0_CA_CMD0 (DDRPHY_AO_BASE_ADDRESS + 0x0A94) + #define SHU_R0_CA_CMD0_RG_RX_ARCLK_R_DLY_DUTY Fld(3, 0) //[2:0] + #define SHU_R0_CA_CMD0_RG_RX_ARCLK_F_DLY_DUTY Fld(3, 4) //[6:4] + #define SHU_R0_CA_CMD0_RG_ARPI_CS Fld(6, 8) //[13:8] + #define SHU_R0_CA_CMD0_RG_ARPI_CMD Fld(6, 16) //[21:16] + #define SHU_R0_CA_CMD0_RG_ARPI_CLK Fld(6, 24) //[29:24] + #define SHU_R0_CA_CMD0_DA_ARPI_DDR400_0D5UI_RK0_CA Fld(1, 30) //[30:30] + #define SHU_R0_CA_CMD0_DA_RX_ARDQSIEN_0D5UI_RK0_CA Fld(1, 31) //[31:31] + +#define DDRPHY_REG_SHU_R0_CA_INI_UIPI (DDRPHY_AO_BASE_ADDRESS + 0x0A98) + #define SHU_R0_CA_INI_UIPI_CURR_INI_PI_CA Fld(7, 0) //[6:0] + #define SHU_R0_CA_INI_UIPI_CURR_INI_UI_CA Fld(8, 8) //[15:8] + +#define DDRPHY_REG_SHU_R0_CA_NEXT_INI_UIPI (DDRPHY_AO_BASE_ADDRESS + 0x0A9C) + #define SHU_R0_CA_NEXT_INI_UIPI_NEXT_INI_PI_CA Fld(7, 0) //[6:0] + #define SHU_R0_CA_NEXT_INI_UIPI_NEXT_INI_UI_CA Fld(8, 8) //[15:8] + #define SHU_R0_CA_NEXT_INI_UIPI_NEXT_INI_UI_P1_CA Fld(8, 24) //[31:24] + +#define DDRPHY_REG_SHU_RK_CA_DQSIEN_MCK_UI_DLY (DDRPHY_AO_BASE_ADDRESS + 0x0AA0) + #define SHU_RK_CA_DQSIEN_MCK_UI_DLY_DQSIEN_UI_P0_CA Fld(4, 0) //[3:0] + #define SHU_RK_CA_DQSIEN_MCK_UI_DLY_DQSIEN_UI_P1_CA Fld(4, 4) //[7:4] + #define SHU_RK_CA_DQSIEN_MCK_UI_DLY_DQSIEN_MCK_P0_CA Fld(4, 16) //[19:16] + #define SHU_RK_CA_DQSIEN_MCK_UI_DLY_DQSIEN_MCK_P1_CA Fld(4, 20) //[23:20] + +#define DDRPHY_REG_SHU_RK_CA_DQSIEN_PI_DLY (DDRPHY_AO_BASE_ADDRESS + 0x0AA4) + #define SHU_RK_CA_DQSIEN_PI_DLY_DQSIEN_PI_CA Fld(7, 0) //[6:0] + +#define DDRPHY_REG_SHU_RK_CA_RODTEN_MCK_UI_DLY (DDRPHY_AO_BASE_ADDRESS + 0x0AA8) + #define SHU_RK_CA_RODTEN_MCK_UI_DLY_RODTEN_UI_P0_CA Fld(3, 0) //[2:0] + #define SHU_RK_CA_RODTEN_MCK_UI_DLY_RODTEN_UI_P1_CA Fld(3, 4) //[6:4] + #define SHU_RK_CA_RODTEN_MCK_UI_DLY_RODTEN_MCK_P0_CA Fld(3, 16) //[18:16] + #define SHU_RK_CA_RODTEN_MCK_UI_DLY_RODTEN_MCK_P1_CA Fld(3, 20) //[22:20] + +#define DDRPHY_REG_SHU_RK_CA_CMD0 (DDRPHY_AO_BASE_ADDRESS + 0x0AAC) + #define SHU_RK_CA_CMD0_RG_RX_ARCA0_OFFC Fld(4, 0) //[3:0] + #define SHU_RK_CA_CMD0_RG_RX_ARCA1_OFFC Fld(4, 4) //[7:4] + #define SHU_RK_CA_CMD0_RG_RX_ARCA2_OFFC Fld(4, 8) //[11:8] + #define SHU_RK_CA_CMD0_RG_RX_ARCA3_OFFC Fld(4, 12) //[15:12] + #define SHU_RK_CA_CMD0_RG_RX_ARCA4_OFFC Fld(4, 16) //[19:16] + #define SHU_RK_CA_CMD0_RG_RX_ARCA5_OFFC Fld(4, 20) //[23:20] + +#define DDRPHY_REG_SHU_RK_CA_CMD1 (DDRPHY_AO_BASE_ADDRESS + 0x0AB0) + #define SHU_RK_CA_CMD1_RG_RX_ARCS0_OFFC Fld(4, 0) //[3:0] + #define SHU_RK_CA_CMD1_RG_RX_ARCS1_OFFC Fld(4, 4) //[7:4] + #define SHU_RK_CA_CMD1_RG_RX_ARCS2_OFFC Fld(4, 8) //[11:8] + #define SHU_RK_CA_CMD1_RG_RX_ARCKE0_OFFC Fld(4, 12) //[15:12] + #define SHU_RK_CA_CMD1_RG_RX_ARCKE1_OFFC Fld(4, 16) //[19:16] + #define SHU_RK_CA_CMD1_RG_RX_ARCKE2_OFFC Fld(4, 20) //[23:20] + +#define DDRPHY_REG_SHU_CA_PHY_VREF_SEL (DDRPHY_AO_BASE_ADDRESS + 0x0AB4) + #define SHU_CA_PHY_VREF_SEL_RG_RX_ARCA_VREF_SEL_LB Fld(7, 0) //[6:0] + #define SHU_CA_PHY_VREF_SEL_RG_RX_ARCA_VREF_SEL_UB Fld(7, 8) //[14:8] + +#define DDRPHY_REG_SHU_CA_CMD0 (DDRPHY_AO_BASE_ADDRESS + 0x0B60) + #define SHU_CA_CMD0_RG_TX_ARCLK_PRE_EN Fld(1, 4) //[4:4] + #define SHU_CA_CMD0_RG_TX_ARCLK_DRVP_PRE Fld(3, 8) //[10:8] + #define SHU_CA_CMD0_RG_TX_ARCLK_DRVN_PRE Fld(3, 12) //[14:12] + #define SHU_CA_CMD0_RG_TX_ARCMD_PRE_EN Fld(1, 20) //[20:20] + #define SHU_CA_CMD0_RG_TX_ARCMD_DRVP_PRE Fld(3, 24) //[26:24] + #define SHU_CA_CMD0_RG_TX_ARCMD_DRVN_PRE Fld(3, 28) //[30:28] + #define SHU_CA_CMD0_R_LP4Y_WDN_MODE_CLK Fld(1, 31) //[31:31] + +#define DDRPHY_REG_SHU_CA_CMD3 (DDRPHY_AO_BASE_ADDRESS + 0x0B64) + #define SHU_CA_CMD3_RG_TX_ARCLK_PU Fld(2, 0) //[1:0] + #define SHU_CA_CMD3_RG_TX_ARCLK_PU_PRE Fld(2, 2) //[3:2] + #define SHU_CA_CMD3_RG_TX_ARCLK_PDB Fld(2, 4) //[5:4] + #define SHU_CA_CMD3_RG_TX_ARCLK_PDB_PRE Fld(2, 6) //[7:6] + #define SHU_CA_CMD3_RG_TX_ARCMD_PU Fld(2, 8) //[9:8] + #define SHU_CA_CMD3_RG_TX_ARCMD_PU_PRE Fld(2, 10) //[11:10] + #define SHU_CA_CMD3_RG_TX_ARCMD_PDB Fld(2, 12) //[13:12] + #define SHU_CA_CMD3_RG_TX_ARCMD_PDB_PRE Fld(2, 14) //[15:14] + +#define DDRPHY_REG_SHU_CA_CMD4 (DDRPHY_AO_BASE_ADDRESS + 0x0B68) + #define SHU_CA_CMD4_RG_ARPI_AA_MCK_DL_CA Fld(6, 0) //[5:0] + #define SHU_CA_CMD4_RG_ARPI_AA_MCK_FB_DL_CA Fld(6, 8) //[13:8] + #define SHU_CA_CMD4_RG_ARPI_DA_MCK_FB_DL_CA Fld(6, 16) //[21:16] + +#define DDRPHY_REG_SHU_CA_CMD5 (DDRPHY_AO_BASE_ADDRESS + 0x0B6C) + #define SHU_CA_CMD5_RG_RX_ARCMD_VREF_SEL Fld(6, 0) //[5:0] + #define SHU_CA_CMD5_RG_RX_ARCMD_VREF_BYPASS Fld(1, 6) //[6:6] + #define SHU_CA_CMD5_RG_ARPI_FB_CA Fld(6, 8) //[13:8] + #define SHU_CA_CMD5_RG_RX_ARCLK_DQSIEN_DLY Fld(3, 16) //[18:16] + #define SHU_CA_CMD5_RG_RX_ARCLK_DQSIEN_RB_DLY Fld(1, 19) //[19:19] + #define SHU_CA_CMD5_RG_RX_ARCLK_DVS_DLY Fld(4, 20) //[23:20] + #define SHU_CA_CMD5_RG_RX_ARCMD_FIFO_DQSI_DLY Fld(3, 29) //[31:29] + +#define DDRPHY_REG_SHU_CA_CMD6 (DDRPHY_AO_BASE_ADDRESS + 0x0B70) + #define SHU_CA_CMD6_RG_ARPI_OFFSET_DQSIEN_CA Fld(6, 0) //[5:0] + #define SHU_CA_CMD6_RG_ARPI_OFFSET_MCTL_CA Fld(6, 6) //[11:6] + #define SHU_CA_CMD6_RG_ARPI_CAP_SEL_CA Fld(7, 12) //[18:12] + #define SHU_CA_CMD6_RG_ARPI_SOPEN_EN_CA Fld(1, 20) //[20:20] + #define SHU_CA_CMD6_RG_ARPI_OPEN_EN_CA Fld(1, 21) //[21:21] + #define SHU_CA_CMD6_RG_ARPI_HYST_SEL_CA Fld(2, 22) //[23:22] + #define SHU_CA_CMD6_RG_ARPI_BUFGP_XLATCH_FORCE_CA_CA Fld(1, 24) //[24:24] + #define SHU_CA_CMD6_RG_ARPI_BUFGP_XLATCH_FORCE_CLK_CA Fld(1, 25) //[25:25] + #define SHU_CA_CMD6_RG_ARPI_SOPEN_CKGEN_EN_CA Fld(1, 26) //[26:26] + #define SHU_CA_CMD6_RG_ARPI_SOPEN_CKGEN_DIV_CA Fld(1, 27) //[27:27] + #define SHU_CA_CMD6_RG_ARPI_DDR400_EN_CA Fld(1, 28) //[28:28] + #define SHU_CA_CMD6_RG_RX_ARCMD_RANK_SEL_SER_MODE Fld(1, 29) //[29:29] + +#define DDRPHY_REG_SHU_CA_CMD1 (DDRPHY_AO_BASE_ADDRESS + 0x0B74) + #define SHU_CA_CMD1_RG_ARPI_MIDPI_EN_CA Fld(1, 0) //[0:0] + #define SHU_CA_CMD1_RG_ARPI_MIDPI_CKDIV4_PREDIV_EN_CA Fld(1, 1) //[1:1] + #define SHU_CA_CMD1_RG_ARPI_MIDPI_CKDIV4_EN_CA Fld(1, 2) //[2:2] + #define SHU_CA_CMD1_RG_ARPI_MIDPI_8PH_DLY_CA Fld(5, 8) //[12:8] + #define SHU_CA_CMD1_RG_ARPI_MIDPI_LDO_VREF_SEL_CA Fld(2, 16) //[17:16] + #define SHU_CA_CMD1_RG_ARPI_MIDPI_CAP_SEL_CA Fld(2, 22) //[23:22] + #define SHU_CA_CMD1_RG_ARPI_MIDPI_VTH_SEL_CA Fld(2, 24) //[25:24] + #define SHU_CA_CMD1_RG_ARPI_8PHASE_XLATCH_FORCE_CA Fld(1, 26) //[26:26] + #define SHU_CA_CMD1_RG_ARPI_MIDPI_DUMMY_EN_CA Fld(1, 27) //[27:27] + #define SHU_CA_CMD1_RG_ARPI_MIDPI_BYPASS_EN_CA Fld(1, 31) //[31:31] + +#define DDRPHY_REG_SHU_CA_CMD2 (DDRPHY_AO_BASE_ADDRESS + 0x0B78) + #define SHU_CA_CMD2_RG_ARPI_TX_CG_SYNC_DIS_CA Fld(1, 0) //[0:0] + #define SHU_CA_CMD2_RG_ARPI_TX_CG_CA_EN_CA Fld(1, 4) //[4:4] + #define SHU_CA_CMD2_RG_ARPI_TX_CG_CLK_EN_CA Fld(1, 5) //[5:5] + #define SHU_CA_CMD2_RG_ARPI_TX_CG_CS_EN_CA Fld(1, 6) //[6:6] + #define SHU_CA_CMD2_RG_ARPI_SMT_XLATCH_FORCE_CLK_CA Fld(1, 8) //[8:8] + #define SHU_CA_CMD2_RG_ARPI_SMT_XLATCH_CA_FORCE_CA Fld(1, 9) //[9:9] + #define SHU_CA_CMD2_RG_ARPI_PSMUX_XLATCH_FORCE_CA_CA Fld(1, 10) //[10:10] + #define SHU_CA_CMD2_RG_ARPI_PSMUX_XLATCH_FORCE_CLK_CA Fld(1, 11) //[11:11] + #define SHU_CA_CMD2_RG_ARPISM_MCK_SEL_CA_SHU Fld(1, 12) //[12:12] + #define SHU_CA_CMD2_RG_ARPI_PD_MCTL_SEL_CA Fld(1, 13) //[13:13] + #define SHU_CA_CMD2_RG_ARPI_OFFSET_LAT_EN_CA Fld(1, 16) //[16:16] + #define SHU_CA_CMD2_RG_ARPI_OFFSET_ASYNC_EN_CA Fld(1, 17) //[17:17] + +#define DDRPHY_REG_SHU_CA_CMD10 (DDRPHY_AO_BASE_ADDRESS + 0x0B7C) + #define SHU_CA_CMD10_RG_RX_ARCLK_SE_EN_CA Fld(1, 0) //[0:0] + #define SHU_CA_CMD10_RG_RX_ARCLK_DQSSTB_CG_EN_CA Fld(1, 1) //[1:1] + #define SHU_CA_CMD10_RG_RX_ARCLK_DQSIEN_RANK_SEL_LAT_EN_CA Fld(1, 2) //[2:2] + #define SHU_CA_CMD10_RG_RX_ARCLK_RANK_SEL_LAT_EN_CA Fld(1, 3) //[3:3] + #define SHU_CA_CMD10_RG_RX_ARCLK_DQSSTB_RPST_HS_EN_CA Fld(1, 4) //[4:4] + #define SHU_CA_CMD10_RG_RX_ARCLK_DQSIEN_MODE_CA Fld(3, 8) //[10:8] + #define SHU_CA_CMD10_RG_RX_ARCLK_DLY_LAT_EN_CA Fld(1, 15) //[15:15] + #define SHU_CA_CMD10_RG_RX_ARCLK_DIFF_SWAP_EN_CA Fld(1, 16) //[16:16] + #define SHU_CA_CMD10_RG_RX_ARCLK_BW_SEL_CA Fld(2, 18) //[19:18] + +#define DDRPHY_REG_SHU_CA_CMD11 (DDRPHY_AO_BASE_ADDRESS + 0x0B80) + #define SHU_CA_CMD11_RG_RX_ARCA_RANK_SEL_SER_EN_CA Fld(1, 0) //[0:0] + #define SHU_CA_CMD11_RG_RX_ARCA_RANK_SEL_LAT_EN_CA Fld(1, 1) //[1:1] + #define SHU_CA_CMD11_RG_RX_ARCA_OFFSETC_LAT_EN_CA Fld(1, 2) //[2:2] + #define SHU_CA_CMD11_RG_RX_ARCA_OFFSETC_EN_CA Fld(1, 3) //[3:3] + #define SHU_CA_CMD11_RG_RX_ARCA_OFFSETC_BIAS_EN_CA Fld(1, 4) //[4:4] + #define SHU_CA_CMD11_RG_RX_ARCA_FRATE_EN_CA Fld(1, 5) //[5:5] + #define SHU_CA_CMD11_RG_RX_ARCA_CDR_EN_CA Fld(1, 6) //[6:6] + #define SHU_CA_CMD11_RG_RX_ARCA_DVS_EN_CA Fld(1, 7) //[7:7] + #define SHU_CA_CMD11_RG_RX_ARCA_DVS_DLY_CA Fld(4, 8) //[11:8] + #define SHU_CA_CMD11_RG_RX_ARCA_DES_MODE_CA Fld(2, 16) //[17:16] + #define SHU_CA_CMD11_RG_RX_ARCA_BW_SEL_CA Fld(2, 18) //[19:18] + +#define DDRPHY_REG_SHU_CA_CMD7 (DDRPHY_AO_BASE_ADDRESS + 0x0B84) + #define SHU_CA_CMD7_R_DMRANKRXDVS_CA Fld(4, 0) //[3:0] + #define SHU_CA_CMD7_R_DMRXDVS_PBYTE_FLAG_OPT_CA Fld(1, 12) //[12:12] + #define SHU_CA_CMD7_R_DMRODTEN_CA Fld(1, 15) //[15:15] + #define SHU_CA_CMD7_R_DMARPI_CG_FB2DLL_DCM_EN_CA Fld(1, 16) //[16:16] + #define SHU_CA_CMD7_R_DMTX_ARPI_CG_CMD_NEW Fld(1, 17) //[17:17] + #define SHU_CA_CMD7_R_DMTX_ARPI_CG_CS_NEW Fld(1, 19) //[19:19] + #define SHU_CA_CMD7_R_LP4Y_SDN_MODE_CLK Fld(1, 20) //[20:20] + #define SHU_CA_CMD7_R_DMRXRANK_CMD_EN Fld(1, 24) //[24:24] + #define SHU_CA_CMD7_R_DMRXRANK_CMD_LAT Fld(3, 25) //[27:25] + #define SHU_CA_CMD7_R_DMRXRANK_CLK_EN Fld(1, 28) //[28:28] + #define SHU_CA_CMD7_R_DMRXRANK_CLK_LAT Fld(3, 29) //[31:29] + +#define DDRPHY_REG_SHU_CA_CMD8 (DDRPHY_AO_BASE_ADDRESS + 0x0B88) + #define SHU_CA_CMD8_R_DMRXDVS_UPD_FORCE_CYC_CA Fld(15, 0) //[14:0] + #define SHU_CA_CMD8_R_DMRXDVS_UPD_FORCE_EN_CA Fld(1, 15) //[15:15] + #define SHU_CA_CMD8_R_DMRANK_RXDLY_PIPE_CG_IG_CA Fld(1, 19) //[19:19] + #define SHU_CA_CMD8_R_RMRODTEN_CG_IG_CA Fld(1, 20) //[20:20] + #define SHU_CA_CMD8_R_RMRX_TOPHY_CG_IG_CA Fld(1, 21) //[21:21] + #define SHU_CA_CMD8_R_DMRXDVS_RDSEL_PIPE_CG_IG_CA Fld(1, 22) //[22:22] + #define SHU_CA_CMD8_R_DMRXDVS_RDSEL_TOG_PIPE_CG_IG_CA Fld(1, 23) //[23:23] + #define SHU_CA_CMD8_R_DMRXDLY_CG_IG_CA Fld(1, 24) //[24:24] + #define SHU_CA_CMD8_R_DMDQSIEN_FLAG_SYNC_CG_IG_CA Fld(1, 26) //[26:26] + #define SHU_CA_CMD8_R_DMDQSIEN_FLAG_PIPE_CG_IG_CA Fld(1, 27) //[27:27] + #define SHU_CA_CMD8_R_DMDQSIEN_RDSEL_PIPE_CG_IG_CA Fld(1, 28) //[28:28] + #define SHU_CA_CMD8_R_DMDQSIEN_RDSEL_TOG_PIPE_CG_IG_CA Fld(1, 29) //[29:29] + #define SHU_CA_CMD8_R_DMRANK_PIPE_CG_IG_CA Fld(1, 30) //[30:30] + #define SHU_CA_CMD8_R_DMRANK_CHG_PIPE_CG_IG_CA Fld(1, 31) //[31:31] + +#define DDRPHY_REG_SHU_CA_CMD9 (DDRPHY_AO_BASE_ADDRESS + 0x0B8C) + #define SHU_CA_CMD9_RG_ARPI_RESERVE_CA Fld(32, 0) //[31:0] + +#define DDRPHY_REG_SHU_CA_CMD12 (DDRPHY_AO_BASE_ADDRESS + 0x0B90) + #define SHU_CA_CMD12_RG_RIMP_REV Fld(8, 0) //[7:0] + #define SHU_CA_CMD12_RG_RIMP_VREF_SEL_ODTN Fld(7, 8) //[14:8] + #define SHU_CA_CMD12_RG_RIMP_VREF_SEL_DRVN Fld(7, 16) //[22:16] + #define SHU_CA_CMD12_RG_RIMP_DRV05 Fld(1, 23) //[23:23] + #define SHU_CA_CMD12_RG_RIMP_VREF_SEL_DRVP Fld(7, 24) //[30:24] + #define SHU_CA_CMD12_RG_RIMP_UNTERM_EN Fld(1, 31) //[31:31] + +#define DDRPHY_REG_SHU_CA_DLL0 (DDRPHY_AO_BASE_ADDRESS + 0x0B94) + #define SHU_CA_DLL0_RG_ARDLL_LCK_DET_LV2_DLY_CA Fld(3, 0) //[2:0] + #define SHU_CA_DLL0_RG_ARDLL_LCK_DET_LV1_DLY_CA Fld(3, 4) //[6:4] + #define SHU_CA_DLL0_RG_ARDLL_LCK_DET_EN_CA Fld(1, 8) //[8:8] + #define SHU_CA_DLL0_RG_ARDLL_IDLECNT_CA Fld(4, 12) //[15:12] + #define SHU_CA_DLL0_RG_ARDLL_HOLD_ON_LOCK_EN_CA Fld(1, 16) //[16:16] + #define SHU_CA_DLL0_RG_ARDLL_GAIN_BOOST_CA Fld(3, 17) //[19:17] + #define SHU_CA_DLL0_RG_ARDLL_GAIN_CA Fld(4, 20) //[23:20] + #define SHU_CA_DLL0_RG_ARDLL_FAST_DIV_EN_CA Fld(1, 24) //[24:24] + #define SHU_CA_DLL0_RG_ARDLL_FAST_PSJP_CA Fld(1, 25) //[25:25] + #define SHU_CA_DLL0_RG_ARDLL_FASTPJ_CK_SEL_CA Fld(1, 26) //[26:26] + #define SHU_CA_DLL0_RG_ARDLL_GEAR2_PSJP_CA Fld(1, 27) //[27:27] + +#define DDRPHY_REG_SHU_CA_DLL1 (DDRPHY_AO_BASE_ADDRESS + 0x0B98) + #define SHU_CA_DLL1_RG_ARDLL_AD_ARFB_CK_EN_CA Fld(1, 0) //[0:0] + #define SHU_CA_DLL1_RG_ARDLL_DIV_MODE_CA Fld(2, 2) //[3:2] + #define SHU_CA_DLL1_RG_ARDLL_UDIV_EN_CA Fld(1, 4) //[4:4] + #define SHU_CA_DLL1_RG_ARDLL_UPDATE_ON_IDLE_EN_CA Fld(1, 5) //[5:5] + #define SHU_CA_DLL1_RG_ARDLL_TRACKING_CA_EN_CA Fld(1, 6) //[6:6] + #define SHU_CA_DLL1_RG_ARDLL_UPDATE_ON_IDLE_MODE_CA Fld(1, 7) //[7:7] + #define SHU_CA_DLL1_RG_ARDLL_SER_MODE_CA Fld(2, 8) //[9:8] + #define SHU_CA_DLL1_RG_ARDLL_PS_EN_CA Fld(1, 10) //[10:10] + #define SHU_CA_DLL1_RG_ARDLL_PSJP_EN_CA Fld(1, 11) //[11:11] + #define SHU_CA_DLL1_RG_ARDLL_PHDIV_CA Fld(1, 12) //[12:12] + #define SHU_CA_DLL1_RG_ARDLL_PHDET_OUT_SEL_CA Fld(1, 13) //[13:13] + #define SHU_CA_DLL1_RG_ARDLL_PHDET_IN_SWAP_CA Fld(1, 14) //[14:14] + #define SHU_CA_DLL1_RG_ARDLL_PHDET_EN_CA Fld(1, 16) //[16:16] + #define SHU_CA_DLL1_RG_ARDLL_DIV_MCTL_CA Fld(2, 18) //[19:18] + #define SHU_CA_DLL1_RG_ARDLL_PGAIN_CA Fld(4, 20) //[23:20] + #define SHU_CA_DLL1_RG_ARDLL_PD_CK_SEL_CA Fld(1, 24) //[24:24] + +#define DDRPHY_REG_SHU_CA_DLL2 (DDRPHY_AO_BASE_ADDRESS + 0x0B9C) + #define SHU_CA_DLL2_RG_ARCMD_REV Fld(32, 0) //[31:0] + +#define DDRPHY_REG_SHU_CA_RANK_SELPH_UI_DLY (DDRPHY_AO_BASE_ADDRESS + 0x0BA0) + #define SHU_CA_RANK_SELPH_UI_DLY_RANKSEL_UI_DLY_P0_CA Fld(3, 0) //[2:0] + #define SHU_CA_RANK_SELPH_UI_DLY_RANKSEL_UI_DLY_P1_CA Fld(3, 4) //[6:4] + #define SHU_CA_RANK_SELPH_UI_DLY_RANKSEL_MCK_DLY_P0_CA Fld(3, 16) //[18:16] + #define SHU_CA_RANK_SELPH_UI_DLY_RANKSEL_MCK_DLY_P1_CA Fld(3, 20) //[22:20] + +#define DDRPHY_REG_SHU_CA_DLL_ARPI2 (DDRPHY_AO_BASE_ADDRESS + 0x0BA4) + #define SHU_CA_DLL_ARPI2_RG_ARPI_MPDIV_CG_CA Fld(1, 10) //[10:10] + #define SHU_CA_DLL_ARPI2_RG_ARPI_CG_CLKIEN Fld(1, 11) //[11:11] + #define SHU_CA_DLL_ARPI2_RG_ARPI_CG_CMD Fld(1, 13) //[13:13] + #define SHU_CA_DLL_ARPI2_RG_ARPI_CG_CLK Fld(1, 15) //[15:15] + #define SHU_CA_DLL_ARPI2_RG_ARPI_CG_CS Fld(1, 16) //[16:16] + #define SHU_CA_DLL_ARPI2_RG_ARPI_CG_FB_CA Fld(1, 17) //[17:17] + #define SHU_CA_DLL_ARPI2_RG_ARPI_CG_MCTL_CA Fld(1, 19) //[19:19] + #define SHU_CA_DLL_ARPI2_RG_ARPI_CG_MCK_FB2DLL_CA Fld(1, 27) //[27:27] + #define SHU_CA_DLL_ARPI2_RG_ARPI_CG_MCK_CA Fld(1, 31) //[31:31] + +#define DDRPHY_REG_SHU_CA_DLL_ARPI3 (DDRPHY_AO_BASE_ADDRESS + 0x0BA8) + #define SHU_CA_DLL_ARPI3_RG_ARPI_CLKIEN_EN Fld(1, 11) //[11:11] + #define SHU_CA_DLL_ARPI3_RG_ARPI_CMD_EN Fld(1, 13) //[13:13] + #define SHU_CA_DLL_ARPI3_RG_ARPI_CLK_EN Fld(1, 15) //[15:15] + #define SHU_CA_DLL_ARPI3_RG_ARPI_CS_EN Fld(1, 16) //[16:16] + #define SHU_CA_DLL_ARPI3_RG_ARPI_FB_EN_CA Fld(1, 17) //[17:17] + #define SHU_CA_DLL_ARPI3_RG_ARPI_MCTL_EN_CA Fld(1, 19) //[19:19] + +#define DDRPHY_REG_SHU_CA_TXDUTY (DDRPHY_AO_BASE_ADDRESS + 0x0BAC) + #define SHU_CA_TXDUTY_DA_TX_ARCA_DUTY_DLY Fld(6, 0) //[5:0] + #define SHU_CA_TXDUTY_DA_TX_ARCLK_DUTY_DLY Fld(6, 8) //[13:8] + #define SHU_CA_TXDUTY_DA_TX_ARCS_DUTY_DLY Fld(6, 16) //[21:16] + +#define DDRPHY_REG_SHU_CA_VREF (DDRPHY_AO_BASE_ADDRESS + 0x0BB0) + #define SHU_CA_VREF_RG_RX_ARCA_VREF_SEL_CLK_CA Fld(7, 0) //[6:0] + #define SHU_CA_VREF_RG_RX_ARCA_VREF_RANK_SEL_EN_CA Fld(1, 16) //[16:16] + #define SHU_CA_VREF_RG_RX_ARCA_VREF_EN_UB_RK1_CA Fld(1, 17) //[17:17] + #define SHU_CA_VREF_RG_RX_ARCA_VREF_EN_UB_RK0_CA Fld(1, 18) //[18:18] + #define SHU_CA_VREF_RG_RX_ARCA_VREF_EN_LB_RK1_CA Fld(1, 19) //[19:19] + #define SHU_CA_VREF_RG_RX_ARCA_VREF_EN_LB_RK0_CA Fld(1, 20) //[20:20] + #define SHU_CA_VREF_RG_RX_ARCA_VREF_EN_CLK_CA Fld(1, 21) //[21:21] + #define SHU_CA_VREF_RG_RX_ARCA_VREF_UNTERM_EN_CA Fld(1, 22) //[22:22] + +#define DDRPHY_REG_SHU_CA_CMD13 (DDRPHY_AO_BASE_ADDRESS + 0x0BB4) + #define SHU_CA_CMD13_RG_TX_ARCA_IO_ODT_DIS_CA Fld(1, 0) //[0:0] + #define SHU_CA_CMD13_RG_TX_ARCA_FRATE_EN_CA Fld(1, 1) //[1:1] + #define SHU_CA_CMD13_RG_TX_ARCA_DLY_LAT_EN_CA Fld(1, 2) //[2:2] + #define SHU_CA_CMD13_RG_TX_ARCLK_READ_BASE_EN_CA Fld(1, 3) //[3:3] + #define SHU_CA_CMD13_RG_TX_ARCLK_PRE_DATA_SEL_CA Fld(1, 5) //[5:5] + #define SHU_CA_CMD13_RG_TX_ARCLK_OE_ODTEN_SWAP_CA Fld(1, 6) //[6:6] + #define SHU_CA_CMD13_RG_TX_ARCLK_OE_ODTEN_CG_EN_CA Fld(1, 7) //[7:7] + #define SHU_CA_CMD13_RG_TX_ARCLK_MCKIO_CG_CA Fld(1, 8) //[8:8] + #define SHU_CA_CMD13_RG_TX_ARCLK_MCKIO_SEL_CA Fld(2, 12) //[13:12] + #define SHU_CA_CMD13_RG_TX_ARCS_MCKIO_SEL_CA Fld(1, 14) //[14:14] + #define SHU_CA_CMD13_RG_TX_ARCLKB_READ_BASE_EN_CA Fld(1, 15) //[15:15] + #define SHU_CA_CMD13_RG_TX_ARCS_OE_ODTEN_CG_EN_CA Fld(1, 16) //[16:16] + #define SHU_CA_CMD13_RG_TX_ARCLKB_READ_BASE_DATA_TIE_EN_CA Fld(1, 17) //[17:17] + #define SHU_CA_CMD13_RG_TX_ARCLK_READ_BASE_DATA_TIE_EN_CA Fld(1, 18) //[18:18] + #define SHU_CA_CMD13_RG_TX_ARCA_READ_BASE_EN_CA Fld(1, 19) //[19:19] + #define SHU_CA_CMD13_RG_TX_ARCA_READ_BASE_DATA_TIE_EN_CA Fld(1, 20) //[20:20] + #define SHU_CA_CMD13_RG_TX_ARCLKB_OE_TIE_SEL_CA Fld(1, 24) //[24:24] + #define SHU_CA_CMD13_RG_TX_ARCLKB_OE_TIE_EN_CA Fld(1, 25) //[25:25] + +#define DDRPHY_REG_SHU_CA_CMD14 (DDRPHY_AO_BASE_ADDRESS + 0x0BB8) + #define SHU_CA_CMD14_RG_TX_ARCA_SER_MODE_CA Fld(2, 4) //[5:4] + #define SHU_CA_CMD14_RG_TX_ARCA_AUX_SER_MODE_CA Fld(1, 6) //[6:6] + #define SHU_CA_CMD14_RG_TX_ARCA_PRE_DATA_SEL_CA Fld(1, 9) //[9:9] + #define SHU_CA_CMD14_RG_TX_ARCA_OE_ODTEN_SWAP_CA Fld(1, 10) //[10:10] + #define SHU_CA_CMD14_RG_TX_ARCA_OE_ODTEN_CG_EN_CA Fld(1, 11) //[11:11] + #define SHU_CA_CMD14_RG_TX_ARCA_MCKIO_SEL_CA Fld(8, 16) //[23:16] + +#define DDRPHY_REG_CA_SHU_MIDPI_CTRL (DDRPHY_AO_BASE_ADDRESS + 0x0BBC) + #define CA_SHU_MIDPI_CTRL_MIDPI_ENABLE_CA Fld(1, 0) //[0:0] + #define CA_SHU_MIDPI_CTRL_MIDPI_DIV4_ENABLE_CA Fld(1, 1) //[1:1] + +#define DDRPHY_REG_MISC_SHU_RK_DQSCTL (DDRPHY_AO_BASE_ADDRESS + 0x0BE0) + #define MISC_SHU_RK_DQSCTL_DQSINCTL Fld(4, 0) //[3:0] + +#define DDRPHY_REG_MISC_SHU_RK_DQSIEN_PICG_CTRL (DDRPHY_AO_BASE_ADDRESS + 0x0BE4) + #define MISC_SHU_RK_DQSIEN_PICG_CTRL_DQSIEN_PICG_HEAD_EXT_LAT Fld(3, 0) //[2:0] + #define MISC_SHU_RK_DQSIEN_PICG_CTRL_DQSIEN_PICG_TAIL_EXT_LAT Fld(3, 4) //[6:4] + +#define DDRPHY_REG_MISC_SHU_RK_DQSCAL (DDRPHY_AO_BASE_ADDRESS + 0x0BE8) + #define MISC_SHU_RK_DQSCAL_DQSIENLLMT Fld(7, 0) //[6:0] + #define MISC_SHU_RK_DQSCAL_DQSIENLLMTEN Fld(1, 7) //[7:7] + #define MISC_SHU_RK_DQSCAL_DQSIENHLMT Fld(7, 8) //[14:8] + #define MISC_SHU_RK_DQSCAL_DQSIENHLMTEN Fld(1, 15) //[15:15] + +#define DDRPHY_REG_MISC_SHU_DRVING7 (DDRPHY_AO_BASE_ADDRESS + 0x0CE0) + #define MISC_SHU_DRVING7_WCK0_DRVN Fld(5, 0) //[4:0] + #define MISC_SHU_DRVING7_WCK0_DRVP Fld(5, 8) //[12:8] + #define MISC_SHU_DRVING7_WCK1_DRVN Fld(5, 16) //[20:16] + #define MISC_SHU_DRVING7_WCK1_DRVP Fld(5, 24) //[28:24] + +#define DDRPHY_REG_MISC_SHU_DRVING8 (DDRPHY_AO_BASE_ADDRESS + 0x0CE4) + #define MISC_SHU_DRVING8_CS_DRVN Fld(5, 0) //[4:0] + #define MISC_SHU_DRVING8_CS_DRVP Fld(5, 8) //[12:8] + +#define DDRPHY_REG_MISC_SHU_IMPEDAMCE_OFFSET1 (DDRPHY_AO_BASE_ADDRESS + 0x0CE8) + #define MISC_SHU_IMPEDAMCE_OFFSET1_DQS0_DRVP_OFF Fld(5, 0) //[4:0] + #define MISC_SHU_IMPEDAMCE_OFFSET1_DQS0_DRVP_OFF_SUB Fld(1, 7) //[7:7] + #define MISC_SHU_IMPEDAMCE_OFFSET1_DQS0_DRVN_OFF Fld(5, 8) //[12:8] + #define MISC_SHU_IMPEDAMCE_OFFSET1_DQS0_DRVN_OFF_SUB Fld(1, 15) //[15:15] + #define MISC_SHU_IMPEDAMCE_OFFSET1_DQS0_ODTN_OFF Fld(5, 16) //[20:16] + #define MISC_SHU_IMPEDAMCE_OFFSET1_DQS0_ODTN_OFF_SUB Fld(1, 23) //[23:23] + +#define DDRPHY_REG_MISC_SHU_IMPEDAMCE_OFFSET2 (DDRPHY_AO_BASE_ADDRESS + 0x0CEC) + #define MISC_SHU_IMPEDAMCE_OFFSET2_DQS1_DRVP_OFF Fld(5, 0) //[4:0] + #define MISC_SHU_IMPEDAMCE_OFFSET2_DQS1_DRVP_OFF_SUB Fld(1, 7) //[7:7] + #define MISC_SHU_IMPEDAMCE_OFFSET2_DQS1_DRVN_OFF Fld(5, 8) //[12:8] + #define MISC_SHU_IMPEDAMCE_OFFSET2_DQS1_DRVN_OFF_SUB Fld(1, 15) //[15:15] + #define MISC_SHU_IMPEDAMCE_OFFSET2_DQS1_ODTN_OFF Fld(5, 16) //[20:16] + #define MISC_SHU_IMPEDAMCE_OFFSET2_DQS1_ODTN_OFF_SUB Fld(1, 23) //[23:23] + +#define DDRPHY_REG_MISC_SHU_IMPEDAMCE_OFFSET3 (DDRPHY_AO_BASE_ADDRESS + 0x0CF0) + #define MISC_SHU_IMPEDAMCE_OFFSET3_DQ0_DRVP_OFF Fld(5, 0) //[4:0] + #define MISC_SHU_IMPEDAMCE_OFFSET3_DQ0_DRVP_OFF_SUB Fld(1, 7) //[7:7] + #define MISC_SHU_IMPEDAMCE_OFFSET3_DQ0_DRVN_OFF Fld(5, 8) //[12:8] + #define MISC_SHU_IMPEDAMCE_OFFSET3_DQ0_DRVN_OFF_SUB Fld(1, 15) //[15:15] + #define MISC_SHU_IMPEDAMCE_OFFSET3_DQ0_ODTN_OFF Fld(5, 16) //[20:16] + #define MISC_SHU_IMPEDAMCE_OFFSET3_DQ0_ODTN_OFF_SUB Fld(1, 23) //[23:23] + +#define DDRPHY_REG_MISC_SHU_IMPEDAMCE_OFFSET4 (DDRPHY_AO_BASE_ADDRESS + 0x0CF4) + #define MISC_SHU_IMPEDAMCE_OFFSET4_DQ1_DRVP_OFF Fld(5, 0) //[4:0] + #define MISC_SHU_IMPEDAMCE_OFFSET4_DQ1_DRVP_OFF_SUB Fld(1, 7) //[7:7] + #define MISC_SHU_IMPEDAMCE_OFFSET4_DQ1_DRVN_OFF Fld(5, 8) //[12:8] + #define MISC_SHU_IMPEDAMCE_OFFSET4_DQ1_DRVN_OFF_SUB Fld(1, 15) //[15:15] + #define MISC_SHU_IMPEDAMCE_OFFSET4_DQ1_ODTN_OFF Fld(5, 16) //[20:16] + #define MISC_SHU_IMPEDAMCE_OFFSET4_DQ1_ODTN_OFF_SUB Fld(1, 23) //[23:23] + +#define DDRPHY_REG_MISC_SHU_IMPEDAMCE_OFFSET5 (DDRPHY_AO_BASE_ADDRESS + 0x0CF8) + #define MISC_SHU_IMPEDAMCE_OFFSET5_WCK0_DRVP_OFF Fld(5, 0) //[4:0] + #define MISC_SHU_IMPEDAMCE_OFFSET5_WCK0_DRVP_OFF_SUB Fld(1, 7) //[7:7] + #define MISC_SHU_IMPEDAMCE_OFFSET5_WCK0_DRVN_OFF Fld(5, 8) //[12:8] + #define MISC_SHU_IMPEDAMCE_OFFSET5_WCK0_DRVN_OFF_SUB Fld(1, 15) //[15:15] + +#define DDRPHY_REG_MISC_SHU_IMPEDAMCE_OFFSET6 (DDRPHY_AO_BASE_ADDRESS + 0x0CFC) + #define MISC_SHU_IMPEDAMCE_OFFSET6_WCK1_DRVP_OFF Fld(5, 0) //[4:0] + #define MISC_SHU_IMPEDAMCE_OFFSET6_WCK1_DRVP_OFF_SUB Fld(1, 7) //[7:7] + #define MISC_SHU_IMPEDAMCE_OFFSET6_WCK1_DRVN_OFF Fld(5, 8) //[12:8] + #define MISC_SHU_IMPEDAMCE_OFFSET6_WCK1_DRVN_OFF_SUB Fld(1, 15) //[15:15] + +#define DDRPHY_REG_MISC_SHU_IMPEDAMCE_OFFSET7 (DDRPHY_AO_BASE_ADDRESS + 0x0D00) + #define MISC_SHU_IMPEDAMCE_OFFSET7_CS_DRVP_OFF Fld(5, 0) //[4:0] + #define MISC_SHU_IMPEDAMCE_OFFSET7_CS_DRVP_OFF_SUB Fld(1, 7) //[7:7] + #define MISC_SHU_IMPEDAMCE_OFFSET7_CS_DRVN_OFF Fld(5, 8) //[12:8] + #define MISC_SHU_IMPEDAMCE_OFFSET7_CS_DRVN_OFF_SUB Fld(1, 15) //[15:15] + +#define DDRPHY_REG_MISC_SHU_IMPEDAMCE_OFFSET8 (DDRPHY_AO_BASE_ADDRESS + 0x0D04) + #define MISC_SHU_IMPEDAMCE_OFFSET8_CMD1_DRVP_OFF Fld(5, 0) //[4:0] + #define MISC_SHU_IMPEDAMCE_OFFSET8_CMD1_DRVP_OFF_SUB Fld(1, 7) //[7:7] + #define MISC_SHU_IMPEDAMCE_OFFSET8_CMD1_DRVN_OFF Fld(5, 8) //[12:8] + #define MISC_SHU_IMPEDAMCE_OFFSET8_CMD1_DRVN_OFF_SUB Fld(1, 15) //[15:15] + #define MISC_SHU_IMPEDAMCE_OFFSET8_CMD1_ODTN_OFF Fld(5, 16) //[20:16] + #define MISC_SHU_IMPEDAMCE_OFFSET8_CMD1_ODTN_OFF_SUB Fld(1, 23) //[23:23] + +#define DDRPHY_REG_MISC_SHU_IMPEDAMCE_OFFSET9 (DDRPHY_AO_BASE_ADDRESS + 0x0D08) + #define MISC_SHU_IMPEDAMCE_OFFSET9_CMD2_DRVP_OFF Fld(5, 0) //[4:0] + #define MISC_SHU_IMPEDAMCE_OFFSET9_CMD2_DRVP_OFF_SUB Fld(1, 7) //[7:7] + #define MISC_SHU_IMPEDAMCE_OFFSET9_CMD2_DRVN_OFF Fld(5, 8) //[12:8] + #define MISC_SHU_IMPEDAMCE_OFFSET9_CMD2_DRVN_OFF_SUB Fld(1, 15) //[15:15] + #define MISC_SHU_IMPEDAMCE_OFFSET9_CMD2_ODTN_OFF Fld(5, 16) //[20:16] + #define MISC_SHU_IMPEDAMCE_OFFSET9_CMD2_ODTN_OFF_SUB Fld(1, 23) //[23:23] + +#define DDRPHY_REG_MISC_SHU_IMPEDAMCE_UPD_DIS1 (DDRPHY_AO_BASE_ADDRESS + 0x0D0C) + #define MISC_SHU_IMPEDAMCE_UPD_DIS1_DQS_DRVP_UPD_DIS Fld(1, 0) //[0:0] + #define MISC_SHU_IMPEDAMCE_UPD_DIS1_DQS_DRVN_UPD_DIS Fld(1, 1) //[1:1] + #define MISC_SHU_IMPEDAMCE_UPD_DIS1_DQS_ODTN_UPD_DIS Fld(1, 2) //[2:2] + #define MISC_SHU_IMPEDAMCE_UPD_DIS1_DQ_DRVP_UPD_DIS Fld(1, 4) //[4:4] + #define MISC_SHU_IMPEDAMCE_UPD_DIS1_DQ_DRVN_UPD_DIS Fld(1, 5) //[5:5] + #define MISC_SHU_IMPEDAMCE_UPD_DIS1_DQ_ODTN_UPD_DIS Fld(1, 6) //[6:6] + #define MISC_SHU_IMPEDAMCE_UPD_DIS1_WCK_DRVP_UPD_DIS Fld(1, 8) //[8:8] + #define MISC_SHU_IMPEDAMCE_UPD_DIS1_WCK_DRVN_UPD_DIS Fld(1, 9) //[9:9] + #define MISC_SHU_IMPEDAMCE_UPD_DIS1_WCK_ODTN_UPD_DIS Fld(1, 10) //[10:10] + #define MISC_SHU_IMPEDAMCE_UPD_DIS1_CS_DRVP_UPD_DIS Fld(1, 12) //[12:12] + #define MISC_SHU_IMPEDAMCE_UPD_DIS1_CS_DRVN_UPD_DIS Fld(1, 13) //[13:13] + #define MISC_SHU_IMPEDAMCE_UPD_DIS1_CS_ODTN_UPD_DIS Fld(1, 14) //[14:14] + #define MISC_SHU_IMPEDAMCE_UPD_DIS1_CMD1_DRVP_UPD_DIS Fld(1, 16) //[16:16] + #define MISC_SHU_IMPEDAMCE_UPD_DIS1_CMD1_DRVN_UPD_DIS Fld(1, 17) //[17:17] + #define MISC_SHU_IMPEDAMCE_UPD_DIS1_CMD1_ODTN_UPD_DIS Fld(1, 18) //[18:18] + #define MISC_SHU_IMPEDAMCE_UPD_DIS1_CMD2_DRVP_UPD_DIS Fld(1, 20) //[20:20] + #define MISC_SHU_IMPEDAMCE_UPD_DIS1_CMD2_DRVN_UPD_DIS Fld(1, 21) //[21:21] + #define MISC_SHU_IMPEDAMCE_UPD_DIS1_CMD2_ODTN_UPD_DIS Fld(1, 22) //[22:22] + #define MISC_SHU_IMPEDAMCE_UPD_DIS1_DRVP_UPD_DIS Fld(1, 28) //[28:28] + #define MISC_SHU_IMPEDAMCE_UPD_DIS1_DRVN_UPD_DIS Fld(1, 29) //[29:29] + #define MISC_SHU_IMPEDAMCE_UPD_DIS1_ODTN_UPD_DIS Fld(1, 30) //[30:30] + +#define DDRPHY_REG_SHU_MISC_SW_IMPCAL (DDRPHY_AO_BASE_ADDRESS + 0x0D10) + #define SHU_MISC_SW_IMPCAL_IMPODTN Fld(5, 16) //[20:16] + +#define DDRPHY_REG_MISC_SHU_STBCAL (DDRPHY_AO_BASE_ADDRESS + 0x0D14) + #define MISC_SHU_STBCAL_DMSTBLAT Fld(4, 0) //[3:0] + #define MISC_SHU_STBCAL_PICGLAT Fld(3, 4) //[6:4] + #define MISC_SHU_STBCAL_DQSG_MODE Fld(1, 8) //[8:8] + #define MISC_SHU_STBCAL_DQSIEN_PICG_MODE Fld(1, 9) //[9:9] + #define MISC_SHU_STBCAL_DQSIEN_DQSSTB_MODE Fld(2, 12) //[13:12] + #define MISC_SHU_STBCAL_DQSIEN_BURST_MODE Fld(1, 14) //[14:14] + #define MISC_SHU_STBCAL_DQSIEN_SELPH_FRUN Fld(1, 15) //[15:15] + #define MISC_SHU_STBCAL_STBCALEN Fld(1, 16) //[16:16] + #define MISC_SHU_STBCAL_STB_SELPHCALEN Fld(1, 17) //[17:17] + #define MISC_SHU_STBCAL_DQSIEN_4TO1_EN Fld(1, 20) //[20:20] + #define MISC_SHU_STBCAL_DQSIEN_8TO1_EN Fld(1, 21) //[21:21] + #define MISC_SHU_STBCAL_DQSIEN_16TO1_EN Fld(1, 22) //[22:22] + +#define DDRPHY_REG_MISC_SHU_STBCAL1 (DDRPHY_AO_BASE_ADDRESS + 0x0D18) + #define MISC_SHU_STBCAL1_DLLFRZRFCOPT Fld(2, 0) //[1:0] + #define MISC_SHU_STBCAL1_DLLFRZWROPT Fld(2, 4) //[5:4] + #define MISC_SHU_STBCAL1_R_RSTBCNT_LATCH_OPT Fld(3, 8) //[10:8] + #define MISC_SHU_STBCAL1_STB_UPDMASK_EN Fld(1, 11) //[11:11] + #define MISC_SHU_STBCAL1_STB_UPDMASKCYC Fld(4, 12) //[15:12] + #define MISC_SHU_STBCAL1_DQSINCTL_PRE_SEL Fld(1, 16) //[16:16] + #define MISC_SHU_STBCAL1_STB_PI_TRACKING_RATIO Fld(6, 20) //[25:20] + +#define DDRPHY_REG_MISC_SHU_DVFSDLL (DDRPHY_AO_BASE_ADDRESS + 0x0D1C) + #define MISC_SHU_DVFSDLL_R_BYPASS_1ST_DLL Fld(1, 0) //[0:0] + #define MISC_SHU_DVFSDLL_R_BYPASS_2ND_DLL Fld(1, 1) //[1:1] + #define MISC_SHU_DVFSDLL_R_DLL_IDLE Fld(7, 4) //[10:4] + #define MISC_SHU_DVFSDLL_R_2ND_DLL_IDLE Fld(7, 16) //[22:16] + +#define DDRPHY_REG_MISC_SHU_RANKCTL (DDRPHY_AO_BASE_ADDRESS + 0x0D20) + #define MISC_SHU_RANKCTL_RANKINCTL_RXDLY Fld(4, 0) //[3:0] + #define MISC_SHU_RANKCTL_RANK_RXDLY_OPT Fld(1, 4) //[4:4] + #define MISC_SHU_RANKCTL_RANKSEL_SELPH_FRUN Fld(1, 15) //[15:15] + #define MISC_SHU_RANKCTL_RANKINCTL_STB Fld(4, 16) //[19:16] + #define MISC_SHU_RANKCTL_RANKINCTL Fld(4, 20) //[23:20] + #define MISC_SHU_RANKCTL_RANKINCTL_ROOT1 Fld(4, 24) //[27:24] + #define MISC_SHU_RANKCTL_RANKINCTL_PHY Fld(4, 28) //[31:28] + +#define DDRPHY_REG_MISC_SHU_PHY_RX_CTRL (DDRPHY_AO_BASE_ADDRESS + 0x0D24) + #define MISC_SHU_PHY_RX_CTRL_RANK_RXDLY_UPDLAT_EN Fld(1, 8) //[8:8] + #define MISC_SHU_PHY_RX_CTRL_RANK_RXDLY_UPD_OFFSET Fld(3, 9) //[11:9] + #define MISC_SHU_PHY_RX_CTRL_RX_IN_GATE_EN_PRE_OFFSET Fld(2, 14) //[15:14] + #define MISC_SHU_PHY_RX_CTRL_RX_IN_GATE_EN_HEAD Fld(3, 16) //[18:16] + #define MISC_SHU_PHY_RX_CTRL_RX_IN_GATE_EN_TAIL Fld(3, 20) //[22:20] + #define MISC_SHU_PHY_RX_CTRL_RX_IN_BUFF_EN_HEAD Fld(3, 24) //[26:24] + #define MISC_SHU_PHY_RX_CTRL_RX_IN_BUFF_EN_TAIL Fld(3, 28) //[30:28] + +#define DDRPHY_REG_MISC_SHU_ODTCTRL (DDRPHY_AO_BASE_ADDRESS + 0x0D28) + #define MISC_SHU_ODTCTRL_RODTEN Fld(1, 0) //[0:0] + #define MISC_SHU_ODTCTRL_RODTENSTB_SELPH_CG_IG Fld(1, 1) //[1:1] + #define MISC_SHU_ODTCTRL_RODT_LAT Fld(4, 4) //[7:4] + #define MISC_SHU_ODTCTRL_RODTEN_SELPH_FRUN Fld(1, 15) //[15:15] + #define MISC_SHU_ODTCTRL_RODTDLY_LAT_OPT Fld(2, 24) //[25:24] + #define MISC_SHU_ODTCTRL_FIXRODT Fld(1, 27) //[27:27] + #define MISC_SHU_ODTCTRL_RODTEN_OPT Fld(1, 29) //[29:29] + #define MISC_SHU_ODTCTRL_RODTE2 Fld(1, 30) //[30:30] + #define MISC_SHU_ODTCTRL_RODTE Fld(1, 31) //[31:31] + +#define DDRPHY_REG_MISC_SHU_RODTENSTB (DDRPHY_AO_BASE_ADDRESS + 0x0D2C) + #define MISC_SHU_RODTENSTB_RODTENSTB_TRACK_EN Fld(1, 0) //[0:0] + #define MISC_SHU_RODTENSTB_RODTEN_P1_ENABLE Fld(1, 1) //[1:1] + #define MISC_SHU_RODTENSTB_RODTENSTB_4BYTE_EN Fld(1, 2) //[2:2] + #define MISC_SHU_RODTENSTB_RODTENSTB_TRACK_UDFLWCTRL Fld(1, 3) //[3:3] + #define MISC_SHU_RODTENSTB_RODTENSTB_SELPH_MODE Fld(1, 4) //[4:4] + #define MISC_SHU_RODTENSTB_RODTENSTB_SELPH_BY_BITTIME Fld(1, 5) //[5:5] + #define MISC_SHU_RODTENSTB_RODTENSTB__UI_OFFSET Fld(4, 8) //[11:8] + #define MISC_SHU_RODTENSTB_RODTENSTB_MCK_OFFSET Fld(4, 12) //[15:12] + #define MISC_SHU_RODTENSTB_RODTENSTB_EXT Fld(16, 16) //[31:16] + +#define DDRPHY_REG_MISC_SHU_RODTENSTB1 (DDRPHY_AO_BASE_ADDRESS + 0x0D30) + #define MISC_SHU_RODTENSTB1_RODTENCGEN_HEAD Fld(2, 4) //[5:4] + #define MISC_SHU_RODTENSTB1_RODTENCGEN_TAIL Fld(2, 6) //[7:6] + +#define DDRPHY_REG_MISC_SHU_DQSG_RETRY1 (DDRPHY_AO_BASE_ADDRESS + 0x0D34) + #define MISC_SHU_DQSG_RETRY1_RETRY_SW_RESET Fld(1, 0) //[0:0] + #define MISC_SHU_DQSG_RETRY1_RETRY_SW_EN Fld(1, 1) //[1:1] + #define MISC_SHU_DQSG_RETRY1_RETRY_DDR1866_PLUS Fld(1, 2) //[2:2] + #define MISC_SHU_DQSG_RETRY1_RETRY_ONCE Fld(1, 3) //[3:3] + #define MISC_SHU_DQSG_RETRY1_RETRY_3TIMES Fld(1, 4) //[4:4] + #define MISC_SHU_DQSG_RETRY1_RETRY_1RANK Fld(1, 5) //[5:5] + #define MISC_SHU_DQSG_RETRY1_RETRY_BY_RANK Fld(1, 6) //[6:6] + #define MISC_SHU_DQSG_RETRY1_RETRY_DM4BYTE Fld(1, 7) //[7:7] + #define MISC_SHU_DQSG_RETRY1_RETRY_DQSIENLAT Fld(4, 8) //[11:8] + #define MISC_SHU_DQSG_RETRY1_RETRY_STBENCMP_ALLBYTE Fld(1, 12) //[12:12] + #define MISC_SHU_DQSG_RETRY1_XSR_DQSG_RETRY_EN Fld(1, 13) //[13:13] + #define MISC_SHU_DQSG_RETRY1_XSR_RETRY_SPM_MODE Fld(1, 14) //[14:14] + #define MISC_SHU_DQSG_RETRY1_RETRY_CMP_DATA Fld(1, 15) //[15:15] + #define MISC_SHU_DQSG_RETRY1_RETRY_ALE_BLOCK_MASK Fld(1, 20) //[20:20] + #define MISC_SHU_DQSG_RETRY1_RETRY_RDY_SEL_DLE Fld(1, 21) //[21:21] + #define MISC_SHU_DQSG_RETRY1_RETRY_USE_NON_EXTEND Fld(1, 22) //[22:22] + #define MISC_SHU_DQSG_RETRY1_RETRY_USE_CG_GATING Fld(1, 23) //[23:23] + #define MISC_SHU_DQSG_RETRY1_RETRY_ROUND_NUM Fld(2, 24) //[25:24] + #define MISC_SHU_DQSG_RETRY1_RETRY_RANKSEL_FROM_PHY Fld(1, 28) //[28:28] + #define MISC_SHU_DQSG_RETRY1_RETRY_PA_DISABLE Fld(1, 29) //[29:29] + #define MISC_SHU_DQSG_RETRY1_RETRY_STBEN_RESET_MSK Fld(1, 30) //[30:30] + #define MISC_SHU_DQSG_RETRY1_RETRY_USE_BURST_MODE Fld(1, 31) //[31:31] + +#define DDRPHY_REG_MISC_SHU_RDAT (DDRPHY_AO_BASE_ADDRESS + 0x0D38) + #define MISC_SHU_RDAT_DATLAT Fld(5, 0) //[4:0] + #define MISC_SHU_RDAT_DATLAT_DSEL Fld(5, 8) //[12:8] + #define MISC_SHU_RDAT_DATLAT_DSEL_PHY Fld(5, 16) //[20:16] + +#define DDRPHY_REG_MISC_SHU_RDAT1 (DDRPHY_AO_BASE_ADDRESS + 0x0D3C) + #define MISC_SHU_RDAT1_R_DMRDSEL_DIV2_OPT Fld(1, 0) //[0:0] + #define MISC_SHU_RDAT1_R_DMRDSEL_LOBYTE_OPT Fld(1, 1) //[1:1] + #define MISC_SHU_RDAT1_R_DMRDSEL_HIBYTE_OPT Fld(1, 2) //[2:2] + #define MISC_SHU_RDAT1_RDATDIV2 Fld(1, 4) //[4:4] + #define MISC_SHU_RDAT1_RDATDIV4 Fld(1, 5) //[5:5] + +#define DDRPHY_REG_SHU_MISC_CLK_CTRL0 (DDRPHY_AO_BASE_ADDRESS + 0x0D40) + #define SHU_MISC_CLK_CTRL0_FMEM_CK_CG_DRAMC_DLL_DIS Fld(1, 0) //[0:0] + #define SHU_MISC_CLK_CTRL0_RESERVED_MISC_CLK_CTRL0_BIT3_1 Fld(3, 1) //[3:1] + #define SHU_MISC_CLK_CTRL0_M_CK_OPENLOOP_MODE_SEL Fld(1, 4) //[4:4] + #define SHU_MISC_CLK_CTRL0_RESERVED_MISC_CLK_CTRL0_BIT31_5 Fld(27, 5) //[31:5] + +#define DDRPHY_REG_SHU_MISC_IMPCAL1 (DDRPHY_AO_BASE_ADDRESS + 0x0D44) + #define SHU_MISC_IMPCAL1_IMPCAL_CHKCYCLE Fld(3, 0) //[2:0] + #define SHU_MISC_IMPCAL1_IMPDRVP Fld(5, 4) //[8:4] + #define SHU_MISC_IMPCAL1_IMPDRVN Fld(5, 12) //[16:12] + #define SHU_MISC_IMPCAL1_IMPCAL_CALEN_CYCLE Fld(3, 17) //[19:17] + #define SHU_MISC_IMPCAL1_IMPCALCNT Fld(8, 20) //[27:20] + #define SHU_MISC_IMPCAL1_IMPCAL_CALICNT Fld(4, 28) //[31:28] + +#define DDRPHY_REG_SHU_MISC_DRVING1 (DDRPHY_AO_BASE_ADDRESS + 0x0D48) + #define SHU_MISC_DRVING1_DQDRVN2 Fld(5, 0) //[4:0] + #define SHU_MISC_DRVING1_DQDRVP2 Fld(5, 5) //[9:5] + #define SHU_MISC_DRVING1_DQSDRVN1 Fld(5, 10) //[14:10] + #define SHU_MISC_DRVING1_DQSDRVP1 Fld(5, 15) //[19:15] + #define SHU_MISC_DRVING1_DQSDRVN2 Fld(5, 20) //[24:20] + #define SHU_MISC_DRVING1_DQSDRVP2 Fld(5, 25) //[29:25] + #define SHU_MISC_DRVING1_DIS_IMP_ODTN_TRACK Fld(1, 30) //[30:30] + #define SHU_MISC_DRVING1_DIS_IMPCAL_HW Fld(1, 31) //[31:31] + +#define DDRPHY_REG_SHU_MISC_DRVING2 (DDRPHY_AO_BASE_ADDRESS + 0x0D4C) + #define SHU_MISC_DRVING2_CMDDRVN1 Fld(5, 0) //[4:0] + #define SHU_MISC_DRVING2_CMDDRVP1 Fld(5, 5) //[9:5] + #define SHU_MISC_DRVING2_CMDDRVN2 Fld(5, 10) //[14:10] + #define SHU_MISC_DRVING2_CMDDRVP2 Fld(5, 15) //[19:15] + #define SHU_MISC_DRVING2_DQDRVN1 Fld(5, 20) //[24:20] + #define SHU_MISC_DRVING2_DQDRVP1 Fld(5, 25) //[29:25] + #define SHU_MISC_DRVING2_DIS_IMPCAL_ODT_EN Fld(1, 31) //[31:31] + +#define DDRPHY_REG_SHU_MISC_DRVING3 (DDRPHY_AO_BASE_ADDRESS + 0x0D50) + #define SHU_MISC_DRVING3_DQODTN2 Fld(5, 0) //[4:0] + #define SHU_MISC_DRVING3_DQODTP2 Fld(5, 5) //[9:5] + #define SHU_MISC_DRVING3_DQSODTN Fld(5, 10) //[14:10] + #define SHU_MISC_DRVING3_DQSODTP Fld(5, 15) //[19:15] + #define SHU_MISC_DRVING3_DQSODTN2 Fld(5, 20) //[24:20] + #define SHU_MISC_DRVING3_DQSODTP2 Fld(5, 25) //[29:25] + +#define DDRPHY_REG_SHU_MISC_DRVING4 (DDRPHY_AO_BASE_ADDRESS + 0x0D54) + #define SHU_MISC_DRVING4_CMDODTN1 Fld(5, 0) //[4:0] + #define SHU_MISC_DRVING4_CMDODTP1 Fld(5, 5) //[9:5] + #define SHU_MISC_DRVING4_CMDODTN2 Fld(5, 10) //[14:10] + #define SHU_MISC_DRVING4_CMDODTP2 Fld(5, 15) //[19:15] + #define SHU_MISC_DRVING4_DQODTN1 Fld(5, 20) //[24:20] + #define SHU_MISC_DRVING4_DQODTP1 Fld(5, 25) //[29:25] + +#define DDRPHY_REG_SHU_MISC_DRVING5 (DDRPHY_AO_BASE_ADDRESS + 0x0D58) + #define SHU_MISC_DRVING5_DQCODTN2 Fld(5, 0) //[4:0] + #define SHU_MISC_DRVING5_DQCODTP2 Fld(5, 5) //[9:5] + #define SHU_MISC_DRVING5_DQCDRVN1 Fld(5, 10) //[14:10] + #define SHU_MISC_DRVING5_DQCDRVP1 Fld(5, 15) //[19:15] + #define SHU_MISC_DRVING5_DQCDRVN2 Fld(5, 20) //[24:20] + #define SHU_MISC_DRVING5_DQCDRVP2 Fld(5, 25) //[29:25] + +#define DDRPHY_REG_SHU_MISC_DRVING6 (DDRPHY_AO_BASE_ADDRESS + 0x0D5C) + #define SHU_MISC_DRVING6_IMP_TXDLY_CMD Fld(6, 0) //[5:0] + #define SHU_MISC_DRVING6_DQCODTN1 Fld(5, 20) //[24:20] + #define SHU_MISC_DRVING6_DQCODTP1 Fld(5, 25) //[29:25] + +#define DDRPHY_REG_SHU_MISC_DUTY_SCAN (DDRPHY_AO_BASE_ADDRESS + 0x0D60) + #define SHU_MISC_DUTY_SCAN_R_DMFREQDIV2 Fld(1, 0) //[0:0] + #define SHU_MISC_DUTY_SCAN_R_DM64BITEN Fld(1, 1) //[1:1] + +#define DDRPHY_REG_SHU_MISC_DMA (DDRPHY_AO_BASE_ADDRESS + 0x0D64) + #define SHU_MISC_DMA_SRAM_RL_2T Fld(1, 0) //[0:0] + +#define DDRPHY_REG_SHU_MISC_RVREF (DDRPHY_AO_BASE_ADDRESS + 0x0D68) + #define SHU_MISC_RVREF_RG_RVREF_SEL_DQ Fld(6, 16) //[21:16] + #define SHU_MISC_RVREF_RG_RVREF_DDR4_SEL Fld(1, 22) //[22:22] + #define SHU_MISC_RVREF_RG_RVREF_DDR3_SEL Fld(1, 23) //[23:23] + #define SHU_MISC_RVREF_RG_RVREF_SEL_CMD Fld(6, 24) //[29:24] + +#define DDRPHY_REG_SHU_MISC_RX_PIPE_CTRL (DDRPHY_AO_BASE_ADDRESS + 0x0D6C) + #define SHU_MISC_RX_PIPE_CTRL_RX_PIPE_BYPASS_EN Fld(1, 0) //[0:0] + +#define DDRPHY_REG_SHU_MISC_TX_PIPE_CTRL (DDRPHY_AO_BASE_ADDRESS + 0x0D70) + #define SHU_MISC_TX_PIPE_CTRL_CMD_TXPIPE_BYPASS_EN Fld(1, 0) //[0:0] + #define SHU_MISC_TX_PIPE_CTRL_CK_TXPIPE_BYPASS_EN Fld(1, 1) //[1:1] + #define SHU_MISC_TX_PIPE_CTRL_TX_PIPE_BYPASS_EN Fld(1, 2) //[2:2] + #define SHU_MISC_TX_PIPE_CTRL_CS_TXPIPE_BYPASS_EN Fld(1, 3) //[3:3] + #define SHU_MISC_TX_PIPE_CTRL_SKIP_TXPIPE_BYPASS Fld(1, 8) //[8:8] + +#define DDRPHY_REG_SHU_MISC_EMI_CTRL (DDRPHY_AO_BASE_ADDRESS + 0x0D74) + #define SHU_MISC_EMI_CTRL_DR_EMI_RESERVE Fld(32, 0) //[31:0] + +#define DDRPHY_REG_SHU_MISC_RANK_SEL_STB (DDRPHY_AO_BASE_ADDRESS + 0x0D78) + #define SHU_MISC_RANK_SEL_STB_RANK_SEL_STB_EN Fld(1, 0) //[0:0] + #define SHU_MISC_RANK_SEL_STB_RANK_SEL_STB_EN_B23 Fld(1, 1) //[1:1] + #define SHU_MISC_RANK_SEL_STB_RANK_SEL_STB_SERMODE Fld(2, 2) //[3:2] + #define SHU_MISC_RANK_SEL_STB_RANK_SEL_STB_TRACK Fld(1, 4) //[4:4] + #define SHU_MISC_RANK_SEL_STB_RANK_SEL_RXDLY_TRACK Fld(1, 5) //[5:5] + #define SHU_MISC_RANK_SEL_STB_RANK_SEL_STB_PHASE_EN Fld(1, 7) //[7:7] + #define SHU_MISC_RANK_SEL_STB_RANK_SEL_PHSINCTL Fld(4, 8) //[11:8] + #define SHU_MISC_RANK_SEL_STB_RANK_SEL_STB_UI_PLUS Fld(4, 16) //[19:16] + #define SHU_MISC_RANK_SEL_STB_RANK_SEL_STB_MCK_PLUS Fld(4, 20) //[23:20] + #define SHU_MISC_RANK_SEL_STB_RANK_SEL_STB_UI_MINUS Fld(4, 24) //[27:24] + #define SHU_MISC_RANK_SEL_STB_RANK_SEL_STB_MCK_MINUS Fld(4, 28) //[31:28] + +#define DDRPHY_REG_SHU_MISC_RDSEL_TRACK (DDRPHY_AO_BASE_ADDRESS + 0x0D7C) + #define SHU_MISC_RDSEL_TRACK_DMDATLAT_I Fld(5, 0) //[4:0] + #define SHU_MISC_RDSEL_TRACK_RDSEL_HWSAVE_MSK Fld(1, 6) //[6:6] + #define SHU_MISC_RDSEL_TRACK_RDSEL_TRACK_EN Fld(1, 7) //[7:7] + #define SHU_MISC_RDSEL_TRACK_SHU_GW_THRD_NEG Fld(12, 8) //[19:8] + #define SHU_MISC_RDSEL_TRACK_SHU_GW_THRD_POS Fld(12, 20) //[31:20] + +#define DDRPHY_REG_SHU_MISC_PRE_TDQSCK (DDRPHY_AO_BASE_ADDRESS + 0x0D80) + #define SHU_MISC_PRE_TDQSCK_PRECAL_DISABLE Fld(1, 0) //[0:0] + +#define DDRPHY_REG_SHU_MISC_ASYNC_FIFO_CTRL (DDRPHY_AO_BASE_ADDRESS + 0x0D84) + #define SHU_MISC_ASYNC_FIFO_CTRL_ASYNC_EN Fld(1, 0) //[0:0] + #define SHU_MISC_ASYNC_FIFO_CTRL_AFIFO_SYNCDEPTH Fld(2, 4) //[5:4] + +#define DDRPHY_REG_MISC_SHU_RX_SELPH_MODE (DDRPHY_AO_BASE_ADDRESS + 0x0D88) + #define MISC_SHU_RX_SELPH_MODE_DQSIEN_SELPH_SERMODE Fld(2, 0) //[1:0] + #define MISC_SHU_RX_SELPH_MODE_RODT_SELPH_SERMODE Fld(2, 4) //[5:4] + #define MISC_SHU_RX_SELPH_MODE_RANK_SELPH_SERMODE Fld(2, 6) //[7:6] + +#define DDRPHY_REG_MISC_SHU_RANK_SEL_LAT (DDRPHY_AO_BASE_ADDRESS + 0x0D8C) + #define MISC_SHU_RANK_SEL_LAT_RANK_SEL_LAT_B0 Fld(4, 0) //[3:0] + #define MISC_SHU_RANK_SEL_LAT_RANK_SEL_LAT_B1 Fld(4, 4) //[7:4] + #define MISC_SHU_RANK_SEL_LAT_RANK_SEL_LAT_CA Fld(4, 8) //[11:8] + +#define DDRPHY_REG_MISC_SHU_DLINE_MON_CTRL (DDRPHY_AO_BASE_ADDRESS + 0x0D90) + #define MISC_SHU_DLINE_MON_CTRL_DLINE_MON_TSHIFT Fld(2, 0) //[1:0] + #define MISC_SHU_DLINE_MON_CTRL_DLINE_MON_DIV Fld(2, 2) //[3:2] + #define MISC_SHU_DLINE_MON_CTRL_DLINE_MON_DLY Fld(7, 8) //[14:8] + #define MISC_SHU_DLINE_MON_CTRL_DLINE_MON_EN Fld(1, 16) //[16:16] + +#define DDRPHY_REG_MISC_SHU_DLINE_MON_CNT (DDRPHY_AO_BASE_ADDRESS + 0x0D94) + #define MISC_SHU_DLINE_MON_CNT_TRIG_DLINE_MON_CNT Fld(16, 0) //[15:0] + +#define DDRPHY_REG_MISC_SHU_MIDPI_CTRL (DDRPHY_AO_BASE_ADDRESS + 0x0D98) + #define MISC_SHU_MIDPI_CTRL_MIDPI_ENABLE Fld(1, 0) //[0:0] + #define MISC_SHU_MIDPI_CTRL_MIDPI_DIV4_ENABLE Fld(1, 1) //[1:1] + +#define DDRPHY_REG_MISC_SHU_RX_CG_CTRL (DDRPHY_AO_BASE_ADDRESS + 0x0DA0) + #define MISC_SHU_RX_CG_CTRL_RX_DCM_OPT Fld(1, 0) //[0:0] + #define MISC_SHU_RX_CG_CTRL_RX_APHY_CTRL_DCM_OPT Fld(1, 1) //[1:1] + #define MISC_SHU_RX_CG_CTRL_RX_RODT_DCM_OPT Fld(1, 2) //[2:2] + #define MISC_SHU_RX_CG_CTRL_RX_DQSIEN_STBCAL_CG_EN Fld(1, 4) //[4:4] + #define MISC_SHU_RX_CG_CTRL_RX_DQSIEN_AUTOK_CG_EN Fld(1, 5) //[5:5] + #define MISC_SHU_RX_CG_CTRL_RX_RDSEL_TRACKING_CG_EN Fld(1, 8) //[8:8] + #define MISC_SHU_RX_CG_CTRL_RX_DQSIEN_RETRY_CG_EN Fld(1, 9) //[9:9] + #define MISC_SHU_RX_CG_CTRL_RX_PRECAL_CG_EN Fld(1, 10) //[10:10] + #define MISC_SHU_RX_CG_CTRL_RX_DCM_EXT_DLY Fld(4, 16) //[19:16] + #define MISC_SHU_RX_CG_CTRL_RX_DCM_WAIT_DLE_EXT_DLY Fld(4, 20) //[23:20] + +#define DDRPHY_REG_MISC_SHU_CG_CTRL0 (DDRPHY_AO_BASE_ADDRESS + 0x0DA4) + #define MISC_SHU_CG_CTRL0_R_PHY_MCK_CG_CTRL Fld(32, 0) //[31:0] + +#define DDRPHY_REG_MISC_STBERR_ALL (DDRPHY_AO_BASE_ADDRESS + 0x1500) + #define MISC_STBERR_ALL_GATING_ERROR_ALL_RK0 Fld(1, 0) //[0:0] + #define MISC_STBERR_ALL_GATING_ERROR_B0_RK0 Fld(1, 1) //[1:1] + #define MISC_STBERR_ALL_GATING_ERROR_B1_RK0 Fld(1, 2) //[2:2] + #define MISC_STBERR_ALL_GATING_ERROR_CA_RK0 Fld(1, 3) //[3:3] + #define MISC_STBERR_ALL_GATING_ERROR_ALL_RK1 Fld(1, 4) //[4:4] + #define MISC_STBERR_ALL_GATING_ERROR_B0_RK1 Fld(1, 5) //[5:5] + #define MISC_STBERR_ALL_GATING_ERROR_B1_RK1 Fld(1, 6) //[6:6] + #define MISC_STBERR_ALL_GATING_ERROR_CA_RK1 Fld(1, 7) //[7:7] + #define MISC_STBERR_ALL_STBENERR_ALL Fld(1, 16) //[16:16] + #define MISC_STBERR_ALL_RX_ARDQ0_FIFO_STBEN_ERR_B0 Fld(1, 24) //[24:24] + #define MISC_STBERR_ALL_RX_ARDQ4_FIFO_STBEN_ERR_B0 Fld(1, 25) //[25:25] + #define MISC_STBERR_ALL_RX_ARDQ0_FIFO_STBEN_ERR_B1 Fld(1, 26) //[26:26] + #define MISC_STBERR_ALL_RX_ARDQ4_FIFO_STBEN_ERR_B1 Fld(1, 27) //[27:27] + #define MISC_STBERR_ALL_RX_ARCA0_FIFO_STBEN_ERR Fld(1, 28) //[28:28] + #define MISC_STBERR_ALL_RX_ARCA4_FIFO_STBEN_ERR Fld(1, 29) //[29:29] + +#define DDRPHY_REG_MISC_STBERR_RK0_R (DDRPHY_AO_BASE_ADDRESS + 0x1504) + #define MISC_STBERR_RK0_R_STBENERR_B0_RK0_R Fld(8, 0) //[7:0] + #define MISC_STBERR_RK0_R_STBENERR_B1_RK0_R Fld(8, 8) //[15:8] + #define MISC_STBERR_RK0_R_STBENERR_CA_RK0_R Fld(8, 16) //[23:16] + +#define DDRPHY_REG_MISC_STBERR_RK0_F (DDRPHY_AO_BASE_ADDRESS + 0x1508) + #define MISC_STBERR_RK0_F_STBENERR_B0_RK0_F Fld(8, 0) //[7:0] + #define MISC_STBERR_RK0_F_STBENERR_B1_RK0_F Fld(8, 8) //[15:8] + #define MISC_STBERR_RK0_F_STBENERR_CA_RK0_F Fld(8, 16) //[23:16] + +#define DDRPHY_REG_MISC_STBERR_RK1_R (DDRPHY_AO_BASE_ADDRESS + 0x150C) + #define MISC_STBERR_RK1_R_STBENERR_B0_RK1_R Fld(8, 0) //[7:0] + #define MISC_STBERR_RK1_R_STBENERR_B1_RK1_R Fld(8, 8) //[15:8] + #define MISC_STBERR_RK1_R_STBENERR_CA_RK1_R Fld(8, 16) //[23:16] + +#define DDRPHY_REG_MISC_STBERR_RK1_F (DDRPHY_AO_BASE_ADDRESS + 0x1510) + #define MISC_STBERR_RK1_F_STBENERR_B0_RK1_F Fld(8, 0) //[7:0] + #define MISC_STBERR_RK1_F_STBENERR_B1_RK1_F Fld(8, 8) //[15:8] + #define MISC_STBERR_RK1_F_STBENERR_CA_RK1_F Fld(8, 16) //[23:16] + +#define DDRPHY_REG_MISC_DDR_RESERVE_STATE (DDRPHY_AO_BASE_ADDRESS + 0x1520) + #define MISC_DDR_RESERVE_STATE_WDT_SM Fld(4, 0) //[3:0] + +#define DDRPHY_REG_MISC_IRQ_STATUS0 (DDRPHY_AO_BASE_ADDRESS + 0x1530) + #define MISC_IRQ_STATUS0_REFRATE_EN Fld(1, 0) //[0:0] + #define MISC_IRQ_STATUS0_REFPENDING_EN Fld(1, 1) //[1:1] + #define MISC_IRQ_STATUS0_PRE_REFRATE_EN Fld(1, 2) //[2:2] + #define MISC_IRQ_STATUS0_RTMRW_ABNORMAL_STOP_EN Fld(1, 3) //[3:3] + #define MISC_IRQ_STATUS0_SREF_REQ_NO_ACK_EN Fld(1, 6) //[6:6] + #define MISC_IRQ_STATUS0_SREF_REQ_SHORT_EN Fld(1, 7) //[7:7] + #define MISC_IRQ_STATUS0_SREF_REQ_DTRIG_EN Fld(1, 8) //[8:8] + #define MISC_IRQ_STATUS0_RTSWCMD_NONVALIDCMD_EN Fld(1, 12) //[12:12] + #define MISC_IRQ_STATUS0_TX_TRACKING1_EN Fld(1, 16) //[16:16] + #define MISC_IRQ_STATUS0_TX_TRACKING2_EN Fld(1, 17) //[17:17] + +#define DDRPHY_REG_MISC_IRQ_STATUS1 (DDRPHY_AO_BASE_ADDRESS + 0x1534) + #define MISC_IRQ_STATUS1_DRAMC_IRQ_OUT_1 Fld(32, 0) //[31:0] + +#define DDRPHY_REG_MISC_IRQ_STATUS2 (DDRPHY_AO_BASE_ADDRESS + 0x1538) + #define MISC_IRQ_STATUS2_PI_TRACKING_WAR_RK1_B0_EN Fld(1, 0) //[0:0] + #define MISC_IRQ_STATUS2_PI_TRACKING_WAR_RK0_B0_EN Fld(1, 1) //[1:1] + #define MISC_IRQ_STATUS2_PI_TRACKING_WAR_RK1_B1_EN Fld(1, 2) //[2:2] + #define MISC_IRQ_STATUS2_PI_TRACKING_WAR_RK0_B1_EN Fld(1, 3) //[3:3] + #define MISC_IRQ_STATUS2_PI_TRACKING_WAR_RK1_CA_EN Fld(1, 4) //[4:4] + #define MISC_IRQ_STATUS2_PI_TRACKING_WAR_RK0_CA_EN Fld(1, 5) //[5:5] + #define MISC_IRQ_STATUS2_STB_GATTING_ERR_EN Fld(1, 7) //[7:7] + #define MISC_IRQ_STATUS2_RX_ARDQ0_FIFO_STBEN_ERR_B0_EN Fld(1, 8) //[8:8] + #define MISC_IRQ_STATUS2_RX_ARDQ4_FIFO_STBEN_ERR_B0_EN Fld(1, 9) //[9:9] + #define MISC_IRQ_STATUS2_RX_ARDQ0_FIFO_STBEN_ERR_B1_EN Fld(1, 10) //[10:10] + #define MISC_IRQ_STATUS2_RX_ARDQ4_FIFO_STBEN_ERR_B1_EN Fld(1, 11) //[11:11] + #define MISC_IRQ_STATUS2_TRACKING_STATUS_ERR_RISING_R1_B1_EN Fld(1, 12) //[12:12] + #define MISC_IRQ_STATUS2_TRACKING_STATUS_ERR_RISING_R1_B0_EN Fld(1, 13) //[13:13] + #define MISC_IRQ_STATUS2_TRACKING_STATUS_ERR_RISING_R0_B1_EN Fld(1, 14) //[14:14] + #define MISC_IRQ_STATUS2_TRACKING_STATUS_ERR_RISING_R0_B0_EN Fld(1, 15) //[15:15] + #define MISC_IRQ_STATUS2_IMP_CLK_ERR_EN Fld(1, 24) //[24:24] + #define MISC_IRQ_STATUS2_IMP_CMD_ERR_EN Fld(1, 25) //[25:25] + #define MISC_IRQ_STATUS2_IMP_DQ1_ERR_EN Fld(1, 26) //[26:26] + #define MISC_IRQ_STATUS2_IMP_DQ0_ERR_EN Fld(1, 27) //[27:27] + #define MISC_IRQ_STATUS2_IMP_DQS_ERR_EN Fld(1, 28) //[28:28] + #define MISC_IRQ_STATUS2_IMP_ODTN_ERR_EN Fld(1, 29) //[29:29] + #define MISC_IRQ_STATUS2_IMP_DRVN_ERR_EN Fld(1, 30) //[30:30] + #define MISC_IRQ_STATUS2_IMP_DRVP_ERR_EN Fld(1, 31) //[31:31] + +#define DDRPHY_REG_MISC_DBG_DB_MESSAGE0 (DDRPHY_AO_BASE_ADDRESS + 0x1600) + #define MISC_DBG_DB_MESSAGE0_DBG_DB_REFRESH_RATE Fld(5, 0) //[4:0] + #define MISC_DBG_DB_MESSAGE0_DBG_DB_REFRESH_QUEUE_CNT Fld(4, 8) //[11:8] + #define MISC_DBG_DB_MESSAGE0_DBG_DB_REFRESH_RATE_CHG_QUEUE_CNT Fld(4, 12) //[15:12] + +#define DDRPHY_REG_MISC_DBG_DB_MESSAGE1 (DDRPHY_AO_BASE_ADDRESS + 0x1604) + #define MISC_DBG_DB_MESSAGE1_DBG_DB_PRE_REFRESH_RATE_RK0 Fld(5, 0) //[4:0] + #define MISC_DBG_DB_MESSAGE1_DBG_DB_PRE_REFRESH_RATE_RK1 Fld(5, 8) //[12:8] + #define MISC_DBG_DB_MESSAGE1_DBG_DB_PRE_REFRESH_RATE_RK0_B1 Fld(5, 16) //[20:16] + #define MISC_DBG_DB_MESSAGE1_DBG_DB_PRE_REFRESH_RATE_RK1_B1 Fld(5, 24) //[28:24] + +#define DDRPHY_REG_MISC_DBG_DB_MESSAGE2 (DDRPHY_AO_BASE_ADDRESS + 0x1608) + #define MISC_DBG_DB_MESSAGE2_DBG_DB_PI_DEC_ACC_CNT_RK0_B0 Fld(6, 0) //[5:0] + #define MISC_DBG_DB_MESSAGE2_DBG_DB_PI_INC_ACC_CNT_RK0_B0 Fld(6, 8) //[13:8] + #define MISC_DBG_DB_MESSAGE2_DBG_DB_PI_DEC_ACC_CNT_RK1_B0 Fld(6, 16) //[21:16] + #define MISC_DBG_DB_MESSAGE2_DBG_DB_PI_INC_ACC_CNT_RK1_B0 Fld(6, 24) //[29:24] + +#define DDRPHY_REG_MISC_DBG_DB_MESSAGE3 (DDRPHY_AO_BASE_ADDRESS + 0x160C) + #define MISC_DBG_DB_MESSAGE3_DBG_DB_DQSIEN_SHU_INI_PI_RK0_B0 Fld(7, 0) //[6:0] + #define MISC_DBG_DB_MESSAGE3_DBG_DB_DQSIEN_SHU_INI_UI_RK0_B0 Fld(8, 8) //[15:8] + #define MISC_DBG_DB_MESSAGE3_DBG_DB_DQSIEN_SHU_CUR_PI_RK0_B0 Fld(7, 16) //[22:16] + #define MISC_DBG_DB_MESSAGE3_DBG_DB_DQSIEN_SHU_CUR_UI_RK0_B0 Fld(8, 24) //[31:24] + +#define DDRPHY_REG_MISC_DBG_DB_MESSAGE4 (DDRPHY_AO_BASE_ADDRESS + 0x1610) + #define MISC_DBG_DB_MESSAGE4_DBG_DB_DQSIEN_SHU_INI_PI_RK1_B0 Fld(7, 0) //[6:0] + #define MISC_DBG_DB_MESSAGE4_DBG_DB_DQSIEN_SHU_INI_UI_RK1_B0 Fld(8, 8) //[15:8] + #define MISC_DBG_DB_MESSAGE4_DBG_DB_DQSIEN_SHU_CUR_PI_RK1_B0 Fld(7, 16) //[22:16] + #define MISC_DBG_DB_MESSAGE4_DBG_DB_DQSIEN_SHU_CUR_UI_RK1_B0 Fld(8, 24) //[31:24] + +#define DDRPHY_REG_MISC_DBG_DB_MESSAGE5 (DDRPHY_AO_BASE_ADDRESS + 0x1614) + #define MISC_DBG_DB_MESSAGE5_DBG_DB_PI_DEC_ACC_CNT_RK0_B1 Fld(6, 0) //[5:0] + #define MISC_DBG_DB_MESSAGE5_DBG_DB_PI_INC_ACC_CNT_RK0_B1 Fld(6, 8) //[13:8] + #define MISC_DBG_DB_MESSAGE5_DBG_DB_PI_DEC_ACC_CNT_RK1_B1 Fld(6, 16) //[21:16] + #define MISC_DBG_DB_MESSAGE5_DBG_DB_PI_INC_ACC_CNT_RK1_B1 Fld(6, 24) //[29:24] + +#define DDRPHY_REG_MISC_DBG_DB_MESSAGE6 (DDRPHY_AO_BASE_ADDRESS + 0x1618) + #define MISC_DBG_DB_MESSAGE6_DBG_DB_DQSIEN_SHU_INI_PI_RK0_B1 Fld(7, 0) //[6:0] + #define MISC_DBG_DB_MESSAGE6_DBG_DB_DQSIEN_SHU_INI_UI_RK0_B1 Fld(8, 8) //[15:8] + #define MISC_DBG_DB_MESSAGE6_DBG_DB_DQSIEN_SHU_CUR_PI_RK0_B1 Fld(7, 16) //[22:16] + #define MISC_DBG_DB_MESSAGE6_DBG_DB_DQSIEN_SHU_CUR_UI_RK0_B1 Fld(8, 24) //[31:24] + +#define DDRPHY_REG_MISC_DBG_DB_MESSAGE7 (DDRPHY_AO_BASE_ADDRESS + 0x161C) + #define MISC_DBG_DB_MESSAGE7_DBG_DB_DQSIEN_SHU_INI_PI_RK1_B1 Fld(7, 0) //[6:0] + #define MISC_DBG_DB_MESSAGE7_DBG_DB_DQSIEN_SHU_INI_UI_RK1_B1 Fld(8, 8) //[15:8] + #define MISC_DBG_DB_MESSAGE7_DBG_DB_DQSIEN_SHU_CUR_PI_RK1_B1 Fld(7, 16) //[22:16] + #define MISC_DBG_DB_MESSAGE7_DBG_DB_DQSIEN_SHU_CUR_UI_RK1_B1 Fld(8, 24) //[31:24] + +#endif // __DDRPHY_AO_REGS_H__ diff --git a/src/vendorcode/mediatek/mt8192/include/Margaux_Register_DDRPHY_MD32.h b/src/vendorcode/mediatek/mt8192/include/Margaux_Register_DDRPHY_MD32.h new file mode 100644 index 000000000000..726aecb7f595 --- /dev/null +++ b/src/vendorcode/mediatek/mt8192/include/Margaux_Register_DDRPHY_MD32.h @@ -0,0 +1,2900 @@ +/* SPDX-License-Identifier: BSD-3-Clause */ + +#ifndef __DDRPHY_MD32_REGS_H__ +#define __DDRPHY_MD32_REGS_H__ + +#define Channel_A_DDRPHY_DPM_BASE_ADDRESS 0x10940000 + +#define DDRPHY_MD32_BASE_ADDRESS Channel_A_DDRPHY_DPM_BASE_VIRTUAL + +#define DDRPHY_MD32_REG_SSPM_CFGREG_SW_RSTN (DDRPHY_MD32_BASE_ADDRESS + 0x0000) + #define SSPM_CFGREG_SW_RSTN_SW_RSTN Fld(1, 0) //[0:0] + +#define DDRPHY_MD32_REG_SSPM_CFGREG_RESOURCE_CTL (DDRPHY_MD32_BASE_ADDRESS + 0x0004) + #define SSPM_CFGREG_RESOURCE_CTL_APSRC_REQ Fld(1, 0) //[0:0] + #define SSPM_CFGREG_RESOURCE_CTL_APSRC_ACK Fld(1, 4) //[4:4] + #define SSPM_CFGREG_RESOURCE_CTL_INFRA_REQ Fld(1, 8) //[8:8] + #define SSPM_CFGREG_RESOURCE_CTL_INFRA_ACK Fld(1, 12) //[12:12] + #define SSPM_CFGREG_RESOURCE_CTL_SRCLKENA_REQ Fld(1, 16) //[16:16] + #define SSPM_CFGREG_RESOURCE_CTL_SRCLKENA_ACK Fld(1, 20) //[20:20] + #define SSPM_CFGREG_RESOURCE_CTL_DCS_ULTRA_REQ Fld(1, 24) //[24:24] + #define SSPM_CFGREG_RESOURCE_CTL_DCS_ULTRA_REQ_ACK Fld(1, 28) //[28:28] + +#define DDRPHY_MD32_REG_SSPM_CFGREG_SYS_RMAP (DDRPHY_MD32_BASE_ADDRESS + 0x0008) + #define SSPM_CFGREG_SYS_RMAP_SYS_RMAP Fld(4, 0) //[3:0] + #define SSPM_CFGREG_SYS_RMAP_DRAM_RMAP0 Fld(6, 4) //[9:4] + #define SSPM_CFGREG_SYS_RMAP_DRAM_RMAP1 Fld(6, 10) //[15:10] + #define SSPM_CFGREG_SYS_RMAP_DRAM_RMAP2 Fld(6, 16) //[21:16] + #define SSPM_CFGREG_SYS_RMAP_DRAM_RMAP3 Fld(6, 22) //[27:22] + #define SSPM_CFGREG_SYS_RMAP_BUS_ARB_POLICY Fld(1, 28) //[28:28] + #define SSPM_CFGREG_SYS_RMAP_H2H_POSTWRITE_DIS Fld(1, 29) //[29:29] + +#define DDRPHY_MD32_REG_SSPM_CFGREG_OCD_BYPASS (DDRPHY_MD32_BASE_ADDRESS + 0x000C) + #define SSPM_CFGREG_OCD_BYPASS_OCD_BYPASS Fld(1, 0) //[0:0] + +#define DDRPHY_MD32_REG_SSPM_CFGREG_MD2HOST_IPC (DDRPHY_MD32_BASE_ADDRESS + 0x0010) + #define SSPM_CFGREG_MD2HOST_IPC_MD2HOST_IPC Fld(1, 0) //[0:0] + #define SSPM_CFGREG_MD2HOST_IPC_MD2HOST_IPC1 Fld(1, 1) //[1:1] + #define SSPM_CFGREG_MD2HOST_IPC_MD2HOST_IPC_INT Fld(1, 8) //[8:8] + #define SSPM_CFGREG_MD2HOST_IPC_MD2HOST_IPC_INT1 Fld(1, 9) //[9:9] + #define SSPM_CFGREG_MD2HOST_IPC_WDT_INT Fld(1, 10) //[10:10] + +#define DDRPHY_MD32_REG_SSPM_CFGREG_MD2SPM_IPC (DDRPHY_MD32_BASE_ADDRESS + 0x0014) + #define SSPM_CFGREG_MD2SPM_IPC_MD2SPM_IPC Fld(1, 0) //[0:0] + +#define DDRPHY_MD32_REG_SSPM_CFGREG_HOST2MD_IPC (DDRPHY_MD32_BASE_ADDRESS + 0x0018) + #define SSPM_CFGREG_HOST2MD_IPC_HOST2MD_IPC Fld(1, 0) //[0:0] + +#define DDRPHY_MD32_REG_SSPM_CFGREG_SPM2MD_IPC (DDRPHY_MD32_BASE_ADDRESS + 0x001C) + #define SSPM_CFGREG_SPM2MD_IPC_SPM2MD_IPC Fld(1, 0) //[0:0] + +#define DDRPHY_MD32_REG_SSPM_CFGREG_GPR0 (DDRPHY_MD32_BASE_ADDRESS + 0x0020) + #define SSPM_CFGREG_GPR0_GPR0 Fld(32, 0) //[31:0] + +#define DDRPHY_MD32_REG_SSPM_CFGREG_GPR1 (DDRPHY_MD32_BASE_ADDRESS + 0x0024) + #define SSPM_CFGREG_GPR1_GPR1 Fld(32, 0) //[31:0] + +#define DDRPHY_MD32_REG_SSPM_CFGREG_GPR2 (DDRPHY_MD32_BASE_ADDRESS + 0x0028) + #define SSPM_CFGREG_GPR2_GPR2 Fld(32, 0) //[31:0] + +#define DDRPHY_MD32_REG_SSPM_CFGREG_GPR3 (DDRPHY_MD32_BASE_ADDRESS + 0x002C) + #define SSPM_CFGREG_GPR3_GPR3 Fld(32, 0) //[31:0] + +#define DDRPHY_MD32_REG_SSPM_CFGREG_GPR4 (DDRPHY_MD32_BASE_ADDRESS + 0x0030) + #define SSPM_CFGREG_GPR4_GPR4 Fld(32, 0) //[31:0] + +#define DDRPHY_MD32_REG_SSPM_CFGREG_GPR5 (DDRPHY_MD32_BASE_ADDRESS + 0x0034) + #define SSPM_CFGREG_GPR5_GPR5 Fld(32, 0) //[31:0] + +#define DDRPHY_MD32_REG_SSPM_CFGREG_DVFS_INFO (DDRPHY_MD32_BASE_ADDRESS + 0x0038) + #define SSPM_CFGREG_DVFS_INFO_DVFS_INFO_0 Fld(32, 0) //[31:0] + +#define DDRPHY_MD32_REG_SSPM_CFGREG_TEMPERATURE (DDRPHY_MD32_BASE_ADDRESS + 0x003C) + #define SSPM_CFGREG_TEMPERATURE_TEMPERATURE Fld(15, 0) //[14:0] + +#define DDRPHY_MD32_REG_SSPM_CFGREG_WDT_CFG (DDRPHY_MD32_BASE_ADDRESS + 0x0040) + #define SSPM_CFGREG_WDT_CFG_WDT_VAL Fld(20, 0) //[19:0] + #define SSPM_CFGREG_WDT_CFG_WDT_EN Fld(1, 31) //[31:31] + +#define DDRPHY_MD32_REG_SSPM_CFGREG_WDT_KICK (DDRPHY_MD32_BASE_ADDRESS + 0x0044) + #define SSPM_CFGREG_WDT_KICK_WDT_KICK Fld(1, 0) //[0:0] + +#define DDRPHY_MD32_REG_SSPM_CFGREG_SEMAPHORE (DDRPHY_MD32_BASE_ADDRESS + 0x0048) + #define SSPM_CFGREG_SEMAPHORE_SEMA_0_M Fld(1, 0) //[0:0] + #define SSPM_CFGREG_SEMAPHORE_SEMA_0_H Fld(1, 1) //[1:1] + #define SSPM_CFGREG_SEMAPHORE_SEMA_1_M Fld(1, 2) //[2:2] + #define SSPM_CFGREG_SEMAPHORE_SEMA_1_H Fld(1, 3) //[3:3] + #define SSPM_CFGREG_SEMAPHORE_SEMA_2_M Fld(1, 4) //[4:4] + #define SSPM_CFGREG_SEMAPHORE_SEMA_2_H Fld(1, 5) //[5:5] + #define SSPM_CFGREG_SEMAPHORE_SEMA_3_M Fld(1, 6) //[6:6] + #define SSPM_CFGREG_SEMAPHORE_SEMA_3_H Fld(1, 7) //[7:7] + #define SSPM_CFGREG_SEMAPHORE_SEMA_4_M Fld(1, 8) //[8:8] + #define SSPM_CFGREG_SEMAPHORE_SEMA_4_H Fld(1, 9) //[9:9] + #define SSPM_CFGREG_SEMAPHORE_SEMA_5_M Fld(1, 10) //[10:10] + #define SSPM_CFGREG_SEMAPHORE_SEMA_5_H Fld(1, 11) //[11:11] + #define SSPM_CFGREG_SEMAPHORE_SEMA_6_M Fld(1, 12) //[12:12] + #define SSPM_CFGREG_SEMAPHORE_SEMA_6_H Fld(1, 13) //[13:13] + #define SSPM_CFGREG_SEMAPHORE_SEMA_7_M Fld(1, 14) //[14:14] + #define SSPM_CFGREG_SEMAPHORE_SEMA_7_H Fld(1, 15) //[15:15] + #define SSPM_CFGREG_SEMAPHORE_SEMA_8_M Fld(1, 16) //[16:16] + #define SSPM_CFGREG_SEMAPHORE_SEMA_8_H Fld(1, 17) //[17:17] + #define SSPM_CFGREG_SEMAPHORE_SEMA_9_M Fld(1, 18) //[18:18] + #define SSPM_CFGREG_SEMAPHORE_SEMA_9_H Fld(1, 19) //[19:19] + #define SSPM_CFGREG_SEMAPHORE_SEMA_10_M Fld(1, 20) //[20:20] + #define SSPM_CFGREG_SEMAPHORE_SEMA_10_H Fld(1, 21) //[21:21] + #define SSPM_CFGREG_SEMAPHORE_SEMA_11_M Fld(1, 22) //[22:22] + #define SSPM_CFGREG_SEMAPHORE_SEMA_11_H Fld(1, 23) //[23:23] + #define SSPM_CFGREG_SEMAPHORE_SEMA_12_M Fld(1, 24) //[24:24] + #define SSPM_CFGREG_SEMAPHORE_SEMA_12_H Fld(1, 25) //[25:25] + #define SSPM_CFGREG_SEMAPHORE_SEMA_13_M Fld(1, 26) //[26:26] + #define SSPM_CFGREG_SEMAPHORE_SEMA_13_H Fld(1, 27) //[27:27] + #define SSPM_CFGREG_SEMAPHORE_SEMA_14_M Fld(1, 28) //[28:28] + #define SSPM_CFGREG_SEMAPHORE_SEMA_14_H Fld(1, 29) //[29:29] + #define SSPM_CFGREG_SEMAPHORE_SEMA_15_M Fld(1, 30) //[30:30] + #define SSPM_CFGREG_SEMAPHORE_SEMA_15_H Fld(1, 31) //[31:31] + +#define DDRPHY_MD32_REG_SSPM_CFGREG_MD32_TBUF_WPTR (DDRPHY_MD32_BASE_ADDRESS + 0x004C) + #define SSPM_CFGREG_MD32_TBUF_WPTR_MON_TBUF_WPTR Fld(4, 0) //[3:0] + +#define DDRPHY_MD32_REG_SSPM_CFGREG_MD32_CCNT (DDRPHY_MD32_BASE_ADDRESS + 0x0050) + #define SSPM_CFGREG_MD32_CCNT_MON_CCNT Fld(32, 0) //[31:0] + +#define DDRPHY_MD32_REG_SSPM_CFGREG_MD32_PCNT0 (DDRPHY_MD32_BASE_ADDRESS + 0x0054) + #define SSPM_CFGREG_MD32_PCNT0_MON_PCNT0 Fld(32, 0) //[31:0] + +#define DDRPHY_MD32_REG_SSPM_CFGREG_MD32_PCNT1 (DDRPHY_MD32_BASE_ADDRESS + 0x0058) + #define SSPM_CFGREG_MD32_PCNT1_MON_PCNT1 Fld(32, 0) //[31:0] + +#define DDRPHY_MD32_REG_SSPM_CFGREG_MD32_PCNT2 (DDRPHY_MD32_BASE_ADDRESS + 0x005C) + #define SSPM_CFGREG_MD32_PCNT2_MON_PCNT2 Fld(32, 0) //[31:0] + +#define DDRPHY_MD32_REG_SSPM_CFGREG_MD32_CONTID (DDRPHY_MD32_BASE_ADDRESS + 0x0060) + #define SSPM_CFGREG_MD32_CONTID_MON_CONTID Fld(32, 0) //[31:0] + +#define DDRPHY_MD32_REG_SSPM_CFGREG_MD32_PC (DDRPHY_MD32_BASE_ADDRESS + 0x0064) + #define SSPM_CFGREG_MD32_PC_MON_PC Fld(32, 0) //[31:0] + +#define DDRPHY_MD32_REG_SSPM_CFGREG_MD32_PC_MON (DDRPHY_MD32_BASE_ADDRESS + 0x0068) + #define SSPM_CFGREG_MD32_PC_MON_MON_PC Fld(32, 0) //[31:0] + +#define DDRPHY_MD32_REG_SSPM_CFGREG_MD32_BUS_STATUS (DDRPHY_MD32_BASE_ADDRESS + 0x006C) + #define SSPM_CFGREG_MD32_BUS_STATUS_BUS_STATUS Fld(32, 0) //[31:0] + +#define DDRPHY_MD32_REG_SSPM_CFGREG_MD32_AHB_M0_ADDR (DDRPHY_MD32_BASE_ADDRESS + 0x0070) + #define SSPM_CFGREG_MD32_AHB_M0_ADDR_AHB_M0_ADDR Fld(32, 0) //[31:0] + +#define DDRPHY_MD32_REG_SSPM_CFGREG_MD32_AHB_M1_ADDR (DDRPHY_MD32_BASE_ADDRESS + 0x0074) + #define SSPM_CFGREG_MD32_AHB_M1_ADDR_AHB_M1_ADDR Fld(32, 0) //[31:0] + +#define DDRPHY_MD32_REG_SSPM_CFGREG_ONE_TIME_LOCK (DDRPHY_MD32_BASE_ADDRESS + 0x0078) + #define SSPM_CFGREG_ONE_TIME_LOCK_ONE_TIME_LOCK Fld(32, 0) //[31:0] + +#define DDRPHY_MD32_REG_SSPM_CFGREG_SECURE_CTRL (DDRPHY_MD32_BASE_ADDRESS + 0x007C) + #define SSPM_CFGREG_SECURE_CTRL_SECURE_CTRL_0 Fld(1, 0) //[0:0] + #define SSPM_CFGREG_SECURE_CTRL_SECURE_CTRL_1 Fld(1, 1) //[1:1] + #define SSPM_CFGREG_SECURE_CTRL_SECURE_CTRL_2 Fld(1, 2) //[2:2] + #define SSPM_CFGREG_SECURE_CTRL_SECURE_CTRL_3 Fld(1, 3) //[3:3] + #define SSPM_CFGREG_SECURE_CTRL_SECURE_CTRL_4 Fld(1, 4) //[4:4] + #define SSPM_CFGREG_SECURE_CTRL_SECURE_CTRL_5 Fld(1, 5) //[5:5] + #define SSPM_CFGREG_SECURE_CTRL_SECURE_CTRL_6 Fld(1, 6) //[6:6] + #define SSPM_CFGREG_SECURE_CTRL_SECURE_CTRL_7 Fld(1, 7) //[7:7] + #define SSPM_CFGREG_SECURE_CTRL_SECURE_CTRL_8 Fld(1, 8) //[8:8] + #define SSPM_CFGREG_SECURE_CTRL_SECURE_CTRL_9 Fld(1, 9) //[9:9] + #define SSPM_CFGREG_SECURE_CTRL_SECURE_CTRL_10 Fld(1, 10) //[10:10] + #define SSPM_CFGREG_SECURE_CTRL_SECURE_CTRL_11 Fld(1, 11) //[11:11] + #define SSPM_CFGREG_SECURE_CTRL_SECURE_CTRL_12 Fld(1, 12) //[12:12] + #define SSPM_CFGREG_SECURE_CTRL_SECURE_CTRL_13 Fld(1, 13) //[13:13] + #define SSPM_CFGREG_SECURE_CTRL_SECURE_CTRL_14 Fld(1, 14) //[14:14] + #define SSPM_CFGREG_SECURE_CTRL_SECURE_CTRL_24 Fld(1, 24) //[24:24] + #define SSPM_CFGREG_SECURE_CTRL_SECURE_CTRL_28 Fld(1, 28) //[28:28] + +#define DDRPHY_MD32_REG_SSPM_CFGREG_TCM_LOCK_CNT (DDRPHY_MD32_BASE_ADDRESS + 0x0080) + #define SSPM_CFGREG_TCM_LOCK_CNT_TCM_LOCK_CNT Fld(8, 0) //[7:0] + +#define DDRPHY_MD32_REG_SSPM_CFGREG_SLPP_S_EN (DDRPHY_MD32_BASE_ADDRESS + 0x0088) + #define SSPM_CFGREG_SLPP_S_EN_SLPP_EN Fld(1, 0) //[0:0] + +#define DDRPHY_MD32_REG_SSPM_CFGREG_P2P_TOEN (DDRPHY_MD32_BASE_ADDRESS + 0x008C) + #define SSPM_CFGREG_P2P_TOEN_P2P_TOEN_0 Fld(1, 0) //[0:0] + #define SSPM_CFGREG_P2P_TOEN_P2P_TOEN_1 Fld(1, 1) //[1:1] + #define SSPM_CFGREG_P2P_TOEN_P2P_TOEN_2 Fld(1, 2) //[2:2] + #define SSPM_CFGREG_P2P_TOEN_P2P_TOEN_3 Fld(1, 3) //[3:3] + #define SSPM_CFGREG_P2P_TOEN_P2P_TOEN_4 Fld(1, 4) //[4:4] + #define SSPM_CFGREG_P2P_TOEN_P2P_TOEN_5 Fld(1, 5) //[5:5] + #define SSPM_CFGREG_P2P_TOEN_P2P_TOEN_6 Fld(1, 6) //[6:6] + +#define DDRPHY_MD32_REG_SSPM_CFGREG_MBOX0_IN_IRQ (DDRPHY_MD32_BASE_ADDRESS + 0x00A0) + #define SSPM_CFGREG_MBOX0_IN_IRQ_MBOX0_IN_IRQ Fld(32, 0) //[31:0] + +#define DDRPHY_MD32_REG_SSPM_CFGREG_MBOX1_IN_IRQ (DDRPHY_MD32_BASE_ADDRESS + 0x00A4) + #define SSPM_CFGREG_MBOX1_IN_IRQ_MBOX1_IN_IRQ Fld(32, 0) //[31:0] + +#define DDRPHY_MD32_REG_SSPM_CFGREG_MBOX2_IN_IRQ (DDRPHY_MD32_BASE_ADDRESS + 0x00A8) + #define SSPM_CFGREG_MBOX2_IN_IRQ_MBOX2_IN_IRQ Fld(32, 0) //[31:0] + +#define DDRPHY_MD32_REG_SSPM_CFGREG_MBOX3_IN_IRQ (DDRPHY_MD32_BASE_ADDRESS + 0x00AC) + #define SSPM_CFGREG_MBOX3_IN_IRQ_MBOX3_IN_IRQ Fld(32, 0) //[31:0] + +#define DDRPHY_MD32_REG_SSPM_CFGREG_MBOX4_IN_IRQ (DDRPHY_MD32_BASE_ADDRESS + 0x00B0) + #define SSPM_CFGREG_MBOX4_IN_IRQ_MBOX4_IN_IRQ Fld(32, 0) //[31:0] + +#define DDRPHY_MD32_REG_SSPM_CFGREG_MBOX0_OUT_IRQ (DDRPHY_MD32_BASE_ADDRESS + 0x00C0) + #define SSPM_CFGREG_MBOX0_OUT_IRQ_MBOX0_OUT_IRQ Fld(32, 0) //[31:0] + +#define DDRPHY_MD32_REG_SSPM_CFGREG_MBOX1_OUT_IRQ (DDRPHY_MD32_BASE_ADDRESS + 0x00C4) + #define SSPM_CFGREG_MBOX1_OUT_IRQ_MBOX1_OUT_IRQ Fld(32, 0) //[31:0] + +#define DDRPHY_MD32_REG_SSPM_CFGREG_MBOX2_OUT_IRQ (DDRPHY_MD32_BASE_ADDRESS + 0x00C8) + #define SSPM_CFGREG_MBOX2_OUT_IRQ_MBOX2_OUT_IRQ Fld(32, 0) //[31:0] + +#define DDRPHY_MD32_REG_SSPM_CFGREG_MBOX3_OUT_IRQ (DDRPHY_MD32_BASE_ADDRESS + 0x00CC) + #define SSPM_CFGREG_MBOX3_OUT_IRQ_MBOX3_OUT_IRQ Fld(32, 0) //[31:0] + +#define DDRPHY_MD32_REG_SSPM_CFGREG_MBOX4_OUT_IRQ (DDRPHY_MD32_BASE_ADDRESS + 0x00D0) + #define SSPM_CFGREG_MBOX4_OUT_IRQ_MBOX4_OUT_IRQ Fld(32, 0) //[31:0] + +#define DDRPHY_MD32_REG_SSPM_CFGREG_ACAO_INT_SET (DDRPHY_MD32_BASE_ADDRESS + 0x00D8) + #define SSPM_CFGREG_ACAO_INT_SET_ACAO_INT_SET Fld(17, 0) //[16:0] + #define SSPM_CFGREG_ACAO_INT_SET_RSV0 Fld(1, 17) //[17:17] + +#define DDRPHY_MD32_REG_SSPM_CFGREG_ACAO_INT_CLR (DDRPHY_MD32_BASE_ADDRESS + 0x00DC) + #define SSPM_CFGREG_ACAO_INT_CLR_ACAO_INT_CLR Fld(17, 0) //[16:0] + #define SSPM_CFGREG_ACAO_INT_CLR_RSV0 Fld(1, 17) //[17:17] + +#define DDRPHY_MD32_REG_SSPM_CFGREG_MBOX0_BASE (DDRPHY_MD32_BASE_ADDRESS + 0x00E0) + #define SSPM_CFGREG_MBOX0_BASE_MBOX0_BASE Fld(13, 0) //[12:0] + +#define DDRPHY_MD32_REG_SSPM_CFGREG_MBOX1_BASE (DDRPHY_MD32_BASE_ADDRESS + 0x00E4) + #define SSPM_CFGREG_MBOX1_BASE_MBOX1_BASE Fld(13, 0) //[12:0] + +#define DDRPHY_MD32_REG_SSPM_CFGREG_MBOX2_BASE (DDRPHY_MD32_BASE_ADDRESS + 0x00E8) + #define SSPM_CFGREG_MBOX2_BASE_MBOX2_BASE Fld(13, 0) //[12:0] + +#define DDRPHY_MD32_REG_SSPM_CFGREG_MBOX3_BASE (DDRPHY_MD32_BASE_ADDRESS + 0x00EC) + #define SSPM_CFGREG_MBOX3_BASE_MBOX3_BASE Fld(13, 0) //[12:0] + +#define DDRPHY_MD32_REG_SSPM_CFGREG_MBOX4_BASE (DDRPHY_MD32_BASE_ADDRESS + 0x00F0) + #define SSPM_CFGREG_MBOX4_BASE_MBOX4_BASE Fld(13, 0) //[12:0] + +#define DDRPHY_MD32_REG_SSPM_CFGREG_MBOX8_7B_BASE (DDRPHY_MD32_BASE_ADDRESS + 0x00F4) + #define SSPM_CFGREG_MBOX8_7B_BASE_MBOX5_7B_4 Fld(5, 0) //[4:0] + +#define DDRPHY_MD32_REG_SSPM_CFGREG_DVFS_INFO_1 (DDRPHY_MD32_BASE_ADDRESS + 0x00F8) + #define SSPM_CFGREG_DVFS_INFO_1_DVFS_INFO_1 Fld(8, 0) //[7:0] + +#define DDRPHY_MD32_REG_SSPM_CFGREG_DVFS_INFO_2 (DDRPHY_MD32_BASE_ADDRESS + 0x00FC) + #define SSPM_CFGREG_DVFS_INFO_2_DVFS_INFO_2 Fld(5, 0) //[4:0] + +#define DDRPHY_MD32_REG_SSPM_CFGREG_RSV_RW_REG0 (DDRPHY_MD32_BASE_ADDRESS + 0x0100) + #define SSPM_CFGREG_RSV_RW_REG0_GICNIRQOUT_IRQ Fld(8, 0) //[7:0] + #define SSPM_CFGREG_RSV_RW_REG0_STANDBYWFI_INQ Fld(8, 8) //[15:8] + #define SSPM_CFGREG_RSV_RW_REG0_SPM_WAKEUP_IRQ Fld(1, 16) //[16:16] + #define SSPM_CFGREG_RSV_RW_REG0_RSV0 Fld(1, 17) //[17:17] + #define SSPM_CFGREG_RSV_RW_REG0_RSV_RW_REG0 Fld(14, 18) //[31:18] + +#define DDRPHY_MD32_REG_SSPM_CFGREG_RSV_RW_REG1 (DDRPHY_MD32_BASE_ADDRESS + 0x0104) + #define SSPM_CFGREG_RSV_RW_REG1_RSV_RW_REG1 Fld(32, 0) //[31:0] + +#define DDRPHY_MD32_REG_SSPM_CFGREG_RSV_RO_REG0 (DDRPHY_MD32_BASE_ADDRESS + 0x0108) + #define SSPM_CFGREG_RSV_RO_REG0_RSV_RO_REG0 Fld(32, 0) //[31:0] + +#define DDRPHY_MD32_REG_SSPM_CFGREG_RSV_RO_REG1 (DDRPHY_MD32_BASE_ADDRESS + 0x010C) + #define SSPM_CFGREG_RSV_RO_REG1_RSV_RO_REG1 Fld(32, 0) //[31:0] + +#define DDRPHY_MD32_REG_SSPM_CFGREG_GPR6 (DDRPHY_MD32_BASE_ADDRESS + 0x0110) + #define SSPM_CFGREG_GPR6_GPR6 Fld(32, 0) //[31:0] + +#define DDRPHY_MD32_REG_SSPM_CFGREG_GPR7 (DDRPHY_MD32_BASE_ADDRESS + 0x0114) + #define SSPM_CFGREG_GPR7_GPR7 Fld(32, 0) //[31:0] + +#define DDRPHY_MD32_REG_SSPM_CFGREG_GPR8 (DDRPHY_MD32_BASE_ADDRESS + 0x0118) + #define SSPM_CFGREG_GPR8_GPR8 Fld(32, 0) //[31:0] + +#define DDRPHY_MD32_REG_SSPM_CFGREG_GPR9 (DDRPHY_MD32_BASE_ADDRESS + 0x011C) + #define SSPM_CFGREG_GPR9_GPR9 Fld(32, 0) //[31:0] + +#define DDRPHY_MD32_REG_SSPM_CFGREG_GPR10 (DDRPHY_MD32_BASE_ADDRESS + 0x0120) + #define SSPM_CFGREG_GPR10_GPR10 Fld(32, 0) //[31:0] + +#define DDRPHY_MD32_REG_SSPM_CFGREG_GPR11 (DDRPHY_MD32_BASE_ADDRESS + 0x0124) + #define SSPM_CFGREG_GPR11_GPR11 Fld(32, 0) //[31:0] + +#define DDRPHY_MD32_REG_SSPM_CFGREG_GPR12 (DDRPHY_MD32_BASE_ADDRESS + 0x0128) + #define SSPM_CFGREG_GPR12_GPR12 Fld(32, 0) //[31:0] + +#define DDRPHY_MD32_REG_SSPM_CFGREG_GPR13 (DDRPHY_MD32_BASE_ADDRESS + 0x012C) + #define SSPM_CFGREG_GPR13_GPR13 Fld(32, 0) //[31:0] + +#define DDRPHY_MD32_REG_SSPM_CFGREG_GPR14 (DDRPHY_MD32_BASE_ADDRESS + 0x0130) + #define SSPM_CFGREG_GPR14_GPR14 Fld(32, 0) //[31:0] + +#define DDRPHY_MD32_REG_SSPM_CFGREG_GPR15 (DDRPHY_MD32_BASE_ADDRESS + 0x0134) + #define SSPM_CFGREG_GPR15_GPR15 Fld(32, 0) //[31:0] + +#define DDRPHY_MD32_REG_SSPM_CFGREG_PC_DRAM_CHA (DDRPHY_MD32_BASE_ADDRESS + 0x013C) + #define SSPM_CFGREG_PC_DRAM_CHA_PC_DRAM_CHA Fld(32, 0) //[31:0] + +#define DDRPHY_MD32_REG_SSPM_CFGREG_PC_DRAM_CHB (DDRPHY_MD32_BASE_ADDRESS + 0x0140) + #define SSPM_CFGREG_PC_DRAM_CHB_PC_DRAM_CHB Fld(32, 0) //[31:0] + +#define DDRPHY_MD32_REG_SSPM_CFGREG_PC_DRAM_CHC (DDRPHY_MD32_BASE_ADDRESS + 0x0144) + #define SSPM_CFGREG_PC_DRAM_CHC_PC_DRAM_CHC Fld(32, 0) //[31:0] + +#define DDRPHY_MD32_REG_SSPM_CFGREG_PC_DRAM_CHD (DDRPHY_MD32_BASE_ADDRESS + 0x0148) + #define SSPM_CFGREG_PC_DRAM_CHD_PC_DRAM_CHD Fld(32, 0) //[31:0] + +#define DDRPHY_MD32_REG_SSPM_CFGREG_MD32_SP (DDRPHY_MD32_BASE_ADDRESS + 0x014C) + #define SSPM_CFGREG_MD32_SP_MON_SP Fld(32, 0) //[31:0] + +#define DDRPHY_MD32_REG_SSPM_CFGREG_MD32_LR (DDRPHY_MD32_BASE_ADDRESS + 0x0150) + #define SSPM_CFGREG_MD32_LR_MON_LR Fld(32, 0) //[31:0] + +#define DDRPHY_MD32_REG_SSPM_CFGREG_BUS_CTRL0 (DDRPHY_MD32_BASE_ADDRESS + 0x0168) + #define SSPM_CFGREG_BUS_CTRL0_BUS_CTRL0 Fld(32, 0) //[31:0] + +#define DDRPHY_MD32_REG_SSPM_CFGREG_BUS_CTRL1 (DDRPHY_MD32_BASE_ADDRESS + 0x016C) + #define SSPM_CFGREG_BUS_CTRL1_BUS_CTRL1 Fld(32, 0) //[31:0] + +#define DDRPHY_MD32_REG_SSPM_CFGREG_BUS_CTRL2 (DDRPHY_MD32_BASE_ADDRESS + 0x0170) + #define SSPM_CFGREG_BUS_CTRL2_BUS_CTRL2 Fld(32, 0) //[31:0] + +#define DDRPHY_MD32_REG_SSPM_CFGREG_DR_APBP2P_CTRL (DDRPHY_MD32_BASE_ADDRESS + 0x0174) + #define SSPM_CFGREG_DR_APBP2P_CTRL_R_APB_BROADCAST_EN Fld(1, 0) //[0:0] + +#define DDRPHY_MD32_REG_SSPM_CFGREG_TBUF_MON_SEL (DDRPHY_MD32_BASE_ADDRESS + 0x0178) + #define SSPM_CFGREG_TBUF_MON_SEL_TBU_MON_SEL Fld(4, 0) //[3:0] + +#define DDRPHY_MD32_REG_SSPM_CFGREG_TBUFL (DDRPHY_MD32_BASE_ADDRESS + 0x017C) + #define SSPM_CFGREG_TBUFL_TBUFL Fld(32, 0) //[31:0] + +#define DDRPHY_MD32_REG_SSPM_CFGREG_TBUFH (DDRPHY_MD32_BASE_ADDRESS + 0x0180) + #define SSPM_CFGREG_TBUFH_TBUFH Fld(32, 0) //[31:0] + +#define DDRPHY_MD32_REG_SSPM_CFGREG_MBIST_CFG (DDRPHY_MD32_BASE_ADDRESS + 0x0190) + #define SSPM_CFGREG_MBIST_CFG_DM_MD32_MBIST_CFG Fld(32, 0) //[31:0] + +#define DDRPHY_MD32_REG_SSPM_CFGREG_SRAM_DELSEL (DDRPHY_MD32_BASE_ADDRESS + 0x0194) + #define SSPM_CFGREG_SRAM_DELSEL_DM_MD32_SRAM_DELSEL_0 Fld(32, 0) //[31:0] + +#define DDRPHY_MD32_REG_SSPM_TIMER0_CON (DDRPHY_MD32_BASE_ADDRESS + 0x1000) + #define SSPM_TIMER0_CON_TIMER0_EN Fld(1, 0) //[0:0] + #define SSPM_TIMER0_CON_TIMER0_RTC Fld(2, 4) //[5:4] + +#define DDRPHY_MD32_REG_SSPM_TIMER0_RESET_VAL (DDRPHY_MD32_BASE_ADDRESS + 0x1004) + #define SSPM_TIMER0_RESET_VAL_TIMER0_RST_VAL Fld(32, 0) //[31:0] + +#define DDRPHY_MD32_REG_SSPM_TIMER0_CUR_VAL (DDRPHY_MD32_BASE_ADDRESS + 0x1008) + #define SSPM_TIMER0_CUR_VAL_TIMER0_CUR_VAL Fld(32, 0) //[31:0] + +#define DDRPHY_MD32_REG_SSPM_TIMER0_IRQ_ACK (DDRPHY_MD32_BASE_ADDRESS + 0x100C) + #define SSPM_TIMER0_IRQ_ACK_TIMER0_IRQ_EN Fld(1, 0) //[0:0] + #define SSPM_TIMER0_IRQ_ACK_TIMER0_IRQ_STATUS Fld(1, 4) //[4:4] + #define SSPM_TIMER0_IRQ_ACK_TIMER0_IRQ_CLR Fld(1, 5) //[5:5] + +#define DDRPHY_MD32_REG_SSPM_TIMER1_CON (DDRPHY_MD32_BASE_ADDRESS + 0x1010) + #define SSPM_TIMER1_CON_TIMER1_EN Fld(1, 0) //[0:0] + #define SSPM_TIMER1_CON_TIMER1_RTC Fld(2, 4) //[5:4] + +#define DDRPHY_MD32_REG_SSPM_TIMER1_RESET_VAL (DDRPHY_MD32_BASE_ADDRESS + 0x1014) + #define SSPM_TIMER1_RESET_VAL_TIMER1_RST_VAL Fld(32, 0) //[31:0] + +#define DDRPHY_MD32_REG_SSPM_TIMER1_CUR_VAL (DDRPHY_MD32_BASE_ADDRESS + 0x1018) + #define SSPM_TIMER1_CUR_VAL_TIMER1_CUR_VAL Fld(32, 0) //[31:0] + +#define DDRPHY_MD32_REG_SSPM_TIMER1_IRQ_ACK (DDRPHY_MD32_BASE_ADDRESS + 0x101C) + #define SSPM_TIMER1_IRQ_ACK_TIMER1_IRQ_EN Fld(1, 0) //[0:0] + #define SSPM_TIMER1_IRQ_ACK_TIMER1_IRQ_STATUS Fld(1, 4) //[4:4] + #define SSPM_TIMER1_IRQ_ACK_TIMER2_IRQ_CLR Fld(1, 5) //[5:5] + +#define DDRPHY_MD32_REG_SSPM_TIMER2_CON (DDRPHY_MD32_BASE_ADDRESS + 0x1020) + #define SSPM_TIMER2_CON_TIMER2_EN Fld(1, 0) //[0:0] + #define SSPM_TIMER2_CON_TIMER2_RTC Fld(2, 4) //[5:4] + +#define DDRPHY_MD32_REG_SSPM_TIMER2_RESET_VAL (DDRPHY_MD32_BASE_ADDRESS + 0x1024) + #define SSPM_TIMER2_RESET_VAL_TIMER2_RST_VAL Fld(32, 0) //[31:0] + +#define DDRPHY_MD32_REG_SSPM_TIMER2_CUR_VAL (DDRPHY_MD32_BASE_ADDRESS + 0x1028) + #define SSPM_TIMER2_CUR_VAL_TIMER2_CUR_VAL Fld(32, 0) //[31:0] + +#define DDRPHY_MD32_REG_SSPM_TIMER2_IRQ_ACK (DDRPHY_MD32_BASE_ADDRESS + 0x102C) + #define SSPM_TIMER2_IRQ_ACK_TIMER2_IRQ_EN Fld(1, 0) //[0:0] + #define SSPM_TIMER2_IRQ_ACK_TIMER2_IRQ_STATUS Fld(1, 4) //[4:4] + #define SSPM_TIMER2_IRQ_ACK_TIMER2_IRQ_CLR Fld(1, 5) //[5:5] + +#define DDRPHY_MD32_REG_SSPM_TIMER3_CON (DDRPHY_MD32_BASE_ADDRESS + 0x1030) + #define SSPM_TIMER3_CON_TIMER3_EN Fld(1, 0) //[0:0] + #define SSPM_TIMER3_CON_TIMER3_RTC Fld(2, 4) //[5:4] + +#define DDRPHY_MD32_REG_SSPM_TIMER3_RESET_VAL (DDRPHY_MD32_BASE_ADDRESS + 0x1034) + #define SSPM_TIMER3_RESET_VAL_TIMER3_RST_VAL Fld(32, 0) //[31:0] + +#define DDRPHY_MD32_REG_SSPM_TIMER3_CUR_VAL (DDRPHY_MD32_BASE_ADDRESS + 0x1038) + #define SSPM_TIMER3_CUR_VAL_TIMER3_CUR_VAL Fld(32, 0) //[31:0] + +#define DDRPHY_MD32_REG_SSPM_TIMER3_IRQ_ACK (DDRPHY_MD32_BASE_ADDRESS + 0x103C) + #define SSPM_TIMER3_IRQ_ACK_TIMER3_IRQ_EN Fld(1, 0) //[0:0] + #define SSPM_TIMER3_IRQ_ACK_TIMER3_IRQ_STATUS Fld(1, 4) //[4:4] + #define SSPM_TIMER3_IRQ_ACK_TIMER3_IRQ_CLR Fld(1, 5) //[5:5] + +#define DDRPHY_MD32_REG_SSPM_OS_TIMER_CON (DDRPHY_MD32_BASE_ADDRESS + 0x1080) + #define SSPM_OS_TIMER_CON_OS_TIMER_EN Fld(1, 0) //[0:0] + +#define DDRPHY_MD32_REG_SSPM_OS_TIMER_CNT_L (DDRPHY_MD32_BASE_ADDRESS + 0x108C) + #define SSPM_OS_TIMER_CNT_L_OS_TIMER_CNT_L Fld(32, 0) //[31:0] + +#define DDRPHY_MD32_REG_SSPM_OS_TIMER_CNT_H (DDRPHY_MD32_BASE_ADDRESS + 0x1090) + #define SSPM_OS_TIMER_CNT_H_OS_TIMER_CNT_H Fld(32, 0) //[31:0] + +#define DDRPHY_MD32_REG_SSPM_OS_TIMER_TVAL (DDRPHY_MD32_BASE_ADDRESS + 0x1094) + #define SSPM_OS_TIMER_TVAL_OS_TIMER_TVAL Fld(32, 0) //[31:0] + +#define DDRPHY_MD32_REG_SSPM_OS_TIMER_IRQ_ACK (DDRPHY_MD32_BASE_ADDRESS + 0x1098) + #define SSPM_OS_TIMER_IRQ_ACK_OS_TIMER_IRQ_EN Fld(1, 0) //[0:0] + #define SSPM_OS_TIMER_IRQ_ACK_OS_TIMER_IRQ_STATUS Fld(1, 4) //[4:4] + #define SSPM_OS_TIMER_IRQ_ACK_OS_TIMER_IRQ_CLR Fld(1, 5) //[5:5] + +#define DDRPHY_MD32_REG_SSPM_INTC_IRQ_RAW_STA0 (DDRPHY_MD32_BASE_ADDRESS + 0x2000) + #define SSPM_INTC_IRQ_RAW_STA0_IRQ_RAW_STA0 Fld(32, 0) //[31:0] + +#define DDRPHY_MD32_REG_SSPM_INTC_IRQ_RAW_STA1 (DDRPHY_MD32_BASE_ADDRESS + 0x2004) + #define SSPM_INTC_IRQ_RAW_STA1_IRQ_RAW_STA1 Fld(32, 0) //[31:0] + +#define DDRPHY_MD32_REG_SSPM_INTC_IRQ_STA0 (DDRPHY_MD32_BASE_ADDRESS + 0x2010) + #define SSPM_INTC_IRQ_STA0_IRQ_STA0 Fld(32, 0) //[31:0] + +#define DDRPHY_MD32_REG_SSPM_INTC_IRQ_STA1 (DDRPHY_MD32_BASE_ADDRESS + 0x2014) + #define SSPM_INTC_IRQ_STA1_IRQ_STA1 Fld(32, 0) //[31:0] + +#define DDRPHY_MD32_REG_SSPM_INTC_IRQ_EN0 (DDRPHY_MD32_BASE_ADDRESS + 0x2020) + #define SSPM_INTC_IRQ_EN0_IRQ_EN0 Fld(32, 0) //[31:0] + +#define DDRPHY_MD32_REG_SSPM_INTC_IRQ_EN1 (DDRPHY_MD32_BASE_ADDRESS + 0x2024) + #define SSPM_INTC_IRQ_EN1_IRQ_EN1 Fld(32, 0) //[31:0] + +#define DDRPHY_MD32_REG_SSPM_INTC_IRQ_WAKE_EN0 (DDRPHY_MD32_BASE_ADDRESS + 0x2030) + #define SSPM_INTC_IRQ_WAKE_EN0_IRQ_WAKE_EN0 Fld(32, 0) //[31:0] + +#define DDRPHY_MD32_REG_SSPM_INTC_IRQ_WAKE_EN1 (DDRPHY_MD32_BASE_ADDRESS + 0x2034) + #define SSPM_INTC_IRQ_WAKE_EN1_IRQ_WAKE_EN1 Fld(32, 0) //[31:0] + +#define DDRPHY_MD32_REG_SSPM_INTC_IRQ_POL0 (DDRPHY_MD32_BASE_ADDRESS + 0x2040) + #define SSPM_INTC_IRQ_POL0_IRQ_POL0 Fld(32, 0) //[31:0] + +#define DDRPHY_MD32_REG_SSPM_INTC_IRQ_POL1 (DDRPHY_MD32_BASE_ADDRESS + 0x2044) + #define SSPM_INTC_IRQ_POL1_IRQ_POL1 Fld(32, 0) //[31:0] + +#define DDRPHY_MD32_REG_SSPM_INTC_IRQ_GRP0_0 (DDRPHY_MD32_BASE_ADDRESS + 0x2050) + #define SSPM_INTC_IRQ_GRP0_0_IRQ_GRP0_0 Fld(32, 0) //[31:0] + +#define DDRPHY_MD32_REG_SSPM_INTC_IRQ_GRP0_1 (DDRPHY_MD32_BASE_ADDRESS + 0x2054) + #define SSPM_INTC_IRQ_GRP0_1_IRQ_GRP0_1 Fld(32, 0) //[31:0] + +#define DDRPHY_MD32_REG_SSPM_INTC_IRQ_GRP1_0 (DDRPHY_MD32_BASE_ADDRESS + 0x2060) + #define SSPM_INTC_IRQ_GRP1_0_IRQ_GRP1_0 Fld(32, 0) //[31:0] + +#define DDRPHY_MD32_REG_SSPM_INTC_IRQ_GRP1_1 (DDRPHY_MD32_BASE_ADDRESS + 0x2064) + #define SSPM_INTC_IRQ_GRP1_1_IRQ_GRP1_1 Fld(32, 0) //[31:0] + +#define DDRPHY_MD32_REG_SSPM_INTC_IRQ_GRP2_0 (DDRPHY_MD32_BASE_ADDRESS + 0x2070) + #define SSPM_INTC_IRQ_GRP2_0_IRQ_GRP2_0 Fld(32, 0) //[31:0] + +#define DDRPHY_MD32_REG_SSPM_INTC_IRQ_GRP2_1 (DDRPHY_MD32_BASE_ADDRESS + 0x2074) + #define SSPM_INTC_IRQ_GRP2_1_IRQ_GRP2_1 Fld(32, 0) //[31:0] + +#define DDRPHY_MD32_REG_SSPM_INTC_IRQ_GRP3_0 (DDRPHY_MD32_BASE_ADDRESS + 0x2080) + #define SSPM_INTC_IRQ_GRP3_0_IRQ_GRP3_0 Fld(32, 0) //[31:0] + +#define DDRPHY_MD32_REG_SSPM_INTC_IRQ_GRP3_1 (DDRPHY_MD32_BASE_ADDRESS + 0x2084) + #define SSPM_INTC_IRQ_GRP3_1_IRQ_GRP3_1 Fld(32, 0) //[31:0] + +#define DDRPHY_MD32_REG_SSPM_INTC_IRQ_GRP4_0 (DDRPHY_MD32_BASE_ADDRESS + 0x2090) + #define SSPM_INTC_IRQ_GRP4_0_IRQ_GRP4_0 Fld(32, 0) //[31:0] + +#define DDRPHY_MD32_REG_SSPM_INTC_IRQ_GRP4_1 (DDRPHY_MD32_BASE_ADDRESS + 0x2094) + #define SSPM_INTC_IRQ_GRP4_1_IRQ_GRP4_1 Fld(32, 0) //[31:0] + +#define DDRPHY_MD32_REG_SSPM_INTC_IRQ_GRP5_0 (DDRPHY_MD32_BASE_ADDRESS + 0x20A0) + #define SSPM_INTC_IRQ_GRP5_0_IRQ_GRP5_0 Fld(32, 0) //[31:0] + +#define DDRPHY_MD32_REG_SSPM_INTC_IRQ_GRP5_1 (DDRPHY_MD32_BASE_ADDRESS + 0x20A4) + #define SSPM_INTC_IRQ_GRP5_1_IRQ_GRP5_1 Fld(32, 0) //[31:0] + +#define DDRPHY_MD32_REG_SSPM_INTC_IRQ_GRP6_0 (DDRPHY_MD32_BASE_ADDRESS + 0x20B0) + #define SSPM_INTC_IRQ_GRP6_0_IRQ_GRP6_0 Fld(32, 0) //[31:0] + +#define DDRPHY_MD32_REG_SSPM_INTC_IRQ_GRP6_1 (DDRPHY_MD32_BASE_ADDRESS + 0x20B4) + #define SSPM_INTC_IRQ_GRP6_1_IRQ_GRP6_1 Fld(32, 0) //[31:0] + +#define DDRPHY_MD32_REG_SSPM_INTC_IRQ_GRP7_0 (DDRPHY_MD32_BASE_ADDRESS + 0x20C0) + #define SSPM_INTC_IRQ_GRP7_0_IRQ_GRP7_0 Fld(32, 0) //[31:0] + +#define DDRPHY_MD32_REG_SSPM_INTC_IRQ_GRP7_1 (DDRPHY_MD32_BASE_ADDRESS + 0x20C4) + #define SSPM_INTC_IRQ_GRP7_1_IRQ_GRP7_1 Fld(32, 0) //[31:0] + +#define DDRPHY_MD32_REG_SSPM_INTC_IRQ_GRP8_0 (DDRPHY_MD32_BASE_ADDRESS + 0x20D0) + #define SSPM_INTC_IRQ_GRP8_0_IRQ_GRP8_0 Fld(32, 0) //[31:0] + +#define DDRPHY_MD32_REG_SSPM_INTC_IRQ_GRP8_1 (DDRPHY_MD32_BASE_ADDRESS + 0x20D4) + #define SSPM_INTC_IRQ_GRP8_1_IRQ_GRP8_1 Fld(32, 0) //[31:0] + +#define DDRPHY_MD32_REG_SSPM_INTC_IRQ_GRP9_0 (DDRPHY_MD32_BASE_ADDRESS + 0x20E0) + #define SSPM_INTC_IRQ_GRP9_0_IRQ_GRP9_0 Fld(32, 0) //[31:0] + +#define DDRPHY_MD32_REG_SSPM_INTC_IRQ_GRP9_1 (DDRPHY_MD32_BASE_ADDRESS + 0x20E4) + #define SSPM_INTC_IRQ_GRP9_1_IRQ_GRP9_1 Fld(32, 0) //[31:0] + +#define DDRPHY_MD32_REG_SSPM_INTC_IRQ_GRP10_0 (DDRPHY_MD32_BASE_ADDRESS + 0x20F0) + #define SSPM_INTC_IRQ_GRP10_0_IRQ_GRP10_0 Fld(32, 0) //[31:0] + +#define DDRPHY_MD32_REG_SSPM_INTC_IRQ_GRP10_1 (DDRPHY_MD32_BASE_ADDRESS + 0x20F4) + #define SSPM_INTC_IRQ_GRP10_1_IRQ_GRP10_1 Fld(32, 0) //[31:0] + +#define DDRPHY_MD32_REG_SSPM_INTC_IRQ_GRP11_0 (DDRPHY_MD32_BASE_ADDRESS + 0x2100) + #define SSPM_INTC_IRQ_GRP11_0_IRQ_GRP11_0 Fld(32, 0) //[31:0] + +#define DDRPHY_MD32_REG_SSPM_INTC_IRQ_GRP11_1 (DDRPHY_MD32_BASE_ADDRESS + 0x2104) + #define SSPM_INTC_IRQ_GRP11_1_IRQ_GRP11_1 Fld(32, 0) //[31:0] + +#define DDRPHY_MD32_REG_SSPM_INTC_IRQ_GRP12_0 (DDRPHY_MD32_BASE_ADDRESS + 0x2110) + #define SSPM_INTC_IRQ_GRP12_0_IRQ_GRP12_0 Fld(32, 0) //[31:0] + +#define DDRPHY_MD32_REG_SSPM_INTC_IRQ_GRP12_1 (DDRPHY_MD32_BASE_ADDRESS + 0x2114) + #define SSPM_INTC_IRQ_GRP12_1_IRQ_GRP12_1 Fld(32, 0) //[31:0] + +#define DDRPHY_MD32_REG_SSPM_INTC_IRQ_GRP13_0 (DDRPHY_MD32_BASE_ADDRESS + 0x2120) + #define SSPM_INTC_IRQ_GRP13_0_IRQ_GRP13_0 Fld(32, 0) //[31:0] + +#define DDRPHY_MD32_REG_SSPM_INTC_IRQ_GRP13_1 (DDRPHY_MD32_BASE_ADDRESS + 0x2124) + #define SSPM_INTC_IRQ_GRP13_1_IRQ_GRP13_1 Fld(32, 0) //[31:0] + +#define DDRPHY_MD32_REG_SSPM_INTC_IRQ_GRP14_0 (DDRPHY_MD32_BASE_ADDRESS + 0x2130) + #define SSPM_INTC_IRQ_GRP14_0_IRQ_GRP14_0 Fld(32, 0) //[31:0] + +#define DDRPHY_MD32_REG_SSPM_INTC_IRQ_GRP14_1 (DDRPHY_MD32_BASE_ADDRESS + 0x2134) + #define SSPM_INTC_IRQ_GRP14_1_IRQ_GRP14_1 Fld(32, 0) //[31:0] + +#define DDRPHY_MD32_REG_SSPM_INTC_IRQ_GRP0_STA0 (DDRPHY_MD32_BASE_ADDRESS + 0x2150) + #define SSPM_INTC_IRQ_GRP0_STA0_IRQ_GRP0_STA0 Fld(32, 0) //[31:0] + +#define DDRPHY_MD32_REG_SSPM_INTC_IRQ_GRP0_STA1 (DDRPHY_MD32_BASE_ADDRESS + 0x2154) + #define SSPM_INTC_IRQ_GRP0_STA1_IRQ_GRP0_STA1 Fld(32, 0) //[31:0] + +#define DDRPHY_MD32_REG_SSPM_INTC_IRQ_GRP1_STA0 (DDRPHY_MD32_BASE_ADDRESS + 0x2160) + #define SSPM_INTC_IRQ_GRP1_STA0_IRQ_GRP1_STA0 Fld(32, 0) //[31:0] + +#define DDRPHY_MD32_REG_SSPM_INTC_IRQ_GRP1_STA1 (DDRPHY_MD32_BASE_ADDRESS + 0x2164) + #define SSPM_INTC_IRQ_GRP1_STA1_IRQ_GRP1_STA1 Fld(32, 0) //[31:0] + +#define DDRPHY_MD32_REG_SSPM_INTC_IRQ_GRP2_STA0 (DDRPHY_MD32_BASE_ADDRESS + 0x2170) + #define SSPM_INTC_IRQ_GRP2_STA0_IRQ_GRP2_STA0 Fld(32, 0) //[31:0] + +#define DDRPHY_MD32_REG_SSPM_INTC_IRQ_GRP2_STA1 (DDRPHY_MD32_BASE_ADDRESS + 0x2174) + #define SSPM_INTC_IRQ_GRP2_STA1_IRQ_GRP2_STA1 Fld(32, 0) //[31:0] + +#define DDRPHY_MD32_REG_SSPM_INTC_IRQ_GRP3_STA0 (DDRPHY_MD32_BASE_ADDRESS + 0x2180) + #define SSPM_INTC_IRQ_GRP3_STA0_IRQ_GRP3_STA0 Fld(32, 0) //[31:0] + +#define DDRPHY_MD32_REG_SSPM_INTC_IRQ_GRP3_STA1 (DDRPHY_MD32_BASE_ADDRESS + 0x2184) + #define SSPM_INTC_IRQ_GRP3_STA1_IRQ_GRP3_STA1 Fld(32, 0) //[31:0] + +#define DDRPHY_MD32_REG_SSPM_INTC_IRQ_GRP4_STA0 (DDRPHY_MD32_BASE_ADDRESS + 0x2190) + #define SSPM_INTC_IRQ_GRP4_STA0_IRQ_GRP4_STA0 Fld(32, 0) //[31:0] + +#define DDRPHY_MD32_REG_SSPM_INTC_IRQ_GRP4_STA1 (DDRPHY_MD32_BASE_ADDRESS + 0x2194) + #define SSPM_INTC_IRQ_GRP4_STA1_IRQ_GRP4_STA1 Fld(32, 0) //[31:0] + +#define DDRPHY_MD32_REG_SSPM_INTC_IRQ_GRP5_STA0 (DDRPHY_MD32_BASE_ADDRESS + 0x21A0) + #define SSPM_INTC_IRQ_GRP5_STA0_IRQ_GRP5_STA0 Fld(32, 0) //[31:0] + +#define DDRPHY_MD32_REG_SSPM_INTC_IRQ_GRP5_STA1 (DDRPHY_MD32_BASE_ADDRESS + 0x21A4) + #define SSPM_INTC_IRQ_GRP5_STA1_IRQ_GRP5_STA1 Fld(32, 0) //[31:0] + +#define DDRPHY_MD32_REG_SSPM_INTC_IRQ_GRP6_STA0 (DDRPHY_MD32_BASE_ADDRESS + 0x21B0) + #define SSPM_INTC_IRQ_GRP6_STA0_IRQ_GRP6_STA0 Fld(32, 0) //[31:0] + +#define DDRPHY_MD32_REG_SSPM_INTC_IRQ_GRP6_STA1 (DDRPHY_MD32_BASE_ADDRESS + 0x21B4) + #define SSPM_INTC_IRQ_GRP6_STA1_IRQ_GRP6_STA1 Fld(32, 0) //[31:0] + +#define DDRPHY_MD32_REG_SSPM_INTC_IRQ_GRP7_STA0 (DDRPHY_MD32_BASE_ADDRESS + 0x21C0) + #define SSPM_INTC_IRQ_GRP7_STA0_IRQ_GRP7_STA0 Fld(32, 0) //[31:0] + +#define DDRPHY_MD32_REG_SSPM_INTC_IRQ_GRP7_STA1 (DDRPHY_MD32_BASE_ADDRESS + 0x21C4) + #define SSPM_INTC_IRQ_GRP7_STA1_IRQ_GRP7_STA1 Fld(32, 0) //[31:0] + +#define DDRPHY_MD32_REG_SSPM_INTC_IRQ_GRP8_STA0 (DDRPHY_MD32_BASE_ADDRESS + 0x21D0) + #define SSPM_INTC_IRQ_GRP8_STA0_IRQ_GRP8_STA0 Fld(32, 0) //[31:0] + +#define DDRPHY_MD32_REG_SSPM_INTC_IRQ_GRP8_STA1 (DDRPHY_MD32_BASE_ADDRESS + 0x21D4) + #define SSPM_INTC_IRQ_GRP8_STA1_IRQ_GRP8_STA1 Fld(32, 0) //[31:0] + +#define DDRPHY_MD32_REG_SSPM_INTC_IRQ_GRP9_STA0 (DDRPHY_MD32_BASE_ADDRESS + 0x21E0) + #define SSPM_INTC_IRQ_GRP9_STA0_IRQ_GRP9_STA0 Fld(32, 0) //[31:0] + +#define DDRPHY_MD32_REG_SSPM_INTC_IRQ_GRP9_STA1 (DDRPHY_MD32_BASE_ADDRESS + 0x21E4) + #define SSPM_INTC_IRQ_GRP9_STA1_IRQ_GRP9_STA1 Fld(32, 0) //[31:0] + +#define DDRPHY_MD32_REG_SSPM_INTC_IRQ_GRP10_STA0 (DDRPHY_MD32_BASE_ADDRESS + 0x21F0) + #define SSPM_INTC_IRQ_GRP10_STA0_IRQ_GRP10_STA0 Fld(32, 0) //[31:0] + +#define DDRPHY_MD32_REG_SSPM_INTC_IRQ_GRP10_STA1 (DDRPHY_MD32_BASE_ADDRESS + 0x21F4) + #define SSPM_INTC_IRQ_GRP10_STA1_IRQ_GRP10_STA1 Fld(32, 0) //[31:0] + +#define DDRPHY_MD32_REG_SSPM_INTC_IRQ_GRP11_STA0 (DDRPHY_MD32_BASE_ADDRESS + 0x2200) + #define SSPM_INTC_IRQ_GRP11_STA0_IRQ_GRP11_STA0 Fld(32, 0) //[31:0] + +#define DDRPHY_MD32_REG_SSPM_INTC_IRQ_GRP11_STA1 (DDRPHY_MD32_BASE_ADDRESS + 0x2204) + #define SSPM_INTC_IRQ_GRP11_STA1_IRQ_GRP11_STA1 Fld(32, 0) //[31:0] + +#define DDRPHY_MD32_REG_SSPM_INTC_IRQ_GRP12_STA0 (DDRPHY_MD32_BASE_ADDRESS + 0x2210) + #define SSPM_INTC_IRQ_GRP12_STA0_IRQ_GRP12_STA0 Fld(32, 0) //[31:0] + +#define DDRPHY_MD32_REG_SSPM_INTC_IRQ_GRP12_STA1 (DDRPHY_MD32_BASE_ADDRESS + 0x2214) + #define SSPM_INTC_IRQ_GRP12_STA1_IRQ_GRP12_STA1 Fld(32, 0) //[31:0] + +#define DDRPHY_MD32_REG_SSPM_INTC_IRQ_GRP13_STA0 (DDRPHY_MD32_BASE_ADDRESS + 0x2220) + #define SSPM_INTC_IRQ_GRP13_STA0_IRQ_GRP13_STA0 Fld(32, 0) //[31:0] + +#define DDRPHY_MD32_REG_SSPM_INTC_IRQ_GRP13_STA1 (DDRPHY_MD32_BASE_ADDRESS + 0x2224) + #define SSPM_INTC_IRQ_GRP13_STA1_IRQ_GRP13_STA1 Fld(32, 0) //[31:0] + +#define DDRPHY_MD32_REG_SSPM_INTC_IRQ_GRP14_STA0 (DDRPHY_MD32_BASE_ADDRESS + 0x2230) + #define SSPM_INTC_IRQ_GRP14_STA0_IRQ_GRP14_STA0 Fld(32, 0) //[31:0] + +#define DDRPHY_MD32_REG_SSPM_INTC_IRQ_GRP14_STA1 (DDRPHY_MD32_BASE_ADDRESS + 0x2234) + #define SSPM_INTC_IRQ_GRP14_STA1_IRQ_GRP14_STA1 Fld(32, 0) //[31:0] + +#define DDRPHY_MD32_REG_SSPM_INTC_IRQ_GRP15_STA0 (DDRPHY_MD32_BASE_ADDRESS + 0x2240) + #define SSPM_INTC_IRQ_GRP15_STA0_IRQ_GRP15_STA0 Fld(32, 0) //[31:0] + +#define DDRPHY_MD32_REG_SSPM_INTC_IRQ_GRP15_STA1 (DDRPHY_MD32_BASE_ADDRESS + 0x2244) + #define SSPM_INTC_IRQ_GRP15_STA1_IRQ_GRP15_STA1 Fld(32, 0) //[31:0] + +#define DDRPHY_MD32_REG_SSPM_INTC_IRQ_OUT (DDRPHY_MD32_BASE_ADDRESS + 0x2250) + #define SSPM_INTC_IRQ_OUT_IRQ_OUT Fld(15, 0) //[14:0] + +#define DDRPHY_MD32_REG_SSPM_INTC_IRQ_CLR_TRG (DDRPHY_MD32_BASE_ADDRESS + 0x2254) + #define SSPM_INTC_IRQ_CLR_TRG_IRQ_CLR_TRG Fld(15, 0) //[14:0] + +#define DDRPHY_MD32_REG_SSPM_INTC_UART_RX_IRQ (DDRPHY_MD32_BASE_ADDRESS + 0x2258) + #define SSPM_INTC_UART_RX_IRQ_UART_RX_IRQ Fld(1, 0) //[0:0] + +#define DDRPHY_MD32_REG_SSPM_CK_EN (DDRPHY_MD32_BASE_ADDRESS + 0x3000) + #define SSPM_CK_EN_R_CLK_EN Fld(12, 0) //[11:0] + #define SSPM_CK_EN_R_LPIF_CLK_FR Fld(1, 12) //[12:12] + #define SSPM_CK_EN_R_DCM_MCLK_DIV Fld(2, 13) //[14:13] + #define SSPM_CK_EN_R_LPIF_CLK_26M Fld(1, 15) //[15:15] + +#define DDRPHY_MD32_REG_SSPM_MCLK_DIV (DDRPHY_MD32_BASE_ADDRESS + 0x3004) + #define SSPM_MCLK_DIV_MCLK_DIV Fld(2, 0) //[1:0] + #define SSPM_MCLK_DIV_RSV0 Fld(2, 2) //[3:2] + #define SSPM_MCLK_DIV_MCLK_SRC Fld(2, 4) //[5:4] + #define SSPM_MCLK_DIV_RSV1 Fld(2, 6) //[7:6] + #define SSPM_MCLK_DIV_MCLK_DCM_EN Fld(1, 8) //[8:8] + #define SSPM_MCLK_DIV_RSV2 Fld(7, 9) //[15:9] + #define SSPM_MCLK_DIV_DIVSW_SEL_O Fld(4, 16) //[19:16] + #define SSPM_MCLK_DIV_CKSRC_SEL_O Fld(4, 20) //[23:20] + #define SSPM_MCLK_DIV_RSV3 Fld(8, 24) //[31:24] + +#define DDRPHY_MD32_REG_SSPM_DCM_CTRL (DDRPHY_MD32_BASE_ADDRESS + 0x3008) + #define SSPM_DCM_CTRL_R_DCM_EN Fld(12, 0) //[11:0] + #define SSPM_DCM_CTRL_WAKEUP_TYPE Fld(1, 28) //[28:28] + #define SSPM_DCM_CTRL_MD32_GATED Fld(1, 30) //[30:30] + #define SSPM_DCM_CTRL_CLK_OFF Fld(1, 31) //[31:31] + +#define DDRPHY_MD32_REG_SSPM_WAKE_INT (DDRPHY_MD32_BASE_ADDRESS + 0x300C) + #define SSPM_WAKE_INT_WAKEUP_INT Fld(1, 0) //[0:0] + +#define DDRPHY_MD32_REG_SSPM_UART_CTRL (DDRPHY_MD32_BASE_ADDRESS + 0x3010) + #define SSPM_UART_CTRL_UART_BCLK_CG Fld(1, 0) //[0:0] + #define SSPM_UART_CTRL_UART_CLK_SEL Fld(2, 1) //[2:1] + #define SSPM_UART_CTRL_UART_RST_N Fld(1, 3) //[3:3] + +#define DDRPHY_MD32_REG_SSPM_DMA_GLBSTA (DDRPHY_MD32_BASE_ADDRESS + 0x4000) + #define SSPM_DMA_GLBSTA_RUN_1 Fld(1, 0) //[0:0] + #define SSPM_DMA_GLBSTA_INTSTA_1 Fld(1, 1) //[1:1] + #define SSPM_DMA_GLBSTA_RUN_2 Fld(1, 2) //[2:2] + #define SSPM_DMA_GLBSTA_INTSTA_2 Fld(1, 3) //[3:3] + #define SSPM_DMA_GLBSTA_RUN_3 Fld(1, 4) //[4:4] + #define SSPM_DMA_GLBSTA_INTSTA_3 Fld(1, 5) //[5:5] + #define SSPM_DMA_GLBSTA_RUN_4 Fld(1, 6) //[6:6] + #define SSPM_DMA_GLBSTA_INTSTA_4 Fld(1, 7) //[7:7] + +#define DDRPHY_MD32_REG_SSPM_DMA_GLBSTA2 (DDRPHY_MD32_BASE_ADDRESS + 0x4004) + #define SSPM_DMA_GLBSTA2_RUN_1 Fld(1, 0) //[0:0] + #define SSPM_DMA_GLBSTA2_INTSTA_1 Fld(1, 1) //[1:1] + #define SSPM_DMA_GLBSTA2_RUN_2 Fld(1, 2) //[2:2] + #define SSPM_DMA_GLBSTA2_INTSTA_2 Fld(1, 3) //[3:3] + #define SSPM_DMA_GLBSTA2_RUN_3 Fld(1, 4) //[4:4] + #define SSPM_DMA_GLBSTA2_INTSTA_3 Fld(1, 5) //[5:5] + #define SSPM_DMA_GLBSTA2_RUN_4 Fld(1, 6) //[6:6] + #define SSPM_DMA_GLBSTA2_INTSTA_4 Fld(1, 7) //[7:7] + +#define DDRPHY_MD32_REG_SSPM_DMA_GLBLIMITER (DDRPHY_MD32_BASE_ADDRESS + 0x4028) + #define SSPM_DMA_GLBLIMITER_GLBLIMITER Fld(4, 0) //[3:0] + +#define DDRPHY_MD32_REG_SSPM_DMA1_SRC (DDRPHY_MD32_BASE_ADDRESS + 0x4100) + #define SSPM_DMA1_SRC_SRC Fld(32, 0) //[31:0] + +#define DDRPHY_MD32_REG_SSPM_DMA1_DST (DDRPHY_MD32_BASE_ADDRESS + 0x4104) + #define SSPM_DMA1_DST_DST Fld(32, 0) //[31:0] + +#define DDRPHY_MD32_REG_SSPM_DMA1_WPPT (DDRPHY_MD32_BASE_ADDRESS + 0x4108) + #define SSPM_DMA1_WPPT_WPPT Fld(16, 0) //[15:0] + +#define DDRPHY_MD32_REG_SSPM_DMA1_WPTO (DDRPHY_MD32_BASE_ADDRESS + 0x410C) + #define SSPM_DMA1_WPTO_WPTO Fld(32, 0) //[31:0] + +#define DDRPHY_MD32_REG_SSPM_DMA1_COUNT (DDRPHY_MD32_BASE_ADDRESS + 0x4110) + #define SSPM_DMA1_COUNT_COUNT Fld(16, 0) //[15:0] + +#define DDRPHY_MD32_REG_SSPM_DMA1_CON (DDRPHY_MD32_BASE_ADDRESS + 0x4114) + #define SSPM_DMA1_CON_SIZE Fld(2, 0) //[1:0] + #define SSPM_DMA1_CON_SRC_BEN Fld(1, 2) //[2:2] + #define SSPM_DMA1_CON_DST_BEN Fld(1, 3) //[3:3] + #define SSPM_DMA1_CON_DRQ Fld(1, 4) //[4:4] + #define SSPM_DMA1_CON_BRUST_TYPE Fld(2, 8) //[9:8] + #define SSPM_DMA1_CON_INTEN Fld(1, 15) //[15:15] + #define SSPM_DMA1_CON_WPSD Fld(1, 16) //[16:16] + #define SSPM_DMA1_CON_WPEN Fld(1, 17) //[17:17] + +#define DDRPHY_MD32_REG_SSPM_DMA1_START (DDRPHY_MD32_BASE_ADDRESS + 0x4118) + #define SSPM_DMA1_START_START Fld(1, 15) //[15:15] + +#define DDRPHY_MD32_REG_SSPM_DMA1_INTSTA (DDRPHY_MD32_BASE_ADDRESS + 0x411C) + #define SSPM_DMA1_INTSTA_INTSTA Fld(1, 15) //[15:15] + +#define DDRPHY_MD32_REG_SSPM_DMA1_ACKINT (DDRPHY_MD32_BASE_ADDRESS + 0x4120) + #define SSPM_DMA1_ACKINT_ACKINT Fld(1, 15) //[15:15] + +#define DDRPHY_MD32_REG_SSPM_DMA1_RLCT (DDRPHY_MD32_BASE_ADDRESS + 0x4124) + #define SSPM_DMA1_RLCT_RLCT Fld(16, 0) //[15:0] + +#define DDRPHY_MD32_REG_SSPM_DMA1_LIMITER (DDRPHY_MD32_BASE_ADDRESS + 0x4128) + #define SSPM_DMA1_LIMITER_LIMITER Fld(8, 0) //[7:0] + +#define DDRPHY_MD32_REG_SSPM_DMA2_SRC (DDRPHY_MD32_BASE_ADDRESS + 0x4200) + #define SSPM_DMA2_SRC_SRC Fld(32, 0) //[31:0] + +#define DDRPHY_MD32_REG_SSPM_DMA2_DST (DDRPHY_MD32_BASE_ADDRESS + 0x4204) + #define SSPM_DMA2_DST_DST Fld(32, 0) //[31:0] + +#define DDRPHY_MD32_REG_SSPM_DMA2_WPPT (DDRPHY_MD32_BASE_ADDRESS + 0x4208) + #define SSPM_DMA2_WPPT_WPPT Fld(16, 0) //[15:0] + +#define DDRPHY_MD32_REG_SSPM_DMA2_WPTO (DDRPHY_MD32_BASE_ADDRESS + 0x420C) + #define SSPM_DMA2_WPTO_WPTO Fld(32, 0) //[31:0] + +#define DDRPHY_MD32_REG_SSPM_DMA2_COUNT (DDRPHY_MD32_BASE_ADDRESS + 0x4210) + #define SSPM_DMA2_COUNT_COUNT Fld(16, 0) //[15:0] + +#define DDRPHY_MD32_REG_SSPM_DMA2_CON (DDRPHY_MD32_BASE_ADDRESS + 0x4214) + #define SSPM_DMA2_CON_SIZE Fld(2, 0) //[1:0] + #define SSPM_DMA2_CON_SRC_BEN Fld(1, 2) //[2:2] + #define SSPM_DMA2_CON_DST_BEN Fld(1, 3) //[3:3] + #define SSPM_DMA2_CON_DRQ Fld(1, 4) //[4:4] + #define SSPM_DMA2_CON_BRUST_TYPE Fld(2, 8) //[9:8] + #define SSPM_DMA2_CON_INTEN Fld(1, 15) //[15:15] + #define SSPM_DMA2_CON_WPSD Fld(1, 16) //[16:16] + #define SSPM_DMA2_CON_WPEN Fld(1, 17) //[17:17] + +#define DDRPHY_MD32_REG_SSPM_DMA2_START (DDRPHY_MD32_BASE_ADDRESS + 0x4218) + #define SSPM_DMA2_START_START Fld(1, 15) //[15:15] + +#define DDRPHY_MD32_REG_SSPM_DMA2_INTSTA (DDRPHY_MD32_BASE_ADDRESS + 0x421C) + #define SSPM_DMA2_INTSTA_INTSTA Fld(1, 15) //[15:15] + +#define DDRPHY_MD32_REG_SSPM_DMA2_ACKINT (DDRPHY_MD32_BASE_ADDRESS + 0x4220) + #define SSPM_DMA2_ACKINT_ACKINT Fld(1, 15) //[15:15] + +#define DDRPHY_MD32_REG_SSPM_DMA2_RLCT (DDRPHY_MD32_BASE_ADDRESS + 0x4224) + #define SSPM_DMA2_RLCT_RLCT Fld(16, 0) //[15:0] + +#define DDRPHY_MD32_REG_SSPM_DMA2_LIMITER (DDRPHY_MD32_BASE_ADDRESS + 0x4228) + #define SSPM_DMA2_LIMITER_LIMITER Fld(8, 0) //[7:0] + +#define DDRPHY_MD32_REG_SSPM_DMA3_SRC (DDRPHY_MD32_BASE_ADDRESS + 0x4300) + #define SSPM_DMA3_SRC_SRC Fld(32, 0) //[31:0] + +#define DDRPHY_MD32_REG_SSPM_DMA3_DST (DDRPHY_MD32_BASE_ADDRESS + 0x4304) + #define SSPM_DMA3_DST_DST Fld(32, 0) //[31:0] + +#define DDRPHY_MD32_REG_SSPM_DMA3_WPPT (DDRPHY_MD32_BASE_ADDRESS + 0x4308) + #define SSPM_DMA3_WPPT_WPPT Fld(16, 0) //[15:0] + +#define DDRPHY_MD32_REG_SSPM_DMA3_WPTO (DDRPHY_MD32_BASE_ADDRESS + 0x430C) + #define SSPM_DMA3_WPTO_WPTO Fld(32, 0) //[31:0] + +#define DDRPHY_MD32_REG_SSPM_DMA3_COUNT (DDRPHY_MD32_BASE_ADDRESS + 0x4310) + #define SSPM_DMA3_COUNT_COUNT Fld(16, 0) //[15:0] + +#define DDRPHY_MD32_REG_SSPM_DMA3_CON (DDRPHY_MD32_BASE_ADDRESS + 0x4314) + #define SSPM_DMA3_CON_SIZE Fld(2, 0) //[1:0] + #define SSPM_DMA3_CON_SRC_BEN Fld(1, 2) //[2:2] + #define SSPM_DMA3_CON_DST_BEN Fld(1, 3) //[3:3] + #define SSPM_DMA3_CON_DRQ Fld(1, 4) //[4:4] + #define SSPM_DMA3_CON_BRUST_TYPE Fld(2, 8) //[9:8] + #define SSPM_DMA3_CON_INTEN Fld(1, 15) //[15:15] + #define SSPM_DMA3_CON_WPSD Fld(1, 16) //[16:16] + #define SSPM_DMA3_CON_WPEN Fld(1, 17) //[17:17] + +#define DDRPHY_MD32_REG_SSPM_DMA3_START (DDRPHY_MD32_BASE_ADDRESS + 0x4318) + #define SSPM_DMA3_START_START Fld(1, 15) //[15:15] + +#define DDRPHY_MD32_REG_SSPM_DMA3_INTSTA (DDRPHY_MD32_BASE_ADDRESS + 0x431C) + #define SSPM_DMA3_INTSTA_INTSTA Fld(1, 15) //[15:15] + +#define DDRPHY_MD32_REG_SSPM_DMA3_ACKINT (DDRPHY_MD32_BASE_ADDRESS + 0x4320) + #define SSPM_DMA3_ACKINT_ACKINT Fld(1, 15) //[15:15] + +#define DDRPHY_MD32_REG_SSPM_DMA3_RLCT (DDRPHY_MD32_BASE_ADDRESS + 0x4324) + #define SSPM_DMA3_RLCT_RLCT Fld(16, 0) //[15:0] + +#define DDRPHY_MD32_REG_SSPM_DMA3_LIMITER (DDRPHY_MD32_BASE_ADDRESS + 0x4328) + #define SSPM_DMA3_LIMITER_LIMITER Fld(8, 0) //[7:0] + +#define DDRPHY_MD32_REG_SSPM_DMA4_SRC (DDRPHY_MD32_BASE_ADDRESS + 0x4400) + #define SSPM_DMA4_SRC_SRC Fld(32, 0) //[31:0] + +#define DDRPHY_MD32_REG_SSPM_DMA4_DST (DDRPHY_MD32_BASE_ADDRESS + 0x4404) + #define SSPM_DMA4_DST_DST Fld(32, 0) //[31:0] + +#define DDRPHY_MD32_REG_SSPM_DMA4_WPPT (DDRPHY_MD32_BASE_ADDRESS + 0x4408) + #define SSPM_DMA4_WPPT_WPPT Fld(16, 0) //[15:0] + +#define DDRPHY_MD32_REG_SSPM_DMA4_WPTO (DDRPHY_MD32_BASE_ADDRESS + 0x440C) + #define SSPM_DMA4_WPTO_WPTO Fld(32, 0) //[31:0] + +#define DDRPHY_MD32_REG_SSPM_DMA4_COUNT (DDRPHY_MD32_BASE_ADDRESS + 0x4410) + #define SSPM_DMA4_COUNT_COUNT Fld(16, 0) //[15:0] + +#define DDRPHY_MD32_REG_SSPM_DMA4_CON (DDRPHY_MD32_BASE_ADDRESS + 0x4414) + #define SSPM_DMA4_CON_SIZE Fld(2, 0) //[1:0] + #define SSPM_DMA4_CON_SRC_BEN Fld(1, 2) //[2:2] + #define SSPM_DMA4_CON_DST_BEN Fld(1, 3) //[3:3] + #define SSPM_DMA4_CON_DRQ Fld(1, 4) //[4:4] + #define SSPM_DMA4_CON_BRUST_TYPE Fld(2, 8) //[9:8] + #define SSPM_DMA4_CON_INTEN Fld(1, 15) //[15:15] + #define SSPM_DMA4_CON_WPSD Fld(1, 16) //[16:16] + #define SSPM_DMA4_CON_WPEN Fld(1, 17) //[17:17] + +#define DDRPHY_MD32_REG_SSPM_DMA4_START (DDRPHY_MD32_BASE_ADDRESS + 0x4418) + #define SSPM_DMA4_START_START Fld(1, 15) //[15:15] + +#define DDRPHY_MD32_REG_SSPM_DMA4_INTSTA (DDRPHY_MD32_BASE_ADDRESS + 0x441C) + #define SSPM_DMA4_INTSTA_INTSTA Fld(1, 15) //[15:15] + +#define DDRPHY_MD32_REG_SSPM_DMA4_ACKINT (DDRPHY_MD32_BASE_ADDRESS + 0x4420) + #define SSPM_DMA4_ACKINT_ACKINT Fld(1, 15) //[15:15] + +#define DDRPHY_MD32_REG_SSPM_DMA4_RLCT (DDRPHY_MD32_BASE_ADDRESS + 0x4424) + #define SSPM_DMA4_RLCT_RLCT Fld(16, 0) //[15:0] + +#define DDRPHY_MD32_REG_SSPM_DMA4_LIMITER (DDRPHY_MD32_BASE_ADDRESS + 0x4428) + #define SSPM_DMA4_LIMITER_LIMITER Fld(8, 0) //[7:0] + +#define DDRPHY_MD32_REG_SSPM_UART_RBR_THR_DLL_ADDR (DDRPHY_MD32_BASE_ADDRESS + 0x5000) + #define SSPM_UART_RBR_THR_DLL_ADDR_RBR Fld(8, 0) //[7:0] + +#define DDRPHY_MD32_REG_SSPM_UART_IER_DLM_ADDR (DDRPHY_MD32_BASE_ADDRESS + 0x5004) + #define SSPM_UART_IER_DLM_ADDR_RHRI Fld(1, 0) //[0:0] + #define SSPM_UART_IER_DLM_ADDR_THRI Fld(1, 1) //[1:1] + #define SSPM_UART_IER_DLM_ADDR_LINT_STSI Fld(1, 2) //[2:2] + #define SSPM_UART_IER_DLM_ADDR_MODEM_STSI Fld(1, 3) //[3:3] + #define SSPM_UART_IER_DLM_ADDR_RESERVED Fld(1, 4) //[4:4] + #define SSPM_UART_IER_DLM_ADDR_XOFFI Fld(1, 5) //[5:5] + #define SSPM_UART_IER_DLM_ADDR_RTSI Fld(1, 6) //[6:6] + #define SSPM_UART_IER_DLM_ADDR_CTSI Fld(1, 7) //[7:7] + +#define DDRPHY_MD32_REG_SSPM_UART_IIR_FCR_EFR_ADDR (DDRPHY_MD32_BASE_ADDRESS + 0x5008) + #define SSPM_UART_IIR_FCR_EFR_ADDR_ID Fld(6, 0) //[5:0] + #define SSPM_UART_IIR_FCR_EFR_ADDR_FIFOE Fld(2, 6) //[7:6] + +#define DDRPHY_MD32_REG_SSPM_UART_LCR_ADDR (DDRPHY_MD32_BASE_ADDRESS + 0x500C) + #define SSPM_UART_LCR_ADDR_CHAR_LENGTH Fld(2, 0) //[1:0] + #define SSPM_UART_LCR_ADDR_STB Fld(1, 2) //[2:2] + #define SSPM_UART_LCR_ADDR_PEN Fld(1, 3) //[3:3] + #define SSPM_UART_LCR_ADDR_EPS Fld(1, 4) //[4:4] + #define SSPM_UART_LCR_ADDR_SP Fld(1, 5) //[5:5] + #define SSPM_UART_LCR_ADDR_SB Fld(1, 6) //[6:6] + #define SSPM_UART_LCR_ADDR_DLAB Fld(1, 7) //[7:7] + +#define DDRPHY_MD32_REG_SSPM_UART_MCR_XON1_ADDR (DDRPHY_MD32_BASE_ADDRESS + 0x5010) + #define SSPM_UART_MCR_XON1_ADDR_RTS Fld(1, 1) //[1:1] + #define SSPM_UART_MCR_XON1_ADDR_LOOPBACK_EN Fld(1, 4) //[4:4] + #define SSPM_UART_MCR_XON1_ADDR_XOFF_STATUS Fld(1, 7) //[7:7] + +#define DDRPHY_MD32_REG_SSPM_UART_LSR_XON2_ADDR (DDRPHY_MD32_BASE_ADDRESS + 0x5014) + #define SSPM_UART_LSR_XON2_ADDR_DR Fld(1, 0) //[0:0] + #define SSPM_UART_LSR_XON2_ADDR_OE Fld(1, 1) //[1:1] + #define SSPM_UART_LSR_XON2_ADDR_PE Fld(1, 2) //[2:2] + #define SSPM_UART_LSR_XON2_ADDR_FE Fld(1, 3) //[3:3] + #define SSPM_UART_LSR_XON2_ADDR_BI Fld(1, 4) //[4:4] + #define SSPM_UART_LSR_XON2_ADDR_THRE Fld(1, 5) //[5:5] + #define SSPM_UART_LSR_XON2_ADDR_TEMT Fld(1, 6) //[6:6] + #define SSPM_UART_LSR_XON2_ADDR_FIFOERR Fld(1, 7) //[7:7] + +#define DDRPHY_MD32_REG_SSPM_UART_MSR_XOFF1_ADDR (DDRPHY_MD32_BASE_ADDRESS + 0x5018) + #define SSPM_UART_MSR_XOFF1_ADDR_DCTS Fld(1, 0) //[0:0] + #define SSPM_UART_MSR_XOFF1_ADDR_CTS Fld(1, 4) //[4:4] + +#define DDRPHY_MD32_REG_SSPM_UART_SCR_XOFF2_ADDR (DDRPHY_MD32_BASE_ADDRESS + 0x501C) + #define SSPM_UART_SCR_XOFF2_ADDR_SCR Fld(8, 0) //[7:0] + +#define DDRPHY_MD32_REG_SSPM_UART_AUTOBAUD_EN_ADDR (DDRPHY_MD32_BASE_ADDRESS + 0x5020) + #define SSPM_UART_AUTOBAUD_EN_ADDR_AUTOBAUD_EN Fld(1, 0) //[0:0] + #define SSPM_UART_AUTOBAUD_EN_ADDR_AUTOBAUD_SEL Fld(1, 1) //[1:1] + #define SSPM_UART_AUTOBAUD_EN_ADDR_SLEEP_ACK_SEL Fld(1, 2) //[2:2] + +#define DDRPHY_MD32_REG_SSPM_UART_RATE_STEP_ADDR (DDRPHY_MD32_BASE_ADDRESS + 0x5024) + #define SSPM_UART_RATE_STEP_ADDR_SPEED Fld(2, 0) //[1:0] + +#define DDRPHY_MD32_REG_SSPM_UART_STEP_COUNT_ADDR (DDRPHY_MD32_BASE_ADDRESS + 0x5028) + #define SSPM_UART_STEP_COUNT_ADDR_SAMPLECOUNT Fld(8, 0) //[7:0] + +#define DDRPHY_MD32_REG_SSPM_UART_SAMPLE_COUNT_ADDR (DDRPHY_MD32_BASE_ADDRESS + 0x502C) + #define SSPM_UART_SAMPLE_COUNT_ADDR_SAMPLEPOINT Fld(8, 0) //[7:0] + +#define DDRPHY_MD32_REG_SSPM_UART_AUTOBAUD_DATA_ADDR (DDRPHY_MD32_BASE_ADDRESS + 0x5030) + #define SSPM_UART_AUTOBAUD_DATA_ADDR_BAUD_RATE Fld(4, 0) //[3:0] + #define SSPM_UART_AUTOBAUD_DATA_ADDR_BAUD_STAT Fld(4, 4) //[7:4] + +#define DDRPHY_MD32_REG_SSPM_UART_RATE_FIX_ADDR (DDRPHY_MD32_BASE_ADDRESS + 0x5034) + #define SSPM_UART_RATE_FIX_ADDR_RATE_FIX Fld(1, 0) //[0:0] + #define SSPM_UART_RATE_FIX_ADDR_AUTOBAUD_RATE_FIX Fld(1, 1) //[1:1] + #define SSPM_UART_RATE_FIX_ADDR_FREQ_SEL Fld(1, 2) //[2:2] + +#define DDRPHY_MD32_REG_SSPM_UART_AUTOBAUD_RATE_ADDR (DDRPHY_MD32_BASE_ADDRESS + 0x5038) + #define SSPM_UART_AUTOBAUD_RATE_ADDR_AUTOBAUDSAMPLE Fld(6, 0) //[5:0] + +#define DDRPHY_MD32_REG_SSPM_UART_GUARD_ADDR (DDRPHY_MD32_BASE_ADDRESS + 0x503C) + #define SSPM_UART_GUARD_ADDR_GUARD_CNT Fld(4, 0) //[3:0] + #define SSPM_UART_GUARD_ADDR_GUARD_EN Fld(1, 4) //[4:4] + +#define DDRPHY_MD32_REG_SSPM_UART_ESC_CHAR_ADDR (DDRPHY_MD32_BASE_ADDRESS + 0x5040) + #define SSPM_UART_ESC_CHAR_ADDR_ESC_CHAR Fld(8, 0) //[7:0] + +#define DDRPHY_MD32_REG_SSPM_UART_ESC_EN_ADDR (DDRPHY_MD32_BASE_ADDRESS + 0x5044) + #define SSPM_UART_ESC_EN_ADDR_ESC_EN Fld(1, 0) //[0:0] + +#define DDRPHY_MD32_REG_SSPM_UART_SLEEP_EN_ADDR (DDRPHY_MD32_BASE_ADDRESS + 0x5048) + #define SSPM_UART_SLEEP_EN_ADDR_SLEEP_EN Fld(1, 0) //[0:0] + +#define DDRPHY_MD32_REG_SSPM_UART_RXDMA_EN_ADDR (DDRPHY_MD32_BASE_ADDRESS + 0x504C) + #define SSPM_UART_RXDMA_EN_ADDR_RX_DMA_EN Fld(1, 0) //[0:0] + #define SSPM_UART_RXDMA_EN_ADDR_TX_DMA_EN Fld(1, 1) //[1:1] + #define SSPM_UART_RXDMA_EN_ADDR_TO_CNT_AUTORST Fld(1, 2) //[2:2] + #define SSPM_UART_RXDMA_EN_ADDR_FIFO_LSR_SEL Fld(1, 3) //[3:3] + +#define DDRPHY_MD32_REG_SSPM_UART_RXTRIG_ADDR (DDRPHY_MD32_BASE_ADDRESS + 0x5050) + #define SSPM_UART_RXTRIG_ADDR_RXTRIG Fld(4, 0) //[3:0] + +#define DDRPHY_MD32_REG_SSPM_UART_FRACDIV_L_ADDR (DDRPHY_MD32_BASE_ADDRESS + 0x5054) + #define SSPM_UART_FRACDIV_L_ADDR_FRACDIV_L Fld(8, 0) //[7:0] + +#define DDRPHY_MD32_REG_SSPM_UART_FRACDIV_M_ADDR (DDRPHY_MD32_BASE_ADDRESS + 0x5058) + #define SSPM_UART_FRACDIV_M_ADDR_FRACDIV_M Fld(2, 0) //[1:0] + +#define DDRPHY_MD32_REG_SSPM_UART_FCR_ADDR (DDRPHY_MD32_BASE_ADDRESS + 0x505C) + #define SSPM_UART_FCR_ADDR_FIFO_EN Fld(1, 0) //[0:0] + #define SSPM_UART_FCR_ADDR_RXFIFO_CLR Fld(1, 1) //[1:1] + #define SSPM_UART_FCR_ADDR_TXFIFO_CLR Fld(1, 2) //[2:2] + #define SSPM_UART_FCR_ADDR_RESERVED Fld(1, 3) //[3:3] + #define SSPM_UART_FCR_ADDR_TFTL1_TFTL0 Fld(2, 4) //[5:4] + #define SSPM_UART_FCR_ADDR_RFTL1_RFTL0 Fld(2, 6) //[7:6] + +#define DDRPHY_MD32_REG_SSPM_UART_DEBUG_ADDR (DDRPHY_MD32_BASE_ADDRESS + 0x5060) + #define SSPM_UART_DEBUG_ADDR_ACC_SEL Fld(1, 0) //[0:0] + +#define DDRPHY_MD32_REG_SSPM_UART_DEBUG_1_ADDR (DDRPHY_MD32_BASE_ADDRESS + 0x5064) + #define SSPM_UART_DEBUG_1_ADDR_TXSTATE Fld(5, 0) //[4:0] + #define SSPM_UART_DEBUG_1_ADDR_XCSTATE Fld(3, 5) //[7:5] + +#define DDRPHY_MD32_REG_SSPM_UART_DEBUG_2_ADDR (DDRPHY_MD32_BASE_ADDRESS + 0x5068) + #define SSPM_UART_DEBUG_2_ADDR_RXSTATE Fld(4, 0) //[3:0] + #define SSPM_UART_DEBUG_2_ADDR_IP_TX_DMA0 Fld(4, 4) //[7:4] + +#define DDRPHY_MD32_REG_SSPM_UART_DEBUG_3_ADDR (DDRPHY_MD32_BASE_ADDRESS + 0x506C) + #define SSPM_UART_DEBUG_3_ADDR_IP_TX_DMA1 Fld(2, 0) //[1:0] + #define SSPM_UART_DEBUG_3_ADDR_TOFFSET_TX_DMA Fld(6, 2) //[7:2] + +#define DDRPHY_MD32_REG_SSPM_UART_DEBUG_4_ADDR (DDRPHY_MD32_BASE_ADDRESS + 0x5070) + #define SSPM_UART_DEBUG_4_ADDR_TX_WOFFSET Fld(6, 0) //[5:0] + #define SSPM_UART_DEBUG_4_ADDR_TX_ROFFSET0 Fld(2, 6) //[7:6] + +#define DDRPHY_MD32_REG_SSPM_UART_DEBUG_5_ADDR (DDRPHY_MD32_BASE_ADDRESS + 0x5074) + #define SSPM_UART_DEBUG_5_ADDR_TX_ROFFSET1 Fld(4, 0) //[3:0] + #define SSPM_UART_DEBUG_5_ADDR_OP_RX_REQ0 Fld(4, 4) //[7:4] + +#define DDRPHY_MD32_REG_SSPM_UART_DEBUG_6_ADDR (DDRPHY_MD32_BASE_ADDRESS + 0x5078) + #define SSPM_UART_DEBUG_6_ADDR_OP_RX_REQ1 Fld(2, 0) //[1:0] + #define SSPM_UART_DEBUG_6_ADDR_ROFFSET_RXDMA Fld(6, 2) //[7:2] + +#define DDRPHY_MD32_REG_SSPM_UART_DEBUG_7_ADDR (DDRPHY_MD32_BASE_ADDRESS + 0x507C) + #define SSPM_UART_DEBUG_7_ADDR_RX_WOFFSET Fld(6, 0) //[5:0] + +#define DDRPHY_MD32_REG_SSPM_UART_DEBUG_8_ADDR (DDRPHY_MD32_BASE_ADDRESS + 0x5080) + #define SSPM_UART_DEBUG_8_ADDR_XON_DET Fld(1, 0) //[0:0] + #define SSPM_UART_DEBUG_8_ADDR_XOFF_DET Fld(1, 1) //[1:1] + #define SSPM_UART_DEBUG_8_ADDR_SUPPLOAD Fld(1, 2) //[2:2] + #define SSPM_UART_DEBUG_8_ADDR_SW_TX_DIS Fld(1, 3) //[3:3] + #define SSPM_UART_DEBUG_8_ADDR_HW_TX_DIS Fld(1, 4) //[4:4] + #define SSPM_UART_DEBUG_8_ADDR_SLEEPING Fld(1, 5) //[5:5] + #define SSPM_UART_DEBUG_8_ADDR_VFIFO_LIMIT Fld(1, 6) //[6:6] + #define SSPM_UART_DEBUG_8_ADDR_HWFIFO_LIMIT Fld(1, 7) //[7:7] + +#define DDRPHY_MD32_REG_SSPM_UART_DEBUG_SEL (DDRPHY_MD32_BASE_ADDRESS + 0x5084) + #define SSPM_UART_DEBUG_SEL_UART_DBG_SEL Fld(3, 0) //[2:0] + +#define DDRPHY_MD32_REG_SSPM_UART_DLL_ADDR (DDRPHY_MD32_BASE_ADDRESS + 0x5090) + #define SSPM_UART_DLL_ADDR_DLL Fld(8, 0) //[7:0] + +#define DDRPHY_MD32_REG_SSPM_UART_DLM_ADDR (DDRPHY_MD32_BASE_ADDRESS + 0x5094) + #define SSPM_UART_DLM_ADDR_DLM Fld(8, 0) //[7:0] + +#define DDRPHY_MD32_REG_SSPM_UART_EFR_ADDR (DDRPHY_MD32_BASE_ADDRESS + 0x5098) + #define SSPM_UART_EFR_ADDR_SW_FLOW_CONTROL Fld(4, 0) //[3:0] + #define SSPM_UART_EFR_ADDR_ENHANCED_EN Fld(1, 4) //[4:4] + #define SSPM_UART_EFR_ADDR_AUTO_RTS_EN Fld(1, 6) //[6:6] + #define SSPM_UART_EFR_ADDR_AUTO_CTS_EN Fld(1, 7) //[7:7] + +#define DDRPHY_MD32_REG_SSPM_UART_FEATURE_SEL (DDRPHY_MD32_BASE_ADDRESS + 0x509C) + #define SSPM_UART_FEATURE_SEL_FEATURE_SEL Fld(1, 0) //[0:0] + +#define DDRPHY_MD32_REG_SSPM_UART_XON1_ADDR (DDRPHY_MD32_BASE_ADDRESS + 0x50A0) + #define SSPM_UART_XON1_ADDR_XON1 Fld(8, 0) //[7:0] + +#define DDRPHY_MD32_REG_SSPM_UART_XON2_ADDR (DDRPHY_MD32_BASE_ADDRESS + 0x50A4) + #define SSPM_UART_XON2_ADDR_XON2 Fld(8, 0) //[7:0] + +#define DDRPHY_MD32_REG_SSPM_UART_XOFF1_ADDR (DDRPHY_MD32_BASE_ADDRESS + 0x50A8) + #define SSPM_UART_XOFF1_ADDR_XOFF1 Fld(8, 0) //[7:0] + +#define DDRPHY_MD32_REG_SSPM_UART_XOFF2_ADDR (DDRPHY_MD32_BASE_ADDRESS + 0x50AC) + #define SSPM_UART_XOFF2_ADDR_XOFF2 Fld(8, 0) //[7:0] + +#define DDRPHY_MD32_REG_SSPM_UART_UART_RX_SEL_ADDR (DDRPHY_MD32_BASE_ADDRESS + 0x50B0) + #define SSPM_UART_UART_RX_SEL_ADDR_USB_RX_SEL Fld(1, 0) //[0:0] + +#define DDRPHY_MD32_REG_SSPM_UART_SLEEP_REQ_ADDR (DDRPHY_MD32_BASE_ADDRESS + 0x50B4) + #define SSPM_UART_SLEEP_REQ_ADDR_SLEEP_REQ Fld(1, 0) //[0:0] + +#define DDRPHY_MD32_REG_SSPM_UART_SLEEP_ACK_ADDR (DDRPHY_MD32_BASE_ADDRESS + 0x50B8) + #define SSPM_UART_SLEEP_ACK_ADDR_SLEEP_ACK Fld(1, 0) //[0:0] + +#define DDRPHY_MD32_REG_SSPM_UART_SPM_SEL (DDRPHY_MD32_BASE_ADDRESS + 0x50BC) + #define SSPM_UART_SPM_SEL_SPM_SEL Fld(1, 0) //[0:0] + +#define DDRPHY_MD32_REG_SSPM_TWAM_CTRL (DDRPHY_MD32_BASE_ADDRESS + 0x6000) + #define SSPM_TWAM_CTRL_TWAM_SW_RST Fld(1, 0) //[0:0] + #define SSPM_TWAM_CTRL_TWAM_EN Fld(1, 1) //[1:1] + #define SSPM_TWAM_CTRL_SPEED_MODE_EN Fld(1, 2) //[2:2] + +#define DDRPHY_MD32_REG_SSPM_TWAM_WINDOW_LEN (DDRPHY_MD32_BASE_ADDRESS + 0x6004) + #define SSPM_TWAM_WINDOW_LEN_TWAM_WINDOW_LEN Fld(32, 0) //[31:0] + +#define DDRPHY_MD32_REG_SSPM_TWAM_MON_TYPE (DDRPHY_MD32_BASE_ADDRESS + 0x6008) + #define SSPM_TWAM_MON_TYPE_TWAM_MON_TYPE0 Fld(2, 0) //[1:0] + #define SSPM_TWAM_MON_TYPE_TWAM_MON_TYPE1 Fld(2, 2) //[3:2] + #define SSPM_TWAM_MON_TYPE_TWAM_MON_TYPE2 Fld(2, 4) //[5:4] + #define SSPM_TWAM_MON_TYPE_TWAM_MON_TYPE3 Fld(2, 6) //[7:6] + #define SSPM_TWAM_MON_TYPE_TWAM_MON_TYPE4 Fld(2, 8) //[9:8] + #define SSPM_TWAM_MON_TYPE_TWAM_MON_TYPE5 Fld(2, 10) //[11:10] + #define SSPM_TWAM_MON_TYPE_TWAM_MON_TYPE6 Fld(2, 12) //[13:12] + #define SSPM_TWAM_MON_TYPE_TWAM_MON_TYPE7 Fld(2, 14) //[15:14] + #define SSPM_TWAM_MON_TYPE_TWAM_MON_TYPE8 Fld(2, 16) //[17:16] + #define SSPM_TWAM_MON_TYPE_TWAM_MON_TYPE9 Fld(2, 18) //[19:18] + #define SSPM_TWAM_MON_TYPE_TWAM_MON_TYPE10 Fld(2, 20) //[21:20] + #define SSPM_TWAM_MON_TYPE_TWAM_MON_TYPE11 Fld(2, 22) //[23:22] + #define SSPM_TWAM_MON_TYPE_TWAM_MON_TYPE12 Fld(2, 24) //[25:24] + #define SSPM_TWAM_MON_TYPE_TWAM_MON_TYPE13 Fld(2, 26) //[27:26] + #define SSPM_TWAM_MON_TYPE_TWAM_MON_TYPE14 Fld(2, 28) //[29:28] + #define SSPM_TWAM_MON_TYPE_TWAM_MON_TYPE15 Fld(2, 30) //[31:30] + +#define DDRPHY_MD32_REG_SSPM_TWAM_SIG_SEL0 (DDRPHY_MD32_BASE_ADDRESS + 0x600C) + #define SSPM_TWAM_SIG_SEL0_TWAM_CH0_SIG_SEL Fld(5, 0) //[4:0] + #define SSPM_TWAM_SIG_SEL0_TWAM_CH1_SIG_SEL Fld(5, 5) //[9:5] + #define SSPM_TWAM_SIG_SEL0_TWAM_CH2_SIG_SEL Fld(5, 10) //[14:10] + #define SSPM_TWAM_SIG_SEL0_TWAM_CH3_SIG_SEL Fld(5, 15) //[19:15] + #define SSPM_TWAM_SIG_SEL0_TWAM_CH4_SIG_SEL Fld(5, 20) //[24:20] + #define SSPM_TWAM_SIG_SEL0_TWAM_CH5_SIG_SEL Fld(5, 25) //[29:25] + +#define DDRPHY_MD32_REG_SSPM_TWAM_SIG_SEL1 (DDRPHY_MD32_BASE_ADDRESS + 0x6010) + #define SSPM_TWAM_SIG_SEL1_TWAM_CH6_SIG_SEL Fld(5, 0) //[4:0] + #define SSPM_TWAM_SIG_SEL1_TWAM_CH7_SIG_SEL Fld(5, 5) //[9:5] + #define SSPM_TWAM_SIG_SEL1_TWAM_CH8_SIG_SEL Fld(5, 10) //[14:10] + #define SSPM_TWAM_SIG_SEL1_TWAM_CH9_SIG_SEL Fld(5, 15) //[19:15] + #define SSPM_TWAM_SIG_SEL1_TWAM_CH10_SIG_SEL Fld(5, 20) //[24:20] + #define SSPM_TWAM_SIG_SEL1_TWAM_CH11_SIG_SEL Fld(5, 25) //[29:25] + +#define DDRPHY_MD32_REG_SSPM_TWAM_SIG_SEL2 (DDRPHY_MD32_BASE_ADDRESS + 0x6014) + #define SSPM_TWAM_SIG_SEL2_TWAM_CH12_SIG_SEL Fld(5, 0) //[4:0] + #define SSPM_TWAM_SIG_SEL2_TWAM_CH13_SIG_SEL Fld(5, 5) //[9:5] + #define SSPM_TWAM_SIG_SEL2_TWAM_CH14_SIG_SEL Fld(5, 10) //[14:10] + #define SSPM_TWAM_SIG_SEL2_TWAM_CH15_SIG_SEL Fld(5, 15) //[19:15] + +#define DDRPHY_MD32_REG_SSPM_TWAM_IRQ (DDRPHY_MD32_BASE_ADDRESS + 0x6018) + #define SSPM_TWAM_IRQ_TIRQ Fld(1, 0) //[0:0] + #define SSPM_TWAM_IRQ_IRQ_CLR Fld(1, 7) //[7:7] + #define SSPM_TWAM_IRQ_IRQ_CLR_FLAG Fld(1, 8) //[8:8] + +#define DDRPHY_MD32_REG_SSPM_TWAM_TIMER (DDRPHY_MD32_BASE_ADDRESS + 0x601C) + #define SSPM_TWAM_TIMER_TWAM_TIMER Fld(32, 0) //[31:0] + +#define DDRPHY_MD32_REG_SSPM_WFI_WFE (DDRPHY_MD32_BASE_ADDRESS + 0x6020) + #define SSPM_WFI_WFE_WFI_WFE Fld(1, 0) //[0:0] + +#define DDRPHY_MD32_REG_SSPM_CUR_IDLE_CNT0 (DDRPHY_MD32_BASE_ADDRESS + 0x6030) + #define SSPM_CUR_IDLE_CNT0_CUR_IDLE_CNT0 Fld(32, 0) //[31:0] + +#define DDRPHY_MD32_REG_SSPM_CUR_IDLE_CNT1 (DDRPHY_MD32_BASE_ADDRESS + 0x6034) + #define SSPM_CUR_IDLE_CNT1_CUR_IDLE_CNT1 Fld(32, 0) //[31:0] + +#define DDRPHY_MD32_REG_SSPM_CUR_IDLE_CNT2 (DDRPHY_MD32_BASE_ADDRESS + 0x6038) + #define SSPM_CUR_IDLE_CNT2_CUR_IDLE_CNT2 Fld(32, 0) //[31:0] + +#define DDRPHY_MD32_REG_SSPM_CUR_IDLE_CNT3 (DDRPHY_MD32_BASE_ADDRESS + 0x603C) + #define SSPM_CUR_IDLE_CNT3_CUR_IDLE_CNT3 Fld(32, 0) //[31:0] + +#define DDRPHY_MD32_REG_SSPM_CUR_IDLE_CNT4 (DDRPHY_MD32_BASE_ADDRESS + 0x6040) + #define SSPM_CUR_IDLE_CNT4_CUR_IDLE_CNT4 Fld(32, 0) //[31:0] + +#define DDRPHY_MD32_REG_SSPM_CUR_IDLE_CNT5 (DDRPHY_MD32_BASE_ADDRESS + 0x6044) + #define SSPM_CUR_IDLE_CNT5_CUR_IDLE_CNT5 Fld(32, 0) //[31:0] + +#define DDRPHY_MD32_REG_SSPM_CUR_IDLE_CNT6 (DDRPHY_MD32_BASE_ADDRESS + 0x6048) + #define SSPM_CUR_IDLE_CNT6_CUR_IDLE_CNT6 Fld(32, 0) //[31:0] + +#define DDRPHY_MD32_REG_SSPM_CUR_IDLE_CNT7 (DDRPHY_MD32_BASE_ADDRESS + 0x604C) + #define SSPM_CUR_IDLE_CNT7_CUR_IDLE_CNT7 Fld(32, 0) //[31:0] + +#define DDRPHY_MD32_REG_SSPM_CUR_IDLE_CNT8 (DDRPHY_MD32_BASE_ADDRESS + 0x6050) + #define SSPM_CUR_IDLE_CNT8_CUR_IDLE_CNT8 Fld(32, 0) //[31:0] + +#define DDRPHY_MD32_REG_SSPM_CUR_IDLE_CNT9 (DDRPHY_MD32_BASE_ADDRESS + 0x6054) + #define SSPM_CUR_IDLE_CNT9_CUR_IDLE_CNT9 Fld(32, 0) //[31:0] + +#define DDRPHY_MD32_REG_SSPM_CUR_IDLE_CNT10 (DDRPHY_MD32_BASE_ADDRESS + 0x6058) + #define SSPM_CUR_IDLE_CNT10_CUR_IDLE_CNT10 Fld(32, 0) //[31:0] + +#define DDRPHY_MD32_REG_SSPM_CUR_IDLE_CNT11 (DDRPHY_MD32_BASE_ADDRESS + 0x605C) + #define SSPM_CUR_IDLE_CNT11_CUR_IDLE_CNT11 Fld(32, 0) //[31:0] + +#define DDRPHY_MD32_REG_SSPM_CUR_IDLE_CNT12 (DDRPHY_MD32_BASE_ADDRESS + 0x6060) + #define SSPM_CUR_IDLE_CNT12_CUR_IDLE_CNT12 Fld(32, 0) //[31:0] + +#define DDRPHY_MD32_REG_SSPM_CUR_IDLE_CNT13 (DDRPHY_MD32_BASE_ADDRESS + 0x6064) + #define SSPM_CUR_IDLE_CNT13_CUR_IDLE_CNT13 Fld(32, 0) //[31:0] + +#define DDRPHY_MD32_REG_SSPM_CUR_IDLE_CNT14 (DDRPHY_MD32_BASE_ADDRESS + 0x6068) + #define SSPM_CUR_IDLE_CNT14_CUR_IDLE_CNT14 Fld(32, 0) //[31:0] + +#define DDRPHY_MD32_REG_SSPM_CUR_IDLE_CNT15 (DDRPHY_MD32_BASE_ADDRESS + 0x606C) + #define SSPM_CUR_IDLE_CNT15_CUR_IDLE_CNT15 Fld(32, 0) //[31:0] + +#define DDRPHY_MD32_REG_SSPM_LAST_IDLE_CNT0 (DDRPHY_MD32_BASE_ADDRESS + 0x6080) + #define SSPM_LAST_IDLE_CNT0_LAST_IDEL_CNT0 Fld(32, 0) //[31:0] + +#define DDRPHY_MD32_REG_SSPM_LAST_IDLE_CNT1 (DDRPHY_MD32_BASE_ADDRESS + 0x6084) + #define SSPM_LAST_IDLE_CNT1_LAST_IDEL_CNT1 Fld(32, 0) //[31:0] + +#define DDRPHY_MD32_REG_SSPM_LAST_IDLE_CNT2 (DDRPHY_MD32_BASE_ADDRESS + 0x6088) + #define SSPM_LAST_IDLE_CNT2_LAST_IDEL_CNT2 Fld(32, 0) //[31:0] + +#define DDRPHY_MD32_REG_SSPM_LAST_IDLE_CNT3 (DDRPHY_MD32_BASE_ADDRESS + 0x608C) + #define SSPM_LAST_IDLE_CNT3_LAST_IDEL_CNT3 Fld(32, 0) //[31:0] + +#define DDRPHY_MD32_REG_SSPM_LAST_IDLE_CNT4 (DDRPHY_MD32_BASE_ADDRESS + 0x6090) + #define SSPM_LAST_IDLE_CNT4_LAST_IDEL_CNT4 Fld(32, 0) //[31:0] + +#define DDRPHY_MD32_REG_SSPM_LAST_IDLE_CNT5 (DDRPHY_MD32_BASE_ADDRESS + 0x6094) + #define SSPM_LAST_IDLE_CNT5_LAST_IDEL_CNT5 Fld(32, 0) //[31:0] + +#define DDRPHY_MD32_REG_SSPM_LAST_IDLE_CNT6 (DDRPHY_MD32_BASE_ADDRESS + 0x6098) + #define SSPM_LAST_IDLE_CNT6_LAST_IDEL_CNT6 Fld(32, 0) //[31:0] + +#define DDRPHY_MD32_REG_SSPM_LAST_IDLE_CNT7 (DDRPHY_MD32_BASE_ADDRESS + 0x609C) + #define SSPM_LAST_IDLE_CNT7_LAST_IDEL_CNT7 Fld(32, 0) //[31:0] + +#define DDRPHY_MD32_REG_SSPM_LAST_IDLE_CNT8 (DDRPHY_MD32_BASE_ADDRESS + 0x60A0) + #define SSPM_LAST_IDLE_CNT8_LAST_IDEL_CNT8 Fld(32, 0) //[31:0] + +#define DDRPHY_MD32_REG_SSPM_LAST_IDLE_CNT9 (DDRPHY_MD32_BASE_ADDRESS + 0x60A4) + #define SSPM_LAST_IDLE_CNT9_LAST_IDEL_CNT9 Fld(32, 0) //[31:0] + +#define DDRPHY_MD32_REG_SSPM_LAST_IDLE_CNT10 (DDRPHY_MD32_BASE_ADDRESS + 0x60A8) + #define SSPM_LAST_IDLE_CNT10_LAST_IDEL_CNT10 Fld(32, 0) //[31:0] + +#define DDRPHY_MD32_REG_SSPM_LAST_IDLE_CNT11 (DDRPHY_MD32_BASE_ADDRESS + 0x60AC) + #define SSPM_LAST_IDLE_CNT11_LAST_IDEL_CNT11 Fld(32, 0) //[31:0] + +#define DDRPHY_MD32_REG_SSPM_LAST_IDLE_CNT12 (DDRPHY_MD32_BASE_ADDRESS + 0x60B0) + #define SSPM_LAST_IDLE_CNT12_LAST_IDEL_CNT12 Fld(32, 0) //[31:0] + +#define DDRPHY_MD32_REG_SSPM_LAST_IDLE_CNT13 (DDRPHY_MD32_BASE_ADDRESS + 0x60B4) + #define SSPM_LAST_IDLE_CNT13_LAST_IDEL_CNT13 Fld(32, 0) //[31:0] + +#define DDRPHY_MD32_REG_SSPM_LAST_IDLE_CNT14 (DDRPHY_MD32_BASE_ADDRESS + 0x60B8) + #define SSPM_LAST_IDLE_CNT14_LAST_IDEL_CNT14 Fld(32, 0) //[31:0] + +#define DDRPHY_MD32_REG_SSPM_LAST_IDLE_CNT15 (DDRPHY_MD32_BASE_ADDRESS + 0x60BC) + #define SSPM_LAST_IDLE_CNT15_LAST_IDEL_CNT15 Fld(32, 0) //[31:0] + +#define DDRPHY_MD32_REG_LPIF_FSM_CFG (DDRPHY_MD32_BASE_ADDRESS + 0x7000) + #define LPIF_FSM_CFG_LPIF_FMS_SW_RSTB Fld(1, 0) //[0:0] + #define LPIF_FSM_CFG_LPIF_INTERNAL_TEST Fld(1, 1) //[1:1] + #define LPIF_FSM_CFG_LPIF_DFS_RUNTIME_MRW_EN Fld(1, 2) //[2:2] + #define LPIF_FSM_CFG_LPIF_FSM_VAL_LOAD_FROM_CFG Fld(1, 3) //[3:3] + #define LPIF_FSM_CFG_LPIF_FSM_CTRL_SINGLE_CH Fld(1, 4) //[4:4] + #define LPIF_FSM_CFG_LPIF_SPM_IN_SYNC_BYPASS Fld(1, 5) //[5:5] + #define LPIF_FSM_CFG_LPIF_FSM_CONTROL_SINGLE_CH_HYBRID_S1 Fld(1, 6) //[6:6] + #define LPIF_FSM_CFG_LPIF_PLL_CONTROL_SINGLE_CHANNEL Fld(1, 7) //[7:7] + #define LPIF_FSM_CFG_LPIF_LP_NEW_8X Fld(1, 8) //[8:8] + #define LPIF_FSM_CFG_LPIF_SHU_SRAM_BASED Fld(1, 9) //[9:9] + #define LPIF_FSM_CFG_LPIF_SHU_INDEX Fld(1, 10) //[10:10] + #define LPIF_FSM_CFG_DBG_LATENCY_CNT_EN Fld(1, 11) //[11:11] + #define LPIF_FSM_CFG_LPIF_FSM Fld(10, 12) //[21:12] + #define LPIF_FSM_CFG_SR_DEBON_EN Fld(1, 22) //[22:22] + #define LPIF_FSM_CFG_SR_MIN_PLS_DEBON_EN Fld(1, 23) //[23:23] + #define LPIF_FSM_CFG_DELAY_PST_ACK_OUTPUT_SEL Fld(4, 24) //[27:24] + #define LPIF_FSM_CFG_DELAY_PST_ABOUT_OUTPUT_SEL Fld(4, 28) //[31:28] + +#define DDRPHY_MD32_REG_LPIF_LOW_POWER_CFG_0 (DDRPHY_MD32_BASE_ADDRESS + 0x7004) + #define LPIF_LOW_POWER_CFG_0_DMSUS_OFF Fld(2, 0) //[1:0] + #define LPIF_LOW_POWER_CFG_0_PHYPLL_EN Fld(2, 2) //[3:2] + #define LPIF_LOW_POWER_CFG_0_DPY_DLL_EN Fld(2, 4) //[5:4] + #define LPIF_LOW_POWER_CFG_0_DPY_2ND_DLL_EN Fld(2, 6) //[7:6] + #define LPIF_LOW_POWER_CFG_0_DPY_DLL_CK_EN Fld(2, 8) //[9:8] + #define LPIF_LOW_POWER_CFG_0_DPY_VREF_EN Fld(2, 10) //[11:10] + #define LPIF_LOW_POWER_CFG_0_EMI_CLK_OFF_REQ Fld(2, 12) //[13:12] + #define LPIF_LOW_POWER_CFG_0_MEM_CK_OFF Fld(2, 14) //[15:14] + #define LPIF_LOW_POWER_CFG_0_DDRPHY_FB_CK_EN Fld(2, 16) //[17:16] + #define LPIF_LOW_POWER_CFG_0_DR_GATE_RETRY_EN Fld(2, 18) //[19:18] + #define LPIF_LOW_POWER_CFG_0_PHYPLL_SHU_EN Fld(2, 20) //[21:20] + #define LPIF_LOW_POWER_CFG_0_PHYPLL_MODE_SW Fld(2, 22) //[23:22] + #define LPIF_LOW_POWER_CFG_0_PHYPLL2_SHU_EN Fld(2, 24) //[25:24] + #define LPIF_LOW_POWER_CFG_0_PHYPLL2_MODE_SW Fld(2, 26) //[27:26] + #define LPIF_LOW_POWER_CFG_0_DR_SHU_EN Fld(2, 28) //[29:28] + #define LPIF_LOW_POWER_CFG_0_DR_SHORT_QUEUE Fld(2, 30) //[31:30] + +#define DDRPHY_MD32_REG_LPIF_LOW_POWER_CFG_1 (DDRPHY_MD32_BASE_ADDRESS + 0x7008) + #define LPIF_LOW_POWER_CFG_1_DR_SHU_LEVEL Fld(4, 0) //[3:0] + #define LPIF_LOW_POWER_CFG_1_DPY_BCLK_ENABLE Fld(2, 4) //[5:4] + #define LPIF_LOW_POWER_CFG_1_SHU_RESTORE Fld(2, 6) //[7:6] + #define LPIF_LOW_POWER_CFG_1_DPHY_PRECAL_UP Fld(2, 8) //[9:8] + #define LPIF_LOW_POWER_CFG_1_DPHY_RXDLY_TRACK_EN Fld(2, 10) //[11:10] + #define LPIF_LOW_POWER_CFG_1_DMY_EN_MOD_SEL Fld(2, 12) //[13:12] + #define LPIF_LOW_POWER_CFG_1_DMYRD_INTV_SEL Fld(2, 14) //[15:14] + #define LPIF_LOW_POWER_CFG_1_DMYRD_EN Fld(2, 16) //[17:16] + #define LPIF_LOW_POWER_CFG_1_TX_TRACKING_DIS Fld(2, 18) //[19:18] + #define LPIF_LOW_POWER_CFG_1_TX_TRACKING_RETRY_EN Fld(2, 20) //[21:20] + #define LPIF_LOW_POWER_CFG_1_DR_SHU_SRAM_LEVEL Fld(8, 22) //[29:22] + #define LPIF_LOW_POWER_CFG_1_DR_SRAM_LOAD Fld(2, 30) //[31:30] + +#define DDRPHY_MD32_REG_LPIF_LOW_POWER_CFG_2 (DDRPHY_MD32_BASE_ADDRESS + 0x700C) + #define LPIF_LOW_POWER_CFG_2_DR_SRAM_RESTORE Fld(2, 0) //[1:0] + #define LPIF_LOW_POWER_CFG_2_DR_SHU_LEVEL_SRAM_LATCH Fld(2, 2) //[3:2] + #define LPIF_LOW_POWER_CFG_2_DPY_MODE_SW Fld(2, 4) //[5:4] + #define LPIF_LOW_POWER_CFG_2_EMI_SLEEP_PROT_EN Fld(1, 6) //[6:6] + #define LPIF_LOW_POWER_CFG_2_MPLLOUT_OFF Fld(1, 7) //[7:7] + #define LPIF_LOW_POWER_CFG_2_DPY_RESERVED Fld(8, 8) //[15:8] + #define LPIF_LOW_POWER_CFG_2_DRAMC_DFS_STA Fld(13, 16) //[28:16] + #define LPIF_LOW_POWER_CFG_2_MPLL_S_OFF Fld(1, 29) //[29:29] + #define LPIF_LOW_POWER_CFG_2_FHC_PAUSE_MPLL Fld(1, 30) //[30:30] + #define LPIF_LOW_POWER_CFG_2_FHC_PAUSE_MEM Fld(1, 31) //[31:31] + +#define DDRPHY_MD32_REG_LPIF_FSM_OUT_CTRL_0 (DDRPHY_MD32_BASE_ADDRESS + 0x7010) + #define LPIF_FSM_OUT_CTRL_0_LOG_OPT_DMSUS_OFF Fld(1, 0) //[0:0] + #define LPIF_FSM_OUT_CTRL_0_LOG_OPT_PHYPLL_EN Fld(1, 1) //[1:1] + #define LPIF_FSM_OUT_CTRL_0_LOG_OPT_DPY_DLL_EN Fld(1, 2) //[2:2] + #define LPIF_FSM_OUT_CTRL_0_LOG_OPT_DPY_2ND_DLL_EN Fld(1, 3) //[3:3] + #define LPIF_FSM_OUT_CTRL_0_LOG_OPT_DPY_DLL_CK_EN Fld(1, 4) //[4:4] + #define LPIF_FSM_OUT_CTRL_0_LOG_OPT_DPY_VREF_EN Fld(1, 5) //[5:5] + #define LPIF_FSM_OUT_CTRL_0_LOG_OPT_EMI_CLK_OFF_REQ Fld(1, 6) //[6:6] + #define LPIF_FSM_OUT_CTRL_0_LOG_OPT_MEM_CK_OFF Fld(1, 7) //[7:7] + #define LPIF_FSM_OUT_CTRL_0_LOG_OPT_DDRPHY_FB_CK_EN Fld(1, 8) //[8:8] + #define LPIF_FSM_OUT_CTRL_0_LOG_OPT_DR_GATE_RETRY_EN Fld(1, 9) //[9:9] + #define LPIF_FSM_OUT_CTRL_0_LOG_OPT_PHYPLL_SHU_EN Fld(1, 10) //[10:10] + #define LPIF_FSM_OUT_CTRL_0_LOG_OPT_PHYPLL_MODE_SW Fld(1, 11) //[11:11] + #define LPIF_FSM_OUT_CTRL_0_LOG_OPT_PHYPLL2_SHU_EN Fld(1, 12) //[12:12] + #define LPIF_FSM_OUT_CTRL_0_LOG_OPT_PHYPLL2_MODE_SW Fld(1, 13) //[13:13] + #define LPIF_FSM_OUT_CTRL_0_LOG_OPT_DR_SHU_EN Fld(1, 14) //[14:14] + #define LPIF_FSM_OUT_CTRL_0_LOG_OPT_DR_SHORT_QUEUE Fld(1, 15) //[15:15] + #define LPIF_FSM_OUT_CTRL_0_LOG_OPT_DR_SHU_LEVEL Fld(1, 16) //[16:16] + #define LPIF_FSM_OUT_CTRL_0_LOG_OPT_DPY_BCLK_ENABLE Fld(1, 17) //[17:17] + #define LPIF_FSM_OUT_CTRL_0_LOG_OPT_SHU_RESTORE Fld(1, 18) //[18:18] + #define LPIF_FSM_OUT_CTRL_0_LOG_OPT_DPHY_PRECAL_UP Fld(1, 19) //[19:19] + #define LPIF_FSM_OUT_CTRL_0_LOG_OPT_DPHY_RXDLY_TRACK_EN Fld(1, 20) //[20:20] + #define LPIF_FSM_OUT_CTRL_0_LOG_OPT_DMY_EN_MOD_SEL Fld(1, 21) //[21:21] + #define LPIF_FSM_OUT_CTRL_0_LOG_OPT_DMYRD_INTV_SEL Fld(1, 22) //[22:22] + #define LPIF_FSM_OUT_CTRL_0_LOG_OPT_DMYRD_EN Fld(1, 23) //[23:23] + #define LPIF_FSM_OUT_CTRL_0_LOG_OPT_TX_TRACKING_DIS Fld(1, 24) //[24:24] + #define LPIF_FSM_OUT_CTRL_0_LOG_OPT_TX_TRACKING_RETRY_EN Fld(1, 25) //[25:25] + #define LPIF_FSM_OUT_CTRL_0_LOG_OPT_DR_SHU_SRAM_LEVEL Fld(1, 26) //[26:26] + #define LPIF_FSM_OUT_CTRL_0_LOG_OPT_DR_SRAM_LOAD Fld(1, 27) //[27:27] + #define LPIF_FSM_OUT_CTRL_0_LOG_OPT_DR_SRAM_RESTORE Fld(1, 28) //[28:28] + #define LPIF_FSM_OUT_CTRL_0_LOG_OPT_DR_SHU_LEVEL_SRAM_LATCH Fld(1, 29) //[29:29] + #define LPIF_FSM_OUT_CTRL_0_LOG_OPT_DPY_RESERVED Fld(1, 30) //[30:30] + #define LPIF_FSM_OUT_CTRL_0_LOG_OPT_DRAMC_DFS_STA Fld(1, 31) //[31:31] + +#define DDRPHY_MD32_REG_LPIF_FSM_OUT_CTRL_1 (DDRPHY_MD32_BASE_ADDRESS + 0x7014) + #define LPIF_FSM_OUT_CTRL_1_LOG_OPT_DPY_MODE_SW Fld(1, 0) //[0:0] + #define LPIF_FSM_OUT_CTRL_1_LOG_OPT_MPLL_S_OFF Fld(1, 1) //[1:1] + #define LPIF_FSM_OUT_CTRL_1_LOG_OPT_FHC_PAUSE_MPLL Fld(1, 2) //[2:2] + #define LPIF_FSM_OUT_CTRL_1_LOG_OPT_FHC_PAUSE_MEM Fld(1, 3) //[3:3] + #define LPIF_FSM_OUT_CTRL_1_LOG_OPT_DPY_MCK8X_EN Fld(1, 4) //[4:4] + #define LPIF_FSM_OUT_CTRL_1_LOG_OPT_DPY_MIDPI_EN Fld(1, 5) //[5:5] + #define LPIF_FSM_OUT_CTRL_1_LOG_OPT_DPY_PI_RESETB_EN Fld(1, 6) //[6:6] + #define LPIF_FSM_OUT_CTRL_1_LOG_OPT_DVFS_MEM_CK_MUX_UPDATE Fld(1, 7) //[7:7] + #define LPIF_FSM_OUT_CTRL_1_LOG_OPT_DVFS_MEM_CK_MUX_SEL Fld(1, 8) //[8:8] + #define LPIF_FSM_OUT_CTRL_1_LOG_OPT_DPY_DSM_EN Fld(1, 9) //[9:9] + #define LPIF_FSM_OUT_CTRL_1_LOG_OPT_DPY_PICG_FREE Fld(1, 10) //[10:10] + #define LPIF_FSM_OUT_CTRL_1_LOG_OPT_DPY_FASTK_RDDQS_EN Fld(1, 11) //[11:11] + #define LPIF_FSM_OUT_CTRL_1_LOG_OPT_DPY_CS_PULL_UP_EN Fld(1, 12) //[12:12] + #define LPIF_FSM_OUT_CTRL_1_LOG_OPT_DPY_CS_PULL_DN_EN Fld(1, 13) //[13:13] + #define LPIF_FSM_OUT_CTRL_1_LOG_OPT_DPY_CA_PULL_UP_EN Fld(1, 14) //[14:14] + #define LPIF_FSM_OUT_CTRL_1_LOG_OPT_DPY_CA_PULL_DN_EN Fld(1, 15) //[15:15] + #define LPIF_FSM_OUT_CTRL_1_LOG_OPT_MPLLOUT_OFF Fld(1, 16) //[16:16] + #define LPIF_FSM_OUT_CTRL_1_LOG_OPT_EMI_S1_MODE_ASYNC Fld(1, 17) //[17:17] + #define LPIF_FSM_OUT_CTRL_1_RESERVED_X14_31_16 Fld(14, 18) //[31:18] + +#define DDRPHY_MD32_REG_LPIF_IPC_MASK_0 (DDRPHY_MD32_BASE_ADDRESS + 0x7018) + #define LPIF_IPC_MASK_0_PWR_STATE_IPC_MASK_0 Fld(1, 0) //[0:0] + #define LPIF_IPC_MASK_0_PWR_STATE_IPC_MASK_01 Fld(1, 1) //[1:1] + #define LPIF_IPC_MASK_0_PWR_STATE_IPC_MASK_02 Fld(1, 2) //[2:2] + #define LPIF_IPC_MASK_0_PWR_STATE_IPC_MASK_03 Fld(1, 3) //[3:3] + #define LPIF_IPC_MASK_0_PWR_STATE_IPC_MASK_04 Fld(1, 4) //[4:4] + #define LPIF_IPC_MASK_0_PWR_STATE_IPC_MASK_05 Fld(1, 5) //[5:5] + #define LPIF_IPC_MASK_0_PWR_STATE_IPC_MASK_06 Fld(1, 6) //[6:6] + #define LPIF_IPC_MASK_0_PWR_STATE_IPC_MASK_07 Fld(1, 7) //[7:7] + #define LPIF_IPC_MASK_0_PWR_STATE_IPC_MASK_08 Fld(1, 8) //[8:8] + #define LPIF_IPC_MASK_0_PWR_STATE_IPC_MASK_09 Fld(1, 9) //[9:9] + #define LPIF_IPC_MASK_0_PWR_STATE_IPC_MASK_0A Fld(1, 10) //[10:10] + #define LPIF_IPC_MASK_0_PWR_STATE_IPC_MASK_0B Fld(1, 11) //[11:11] + #define LPIF_IPC_MASK_0_PWR_STATE_IPC_MASK_0C Fld(1, 12) //[12:12] + #define LPIF_IPC_MASK_0_PWR_STATE_IPC_MASK_0D Fld(1, 13) //[13:13] + #define LPIF_IPC_MASK_0_PWR_STATE_IPC_MASK_0E Fld(1, 14) //[14:14] + #define LPIF_IPC_MASK_0_PWR_STATE_IPC_MASK_0F Fld(1, 15) //[15:15] + #define LPIF_IPC_MASK_0_PWR_STATE_IPC_MASK_10 Fld(1, 16) //[16:16] + #define LPIF_IPC_MASK_0_PWR_STATE_IPC_MASK_11 Fld(1, 17) //[17:17] + #define LPIF_IPC_MASK_0_PWR_STATE_IPC_MASK_12 Fld(1, 18) //[18:18] + #define LPIF_IPC_MASK_0_PWR_STATE_IPC_MASK_13 Fld(1, 19) //[19:19] + #define LPIF_IPC_MASK_0_PWR_STATE_IPC_MASK_14 Fld(1, 20) //[20:20] + #define LPIF_IPC_MASK_0_PWR_STATE_IPC_MASK_15 Fld(1, 21) //[21:21] + #define LPIF_IPC_MASK_0_PWR_STATE_IPC_MASK_16 Fld(1, 22) //[22:22] + #define LPIF_IPC_MASK_0_PWR_STATE_IPC_MASK_17 Fld(1, 23) //[23:23] + #define LPIF_IPC_MASK_0_PWR_STATE_IPC_MASK_18 Fld(1, 24) //[24:24] + #define LPIF_IPC_MASK_0_PWR_STATE_IPC_MASK_19 Fld(1, 25) //[25:25] + #define LPIF_IPC_MASK_0_PWR_STATE_IPC_MASK_1A Fld(1, 26) //[26:26] + #define LPIF_IPC_MASK_0_PWR_STATE_IPC_MASK_1B Fld(1, 27) //[27:27] + #define LPIF_IPC_MASK_0_PWR_STATE_IPC_MASK_1C Fld(1, 28) //[28:28] + #define LPIF_IPC_MASK_0_PWR_STATE_IPC_MASK_1D Fld(1, 29) //[29:29] + #define LPIF_IPC_MASK_0_PWR_STATE_IPC_MASK_1E Fld(1, 30) //[30:30] + #define LPIF_IPC_MASK_0_PWR_STATE_IPC_MASK_1F Fld(1, 31) //[31:31] + +#define DDRPHY_MD32_REG_LPIF_IPC_MASK_1 (DDRPHY_MD32_BASE_ADDRESS + 0x701C) + #define LPIF_IPC_MASK_1_PWR_STATE_IPC_MASK_RESERVED Fld(32, 0) //[31:0] + +#define DDRPHY_MD32_REG_LPIF_FSM_CTRL_0 (DDRPHY_MD32_BASE_ADDRESS + 0x7020) + #define LPIF_FSM_CTRL_0_LPIF_SW_DDR_PST_ABORT_ACK Fld(1, 0) //[0:0] + #define LPIF_FSM_CTRL_0_LPIF_SW_DDR_PST_ACK Fld(1, 1) //[1:1] + #define LPIF_FSM_CTRL_0_RELEASE_LPIF_IRQ Fld(1, 2) //[2:2] + #define LPIF_FSM_CTRL_0_RELEASE_DDR_PST_ACK Fld(1, 3) //[3:3] + #define LPIF_FSM_CTRL_0_DFS_STATUS_RECORD Fld(4, 4) //[7:4] + #define LPIF_FSM_CTRL_0_DVS_STATUS_RECORD Fld(1, 8) //[8:8] + #define LPIF_FSM_CTRL_0_RUN_TIME_STATUS_RECORD Fld(1, 9) //[9:9] + #define LPIF_FSM_CTRL_0_RESERVED_X20_11_10 Fld(2, 10) //[11:10] + #define LPIF_FSM_CTRL_0_DFS_STATUS_RECORD_UPDATE Fld(1, 12) //[12:12] + #define LPIF_FSM_CTRL_0_DVS_STATUS_RECORD_UPDATE Fld(1, 13) //[13:13] + #define LPIF_FSM_CTRL_0_RUN_TIME_STATUS_RECORD_UPDATE Fld(1, 14) //[14:14] + #define LPIF_FSM_CTRL_0_RESERVED_X20_15_15 Fld(1, 15) //[15:15] + #define LPIF_FSM_CTRL_0_JUMP_TO_SIDLE Fld(1, 16) //[16:16] + #define LPIF_FSM_CTRL_0_JUMP_TO_SR Fld(1, 17) //[17:17] + #define LPIF_FSM_CTRL_0_JUMP_TO_S1 Fld(1, 18) //[18:18] + #define LPIF_FSM_CTRL_0_JUMP_TO_S0 Fld(1, 19) //[19:19] + #define LPIF_FSM_CTRL_0_JUMP_TO_HYBRID_S1 Fld(1, 20) //[20:20] + #define LPIF_FSM_CTRL_0_JUMP_TO_DFS Fld(1, 21) //[21:21] + #define LPIF_FSM_CTRL_0_JUMP_TO_DVS_ENTR Fld(1, 22) //[22:22] + #define LPIF_FSM_CTRL_0_JUMP_TO_DVS_EXIT Fld(1, 23) //[23:23] + #define LPIF_FSM_CTRL_0_JUMP_TO_EN_RUNTIME Fld(1, 24) //[24:24] + #define LPIF_FSM_CTRL_0_JUMP_TO_DIS_RUNTIME Fld(1, 25) //[25:25] + #define LPIF_FSM_CTRL_0_DRAMC_S0_STATUS Fld(2, 26) //[27:26] + #define LPIF_FSM_CTRL_0_RESERVED_X20_31_28 Fld(4, 28) //[31:28] + +#define DDRPHY_MD32_REG_LPIF_FSM_CTRL_1 (DDRPHY_MD32_BASE_ADDRESS + 0x7024) + #define LPIF_FSM_CTRL_1_RXDLY_TRACK_EN_0 Fld(1, 0) //[0:0] + #define LPIF_FSM_CTRL_1_RXDLY_TRACK_EN_1 Fld(1, 1) //[1:1] + #define LPIF_FSM_CTRL_1_RXDLY_TRACK_EN_2 Fld(1, 2) //[2:2] + #define LPIF_FSM_CTRL_1_RXDLY_TRACK_EN_3 Fld(1, 3) //[3:3] + #define LPIF_FSM_CTRL_1_RXDLY_TRACK_EN_4 Fld(1, 4) //[4:4] + #define LPIF_FSM_CTRL_1_RXDLY_TRACK_EN_5 Fld(1, 5) //[5:5] + #define LPIF_FSM_CTRL_1_RXDLY_TRACK_EN_6 Fld(1, 6) //[6:6] + #define LPIF_FSM_CTRL_1_RXDLY_TRACK_EN_7 Fld(1, 7) //[7:7] + #define LPIF_FSM_CTRL_1_RXDLY_TRACK_EN_8 Fld(1, 8) //[8:8] + #define LPIF_FSM_CTRL_1_RXDLY_TRACK_EN_9 Fld(1, 9) //[9:9] + #define LPIF_FSM_CTRL_1_RXDLY_TRACK_EN_10 Fld(1, 10) //[10:10] + #define LPIF_FSM_CTRL_1_RXDLY_TRACK_EN_11 Fld(1, 11) //[11:11] + #define LPIF_FSM_CTRL_1_RXDLY_TRACK_EN_12 Fld(1, 12) //[12:12] + #define LPIF_FSM_CTRL_1_RXDLY_TRACK_EN_13 Fld(1, 13) //[13:13] + #define LPIF_FSM_CTRL_1_RXDLY_TRACK_EN_14 Fld(1, 14) //[14:14] + #define LPIF_FSM_CTRL_1_RXDLY_TRACK_EN_15 Fld(1, 15) //[15:15] + #define LPIF_FSM_CTRL_1_DMYRD_EN_0 Fld(1, 16) //[16:16] + #define LPIF_FSM_CTRL_1_DMYRD_EN_1 Fld(1, 17) //[17:17] + #define LPIF_FSM_CTRL_1_DMYRD_EN_2 Fld(1, 18) //[18:18] + #define LPIF_FSM_CTRL_1_DMYRD_EN_3 Fld(1, 19) //[19:19] + #define LPIF_FSM_CTRL_1_DMYRD_EN_4 Fld(1, 20) //[20:20] + #define LPIF_FSM_CTRL_1_DMYRD_EN_5 Fld(1, 21) //[21:21] + #define LPIF_FSM_CTRL_1_DMYRD_EN_6 Fld(1, 22) //[22:22] + #define LPIF_FSM_CTRL_1_DMYRD_EN_7 Fld(1, 23) //[23:23] + #define LPIF_FSM_CTRL_1_DMYRD_EN_8 Fld(1, 24) //[24:24] + #define LPIF_FSM_CTRL_1_DMYRD_EN_9 Fld(1, 25) //[25:25] + #define LPIF_FSM_CTRL_1_DMYRD_EN_10 Fld(1, 26) //[26:26] + #define LPIF_FSM_CTRL_1_DMYRD_EN_11 Fld(1, 27) //[27:27] + #define LPIF_FSM_CTRL_1_DMYRD_EN_12 Fld(1, 28) //[28:28] + #define LPIF_FSM_CTRL_1_DMYRD_EN_13 Fld(1, 29) //[29:29] + #define LPIF_FSM_CTRL_1_DMYRD_EN_14 Fld(1, 30) //[30:30] + #define LPIF_FSM_CTRL_1_DMYRD_EN_15 Fld(1, 31) //[31:31] + +#define DDRPHY_MD32_REG_LPIF_FSM_CTRL_2 (DDRPHY_MD32_BASE_ADDRESS + 0x7028) + #define LPIF_FSM_CTRL_2_TX_TRACKING_DIS_0 Fld(1, 0) //[0:0] + #define LPIF_FSM_CTRL_2_TX_TRACKING_DIS_1 Fld(1, 1) //[1:1] + #define LPIF_FSM_CTRL_2_TX_TRACKING_DIS_2 Fld(1, 2) //[2:2] + #define LPIF_FSM_CTRL_2_TX_TRACKING_DIS_3 Fld(1, 3) //[3:3] + #define LPIF_FSM_CTRL_2_TX_TRACKING_DIS_4 Fld(1, 4) //[4:4] + #define LPIF_FSM_CTRL_2_TX_TRACKING_DIS_5 Fld(1, 5) //[5:5] + #define LPIF_FSM_CTRL_2_TX_TRACKING_DIS_6 Fld(1, 6) //[6:6] + #define LPIF_FSM_CTRL_2_TX_TRACKING_DIS_7 Fld(1, 7) //[7:7] + #define LPIF_FSM_CTRL_2_TX_TRACKING_DIS_8 Fld(1, 8) //[8:8] + #define LPIF_FSM_CTRL_2_TX_TRACKING_DIS_9 Fld(1, 9) //[9:9] + #define LPIF_FSM_CTRL_2_TX_TRACKING_DIS_10 Fld(1, 10) //[10:10] + #define LPIF_FSM_CTRL_2_TX_TRACKING_DIS_11 Fld(1, 11) //[11:11] + #define LPIF_FSM_CTRL_2_TX_TRACKING_DIS_12 Fld(1, 12) //[12:12] + #define LPIF_FSM_CTRL_2_TX_TRACKING_DIS_13 Fld(1, 13) //[13:13] + #define LPIF_FSM_CTRL_2_TX_TRACKING_DIS_14 Fld(1, 14) //[14:14] + #define LPIF_FSM_CTRL_2_TX_TRACKING_DIS_15 Fld(1, 15) //[15:15] + #define LPIF_FSM_CTRL_2_DR_SRAM_RESTORE_0 Fld(1, 16) //[16:16] + #define LPIF_FSM_CTRL_2_DR_SRAM_RESTORE_1 Fld(1, 17) //[17:17] + #define LPIF_FSM_CTRL_2_DR_SRAM_RESTORE_2 Fld(1, 18) //[18:18] + #define LPIF_FSM_CTRL_2_DR_SRAM_RESTORE_3 Fld(1, 19) //[19:19] + #define LPIF_FSM_CTRL_2_DR_SRAM_RESTORE_4 Fld(1, 20) //[20:20] + #define LPIF_FSM_CTRL_2_DR_SRAM_RESTORE_5 Fld(1, 21) //[21:21] + #define LPIF_FSM_CTRL_2_DR_SRAM_RESTORE_6 Fld(1, 22) //[22:22] + #define LPIF_FSM_CTRL_2_DR_SRAM_RESTORE_7 Fld(1, 23) //[23:23] + #define LPIF_FSM_CTRL_2_DR_SRAM_RESTORE_8 Fld(1, 24) //[24:24] + #define LPIF_FSM_CTRL_2_DR_SRAM_RESTORE_9 Fld(1, 25) //[25:25] + #define LPIF_FSM_CTRL_2_DR_SRAM_RESTORE_10 Fld(1, 26) //[26:26] + #define LPIF_FSM_CTRL_2_DR_SRAM_RESTORE_11 Fld(1, 27) //[27:27] + #define LPIF_FSM_CTRL_2_DR_SRAM_RESTORE_12 Fld(1, 28) //[28:28] + #define LPIF_FSM_CTRL_2_DR_SRAM_RESTORE_13 Fld(1, 29) //[29:29] + #define LPIF_FSM_CTRL_2_DR_SRAM_RESTORE_14 Fld(1, 30) //[30:30] + #define LPIF_FSM_CTRL_2_DR_SRAM_RESTORE_15 Fld(1, 31) //[31:31] + +#define DDRPHY_MD32_REG_LPIF_FSM_CTRL_3 (DDRPHY_MD32_BASE_ADDRESS + 0x702C) + #define LPIF_FSM_CTRL_3_TX_TRACK_RETRY_EN_0 Fld(1, 0) //[0:0] + #define LPIF_FSM_CTRL_3_TX_TRACK_RETRY_EN_1 Fld(1, 1) //[1:1] + #define LPIF_FSM_CTRL_3_TX_TRACK_RETRY_EN_2 Fld(1, 2) //[2:2] + #define LPIF_FSM_CTRL_3_TX_TRACK_RETRY_EN_3 Fld(1, 3) //[3:3] + #define LPIF_FSM_CTRL_3_TX_TRACK_RETRY_EN_4 Fld(1, 4) //[4:4] + #define LPIF_FSM_CTRL_3_TX_TRACK_RETRY_EN_5 Fld(1, 5) //[5:5] + #define LPIF_FSM_CTRL_3_TX_TRACK_RETRY_EN_6 Fld(1, 6) //[6:6] + #define LPIF_FSM_CTRL_3_TX_TRACK_RETRY_EN_7 Fld(1, 7) //[7:7] + #define LPIF_FSM_CTRL_3_TX_TRACK_RETRY_EN_8 Fld(1, 8) //[8:8] + #define LPIF_FSM_CTRL_3_TX_TRACK_RETRY_EN_9 Fld(1, 9) //[9:9] + #define LPIF_FSM_CTRL_3_TX_TRACK_RETRY_EN_10 Fld(1, 10) //[10:10] + #define LPIF_FSM_CTRL_3_TX_TRACK_RETRY_EN_11 Fld(1, 11) //[11:11] + #define LPIF_FSM_CTRL_3_TX_TRACK_RETRY_EN_12 Fld(1, 12) //[12:12] + #define LPIF_FSM_CTRL_3_TX_TRACK_RETRY_EN_13 Fld(1, 13) //[13:13] + #define LPIF_FSM_CTRL_3_TX_TRACK_RETRY_EN_14 Fld(1, 14) //[14:14] + #define LPIF_FSM_CTRL_3_TX_TRACK_RETRY_EN_15 Fld(1, 15) //[15:15] + #define LPIF_FSM_CTRL_3_RX_GATING_RETRY_EN_0 Fld(1, 16) //[16:16] + #define LPIF_FSM_CTRL_3_RX_GATING_RETRY_EN_1 Fld(1, 17) //[17:17] + #define LPIF_FSM_CTRL_3_RX_GATING_RETRY_EN_2 Fld(1, 18) //[18:18] + #define LPIF_FSM_CTRL_3_RX_GATING_RETRY_EN_3 Fld(1, 19) //[19:19] + #define LPIF_FSM_CTRL_3_RX_GATING_RETRY_EN_4 Fld(1, 20) //[20:20] + #define LPIF_FSM_CTRL_3_RX_GATING_RETRY_EN_5 Fld(1, 21) //[21:21] + #define LPIF_FSM_CTRL_3_RX_GATING_RETRY_EN_6 Fld(1, 22) //[22:22] + #define LPIF_FSM_CTRL_3_RX_GATING_RETRY_EN_7 Fld(1, 23) //[23:23] + #define LPIF_FSM_CTRL_3_RX_GATING_RETRY_EN_8 Fld(1, 24) //[24:24] + #define LPIF_FSM_CTRL_3_RX_GATING_RETRY_EN_9 Fld(1, 25) //[25:25] + #define LPIF_FSM_CTRL_3_RX_GATING_RETRY_EN_10 Fld(1, 26) //[26:26] + #define LPIF_FSM_CTRL_3_RX_GATING_RETRY_EN_11 Fld(1, 27) //[27:27] + #define LPIF_FSM_CTRL_3_RX_GATING_RETRY_EN_12 Fld(1, 28) //[28:28] + #define LPIF_FSM_CTRL_3_RX_GATING_RETRY_EN_13 Fld(1, 29) //[29:29] + #define LPIF_FSM_CTRL_3_RX_GATING_RETRY_EN_14 Fld(1, 30) //[30:30] + #define LPIF_FSM_CTRL_3_RX_GATING_RETRY_EN_15 Fld(1, 31) //[31:31] + +#define DDRPHY_MD32_REG_LPIF_FSM_CTRL_4 (DDRPHY_MD32_BASE_ADDRESS + 0x7030) + #define LPIF_FSM_CTRL_4_DLL_ALL_SLAVE_EN_0 Fld(1, 0) //[0:0] + #define LPIF_FSM_CTRL_4_DLL_ALL_SLAVE_EN_1 Fld(1, 1) //[1:1] + #define LPIF_FSM_CTRL_4_DLL_ALL_SLAVE_EN_2 Fld(1, 2) //[2:2] + #define LPIF_FSM_CTRL_4_DLL_ALL_SLAVE_EN_3 Fld(1, 3) //[3:3] + #define LPIF_FSM_CTRL_4_DLL_ALL_SLAVE_EN_4 Fld(1, 4) //[4:4] + #define LPIF_FSM_CTRL_4_DLL_ALL_SLAVE_EN_5 Fld(1, 5) //[5:5] + #define LPIF_FSM_CTRL_4_DLL_ALL_SLAVE_EN_6 Fld(1, 6) //[6:6] + #define LPIF_FSM_CTRL_4_DLL_ALL_SLAVE_EN_7 Fld(1, 7) //[7:7] + #define LPIF_FSM_CTRL_4_DLL_ALL_SLAVE_EN_8 Fld(1, 8) //[8:8] + #define LPIF_FSM_CTRL_4_DLL_ALL_SLAVE_EN_9 Fld(1, 9) //[9:9] + #define LPIF_FSM_CTRL_4_DLL_ALL_SLAVE_EN_10 Fld(1, 10) //[10:10] + #define LPIF_FSM_CTRL_4_DLL_ALL_SLAVE_EN_11 Fld(1, 11) //[11:11] + #define LPIF_FSM_CTRL_4_DLL_ALL_SLAVE_EN_12 Fld(1, 12) //[12:12] + #define LPIF_FSM_CTRL_4_DLL_ALL_SLAVE_EN_13 Fld(1, 13) //[13:13] + #define LPIF_FSM_CTRL_4_DLL_ALL_SLAVE_EN_14 Fld(1, 14) //[14:14] + #define LPIF_FSM_CTRL_4_DLL_ALL_SLAVE_EN_15 Fld(1, 15) //[15:15] + #define LPIF_FSM_CTRL_4_IMPEDANCE_TRACKING_EN_0 Fld(1, 16) //[16:16] + #define LPIF_FSM_CTRL_4_IMPEDANCE_TRACKING_EN_1 Fld(1, 17) //[17:17] + #define LPIF_FSM_CTRL_4_IMPEDANCE_TRACKING_EN_2 Fld(1, 18) //[18:18] + #define LPIF_FSM_CTRL_4_IMPEDANCE_TRACKING_EN_3 Fld(1, 19) //[19:19] + #define LPIF_FSM_CTRL_4_IMPEDANCE_TRACKING_EN_4 Fld(1, 20) //[20:20] + #define LPIF_FSM_CTRL_4_IMPEDANCE_TRACKING_EN_5 Fld(1, 21) //[21:21] + #define LPIF_FSM_CTRL_4_IMPEDANCE_TRACKING_EN_6 Fld(1, 22) //[22:22] + #define LPIF_FSM_CTRL_4_IMPEDANCE_TRACKING_EN_7 Fld(1, 23) //[23:23] + #define LPIF_FSM_CTRL_4_IMPEDANCE_TRACKING_EN_8 Fld(1, 24) //[24:24] + #define LPIF_FSM_CTRL_4_IMPEDANCE_TRACKING_EN_9 Fld(1, 25) //[25:25] + #define LPIF_FSM_CTRL_4_IMPEDANCE_TRACKING_EN_10 Fld(1, 26) //[26:26] + #define LPIF_FSM_CTRL_4_IMPEDANCE_TRACKING_EN_11 Fld(1, 27) //[27:27] + #define LPIF_FSM_CTRL_4_IMPEDANCE_TRACKING_EN_12 Fld(1, 28) //[28:28] + #define LPIF_FSM_CTRL_4_IMPEDANCE_TRACKING_EN_13 Fld(1, 29) //[29:29] + #define LPIF_FSM_CTRL_4_IMPEDANCE_TRACKING_EN_14 Fld(1, 30) //[30:30] + #define LPIF_FSM_CTRL_4_IMPEDANCE_TRACKING_EN_15 Fld(1, 31) //[31:31] + +#define DDRPHY_MD32_REG_LPIF_FSM_CFG_1 (DDRPHY_MD32_BASE_ADDRESS + 0x7034) + #define LPIF_FSM_CFG_1_LPIF_LEGACY_CONTROL Fld(1, 0) //[0:0] + #define LPIF_FSM_CFG_1_LPIF_LEGACY_CONTROL_2ND Fld(1, 1) //[1:1] + #define LPIF_FSM_CFG_1_LPIF_LEGACY_CONTROL_FOR_PWR Fld(1, 2) //[2:2] + #define LPIF_FSM_CFG_1_LPIF_LEGACY_CONTROL_FOR_PWR_2ND Fld(1, 3) //[3:3] + #define LPIF_FSM_CFG_1_LPIF_OUTPUT_PATH_FROM_SW Fld(1, 4) //[4:4] + #define LPIF_FSM_CFG_1_LPIF_OUTPUT_PATH_FROM_SW_2ND Fld(1, 5) //[5:5] + #define LPIF_FSM_CFG_1_LPIF_POWER_CONTROL_SEL Fld(1, 6) //[6:6] + #define LPIF_FSM_CFG_1_LPIF_POWER_CONTROL_SEL_2ND Fld(1, 7) //[7:7] + +#define DDRPHY_MD32_REG_LPIF_LOW_POWER_CFG_3 (DDRPHY_MD32_BASE_ADDRESS + 0x7038) + #define LPIF_LOW_POWER_CFG_3_DPY_MCK8X_EN Fld(2, 0) //[1:0] + #define LPIF_LOW_POWER_CFG_3_DPY_MIDPI_EN Fld(2, 2) //[3:2] + #define LPIF_LOW_POWER_CFG_3_DPY_PI_RESETB_EN Fld(2, 4) //[5:4] + #define LPIF_LOW_POWER_CFG_3_DVFS_MEM_CK_MUX_UPDATE Fld(2, 6) //[7:6] + #define LPIF_LOW_POWER_CFG_3_DVFS_MEM_CK_MUX_SEL Fld(4, 8) //[11:8] + #define LPIF_LOW_POWER_CFG_3_DPY_DSM_EN Fld(2, 12) //[13:12] + #define LPIF_LOW_POWER_CFG_3_DPY_FASTK_RDDQS_EN Fld(2, 14) //[15:14] + #define LPIF_LOW_POWER_CFG_3_DPY_CS_PULL_UP_EN Fld(2, 16) //[17:16] + #define LPIF_LOW_POWER_CFG_3_DPY_CS_PULL_DN_EN Fld(2, 18) //[19:18] + #define LPIF_LOW_POWER_CFG_3_DPY_CA_PULL_UP_EN Fld(2, 20) //[21:20] + #define LPIF_LOW_POWER_CFG_3_DPY_CA_PULL_DN_EN Fld(2, 22) //[23:22] + #define LPIF_LOW_POWER_CFG_3_EMI_S1_MODE_ASYNC Fld(1, 24) //[24:24] + #define LPIF_LOW_POWER_CFG_3_RESERVED_X38_25_25 Fld(1, 25) //[25:25] + #define LPIF_LOW_POWER_CFG_3_DPY_PICG_FREE Fld(2, 26) //[27:26] + #define LPIF_LOW_POWER_CFG_3_RESERVED_X38_31_28 Fld(4, 28) //[31:28] + +#define DDRPHY_MD32_REG_LPIF_DFD_DBUG_0 (DDRPHY_MD32_BASE_ADDRESS + 0x703C) + #define LPIF_DFD_DBUG_0_LPIF_DFD_DEBUG_ISO_EN Fld(1, 0) //[0:0] + #define LPIF_DFD_DBUG_0_MD32_DRAMC_CKGEN_MCK_CG_EN Fld(1, 1) //[1:1] + #define LPIF_DFD_DBUG_0_RESERVED_X3C_31_2 Fld(30, 2) //[31:2] + +#define DDRPHY_MD32_REG_LPIF_RESERVED_3 (DDRPHY_MD32_BASE_ADDRESS + 0x7040) + #define LPIF_RESERVED_3_RESERVED_X40_31_0 Fld(32, 0) //[31:0] + +#define DDRPHY_MD32_REG_LPIF_TIMING_COUNTER_CTRL_0 (DDRPHY_MD32_BASE_ADDRESS + 0x7044) + #define LPIF_TIMING_COUNTER_CTRL_0_COUNTER_TIME_OUT_CLR Fld(1, 0) //[0:0] + #define LPIF_TIMING_COUNTER_CTRL_0_COUNTER_20US_CLR Fld(1, 1) //[1:1] + #define LPIF_TIMING_COUNTER_CTRL_0_COUNTER_12US_CLR Fld(1, 2) //[2:2] + #define LPIF_TIMING_COUNTER_CTRL_0_COUNTER_DLL_1ST_LOCKING_CLR Fld(1, 3) //[3:3] + #define LPIF_TIMING_COUNTER_CTRL_0_COUNTER_DLL_2ND_LOCKING_CLR Fld(1, 4) //[4:4] + #define LPIF_TIMING_COUNTER_CTRL_0_COUNTER_CK_OFF_TO_DMSUS_CLR Fld(1, 5) //[5:5] + #define LPIF_TIMING_COUNTER_CTRL_0_COUNTER_50NS_CLR Fld(1, 6) //[6:6] + #define LPIF_TIMING_COUNTER_CTRL_0_COUNTER_4US_CLR Fld(1, 7) //[7:7] + #define LPIF_TIMING_COUNTER_CTRL_0_COUNTER_SR_DEBON_CLR Fld(1, 8) //[8:8] + #define LPIF_TIMING_COUNTER_CTRL_0_COUNTER_SR_MIN_PLS_DEBON_CLR Fld(1, 9) //[9:9] + #define LPIF_TIMING_COUNTER_CTRL_0_COUNTER_HW_S1_STEP_CLR Fld(1, 10) //[10:10] + #define LPIF_TIMING_COUNTER_CTRL_0_COUNTER_256MCK_CLR Fld(1, 11) //[11:11] + #define LPIF_TIMING_COUNTER_CTRL_0_RESERVED_X44_31_12 Fld(20, 12) //[31:12] + +#define DDRPHY_MD32_REG_LPIF_TIMING_COUNTER_CTRL_1 (DDRPHY_MD32_BASE_ADDRESS + 0x7048) + #define LPIF_TIMING_COUNTER_CTRL_1_FSM_COUNTER_CLK2 Fld(4, 0) //[3:0] + #define LPIF_TIMING_COUNTER_CTRL_1_FSM_COUNTER_CLK1 Fld(4, 4) //[7:4] + #define LPIF_TIMING_COUNTER_CTRL_1_FSM_COUNTER_CLK0 Fld(4, 8) //[11:8] + #define LPIF_TIMING_COUNTER_CTRL_1_COUNTER_SR_MIN_PLS_DEBON Fld(8, 12) //[19:12] + #define LPIF_TIMING_COUNTER_CTRL_1_COUNTER_SR_DEBON Fld(11, 20) //[30:20] + #define LPIF_TIMING_COUNTER_CTRL_1_RESERVED_X44_31_31 Fld(1, 31) //[31:31] + +#define DDRPHY_MD32_REG_LPIF_TIMING_COUNTER_CTRL_2 (DDRPHY_MD32_BASE_ADDRESS + 0x704C) + #define LPIF_TIMING_COUNTER_CTRL_2_COUNTER_DLL_1ST_LOCKING_CLK2 Fld(8, 0) //[7:0] + #define LPIF_TIMING_COUNTER_CTRL_2_COUNTER_DLL_2ND_LOCKING_CLK2 Fld(8, 8) //[15:8] + #define LPIF_TIMING_COUNTER_CTRL_2_COUNTER_CK_OFF_TO_DMSUS_CLK2 Fld(8, 16) //[23:16] + #define LPIF_TIMING_COUNTER_CTRL_2_COUNTER_50NS_CLK2 Fld(8, 24) //[31:24] + +#define DDRPHY_MD32_REG_LPIF_TIMING_COUNTER_CTRL_3 (DDRPHY_MD32_BASE_ADDRESS + 0x7050) + #define LPIF_TIMING_COUNTER_CTRL_3_COUNTER_DLL_1ST_LOCKING_CLK1 Fld(8, 0) //[7:0] + #define LPIF_TIMING_COUNTER_CTRL_3_COUNTER_DLL_2ND_LOCKING_CLK1 Fld(8, 8) //[15:8] + #define LPIF_TIMING_COUNTER_CTRL_3_COUNTER_CK_OFF_TO_DMSUS_CLK1 Fld(8, 16) //[23:16] + #define LPIF_TIMING_COUNTER_CTRL_3_COUNTER_50NS_CLK1 Fld(8, 24) //[31:24] + +#define DDRPHY_MD32_REG_LPIF_TIMING_COUNTER_CTRL_4 (DDRPHY_MD32_BASE_ADDRESS + 0x7054) + #define LPIF_TIMING_COUNTER_CTRL_4_COUNTER_DLL_1ST_LOCKING_CLK0 Fld(8, 0) //[7:0] + #define LPIF_TIMING_COUNTER_CTRL_4_COUNTER_DLL_2ND_LOCKING_CLK0 Fld(8, 8) //[15:8] + #define LPIF_TIMING_COUNTER_CTRL_4_COUNTER_CK_OFF_TO_DMSUS_CLK0 Fld(8, 16) //[23:16] + #define LPIF_TIMING_COUNTER_CTRL_4_COUNTER_50NS_CLK0 Fld(8, 24) //[31:24] + +#define DDRPHY_MD32_REG_LPIF_TIMING_COUNTER_CTRL_5 (DDRPHY_MD32_BASE_ADDRESS + 0x7058) + #define LPIF_TIMING_COUNTER_CTRL_5_COUNTER_20US_26M Fld(10, 0) //[9:0] + #define LPIF_TIMING_COUNTER_CTRL_5_RESERVED_X58_15_10 Fld(6, 10) //[15:10] + #define LPIF_TIMING_COUNTER_CTRL_5_COUNTER_TIME_OUT_26M Fld(16, 16) //[31:16] + +#define DDRPHY_MD32_REG_LPIF_TIMING_COUNTER_CTRL_6 (DDRPHY_MD32_BASE_ADDRESS + 0x705C) + #define LPIF_TIMING_COUNTER_CTRL_6_COUNTER_12US_26M Fld(10, 0) //[9:0] + #define LPIF_TIMING_COUNTER_CTRL_6_RESERVED_X5C_15_11 Fld(2, 10) //[11:10] + #define LPIF_TIMING_COUNTER_CTRL_6_COUNTER_4US_26M Fld(10, 12) //[21:12] + #define LPIF_TIMING_COUNTER_CTRL_6_RESERVED_X5C_31_22 Fld(10, 22) //[31:22] + +#define DDRPHY_MD32_REG_LPIF_FSM_CTRL_5 (DDRPHY_MD32_BASE_ADDRESS + 0x7060) + #define LPIF_FSM_CTRL_5_DRAM_PAR_CLOCK_MODE_0 Fld(2, 0) //[1:0] + #define LPIF_FSM_CTRL_5_DRAM_PAR_CLOCK_MODE_1 Fld(2, 2) //[3:2] + #define LPIF_FSM_CTRL_5_DRAM_PAR_CLOCK_MODE_2 Fld(2, 4) //[5:4] + #define LPIF_FSM_CTRL_5_DRAM_PAR_CLOCK_MODE_3 Fld(2, 6) //[7:6] + #define LPIF_FSM_CTRL_5_DRAM_PAR_CLOCK_MODE_4 Fld(2, 8) //[9:8] + #define LPIF_FSM_CTRL_5_DRAM_PAR_CLOCK_MODE_5 Fld(2, 10) //[11:10] + #define LPIF_FSM_CTRL_5_DRAM_PAR_CLOCK_MODE_6 Fld(2, 12) //[13:12] + #define LPIF_FSM_CTRL_5_DRAM_PAR_CLOCK_MODE_7 Fld(2, 14) //[15:14] + #define LPIF_FSM_CTRL_5_DRAM_PAR_CLOCK_MODE_8 Fld(2, 16) //[17:16] + #define LPIF_FSM_CTRL_5_DRAM_PAR_CLOCK_MODE_9 Fld(2, 18) //[19:18] + #define LPIF_FSM_CTRL_5_DRAM_PAR_CLOCK_MODE_10 Fld(2, 20) //[21:20] + #define LPIF_FSM_CTRL_5_DRAM_PAR_CLOCK_MODE_11 Fld(2, 22) //[23:22] + #define LPIF_FSM_CTRL_5_DRAM_PAR_CLOCK_MODE_12 Fld(2, 24) //[25:24] + #define LPIF_FSM_CTRL_5_DRAM_PAR_CLOCK_MODE_13 Fld(2, 26) //[27:26] + #define LPIF_FSM_CTRL_5_DRAM_PAR_CLOCK_MODE_14 Fld(2, 28) //[29:28] + #define LPIF_FSM_CTRL_5_DRAM_PAR_CLOCK_MODE_15 Fld(2, 30) //[31:30] + +#define DDRPHY_MD32_REG_LPIF_RESERVED_5 (DDRPHY_MD32_BASE_ADDRESS + 0x7064) + #define LPIF_RESERVED_5_COUNTER_HW_S1_STEP Fld(4, 0) //[3:0] + #define LPIF_RESERVED_5_COUNTER_256MCK Fld(9, 4) //[12:4] + #define LPIF_RESERVED_5_RESERVED_X64_31_13 Fld(19, 13) //[31:13] + +#define DDRPHY_MD32_REG_LPIF_RESERVED_6 (DDRPHY_MD32_BASE_ADDRESS + 0x7068) + #define LPIF_RESERVED_6_MAX_CNT_SREF_REQ_HIGH_TO_SREF_ACK Fld(8, 0) //[7:0] + #define LPIF_RESERVED_6_MAX_CNT_SREF_REQ_LOW_TO_SREF_ACK Fld(8, 8) //[15:8] + #define LPIF_RESERVED_6_MAX_CNT_SHU_EN_HIGH_TO_ACK Fld(8, 16) //[23:16] + #define LPIF_RESERVED_6_MAX_CNT_HW_S1_REQ_LOW_TO_SREF_ACK_LOW Fld(8, 24) //[31:24] + +#define DDRPHY_MD32_REG_LPIF_RESERVED_7 (DDRPHY_MD32_BASE_ADDRESS + 0x706C) + #define LPIF_RESERVED_7_RESERVED_X6C_31_0 Fld(32, 0) //[31:0] + +#define DDRPHY_MD32_REG_LPIF_RESERVED_8 (DDRPHY_MD32_BASE_ADDRESS + 0x7070) + #define LPIF_RESERVED_8_RESERVED_X70_31_0 Fld(32, 0) //[31:0] + +#define DDRPHY_MD32_REG_LPIF_RESERVED_9 (DDRPHY_MD32_BASE_ADDRESS + 0x7074) + #define LPIF_RESERVED_9_RESERVED_X74_31_0 Fld(32, 0) //[31:0] + +#define DDRPHY_MD32_REG_LPIF_RESERVED_10 (DDRPHY_MD32_BASE_ADDRESS + 0x7078) + #define LPIF_RESERVED_10_RESERVED_X78_31_0 Fld(32, 0) //[31:0] + +#define DDRPHY_MD32_REG_LPIF_RESERVED_11 (DDRPHY_MD32_BASE_ADDRESS + 0x707C) + #define LPIF_RESERVED_11_RESERVED_X7C_31_0 Fld(32, 0) //[31:0] + +#define DDRPHY_MD32_REG_LPIF_SEMA_0 (DDRPHY_MD32_BASE_ADDRESS + 0x7080) + #define LPIF_SEMA_0_SEMA_0_M0 Fld(1, 0) //[0:0] + #define LPIF_SEMA_0_SEMA_1_M0 Fld(1, 1) //[1:1] + #define LPIF_SEMA_0_SEMA_2_M0 Fld(1, 2) //[2:2] + #define LPIF_SEMA_0_SEMA_3_M0 Fld(1, 3) //[3:3] + #define LPIF_SEMA_0_SEMA_4_M0 Fld(1, 4) //[4:4] + #define LPIF_SEMA_0_SEMA_5_M0 Fld(1, 5) //[5:5] + #define LPIF_SEMA_0_SEMA_6_M0 Fld(1, 6) //[6:6] + #define LPIF_SEMA_0_SEMA_7_M0 Fld(1, 7) //[7:7] + #define LPIF_SEMA_0_RESERVED_X80_31_8 Fld(24, 8) //[31:8] + +#define DDRPHY_MD32_REG_LPIF_SEMA_1 (DDRPHY_MD32_BASE_ADDRESS + 0x7084) + #define LPIF_SEMA_1_SEMA_0_M1 Fld(1, 0) //[0:0] + #define LPIF_SEMA_1_SEMA_1_M1 Fld(1, 1) //[1:1] + #define LPIF_SEMA_1_SEMA_2_M1 Fld(1, 2) //[2:2] + #define LPIF_SEMA_1_SEMA_3_M1 Fld(1, 3) //[3:3] + #define LPIF_SEMA_1_SEMA_4_M1 Fld(1, 4) //[4:4] + #define LPIF_SEMA_1_SEMA_5_M1 Fld(1, 5) //[5:5] + #define LPIF_SEMA_1_SEMA_6_M1 Fld(1, 6) //[6:6] + #define LPIF_SEMA_1_SEMA_7_M1 Fld(1, 7) //[7:7] + #define LPIF_SEMA_1_RESERVED_X84_31_8 Fld(24, 8) //[31:8] + +#define DDRPHY_MD32_REG_LPIF_SEMA_2 (DDRPHY_MD32_BASE_ADDRESS + 0x7088) + #define LPIF_SEMA_2_SEMA_0_M2 Fld(1, 0) //[0:0] + #define LPIF_SEMA_2_SEMA_1_M2 Fld(1, 1) //[1:1] + #define LPIF_SEMA_2_SEMA_2_M2 Fld(1, 2) //[2:2] + #define LPIF_SEMA_2_SEMA_3_M2 Fld(1, 3) //[3:3] + #define LPIF_SEMA_2_SEMA_4_M2 Fld(1, 4) //[4:4] + #define LPIF_SEMA_2_SEMA_5_M2 Fld(1, 5) //[5:5] + #define LPIF_SEMA_2_SEMA_6_M2 Fld(1, 6) //[6:6] + #define LPIF_SEMA_2_SEMA_7_M2 Fld(1, 7) //[7:7] + #define LPIF_SEMA_2_RESERVED_X88_31_8 Fld(24, 8) //[31:8] + +#define DDRPHY_MD32_REG_LPIF_SEMA_3 (DDRPHY_MD32_BASE_ADDRESS + 0x708C) + #define LPIF_SEMA_3_SEMA_0_M3 Fld(1, 0) //[0:0] + #define LPIF_SEMA_3_SEMA_1_M3 Fld(1, 1) //[1:1] + #define LPIF_SEMA_3_SEMA_2_M3 Fld(1, 2) //[2:2] + #define LPIF_SEMA_3_SEMA_3_M3 Fld(1, 3) //[3:3] + #define LPIF_SEMA_3_SEMA_4_M3 Fld(1, 4) //[4:4] + #define LPIF_SEMA_3_SEMA_5_M3 Fld(1, 5) //[5:5] + #define LPIF_SEMA_3_SEMA_6_M3 Fld(1, 6) //[6:6] + #define LPIF_SEMA_3_SEMA_7_M3 Fld(1, 7) //[7:7] + #define LPIF_SEMA_3_RESERVED_X8C_31_8 Fld(24, 8) //[31:8] + +#define DDRPHY_MD32_REG_LPIF_RESERVED_16 (DDRPHY_MD32_BASE_ADDRESS + 0x7090) + #define LPIF_RESERVED_16_RESERVED_X90_31_0 Fld(32, 0) //[31:0] + +#define DDRPHY_MD32_REG_LPIF_RESERVED_17 (DDRPHY_MD32_BASE_ADDRESS + 0x7094) + #define LPIF_RESERVED_17_RESERVED_X94_31_0 Fld(32, 0) //[31:0] + +#define DDRPHY_MD32_REG_LPIF_RESERVED_18 (DDRPHY_MD32_BASE_ADDRESS + 0x7098) + #define LPIF_RESERVED_18_RESERVED_X98_31_0 Fld(32, 0) //[31:0] + +#define DDRPHY_MD32_REG_LPIF_DUMMY_REG (DDRPHY_MD32_BASE_ADDRESS + 0x709C) + #define LPIF_DUMMY_REG_DUMMY_REG Fld(32, 0) //[31:0] + +#define DDRPHY_MD32_REG_LPIF_STATUS_0 (DDRPHY_MD32_BASE_ADDRESS + 0x70A0) + #define LPIF_STATUS_0_LPIF_DDR_PST Fld(32, 0) //[31:0] + +#define DDRPHY_MD32_REG_LPIF_STATUS_1 (DDRPHY_MD32_BASE_ADDRESS + 0x70A4) + #define LPIF_STATUS_1_DDR_PST_REQ Fld(1, 0) //[0:0] + #define LPIF_STATUS_1_DDR_PST_ABORT_REQ Fld(1, 1) //[1:1] + #define LPIF_STATUS_1_DDR_PST_ABORT_REQ_LATCH Fld(1, 2) //[2:2] + #define LPIF_STATUS_1_LPC_INTERNAL_COUNTER_ABORT_FLAG Fld(1, 3) //[3:3] + #define LPIF_STATUS_1_RESERVED_XA4_31_4 Fld(28, 4) //[31:4] + +#define DDRPHY_MD32_REG_LPIF_STATUS_2 (DDRPHY_MD32_BASE_ADDRESS + 0x70A8) + #define LPIF_STATUS_2_DESTINATION_DDR_PST Fld(32, 0) //[31:0] + +#define DDRPHY_MD32_REG_LPIF_STATUS_3 (DDRPHY_MD32_BASE_ADDRESS + 0x70AC) + #define LPIF_STATUS_3_CUR_DDR_PST_STA Fld(32, 0) //[31:0] + +#define DDRPHY_MD32_REG_LPIF_STATUS_4 (DDRPHY_MD32_BASE_ADDRESS + 0x70B0) + #define LPIF_STATUS_4_EMI_CLK_OFF_REQ_ACK Fld(2, 0) //[1:0] + #define LPIF_STATUS_4_RESERVED_XB0_3_2 Fld(2, 2) //[3:2] + #define LPIF_STATUS_4_DRAMC_DFS_STA Fld(4, 4) //[7:4] + #define LPIF_STATUS_4_DQSSOC_REQ Fld(2, 8) //[9:8] + #define LPIF_STATUS_4_RESERVED_XB0_11_10 Fld(2, 10) //[11:10] + #define LPIF_STATUS_4_DR_SHORT_QUEUE_ACK Fld(2, 12) //[13:12] + #define LPIF_STATUS_4_DR_SHU_EN_ACK Fld(2, 14) //[15:14] + #define LPIF_STATUS_4_DR_SRAM_PLL_LOAD_ACK Fld(2, 16) //[17:16] + #define LPIF_STATUS_4_DR_SRAM_LOAD_ACK Fld(2, 18) //[19:18] + #define LPIF_STATUS_4_DR_SRAM_RESTORE_ACK Fld(2, 20) //[21:20] + #define LPIF_STATUS_4_TX_TRACKING_DIS_ACK Fld(2, 22) //[23:22] + #define LPIF_STATUS_4_RESERVED_XB0_27_24 Fld(4, 24) //[27:24] + #define LPIF_STATUS_4_DDR_PST_ACK Fld(1, 28) //[28:28] + #define LPIF_STATUS_4_DDR_PST_ABORT_ACK Fld(1, 29) //[29:29] + #define LPIF_STATUS_4_RESERVED_XB0_31_30 Fld(2, 30) //[31:30] + +#define DDRPHY_MD32_REG_LPIF_STATUS_5 (DDRPHY_MD32_BASE_ADDRESS + 0x70B4) + #define LPIF_STATUS_5_DDR_PST_STA_D0 Fld(6, 0) //[5:0] + #define LPIF_STATUS_5_DDR_PST_ACK_D0 Fld(1, 6) //[6:6] + #define LPIF_STATUS_5_DDR_PST_ABORT_ACK_D0 Fld(1, 7) //[7:7] + #define LPIF_STATUS_5_DDR_PST_STA_D1 Fld(6, 8) //[13:8] + #define LPIF_STATUS_5_DDR_PST_ACK_D1 Fld(1, 14) //[14:14] + #define LPIF_STATUS_5_DDR_PST_ABORT_ACK_D1 Fld(1, 15) //[15:15] + #define LPIF_STATUS_5_DDR_PST_STA_D2 Fld(6, 16) //[21:16] + #define LPIF_STATUS_5_DDR_PST_ACK_D2 Fld(1, 22) //[22:22] + #define LPIF_STATUS_5_DDR_PST_ABORT_ACK_D2 Fld(1, 23) //[23:23] + #define LPIF_STATUS_5_DDR_PST_STA_D3 Fld(6, 24) //[29:24] + #define LPIF_STATUS_5_DDR_PST_ACK_D3 Fld(1, 30) //[30:30] + #define LPIF_STATUS_5_DDR_PST_ABORT_ACK_D3 Fld(1, 31) //[31:31] + +#define DDRPHY_MD32_REG_LPIF_STATUS_6 (DDRPHY_MD32_BASE_ADDRESS + 0x70B8) + #define LPIF_STATUS_6_DDR_PST_STA_D4 Fld(6, 0) //[5:0] + #define LPIF_STATUS_6_DDR_PST_ACK_D4 Fld(1, 6) //[6:6] + #define LPIF_STATUS_6_DDR_PST_ABORT_ACK_D4 Fld(1, 7) //[7:7] + #define LPIF_STATUS_6_DDR_PST_STA_D5 Fld(6, 8) //[13:8] + #define LPIF_STATUS_6_DDR_PST_ACK_D5 Fld(1, 14) //[14:14] + #define LPIF_STATUS_6_DDR_PST_ABORT_ACK_D5 Fld(1, 15) //[15:15] + #define LPIF_STATUS_6_DDR_PST_STA_D6 Fld(6, 16) //[21:16] + #define LPIF_STATUS_6_DDR_PST_ACK_D6 Fld(1, 22) //[22:22] + #define LPIF_STATUS_6_DDR_PST_ABORT_ACK_D6 Fld(1, 23) //[23:23] + #define LPIF_STATUS_6_DDR_PST_STA_D7 Fld(6, 24) //[29:24] + #define LPIF_STATUS_6_DDR_PST_ACK_D7 Fld(1, 30) //[30:30] + #define LPIF_STATUS_6_DDR_PST_ABORT_ACK_D7 Fld(1, 31) //[31:31] + +#define DDRPHY_MD32_REG_LPIF_STATUS_7 (DDRPHY_MD32_BASE_ADDRESS + 0x70BC) + #define LPIF_STATUS_7_DDR_PST_STA_D8 Fld(6, 0) //[5:0] + #define LPIF_STATUS_7_DDR_PST_ACK_D8 Fld(1, 6) //[6:6] + #define LPIF_STATUS_7_DDR_PST_ABORT_ACK_D8 Fld(1, 7) //[7:7] + #define LPIF_STATUS_7_DDR_PST_STA_D9 Fld(6, 8) //[13:8] + #define LPIF_STATUS_7_DDR_PST_ACK_D9 Fld(1, 14) //[14:14] + #define LPIF_STATUS_7_DDR_PST_ABORT_ACK_D9 Fld(1, 15) //[15:15] + #define LPIF_STATUS_7_DDR_PST_STA_DA Fld(6, 16) //[21:16] + #define LPIF_STATUS_7_DDR_PST_ACK_DA Fld(1, 22) //[22:22] + #define LPIF_STATUS_7_DDR_PST_ABORT_ACK_DA Fld(1, 23) //[23:23] + #define LPIF_STATUS_7_DDR_PST_STA_DB Fld(6, 24) //[29:24] + #define LPIF_STATUS_7_DDR_PST_ACK_DB Fld(1, 30) //[30:30] + #define LPIF_STATUS_7_DDR_PST_ABORT_ACK_DB Fld(1, 31) //[31:31] + +#define DDRPHY_MD32_REG_LPIF_STATUS_8 (DDRPHY_MD32_BASE_ADDRESS + 0x70C0) + #define LPIF_STATUS_8_DDR_PST_STA_DC Fld(6, 0) //[5:0] + #define LPIF_STATUS_8_DDR_PST_ACK_DC Fld(1, 6) //[6:6] + #define LPIF_STATUS_8_DDR_PST_ABORT_ACK_DC Fld(1, 7) //[7:7] + #define LPIF_STATUS_8_DDR_PST_STA_DD Fld(6, 8) //[13:8] + #define LPIF_STATUS_8_DDR_PST_ACK_DD Fld(1, 14) //[14:14] + #define LPIF_STATUS_8_DDR_PST_ABORT_ACK_DD Fld(1, 15) //[15:15] + #define LPIF_STATUS_8_DDR_PST_STA_DE Fld(6, 16) //[21:16] + #define LPIF_STATUS_8_DDR_PST_ACK_DE Fld(1, 22) //[22:22] + #define LPIF_STATUS_8_DDR_PST_ABORT_ACK_DE Fld(1, 23) //[23:23] + #define LPIF_STATUS_8_DDR_PST_STA_DF Fld(6, 24) //[29:24] + #define LPIF_STATUS_8_DDR_PST_ACK_DF Fld(1, 30) //[30:30] + #define LPIF_STATUS_8_DDR_PST_ABORT_ACK_DF Fld(1, 31) //[31:31] + +#define DDRPHY_MD32_REG_LPIF_STATUS_9 (DDRPHY_MD32_BASE_ADDRESS + 0x70C4) + #define LPIF_STATUS_9_DRAMC_DMSUS_OFF Fld(2, 0) //[1:0] + #define LPIF_STATUS_9_DRAMC_PHYPLL_EN Fld(2, 2) //[3:2] + #define LPIF_STATUS_9_DRAMC_DPY_DLL_EN Fld(2, 4) //[5:4] + #define LPIF_STATUS_9_DRAMC_DPY_2ND_DLL_EN Fld(2, 6) //[7:6] + #define LPIF_STATUS_9_DRAMC_DPY_DLL_CK_EN Fld(2, 8) //[9:8] + #define LPIF_STATUS_9_DRAMC_DPY_VREF_EN Fld(2, 10) //[11:10] + #define LPIF_STATUS_9_DRAMC_EMI_CLK_OFF_REQ Fld(2, 12) //[13:12] + #define LPIF_STATUS_9_DRAMC_MEM_CK_OFF Fld(2, 14) //[15:14] + #define LPIF_STATUS_9_DRAMC_DDRPHY_FB_CK_EN Fld(2, 16) //[17:16] + #define LPIF_STATUS_9_DRAMC_DR_GATE_RETRY_EN Fld(2, 18) //[19:18] + #define LPIF_STATUS_9_DRAMC_PHYPLL_SHU_EN Fld(2, 20) //[21:20] + #define LPIF_STATUS_9_DRAMC_PHYPLL_MODE_SW Fld(2, 22) //[23:22] + #define LPIF_STATUS_9_DRAMC_PHYPLL2_SHU_EN Fld(2, 24) //[25:24] + #define LPIF_STATUS_9_DRAMC_PHYPLL2_MODE_SW Fld(2, 26) //[27:26] + #define LPIF_STATUS_9_DRAMC_DR_SHU_EN Fld(2, 28) //[29:28] + #define LPIF_STATUS_9_DRAMC_DR_SHORT_QUEUE Fld(2, 30) //[31:30] + +#define DDRPHY_MD32_REG_LPIF_STATUS_10 (DDRPHY_MD32_BASE_ADDRESS + 0x70C8) + #define LPIF_STATUS_10_DRAMC_DR_SHU_LEVEL Fld(4, 0) //[3:0] + #define LPIF_STATUS_10_DRAMC_DPY_BCLK_ENABLE Fld(2, 4) //[5:4] + #define LPIF_STATUS_10_DRAMC_SHU_RESTORE Fld(2, 6) //[7:6] + #define LPIF_STATUS_10_DRAMC_DPHY_PRECAL_UP Fld(2, 8) //[9:8] + #define LPIF_STATUS_10_DRAMC_DPHY_RXDLY_TRACK_EN Fld(2, 10) //[11:10] + #define LPIF_STATUS_10_DRAMC_DMY_EN_MOD_SEL Fld(2, 12) //[13:12] + #define LPIF_STATUS_10_DRAMC_DMYRD_INTV_SEL Fld(2, 14) //[15:14] + #define LPIF_STATUS_10_DRAMC_DMYRD_EN Fld(2, 16) //[17:16] + #define LPIF_STATUS_10_DRAMC_TX_TRACKING_DIS Fld(2, 18) //[19:18] + #define LPIF_STATUS_10_DRAMC_TX_TRACKING_RETRY_EN Fld(2, 20) //[21:20] + #define LPIF_STATUS_10_DRAMC_DR_SHU_SRAM_LEVEL Fld(8, 22) //[29:22] + #define LPIF_STATUS_10_DRAMC_DR_SRAM_LOAD Fld(2, 30) //[31:30] + +#define DDRPHY_MD32_REG_LPIF_STATUS_11 (DDRPHY_MD32_BASE_ADDRESS + 0x70CC) + #define LPIF_STATUS_11_DRAMC_DR_SRAM_RESTORE Fld(2, 0) //[1:0] + #define LPIF_STATUS_11_DRAMC_DR_SHU_LEVEL_SRAM_LATCH Fld(2, 2) //[3:2] + #define LPIF_STATUS_11_DRAMC_DPY_MODE_SW Fld(2, 4) //[5:4] + #define LPIF_STATUS_11_RESERVED_XCC_7_6 Fld(2, 6) //[7:6] + #define LPIF_STATUS_11_DRAMC_DPY_RESERVED Fld(8, 8) //[15:8] + #define LPIF_STATUS_11_DRAMC_DRAMC_DFS_CON Fld(13, 16) //[28:16] + #define LPIF_STATUS_11_RESERVED_XCC_31_27 Fld(3, 29) //[31:29] + +#define DDRPHY_MD32_REG_LPIF_STATUS_12 (DDRPHY_MD32_BASE_ADDRESS + 0x70D0) + #define LPIF_STATUS_12_FSM_TIME_OUT_FLAG Fld(1, 0) //[0:0] + #define LPIF_STATUS_12_EXP_FSM_JUMP Fld(1, 1) //[1:1] + #define LPIF_STATUS_12_IRQ_LPIF_LOW_POWER Fld(1, 2) //[2:2] + #define LPIF_STATUS_12_IRQ_LPIF_OTHERS_STATE Fld(1, 3) //[3:3] + #define LPIF_STATUS_12_DFS_STATUS_RECORD Fld(4, 4) //[7:4] + #define LPIF_STATUS_12_DVS_STATUS_RECORD Fld(1, 8) //[8:8] + #define LPIF_STATUS_12_RUNTIME_STATUS_RECORD Fld(1, 9) //[9:9] + #define LPIF_STATUS_12_RESERVED_XD0_11_10 Fld(2, 10) //[11:10] + #define LPIF_STATUS_12_MUX_LPIF_DPHY_RXDLY_TRACK_EN Fld(1, 12) //[12:12] + #define LPIF_STATUS_12_MUX_LPIF_DMYRD_EN Fld(1, 13) //[13:13] + #define LPIF_STATUS_12_MUX_LPIF_TX_TRACKING_DIS Fld(1, 14) //[14:14] + #define LPIF_STATUS_12_MUX_LPIF_DR_SRAM_RESTORE Fld(1, 15) //[15:15] + #define LPIF_STATUS_12_MUX_LPIF_TX_TRACK_RETRY_EN Fld(1, 16) //[16:16] + #define LPIF_STATUS_12_MUX_LPIF_RX_GATING_RETRY_EN Fld(1, 17) //[17:17] + #define LPIF_STATUS_12_MUX_LPIF_DLL_ALL_SLAVE_EN Fld(1, 18) //[18:18] + #define LPIF_STATUS_12_MUX_LPIF_IMPEDANCE_TRACKING_EN Fld(1, 19) //[19:19] + #define LPIF_STATUS_12_MUX_LPIF_DPHY_RXDLY_TRACK_EN_PREV Fld(1, 20) //[20:20] + #define LPIF_STATUS_12_MUX_LPIF_DMYRD_EN_PREV Fld(1, 21) //[21:21] + #define LPIF_STATUS_12_MUX_LPIF_TX_TRACKING_DIS_PREV Fld(1, 22) //[22:22] + #define LPIF_STATUS_12_MUX_LPIF_DR_SRAM_RESTORE_PREV Fld(1, 23) //[23:23] + #define LPIF_STATUS_12_MUX_LPIF_TX_TRACK_RETRY_EN_PREV Fld(1, 24) //[24:24] + #define LPIF_STATUS_12_MUX_LPIF_RX_GATING_RETRY_EN_PREV Fld(1, 25) //[25:25] + #define LPIF_STATUS_12_MUX_LPIF_DLL_ALL_SLAVE_EN_PREV Fld(1, 26) //[26:26] + #define LPIF_STATUS_12_MUX_LPIF_IMPEDANCE_TRACKING_EN_PREV Fld(1, 27) //[27:27] + #define LPIF_STATUS_12_SHU_INDEX Fld(1, 28) //[28:28] + #define LPIF_STATUS_12_RESERVED_XD0_31_29 Fld(3, 29) //[31:29] + +#define DDRPHY_MD32_REG_LPIF_STATUS_13 (DDRPHY_MD32_BASE_ADDRESS + 0x70D4) + #define LPIF_STATUS_13_COUNTER_TIME_OUT_FLAG Fld(1, 0) //[0:0] + #define LPIF_STATUS_13_COUNTER_20US_DONE Fld(1, 1) //[1:1] + #define LPIF_STATUS_13_COUNTER_12US_DONE Fld(1, 2) //[2:2] + #define LPIF_STATUS_13_COUNTER_DLL_1ST_LOCKING_DONE Fld(1, 3) //[3:3] + #define LPIF_STATUS_13_COUNTER_DLL_2ND_LOCKING_DONE Fld(1, 4) //[4:4] + #define LPIF_STATUS_13_COUNTER_CK_OFF_TO_DMSUS_DONE Fld(1, 5) //[5:5] + #define LPIF_STATUS_13_COUNTER_50NS_DONE Fld(1, 6) //[6:6] + #define LPIF_STATUS_13_COUNTER_4US_DONE Fld(1, 7) //[7:7] + #define LPIF_STATUS_13_LPIF_FSM Fld(10, 8) //[17:8] + #define LPIF_STATUS_13_COUNTER_SR_DEBON_DONE Fld(2, 18) //[19:18] + #define LPIF_STATUS_13_COUNTER_SR_MIN_PLS_DEBON_DONE Fld(2, 20) //[21:20] + #define LPIF_STATUS_13_HW_S1_STEP_COUNTER_DONE Fld(1, 22) //[22:22] + #define LPIF_STATUS_13_COUNTER_256MCK_DONE Fld(1, 23) //[23:23] + #define LPIF_STATUS_13_MUX_LPIF_DRAM_PAR_CLOCK_MODE Fld(2, 24) //[25:24] + #define LPIF_STATUS_13_MUX_LPIF_DRAM_PAR_CLOCK_MODE_PREV Fld(2, 26) //[27:26] + #define LPIF_STATUS_13_RESERVED_XD4_31_28 Fld(4, 28) //[31:28] + +#define DDRPHY_MD32_REG_LPIF_STATUS_14 (DDRPHY_MD32_BASE_ADDRESS + 0x70D8) + #define LPIF_STATUS_14_DRAMC_DPY_MCK8X_EN Fld(2, 0) //[1:0] + #define LPIF_STATUS_14_DRAMC_DPY_MIDPI_EN Fld(2, 2) //[3:2] + #define LPIF_STATUS_14_DRAMC_DPY_PI_RESETB_EN Fld(2, 4) //[5:4] + #define LPIF_STATUS_14_DRAMC_DVFS_MEM_CK_MUX_UPDATE Fld(2, 6) //[7:6] + #define LPIF_STATUS_14_DRAMC_DVFS_MEM_CK_MUX_SEL Fld(4, 8) //[11:8] + #define LPIF_STATUS_14_DRAMC_DPY_DSM_EN Fld(2, 12) //[13:12] + #define LPIF_STATUS_14_DRAMC_DPY_FASTK_RDDQS_EN Fld(2, 14) //[15:14] + #define LPIF_STATUS_14_DRAMC_DPY_CS_PULL_UP_EN Fld(2, 16) //[17:16] + #define LPIF_STATUS_14_DRAMC_DPY_CS_PULL_DN_EN Fld(2, 18) //[19:18] + #define LPIF_STATUS_14_DRAMC_DPY_CA_PULL_UP_EN Fld(2, 20) //[21:20] + #define LPIF_STATUS_14_DRAMC_DPY_CA_PULL_DN_EN Fld(2, 22) //[23:22] + #define LPIF_STATUS_14_DRAMC_FHC_PAUSE_MEM Fld(1, 24) //[24:24] + #define LPIF_STATUS_14_DRAMC_FHC_PAUSE_MPLL Fld(1, 25) //[25:25] + #define LPIF_STATUS_14_DRAMC_MPLL_S_OFF Fld(1, 26) //[26:26] + #define LPIF_STATUS_14_DRAMC_MPLLOUT_OFF Fld(1, 27) //[27:27] + #define LPIF_STATUS_14_DRAMC_EMI_S1_MODE_ASYNC Fld(1, 28) //[28:28] + #define LPIF_STATUS_14_RESERVED_XD8_29_29 Fld(1, 29) //[29:29] + #define LPIF_STATUS_14_DRAMC_DPY_PICG_FREE Fld(2, 30) //[31:30] + +#define DDRPHY_MD32_REG_LPIF_RESERVED_20 (DDRPHY_MD32_BASE_ADDRESS + 0x70DC) + #define LPIF_RESERVED_20_RESERVED_XDC_31_0 Fld(32, 0) //[31:0] + +#define DDRPHY_MD32_REG_LPIF_STATUS_15 (DDRPHY_MD32_BASE_ADDRESS + 0x70E0) + #define LPIF_STATUS_15_DRAMC_PWR_RST_B Fld(2, 0) //[1:0] + #define LPIF_STATUS_15_DRAMC_PWR_ISO Fld(2, 2) //[3:2] + #define LPIF_STATUS_15_DRAMC_PWR_ON Fld(2, 4) //[5:4] + #define LPIF_STATUS_15_DRAMC_PWR_ON_2ND Fld(2, 6) //[7:6] + #define LPIF_STATUS_15_DRAMC_PWR_CLK_DIS Fld(2, 8) //[9:8] + #define LPIF_STATUS_15_DRAMC_MPLL_OFF Fld(1, 12) //[12:12] + #define LPIF_STATUS_15_DRAMC_PWR_SRAM_PDN Fld(4, 16) //[19:16] + #define LPIF_STATUS_15_DRAMC_PWR_SC_SRAM_PDN_ACK Fld(1, 20) //[20:20] + #define LPIF_STATUS_15_DRAMC_SHU_SRAM_SLEEP_B Fld(2, 24) //[25:24] + #define LPIF_STATUS_15_DRAMC_SHU_SRAM_CKISO Fld(2, 26) //[27:26] + #define LPIF_STATUS_15_DRAMC_SHU_SRAM_ISOINT_B Fld(2, 28) //[29:28] + #define LPIF_STATUS_15_DRAMC_SHU_SRAM_PDN Fld(2, 30) //[31:30] + +#define DDRPHY_MD32_REG_LPIF_STATUS_16 (DDRPHY_MD32_BASE_ADDRESS + 0x70E4) + #define LPIF_STATUS_16_SC_PWR_RST_B Fld(2, 0) //[1:0] + #define LPIF_STATUS_16_SC_PWR_ISO Fld(2, 2) //[3:2] + #define LPIF_STATUS_16_SC_PWR_ON Fld(2, 4) //[5:4] + #define LPIF_STATUS_16_SC_PWR_ON_2ND Fld(2, 6) //[7:6] + #define LPIF_STATUS_16_SC_PWR_CLK_DIS Fld(2, 8) //[9:8] + #define LPIF_STATUS_16_RESERVED_XE4_11_10 Fld(2, 10) //[11:10] + #define LPIF_STATUS_16_SC_MPLL_OFF Fld(1, 12) //[12:12] + #define LPIF_STATUS_16_RESERVED_XE4_15_13 Fld(3, 13) //[15:13] + #define LPIF_STATUS_16_SC_PWR_SRAM_PDN Fld(4, 16) //[19:16] + #define LPIF_STATUS_16_RESERVED_XE4_23_20 Fld(4, 20) //[23:20] + #define LPIF_STATUS_16_SC_SHU_SRAM_SLEEP_B Fld(2, 24) //[25:24] + #define LPIF_STATUS_16_RESERVED_XE4_26_26 Fld(1, 26) //[26:26] + #define LPIF_STATUS_16_SC_SHU_SRAM_CKISO Fld(1, 27) //[27:27] + #define LPIF_STATUS_16_RESERVED_XE4_28_28 Fld(1, 28) //[28:28] + #define LPIF_STATUS_16_SC_SHU_SRAM_ISOINT_B Fld(1, 29) //[29:29] + #define LPIF_STATUS_16_SC_SHU_SRAM_PDN Fld(2, 30) //[31:30] + +#define DDRPHY_MD32_REG_LPIF_STATUS_17 (DDRPHY_MD32_BASE_ADDRESS + 0x70E8) + #define LPIF_STATUS_17_LPIF_PWR_RST_B Fld(2, 0) //[1:0] + #define LPIF_STATUS_17_LPIF_PWR_ISO Fld(2, 2) //[3:2] + #define LPIF_STATUS_17_LPIF_PWR_ON Fld(2, 4) //[5:4] + #define LPIF_STATUS_17_LPIF_PWR_ON_2ND Fld(2, 6) //[7:6] + #define LPIF_STATUS_17_LPIF_PWR_CLK_DIS Fld(2, 8) //[9:8] + #define LPIF_STATUS_17_LPIF_MPLL_OFF Fld(1, 12) //[12:12] + #define LPIF_STATUS_17_LPIF_PWR_SRAM_PDN Fld(8, 16) //[23:16] + #define LPIF_STATUS_17_LPIF_SHU_SRAM_SLEEP_B Fld(2, 24) //[25:24] + #define LPIF_STATUS_17_LPIF_SHU_SRAM_CKISO Fld(2, 26) //[27:26] + #define LPIF_STATUS_17_LPIF_SHU_SRAM_ISOINT_B Fld(2, 28) //[29:28] + #define LPIF_STATUS_17_LPIF_SHU_SRAM_PDN Fld(2, 30) //[31:30] + +#define DDRPHY_MD32_REG_LPIF_STATUS_18 (DDRPHY_MD32_BASE_ADDRESS + 0x70EC) + #define LPIF_STATUS_18_DRAMC_LPIF_COM Fld(32, 0) //[31:0] + +#define DDRPHY_MD32_REG_LPIF_STATUS_19 (DDRPHY_MD32_BASE_ADDRESS + 0x70F0) + #define LPIF_STATUS_19_DRAMC_LPIF_STA Fld(32, 0) //[31:0] + +#define DDRPHY_MD32_REG_LPIF_MISC_CTL_0 (DDRPHY_MD32_BASE_ADDRESS + 0x70F4) + #define LPIF_MISC_CTL_0_EMI_SLEEP_IDLE Fld(1, 0) //[0:0] + +#define DDRPHY_MD32_REG_LPIF_MISC_CTL_1 (DDRPHY_MD32_BASE_ADDRESS + 0x70F8) + #define LPIF_MISC_CTL_1_PWR_RST_B Fld(2, 0) //[1:0] + #define LPIF_MISC_CTL_1_PWR_ISO Fld(2, 2) //[3:2] + #define LPIF_MISC_CTL_1_PWR_ON Fld(2, 4) //[5:4] + #define LPIF_MISC_CTL_1_PWR_ON_2ND Fld(2, 6) //[7:6] + #define LPIF_MISC_CTL_1_PWR_CLK_DIS Fld(2, 8) //[9:8] + #define LPIF_MISC_CTL_1_MPLL_OFF Fld(1, 12) //[12:12] + #define LPIF_MISC_CTL_1_PWR_SRAM_PDN Fld(8, 16) //[23:16] + #define LPIF_MISC_CTL_1_SHU_SRAM_SLEEP_B Fld(2, 24) //[25:24] + #define LPIF_MISC_CTL_1_SHU_SRAM_CKISO Fld(2, 26) //[27:26] + #define LPIF_MISC_CTL_1_SHU_SRAM_ISOINT_B Fld(2, 28) //[29:28] + #define LPIF_MISC_CTL_1_SHU_SRAM_PDN Fld(2, 30) //[31:30] + +#define DDRPHY_MD32_REG_LPIF_MISC_STATUS_0 (DDRPHY_MD32_BASE_ADDRESS + 0x70FC) + #define LPIF_MISC_STATUS_0_PWR_ON_ACK Fld(2, 0) //[1:0] + #define LPIF_MISC_STATUS_0_PWR_ON_2ND_ACK Fld(2, 2) //[3:2] + #define LPIF_MISC_STATUS_0_SRAM_PDN_ACK Fld(4, 8) //[11:8] + +#define DDRPHY_MD32_REG_LPIF_DVFS_CMD_0 (DDRPHY_MD32_BASE_ADDRESS + 0x7100) + #define LPIF_DVFS_CMD_0_DVFS_CMD0 Fld(32, 0) //[31:0] + +#define DDRPHY_MD32_REG_LPIF_DVFS_CMD_1 (DDRPHY_MD32_BASE_ADDRESS + 0x7104) + #define LPIF_DVFS_CMD_1_DVFS_CMD1 Fld(32, 0) //[31:0] + +#define DDRPHY_MD32_REG_LPIF_DVFS_CMD_2 (DDRPHY_MD32_BASE_ADDRESS + 0x7108) + #define LPIF_DVFS_CMD_2_DVFS_CMD2 Fld(32, 0) //[31:0] + +#define DDRPHY_MD32_REG_LPIF_DVFS_CMD_3 (DDRPHY_MD32_BASE_ADDRESS + 0x710C) + #define LPIF_DVFS_CMD_3_DVFS_CMD3 Fld(32, 0) //[31:0] + +#define DDRPHY_MD32_REG_LPIF_DVFS_CMD_4 (DDRPHY_MD32_BASE_ADDRESS + 0x7110) + #define LPIF_DVFS_CMD_4_DVFS_CMD4 Fld(32, 0) //[31:0] + +#define DDRPHY_MD32_REG_LPIF_DVFS_CMD_5 (DDRPHY_MD32_BASE_ADDRESS + 0x7114) + #define LPIF_DVFS_CMD_5_DVFS_CMD5 Fld(32, 0) //[31:0] + +#define DDRPHY_MD32_REG_LPIF_DVFS_CMD_6 (DDRPHY_MD32_BASE_ADDRESS + 0x7118) + #define LPIF_DVFS_CMD_6_DVFS_CMD6 Fld(32, 0) //[31:0] + +#define DDRPHY_MD32_REG_LPIF_DVFS_CMD_7 (DDRPHY_MD32_BASE_ADDRESS + 0x711C) + #define LPIF_DVFS_CMD_7_DVFS_CMD7 Fld(32, 0) //[31:0] + +#define DDRPHY_MD32_REG_LPIF_DVFS_CMD_8 (DDRPHY_MD32_BASE_ADDRESS + 0x7120) + #define LPIF_DVFS_CMD_8_DVFS_CMD8 Fld(32, 0) //[31:0] + +#define DDRPHY_MD32_REG_LPIF_DVFS_CMD_9 (DDRPHY_MD32_BASE_ADDRESS + 0x7124) + #define LPIF_DVFS_CMD_9_DVFS_CMD9 Fld(32, 0) //[31:0] + +#define DDRPHY_MD32_REG_LPIF_DVFS_CMD_10 (DDRPHY_MD32_BASE_ADDRESS + 0x7128) + #define LPIF_DVFS_CMD_10_DVFS_CMD10 Fld(32, 0) //[31:0] + +#define DDRPHY_MD32_REG_LPIF_DVFS_CMD_11 (DDRPHY_MD32_BASE_ADDRESS + 0x712C) + #define LPIF_DVFS_CMD_11_DVFS_CMD11 Fld(32, 0) //[31:0] + +#define DDRPHY_MD32_REG_LPIF_DVFS_CMD_12 (DDRPHY_MD32_BASE_ADDRESS + 0x7130) + #define LPIF_DVFS_CMD_12_DVFS_CMD12 Fld(32, 0) //[31:0] + +#define DDRPHY_MD32_REG_LPIF_DVFS_CMD_13 (DDRPHY_MD32_BASE_ADDRESS + 0x7134) + #define LPIF_DVFS_CMD_13_DVFS_CMD13 Fld(32, 0) //[31:0] + +#define DDRPHY_MD32_REG_LPIF_DVFS_CMD_14 (DDRPHY_MD32_BASE_ADDRESS + 0x7138) + #define LPIF_DVFS_CMD_14_DVFS_CMD14 Fld(32, 0) //[31:0] + +#define DDRPHY_MD32_REG_LPIF_DVFS_CMD_15 (DDRPHY_MD32_BASE_ADDRESS + 0x713C) + #define LPIF_DVFS_CMD_15_DVFS_CMD15 Fld(32, 0) //[31:0] + +#define DDRPHY_MD32_REG_LPIF_DVFS_CMD_16 (DDRPHY_MD32_BASE_ADDRESS + 0x7140) + #define LPIF_DVFS_CMD_16_DVFS_CMD16 Fld(32, 0) //[31:0] + +#define DDRPHY_MD32_REG_LPIF_DVFS_CMD_17 (DDRPHY_MD32_BASE_ADDRESS + 0x7144) + #define LPIF_DVFS_CMD_17_DVFS_CMD17 Fld(32, 0) //[31:0] + +#define DDRPHY_MD32_REG_LPIF_DVFS_CMD_18 (DDRPHY_MD32_BASE_ADDRESS + 0x7148) + #define LPIF_DVFS_CMD_18_DVFS_CMD18 Fld(32, 0) //[31:0] + +#define DDRPHY_MD32_REG_LPIF_DVFS_CMD_19 (DDRPHY_MD32_BASE_ADDRESS + 0x714C) + #define LPIF_DVFS_CMD_19_DVFS_CMD19 Fld(32, 0) //[31:0] + +#define DDRPHY_MD32_REG_LPIF_DVFS_CMD_20 (DDRPHY_MD32_BASE_ADDRESS + 0x7150) + #define LPIF_DVFS_CMD_20_DVFS_CMD20 Fld(32, 0) //[31:0] + +#define DDRPHY_MD32_REG_LPIF_DVFS_CMD_21 (DDRPHY_MD32_BASE_ADDRESS + 0x7154) + #define LPIF_DVFS_CMD_21_DVFS_CMD21 Fld(32, 0) //[31:0] + +#define DDRPHY_MD32_REG_LPIF_DVFS_CMD_22 (DDRPHY_MD32_BASE_ADDRESS + 0x7158) + #define LPIF_DVFS_CMD_22_DVFS_CMD22 Fld(32, 0) //[31:0] + +#define DDRPHY_MD32_REG_LPIF_DVFS_CMD_23 (DDRPHY_MD32_BASE_ADDRESS + 0x715C) + #define LPIF_DVFS_CMD_23_DVFS_CMD23 Fld(32, 0) //[31:0] + +#define DDRPHY_MD32_REG_LPIF_DVFS_CONFIG (DDRPHY_MD32_BASE_ADDRESS + 0x7160) + #define LPIF_DVFS_CONFIG_DVFS_CON Fld(32, 0) //[31:0] + +#define DDRPHY_MD32_REG_LPIF_DVFS_STATUS_0 (DDRPHY_MD32_BASE_ADDRESS + 0x7164) + #define LPIF_DVFS_STATUS_0_DVFS_CMD_ACK Fld(1, 0) //[0:0] + #define LPIF_DVFS_STATUS_0_DVFS_CMD_REQ Fld(1, 1) //[1:1] + +#define DDRPHY_MD32_REG_LPIF_DVFS_STATUS_1 (DDRPHY_MD32_BASE_ADDRESS + 0x7168) + #define LPIF_DVFS_STATUS_1_DVFS_CMD_DAT Fld(32, 0) //[31:0] + +#define DDRPHY_MD32_REG_LPIF_DVFS_STATUS_2 (DDRPHY_MD32_BASE_ADDRESS + 0x716C) + #define LPIF_DVFS_STATUS_2_DVFS_CON_STA Fld(32, 0) //[31:0] + +#define DDRPHY_MD32_REG_LPIF_RESERVED_170 (DDRPHY_MD32_BASE_ADDRESS + 0x7170) + #define LPIF_RESERVED_170_RESERVED_X170_31_0 Fld(32, 0) //[31:0] + +#define DDRPHY_MD32_REG_LPIF_RESERVED_174 (DDRPHY_MD32_BASE_ADDRESS + 0x7174) + #define LPIF_RESERVED_174_RESERVED_X174_31_0 Fld(32, 0) //[31:0] + +#define DDRPHY_MD32_REG_LPIF_RESERVED_178 (DDRPHY_MD32_BASE_ADDRESS + 0x7178) + #define LPIF_RESERVED_178_RESERVED_X178_31_0 Fld(32, 0) //[31:0] + +#define DDRPHY_MD32_REG_LPIF_RESERVED_17C (DDRPHY_MD32_BASE_ADDRESS + 0x717C) + #define LPIF_RESERVED_17C_RESERVED_X17C_31_0 Fld(32, 0) //[31:0] + +#define DDRPHY_MD32_REG_LPIF_MR_OP_STORE_SHU_0_0 (DDRPHY_MD32_BASE_ADDRESS + 0x7180) + #define LPIF_MR_OP_STORE_SHU_0_0_MR_OP_SET_SHU_0_0 Fld(8, 0) //[7:0] + #define LPIF_MR_OP_STORE_SHU_0_0_MR_OP_SET_SHU_0_1 Fld(8, 8) //[15:8] + #define LPIF_MR_OP_STORE_SHU_0_0_MR_OP_SET_SHU_0_2 Fld(8, 16) //[23:16] + #define LPIF_MR_OP_STORE_SHU_0_0_MR_OP_SET_SHU_0_3 Fld(8, 24) //[31:24] + +#define DDRPHY_MD32_REG_LPIF_MR_OP_STORE_SHU_0_1 (DDRPHY_MD32_BASE_ADDRESS + 0x7184) + #define LPIF_MR_OP_STORE_SHU_0_1_MR_OP_SET_SHU_0_4 Fld(8, 0) //[7:0] + #define LPIF_MR_OP_STORE_SHU_0_1_MR_OP_SET_SHU_0_5 Fld(8, 8) //[15:8] + #define LPIF_MR_OP_STORE_SHU_0_1_MR_OP_SET_SHU_0_6 Fld(8, 16) //[23:16] + #define LPIF_MR_OP_STORE_SHU_0_1_MR_OP_SET_SHU_0_7 Fld(8, 24) //[31:24] + +#define DDRPHY_MD32_REG_LPIF_MR_OP_STORE_SHU_0_2 (DDRPHY_MD32_BASE_ADDRESS + 0x7188) + #define LPIF_MR_OP_STORE_SHU_0_2_MR_OP_SET_SHU_0_8 Fld(8, 0) //[7:0] + #define LPIF_MR_OP_STORE_SHU_0_2_MR_OP_SET_SHU_0_9 Fld(8, 8) //[15:8] + #define LPIF_MR_OP_STORE_SHU_0_2_MR_OP_SET_SHU_0_10 Fld(8, 16) //[23:16] + #define LPIF_MR_OP_STORE_SHU_0_2_MR_OP_SET_SHU_0_11 Fld(8, 24) //[31:24] + +#define DDRPHY_MD32_REG_LPIF_MR_OP_STORE_SHU_0_3 (DDRPHY_MD32_BASE_ADDRESS + 0x718C) + #define LPIF_MR_OP_STORE_SHU_0_3_MR_OP_SET_SHU_0_12 Fld(8, 0) //[7:0] + #define LPIF_MR_OP_STORE_SHU_0_3_MR_OP_SET_SHU_0_13 Fld(8, 8) //[15:8] + #define LPIF_MR_OP_STORE_SHU_0_3_MR_OP_SET_SHU_0_14 Fld(8, 16) //[23:16] + #define LPIF_MR_OP_STORE_SHU_0_3_MR_OP_SET_SHU_0_15 Fld(8, 24) //[31:24] + +#define DDRPHY_MD32_REG_LPIF_MR_OP_STORE_SHU_1_0 (DDRPHY_MD32_BASE_ADDRESS + 0x7190) + #define LPIF_MR_OP_STORE_SHU_1_0_MR_OP_SET_SHU_1_0 Fld(8, 0) //[7:0] + #define LPIF_MR_OP_STORE_SHU_1_0_MR_OP_SET_SHU_1_1 Fld(8, 8) //[15:8] + #define LPIF_MR_OP_STORE_SHU_1_0_MR_OP_SET_SHU_1_2 Fld(8, 16) //[23:16] + #define LPIF_MR_OP_STORE_SHU_1_0_MR_OP_SET_SHU_1_3 Fld(8, 24) //[31:24] + +#define DDRPHY_MD32_REG_LPIF_MR_OP_STORE_SHU_1_1 (DDRPHY_MD32_BASE_ADDRESS + 0x7194) + #define LPIF_MR_OP_STORE_SHU_1_1_MR_OP_SET_SHU_1_4 Fld(8, 0) //[7:0] + #define LPIF_MR_OP_STORE_SHU_1_1_MR_OP_SET_SHU_1_5 Fld(8, 8) //[15:8] + #define LPIF_MR_OP_STORE_SHU_1_1_MR_OP_SET_SHU_1_6 Fld(8, 16) //[23:16] + #define LPIF_MR_OP_STORE_SHU_1_1_MR_OP_SET_SHU_1_7 Fld(8, 24) //[31:24] + +#define DDRPHY_MD32_REG_LPIF_MR_OP_STORE_SHU_1_2 (DDRPHY_MD32_BASE_ADDRESS + 0x7198) + #define LPIF_MR_OP_STORE_SHU_1_2_MR_OP_SET_SHU_1_8 Fld(8, 0) //[7:0] + #define LPIF_MR_OP_STORE_SHU_1_2_MR_OP_SET_SHU_1_9 Fld(8, 8) //[15:8] + #define LPIF_MR_OP_STORE_SHU_1_2_MR_OP_SET_SHU_1_10 Fld(8, 16) //[23:16] + #define LPIF_MR_OP_STORE_SHU_1_2_MR_OP_SET_SHU_1_11 Fld(8, 24) //[31:24] + +#define DDRPHY_MD32_REG_LPIF_MR_OP_STORE_SHU_1_3 (DDRPHY_MD32_BASE_ADDRESS + 0x719C) + #define LPIF_MR_OP_STORE_SHU_1_3_MR_OP_SET_SHU_1_12 Fld(8, 0) //[7:0] + #define LPIF_MR_OP_STORE_SHU_1_3_MR_OP_SET_SHU_1_13 Fld(8, 8) //[15:8] + #define LPIF_MR_OP_STORE_SHU_1_3_MR_OP_SET_SHU_1_14 Fld(8, 16) //[23:16] + #define LPIF_MR_OP_STORE_SHU_1_3_MR_OP_SET_SHU_1_15 Fld(8, 24) //[31:24] + +#define DDRPHY_MD32_REG_LPIF_MR_OP_STORE_SHU_2_0 (DDRPHY_MD32_BASE_ADDRESS + 0x71A0) + #define LPIF_MR_OP_STORE_SHU_2_0_MR_OP_SET_SHU_2_0 Fld(8, 0) //[7:0] + #define LPIF_MR_OP_STORE_SHU_2_0_MR_OP_SET_SHU_2_1 Fld(8, 8) //[15:8] + #define LPIF_MR_OP_STORE_SHU_2_0_MR_OP_SET_SHU_2_2 Fld(8, 16) //[23:16] + #define LPIF_MR_OP_STORE_SHU_2_0_MR_OP_SET_SHU_2_3 Fld(8, 24) //[31:24] + +#define DDRPHY_MD32_REG_LPIF_MR_OP_STORE_SHU_2_1 (DDRPHY_MD32_BASE_ADDRESS + 0x71A4) + #define LPIF_MR_OP_STORE_SHU_2_1_MR_OP_SET_SHU_2_4 Fld(8, 0) //[7:0] + #define LPIF_MR_OP_STORE_SHU_2_1_MR_OP_SET_SHU_2_5 Fld(8, 8) //[15:8] + #define LPIF_MR_OP_STORE_SHU_2_1_MR_OP_SET_SHU_2_6 Fld(8, 16) //[23:16] + #define LPIF_MR_OP_STORE_SHU_2_1_MR_OP_SET_SHU_2_7 Fld(8, 24) //[31:24] + +#define DDRPHY_MD32_REG_LPIF_MR_OP_STORE_SHU_2_2 (DDRPHY_MD32_BASE_ADDRESS + 0x71A8) + #define LPIF_MR_OP_STORE_SHU_2_2_MR_OP_SET_SHU_2_8 Fld(8, 0) //[7:0] + #define LPIF_MR_OP_STORE_SHU_2_2_MR_OP_SET_SHU_2_9 Fld(8, 8) //[15:8] + #define LPIF_MR_OP_STORE_SHU_2_2_MR_OP_SET_SHU_2_10 Fld(8, 16) //[23:16] + #define LPIF_MR_OP_STORE_SHU_2_2_MR_OP_SET_SHU_2_11 Fld(8, 24) //[31:24] + +#define DDRPHY_MD32_REG_LPIF_MR_OP_STORE_SHU_2_3 (DDRPHY_MD32_BASE_ADDRESS + 0x71AC) + #define LPIF_MR_OP_STORE_SHU_2_3_MR_OP_SET_SHU_2_12 Fld(8, 0) //[7:0] + #define LPIF_MR_OP_STORE_SHU_2_3_MR_OP_SET_SHU_2_13 Fld(8, 8) //[15:8] + #define LPIF_MR_OP_STORE_SHU_2_3_MR_OP_SET_SHU_2_14 Fld(8, 16) //[23:16] + #define LPIF_MR_OP_STORE_SHU_2_3_MR_OP_SET_SHU_2_15 Fld(8, 24) //[31:24] + +#define DDRPHY_MD32_REG_LPIF_MR_OP_STORE_SHU_3_0 (DDRPHY_MD32_BASE_ADDRESS + 0x71B0) + #define LPIF_MR_OP_STORE_SHU_3_0_MR_OP_SET_SHU_3_0 Fld(8, 0) //[7:0] + #define LPIF_MR_OP_STORE_SHU_3_0_MR_OP_SET_SHU_3_1 Fld(8, 8) //[15:8] + #define LPIF_MR_OP_STORE_SHU_3_0_MR_OP_SET_SHU_3_2 Fld(8, 16) //[23:16] + #define LPIF_MR_OP_STORE_SHU_3_0_MR_OP_SET_SHU_3_3 Fld(8, 24) //[31:24] + +#define DDRPHY_MD32_REG_LPIF_MR_OP_STORE_SHU_3_1 (DDRPHY_MD32_BASE_ADDRESS + 0x71B4) + #define LPIF_MR_OP_STORE_SHU_3_1_MR_OP_SET_SHU_3_4 Fld(8, 0) //[7:0] + #define LPIF_MR_OP_STORE_SHU_3_1_MR_OP_SET_SHU_3_5 Fld(8, 8) //[15:8] + #define LPIF_MR_OP_STORE_SHU_3_1_MR_OP_SET_SHU_3_6 Fld(8, 16) //[23:16] + #define LPIF_MR_OP_STORE_SHU_3_1_MR_OP_SET_SHU_3_7 Fld(8, 24) //[31:24] + +#define DDRPHY_MD32_REG_LPIF_MR_OP_STORE_SHU_3_2 (DDRPHY_MD32_BASE_ADDRESS + 0x71B8) + #define LPIF_MR_OP_STORE_SHU_3_2_MR_OP_SET_SHU_3_8 Fld(8, 0) //[7:0] + #define LPIF_MR_OP_STORE_SHU_3_2_MR_OP_SET_SHU_3_9 Fld(8, 8) //[15:8] + #define LPIF_MR_OP_STORE_SHU_3_2_MR_OP_SET_SHU_3_10 Fld(8, 16) //[23:16] + #define LPIF_MR_OP_STORE_SHU_3_2_MR_OP_SET_SHU_3_11 Fld(8, 24) //[31:24] + +#define DDRPHY_MD32_REG_LPIF_MR_OP_STORE_SHU_3_3 (DDRPHY_MD32_BASE_ADDRESS + 0x71BC) + #define LPIF_MR_OP_STORE_SHU_3_3_MR_OP_SET_SHU_3_12 Fld(8, 0) //[7:0] + #define LPIF_MR_OP_STORE_SHU_3_3_MR_OP_SET_SHU_3_13 Fld(8, 8) //[15:8] + #define LPIF_MR_OP_STORE_SHU_3_3_MR_OP_SET_SHU_3_14 Fld(8, 16) //[23:16] + #define LPIF_MR_OP_STORE_SHU_3_3_MR_OP_SET_SHU_3_15 Fld(8, 24) //[31:24] + +#define DDRPHY_MD32_REG_LPIF_MR_OP_STORE_SHU_4_0 (DDRPHY_MD32_BASE_ADDRESS + 0x71C0) + #define LPIF_MR_OP_STORE_SHU_4_0_MR_OP_SET_SHU_4_0 Fld(8, 0) //[7:0] + #define LPIF_MR_OP_STORE_SHU_4_0_MR_OP_SET_SHU_4_1 Fld(8, 8) //[15:8] + #define LPIF_MR_OP_STORE_SHU_4_0_MR_OP_SET_SHU_4_2 Fld(8, 16) //[23:16] + #define LPIF_MR_OP_STORE_SHU_4_0_MR_OP_SET_SHU_4_3 Fld(8, 24) //[31:24] + +#define DDRPHY_MD32_REG_LPIF_MR_OP_STORE_SHU_4_1 (DDRPHY_MD32_BASE_ADDRESS + 0x71C4) + #define LPIF_MR_OP_STORE_SHU_4_1_MR_OP_SET_SHU_4_4 Fld(8, 0) //[7:0] + #define LPIF_MR_OP_STORE_SHU_4_1_MR_OP_SET_SHU_4_5 Fld(8, 8) //[15:8] + #define LPIF_MR_OP_STORE_SHU_4_1_MR_OP_SET_SHU_4_6 Fld(8, 16) //[23:16] + #define LPIF_MR_OP_STORE_SHU_4_1_MR_OP_SET_SHU_4_7 Fld(8, 24) //[31:24] + +#define DDRPHY_MD32_REG_LPIF_MR_OP_STORE_SHU_4_2 (DDRPHY_MD32_BASE_ADDRESS + 0x71C8) + #define LPIF_MR_OP_STORE_SHU_4_2_MR_OP_SET_SHU_4_8 Fld(8, 0) //[7:0] + #define LPIF_MR_OP_STORE_SHU_4_2_MR_OP_SET_SHU_4_9 Fld(8, 8) //[15:8] + #define LPIF_MR_OP_STORE_SHU_4_2_MR_OP_SET_SHU_4_10 Fld(8, 16) //[23:16] + #define LPIF_MR_OP_STORE_SHU_4_2_MR_OP_SET_SHU_4_11 Fld(8, 24) //[31:24] + +#define DDRPHY_MD32_REG_LPIF_MR_OP_STORE_SHU_4_3 (DDRPHY_MD32_BASE_ADDRESS + 0x71CC) + #define LPIF_MR_OP_STORE_SHU_4_3_MR_OP_SET_SHU_4_12 Fld(8, 0) //[7:0] + #define LPIF_MR_OP_STORE_SHU_4_3_MR_OP_SET_SHU_4_13 Fld(8, 8) //[15:8] + #define LPIF_MR_OP_STORE_SHU_4_3_MR_OP_SET_SHU_4_14 Fld(8, 16) //[23:16] + #define LPIF_MR_OP_STORE_SHU_4_3_MR_OP_SET_SHU_4_15 Fld(8, 24) //[31:24] + +#define DDRPHY_MD32_REG_LPIF_MR_OP_STORE_SHU_5_0 (DDRPHY_MD32_BASE_ADDRESS + 0x71D0) + #define LPIF_MR_OP_STORE_SHU_5_0_MR_OP_SET_SHU_5_0 Fld(8, 0) //[7:0] + #define LPIF_MR_OP_STORE_SHU_5_0_MR_OP_SET_SHU_5_1 Fld(8, 8) //[15:8] + #define LPIF_MR_OP_STORE_SHU_5_0_MR_OP_SET_SHU_5_2 Fld(8, 16) //[23:16] + #define LPIF_MR_OP_STORE_SHU_5_0_MR_OP_SET_SHU_5_3 Fld(8, 24) //[31:24] + +#define DDRPHY_MD32_REG_LPIF_MR_OP_STORE_SHU_5_1 (DDRPHY_MD32_BASE_ADDRESS + 0x71D4) + #define LPIF_MR_OP_STORE_SHU_5_1_MR_OP_SET_SHU_5_4 Fld(8, 0) //[7:0] + #define LPIF_MR_OP_STORE_SHU_5_1_MR_OP_SET_SHU_5_5 Fld(8, 8) //[15:8] + #define LPIF_MR_OP_STORE_SHU_5_1_MR_OP_SET_SHU_5_6 Fld(8, 16) //[23:16] + #define LPIF_MR_OP_STORE_SHU_5_1_MR_OP_SET_SHU_5_7 Fld(8, 24) //[31:24] + +#define DDRPHY_MD32_REG_LPIF_MR_OP_STORE_SHU_5_2 (DDRPHY_MD32_BASE_ADDRESS + 0x71D8) + #define LPIF_MR_OP_STORE_SHU_5_2_MR_OP_SET_SHU_5_8 Fld(8, 0) //[7:0] + #define LPIF_MR_OP_STORE_SHU_5_2_MR_OP_SET_SHU_5_9 Fld(8, 8) //[15:8] + #define LPIF_MR_OP_STORE_SHU_5_2_MR_OP_SET_SHU_5_10 Fld(8, 16) //[23:16] + #define LPIF_MR_OP_STORE_SHU_5_2_MR_OP_SET_SHU_5_11 Fld(8, 24) //[31:24] + +#define DDRPHY_MD32_REG_LPIF_MR_OP_STORE_SHU_5_3 (DDRPHY_MD32_BASE_ADDRESS + 0x71DC) + #define LPIF_MR_OP_STORE_SHU_5_3_MR_OP_SET_SHU_5_12 Fld(8, 0) //[7:0] + #define LPIF_MR_OP_STORE_SHU_5_3_MR_OP_SET_SHU_5_13 Fld(8, 8) //[15:8] + #define LPIF_MR_OP_STORE_SHU_5_3_MR_OP_SET_SHU_5_14 Fld(8, 16) //[23:16] + #define LPIF_MR_OP_STORE_SHU_5_3_MR_OP_SET_SHU_5_15 Fld(8, 24) //[31:24] + +#define DDRPHY_MD32_REG_LPIF_MR_OP_STORE_SHU_6_0 (DDRPHY_MD32_BASE_ADDRESS + 0x71E0) + #define LPIF_MR_OP_STORE_SHU_6_0_MR_OP_SET_SHU_6_0 Fld(8, 0) //[7:0] + #define LPIF_MR_OP_STORE_SHU_6_0_MR_OP_SET_SHU_6_1 Fld(8, 8) //[15:8] + #define LPIF_MR_OP_STORE_SHU_6_0_MR_OP_SET_SHU_6_2 Fld(8, 16) //[23:16] + #define LPIF_MR_OP_STORE_SHU_6_0_MR_OP_SET_SHU_6_3 Fld(8, 24) //[31:24] + +#define DDRPHY_MD32_REG_LPIF_MR_OP_STORE_SHU_6_1 (DDRPHY_MD32_BASE_ADDRESS + 0x71E4) + #define LPIF_MR_OP_STORE_SHU_6_1_MR_OP_SET_SHU_6_4 Fld(8, 0) //[7:0] + #define LPIF_MR_OP_STORE_SHU_6_1_MR_OP_SET_SHU_6_5 Fld(8, 8) //[15:8] + #define LPIF_MR_OP_STORE_SHU_6_1_MR_OP_SET_SHU_6_6 Fld(8, 16) //[23:16] + #define LPIF_MR_OP_STORE_SHU_6_1_MR_OP_SET_SHU_6_7 Fld(8, 24) //[31:24] + +#define DDRPHY_MD32_REG_LPIF_MR_OP_STORE_SHU_6_2 (DDRPHY_MD32_BASE_ADDRESS + 0x71E8) + #define LPIF_MR_OP_STORE_SHU_6_2_MR_OP_SET_SHU_6_8 Fld(8, 0) //[7:0] + #define LPIF_MR_OP_STORE_SHU_6_2_MR_OP_SET_SHU_6_9 Fld(8, 8) //[15:8] + #define LPIF_MR_OP_STORE_SHU_6_2_MR_OP_SET_SHU_6_10 Fld(8, 16) //[23:16] + #define LPIF_MR_OP_STORE_SHU_6_2_MR_OP_SET_SHU_6_11 Fld(8, 24) //[31:24] + +#define DDRPHY_MD32_REG_LPIF_MR_OP_STORE_SHU_6_3 (DDRPHY_MD32_BASE_ADDRESS + 0x71EC) + #define LPIF_MR_OP_STORE_SHU_6_3_MR_OP_SET_SHU_6_12 Fld(8, 0) //[7:0] + #define LPIF_MR_OP_STORE_SHU_6_3_MR_OP_SET_SHU_6_13 Fld(8, 8) //[15:8] + #define LPIF_MR_OP_STORE_SHU_6_3_MR_OP_SET_SHU_6_14 Fld(8, 16) //[23:16] + #define LPIF_MR_OP_STORE_SHU_6_3_MR_OP_SET_SHU_6_15 Fld(8, 24) //[31:24] + +#define DDRPHY_MD32_REG_LPIF_MR_OP_STORE_SHU_7_0 (DDRPHY_MD32_BASE_ADDRESS + 0x71F0) + #define LPIF_MR_OP_STORE_SHU_7_0_MR_OP_SET_SHU_7_0 Fld(8, 0) //[7:0] + #define LPIF_MR_OP_STORE_SHU_7_0_MR_OP_SET_SHU_7_1 Fld(8, 8) //[15:8] + #define LPIF_MR_OP_STORE_SHU_7_0_MR_OP_SET_SHU_7_2 Fld(8, 16) //[23:16] + #define LPIF_MR_OP_STORE_SHU_7_0_MR_OP_SET_SHU_7_3 Fld(8, 24) //[31:24] + +#define DDRPHY_MD32_REG_LPIF_MR_OP_STORE_SHU_7_1 (DDRPHY_MD32_BASE_ADDRESS + 0x71F4) + #define LPIF_MR_OP_STORE_SHU_7_1_MR_OP_SET_SHU_7_4 Fld(8, 0) //[7:0] + #define LPIF_MR_OP_STORE_SHU_7_1_MR_OP_SET_SHU_7_5 Fld(8, 8) //[15:8] + #define LPIF_MR_OP_STORE_SHU_7_1_MR_OP_SET_SHU_7_6 Fld(8, 16) //[23:16] + #define LPIF_MR_OP_STORE_SHU_7_1_MR_OP_SET_SHU_7_7 Fld(8, 24) //[31:24] + +#define DDRPHY_MD32_REG_LPIF_MR_OP_STORE_SHU_7_2 (DDRPHY_MD32_BASE_ADDRESS + 0x71F8) + #define LPIF_MR_OP_STORE_SHU_7_2_MR_OP_SET_SHU_7_8 Fld(8, 0) //[7:0] + #define LPIF_MR_OP_STORE_SHU_7_2_MR_OP_SET_SHU_7_9 Fld(8, 8) //[15:8] + #define LPIF_MR_OP_STORE_SHU_7_2_MR_OP_SET_SHU_7_10 Fld(8, 16) //[23:16] + #define LPIF_MR_OP_STORE_SHU_7_2_MR_OP_SET_SHU_7_11 Fld(8, 24) //[31:24] + +#define DDRPHY_MD32_REG_LPIF_MR_OP_STORE_SHU_7_3 (DDRPHY_MD32_BASE_ADDRESS + 0x71FC) + #define LPIF_MR_OP_STORE_SHU_7_3_MR_OP_SET_SHU_7_12 Fld(8, 0) //[7:0] + #define LPIF_MR_OP_STORE_SHU_7_3_MR_OP_SET_SHU_7_13 Fld(8, 8) //[15:8] + #define LPIF_MR_OP_STORE_SHU_7_3_MR_OP_SET_SHU_7_14 Fld(8, 16) //[23:16] + #define LPIF_MR_OP_STORE_SHU_7_3_MR_OP_SET_SHU_7_15 Fld(8, 24) //[31:24] + +#define DDRPHY_MD32_REG_LPIF_MR_OP_STORE_SHU_8_0 (DDRPHY_MD32_BASE_ADDRESS + 0x7200) + #define LPIF_MR_OP_STORE_SHU_8_0_MR_OP_SET_SHU_8_0 Fld(8, 0) //[7:0] + #define LPIF_MR_OP_STORE_SHU_8_0_MR_OP_SET_SHU_8_1 Fld(8, 8) //[15:8] + #define LPIF_MR_OP_STORE_SHU_8_0_MR_OP_SET_SHU_8_2 Fld(8, 16) //[23:16] + #define LPIF_MR_OP_STORE_SHU_8_0_MR_OP_SET_SHU_8_3 Fld(8, 24) //[31:24] + +#define DDRPHY_MD32_REG_LPIF_MR_OP_STORE_SHU_8_1 (DDRPHY_MD32_BASE_ADDRESS + 0x7204) + #define LPIF_MR_OP_STORE_SHU_8_1_MR_OP_SET_SHU_8_4 Fld(8, 0) //[7:0] + #define LPIF_MR_OP_STORE_SHU_8_1_MR_OP_SET_SHU_8_5 Fld(8, 8) //[15:8] + #define LPIF_MR_OP_STORE_SHU_8_1_MR_OP_SET_SHU_8_6 Fld(8, 16) //[23:16] + #define LPIF_MR_OP_STORE_SHU_8_1_MR_OP_SET_SHU_8_7 Fld(8, 24) //[31:24] + +#define DDRPHY_MD32_REG_LPIF_MR_OP_STORE_SHU_8_2 (DDRPHY_MD32_BASE_ADDRESS + 0x7208) + #define LPIF_MR_OP_STORE_SHU_8_2_MR_OP_SET_SHU_8_8 Fld(8, 0) //[7:0] + #define LPIF_MR_OP_STORE_SHU_8_2_MR_OP_SET_SHU_8_9 Fld(8, 8) //[15:8] + #define LPIF_MR_OP_STORE_SHU_8_2_MR_OP_SET_SHU_8_10 Fld(8, 16) //[23:16] + #define LPIF_MR_OP_STORE_SHU_8_2_MR_OP_SET_SHU_8_11 Fld(8, 24) //[31:24] + +#define DDRPHY_MD32_REG_LPIF_MR_OP_STORE_SHU_8_3 (DDRPHY_MD32_BASE_ADDRESS + 0x720C) + #define LPIF_MR_OP_STORE_SHU_8_3_MR_OP_SET_SHU_8_12 Fld(8, 0) //[7:0] + #define LPIF_MR_OP_STORE_SHU_8_3_MR_OP_SET_SHU_8_13 Fld(8, 8) //[15:8] + #define LPIF_MR_OP_STORE_SHU_8_3_MR_OP_SET_SHU_8_14 Fld(8, 16) //[23:16] + #define LPIF_MR_OP_STORE_SHU_8_3_MR_OP_SET_SHU_8_15 Fld(8, 24) //[31:24] + +#define DDRPHY_MD32_REG_LPIF_MR_OP_STORE_SHU_9_0 (DDRPHY_MD32_BASE_ADDRESS + 0x7210) + #define LPIF_MR_OP_STORE_SHU_9_0_MR_OP_SET_SHU_9_0 Fld(8, 0) //[7:0] + #define LPIF_MR_OP_STORE_SHU_9_0_MR_OP_SET_SHU_9_1 Fld(8, 8) //[15:8] + #define LPIF_MR_OP_STORE_SHU_9_0_MR_OP_SET_SHU_9_2 Fld(8, 16) //[23:16] + #define LPIF_MR_OP_STORE_SHU_9_0_MR_OP_SET_SHU_9_3 Fld(8, 24) //[31:24] + +#define DDRPHY_MD32_REG_LPIF_MR_OP_STORE_SHU_9_1 (DDRPHY_MD32_BASE_ADDRESS + 0x7214) + #define LPIF_MR_OP_STORE_SHU_9_1_MR_OP_SET_SHU_9_4 Fld(8, 0) //[7:0] + #define LPIF_MR_OP_STORE_SHU_9_1_MR_OP_SET_SHU_9_5 Fld(8, 8) //[15:8] + #define LPIF_MR_OP_STORE_SHU_9_1_MR_OP_SET_SHU_9_6 Fld(8, 16) //[23:16] + #define LPIF_MR_OP_STORE_SHU_9_1_MR_OP_SET_SHU_9_7 Fld(8, 24) //[31:24] + +#define DDRPHY_MD32_REG_LPIF_MR_OP_STORE_SHU_9_2 (DDRPHY_MD32_BASE_ADDRESS + 0x7218) + #define LPIF_MR_OP_STORE_SHU_9_2_MR_OP_SET_SHU_9_8 Fld(8, 0) //[7:0] + #define LPIF_MR_OP_STORE_SHU_9_2_MR_OP_SET_SHU_9_9 Fld(8, 8) //[15:8] + #define LPIF_MR_OP_STORE_SHU_9_2_MR_OP_SET_SHU_9_10 Fld(8, 16) //[23:16] + #define LPIF_MR_OP_STORE_SHU_9_2_MR_OP_SET_SHU_9_11 Fld(8, 24) //[31:24] + +#define DDRPHY_MD32_REG_LPIF_MR_OP_STORE_SHU_9_3 (DDRPHY_MD32_BASE_ADDRESS + 0x721C) + #define LPIF_MR_OP_STORE_SHU_9_3_MR_OP_SET_SHU_9_12 Fld(8, 0) //[7:0] + #define LPIF_MR_OP_STORE_SHU_9_3_MR_OP_SET_SHU_9_13 Fld(8, 8) //[15:8] + #define LPIF_MR_OP_STORE_SHU_9_3_MR_OP_SET_SHU_9_14 Fld(8, 16) //[23:16] + #define LPIF_MR_OP_STORE_SHU_9_3_MR_OP_SET_SHU_9_15 Fld(8, 24) //[31:24] + +#define DDRPHY_MD32_REG_LPIF_MR_OP_STORE_SHU_10_0 (DDRPHY_MD32_BASE_ADDRESS + 0x7220) + #define LPIF_MR_OP_STORE_SHU_10_0_MR_OP_SET_SHU_10_0 Fld(8, 0) //[7:0] + #define LPIF_MR_OP_STORE_SHU_10_0_MR_OP_SET_SHU_10_1 Fld(8, 8) //[15:8] + #define LPIF_MR_OP_STORE_SHU_10_0_MR_OP_SET_SHU_10_2 Fld(8, 16) //[23:16] + #define LPIF_MR_OP_STORE_SHU_10_0_MR_OP_SET_SHU_10_3 Fld(8, 24) //[31:24] + +#define DDRPHY_MD32_REG_LPIF_MR_OP_STORE_SHU_10_1 (DDRPHY_MD32_BASE_ADDRESS + 0x7224) + #define LPIF_MR_OP_STORE_SHU_10_1_MR_OP_SET_SHU_10_4 Fld(8, 0) //[7:0] + #define LPIF_MR_OP_STORE_SHU_10_1_MR_OP_SET_SHU_10_5 Fld(8, 8) //[15:8] + #define LPIF_MR_OP_STORE_SHU_10_1_MR_OP_SET_SHU_10_6 Fld(8, 16) //[23:16] + #define LPIF_MR_OP_STORE_SHU_10_1_MR_OP_SET_SHU_10_7 Fld(8, 24) //[31:24] + +#define DDRPHY_MD32_REG_LPIF_MR_OP_STORE_SHU_10_2 (DDRPHY_MD32_BASE_ADDRESS + 0x7228) + #define LPIF_MR_OP_STORE_SHU_10_2_MR_OP_SET_SHU_10_8 Fld(8, 0) //[7:0] + #define LPIF_MR_OP_STORE_SHU_10_2_MR_OP_SET_SHU_10_9 Fld(8, 8) //[15:8] + #define LPIF_MR_OP_STORE_SHU_10_2_MR_OP_SET_SHU_10_10 Fld(8, 16) //[23:16] + #define LPIF_MR_OP_STORE_SHU_10_2_MR_OP_SET_SHU_10_11 Fld(8, 24) //[31:24] + +#define DDRPHY_MD32_REG_LPIF_MR_OP_STORE_SHU_10_3 (DDRPHY_MD32_BASE_ADDRESS + 0x722C) + #define LPIF_MR_OP_STORE_SHU_10_3_MR_OP_SET_SHU_10_12 Fld(8, 0) //[7:0] + #define LPIF_MR_OP_STORE_SHU_10_3_MR_OP_SET_SHU_10_13 Fld(8, 8) //[15:8] + #define LPIF_MR_OP_STORE_SHU_10_3_MR_OP_SET_SHU_10_14 Fld(8, 16) //[23:16] + #define LPIF_MR_OP_STORE_SHU_10_3_MR_OP_SET_SHU_10_15 Fld(8, 24) //[31:24] + +#define DDRPHY_MD32_REG_LPIF_MR_OP_STORE_SHU_11_0 (DDRPHY_MD32_BASE_ADDRESS + 0x7230) + #define LPIF_MR_OP_STORE_SHU_11_0_MR_OP_SET_SHU_11_0 Fld(8, 0) //[7:0] + #define LPIF_MR_OP_STORE_SHU_11_0_MR_OP_SET_SHU_11_1 Fld(8, 8) //[15:8] + #define LPIF_MR_OP_STORE_SHU_11_0_MR_OP_SET_SHU_11_2 Fld(8, 16) //[23:16] + #define LPIF_MR_OP_STORE_SHU_11_0_MR_OP_SET_SHU_11_3 Fld(8, 24) //[31:24] + +#define DDRPHY_MD32_REG_LPIF_MR_OP_STORE_SHU_11_1 (DDRPHY_MD32_BASE_ADDRESS + 0x7234) + #define LPIF_MR_OP_STORE_SHU_11_1_MR_OP_SET_SHU_11_4 Fld(8, 0) //[7:0] + #define LPIF_MR_OP_STORE_SHU_11_1_MR_OP_SET_SHU_11_5 Fld(8, 8) //[15:8] + #define LPIF_MR_OP_STORE_SHU_11_1_MR_OP_SET_SHU_11_6 Fld(8, 16) //[23:16] + #define LPIF_MR_OP_STORE_SHU_11_1_MR_OP_SET_SHU_11_7 Fld(8, 24) //[31:24] + +#define DDRPHY_MD32_REG_LPIF_MR_OP_STORE_SHU_11_2 (DDRPHY_MD32_BASE_ADDRESS + 0x7238) + #define LPIF_MR_OP_STORE_SHU_11_2_MR_OP_SET_SHU_11_8 Fld(8, 0) //[7:0] + #define LPIF_MR_OP_STORE_SHU_11_2_MR_OP_SET_SHU_11_9 Fld(8, 8) //[15:8] + #define LPIF_MR_OP_STORE_SHU_11_2_MR_OP_SET_SHU_11_10 Fld(8, 16) //[23:16] + #define LPIF_MR_OP_STORE_SHU_11_2_MR_OP_SET_SHU_11_11 Fld(8, 24) //[31:24] + +#define DDRPHY_MD32_REG_LPIF_MR_OP_STORE_SHU_11_3 (DDRPHY_MD32_BASE_ADDRESS + 0x723C) + #define LPIF_MR_OP_STORE_SHU_11_3_MR_OP_SET_SHU_11_12 Fld(8, 0) //[7:0] + #define LPIF_MR_OP_STORE_SHU_11_3_MR_OP_SET_SHU_11_13 Fld(8, 8) //[15:8] + #define LPIF_MR_OP_STORE_SHU_11_3_MR_OP_SET_SHU_11_14 Fld(8, 16) //[23:16] + #define LPIF_MR_OP_STORE_SHU_11_3_MR_OP_SET_SHU_11_15 Fld(8, 24) //[31:24] + +#define DDRPHY_MD32_REG_LPIF_MR_OP_STORE_SHU_12_0 (DDRPHY_MD32_BASE_ADDRESS + 0x7240) + #define LPIF_MR_OP_STORE_SHU_12_0_MR_OP_SET_SHU_12_0 Fld(8, 0) //[7:0] + #define LPIF_MR_OP_STORE_SHU_12_0_MR_OP_SET_SHU_12_1 Fld(8, 8) //[15:8] + #define LPIF_MR_OP_STORE_SHU_12_0_MR_OP_SET_SHU_12_2 Fld(8, 16) //[23:16] + #define LPIF_MR_OP_STORE_SHU_12_0_MR_OP_SET_SHU_12_3 Fld(8, 24) //[31:24] + +#define DDRPHY_MD32_REG_LPIF_MR_OP_STORE_SHU_12_1 (DDRPHY_MD32_BASE_ADDRESS + 0x7244) + #define LPIF_MR_OP_STORE_SHU_12_1_MR_OP_SET_SHU_12_4 Fld(8, 0) //[7:0] + #define LPIF_MR_OP_STORE_SHU_12_1_MR_OP_SET_SHU_12_5 Fld(8, 8) //[15:8] + #define LPIF_MR_OP_STORE_SHU_12_1_MR_OP_SET_SHU_12_6 Fld(8, 16) //[23:16] + #define LPIF_MR_OP_STORE_SHU_12_1_MR_OP_SET_SHU_12_7 Fld(8, 24) //[31:24] + +#define DDRPHY_MD32_REG_LPIF_MR_OP_STORE_SHU_12_2 (DDRPHY_MD32_BASE_ADDRESS + 0x7248) + #define LPIF_MR_OP_STORE_SHU_12_2_MR_OP_SET_SHU_12_8 Fld(8, 0) //[7:0] + #define LPIF_MR_OP_STORE_SHU_12_2_MR_OP_SET_SHU_12_9 Fld(8, 8) //[15:8] + #define LPIF_MR_OP_STORE_SHU_12_2_MR_OP_SET_SHU_12_10 Fld(8, 16) //[23:16] + #define LPIF_MR_OP_STORE_SHU_12_2_MR_OP_SET_SHU_12_11 Fld(8, 24) //[31:24] + +#define DDRPHY_MD32_REG_LPIF_MR_OP_STORE_SHU_12_3 (DDRPHY_MD32_BASE_ADDRESS + 0x724C) + #define LPIF_MR_OP_STORE_SHU_12_3_MR_OP_SET_SHU_12_12 Fld(8, 0) //[7:0] + #define LPIF_MR_OP_STORE_SHU_12_3_MR_OP_SET_SHU_12_13 Fld(8, 8) //[15:8] + #define LPIF_MR_OP_STORE_SHU_12_3_MR_OP_SET_SHU_12_14 Fld(8, 16) //[23:16] + #define LPIF_MR_OP_STORE_SHU_12_3_MR_OP_SET_SHU_12_15 Fld(8, 24) //[31:24] + +#define DDRPHY_MD32_REG_LPIF_MR_OP_STORE_SHU_13_0 (DDRPHY_MD32_BASE_ADDRESS + 0x7250) + #define LPIF_MR_OP_STORE_SHU_13_0_MR_OP_SET_SHU_13_0 Fld(8, 0) //[7:0] + #define LPIF_MR_OP_STORE_SHU_13_0_MR_OP_SET_SHU_13_1 Fld(8, 8) //[15:8] + #define LPIF_MR_OP_STORE_SHU_13_0_MR_OP_SET_SHU_13_2 Fld(8, 16) //[23:16] + #define LPIF_MR_OP_STORE_SHU_13_0_MR_OP_SET_SHU_13_3 Fld(8, 24) //[31:24] + +#define DDRPHY_MD32_REG_LPIF_MR_OP_STORE_SHU_13_1 (DDRPHY_MD32_BASE_ADDRESS + 0x7254) + #define LPIF_MR_OP_STORE_SHU_13_1_MR_OP_SET_SHU_13_4 Fld(8, 0) //[7:0] + #define LPIF_MR_OP_STORE_SHU_13_1_MR_OP_SET_SHU_13_5 Fld(8, 8) //[15:8] + #define LPIF_MR_OP_STORE_SHU_13_1_MR_OP_SET_SHU_13_6 Fld(8, 16) //[23:16] + #define LPIF_MR_OP_STORE_SHU_13_1_MR_OP_SET_SHU_13_7 Fld(8, 24) //[31:24] + +#define DDRPHY_MD32_REG_LPIF_MR_OP_STORE_SHU_13_2 (DDRPHY_MD32_BASE_ADDRESS + 0x7258) + #define LPIF_MR_OP_STORE_SHU_13_2_MR_OP_SET_SHU_13_8 Fld(8, 0) //[7:0] + #define LPIF_MR_OP_STORE_SHU_13_2_MR_OP_SET_SHU_13_9 Fld(8, 8) //[15:8] + #define LPIF_MR_OP_STORE_SHU_13_2_MR_OP_SET_SHU_13_10 Fld(8, 16) //[23:16] + #define LPIF_MR_OP_STORE_SHU_13_2_MR_OP_SET_SHU_13_11 Fld(8, 24) //[31:24] + +#define DDRPHY_MD32_REG_LPIF_MR_OP_STORE_SHU_13_3 (DDRPHY_MD32_BASE_ADDRESS + 0x725C) + #define LPIF_MR_OP_STORE_SHU_13_3_MR_OP_SET_SHU_13_12 Fld(8, 0) //[7:0] + #define LPIF_MR_OP_STORE_SHU_13_3_MR_OP_SET_SHU_13_13 Fld(8, 8) //[15:8] + #define LPIF_MR_OP_STORE_SHU_13_3_MR_OP_SET_SHU_13_14 Fld(8, 16) //[23:16] + #define LPIF_MR_OP_STORE_SHU_13_3_MR_OP_SET_SHU_13_15 Fld(8, 24) //[31:24] + +#define DDRPHY_MD32_REG_LPIF_MR_OP_STORE_SHU_14_0 (DDRPHY_MD32_BASE_ADDRESS + 0x7260) + #define LPIF_MR_OP_STORE_SHU_14_0_MR_OP_SET_SHU_14_0 Fld(8, 0) //[7:0] + #define LPIF_MR_OP_STORE_SHU_14_0_MR_OP_SET_SHU_14_1 Fld(8, 8) //[15:8] + #define LPIF_MR_OP_STORE_SHU_14_0_MR_OP_SET_SHU_14_2 Fld(8, 16) //[23:16] + #define LPIF_MR_OP_STORE_SHU_14_0_MR_OP_SET_SHU_14_3 Fld(8, 24) //[31:24] + +#define DDRPHY_MD32_REG_LPIF_MR_OP_STORE_SHU_14_1 (DDRPHY_MD32_BASE_ADDRESS + 0x7264) + #define LPIF_MR_OP_STORE_SHU_14_1_MR_OP_SET_SHU_14_4 Fld(8, 0) //[7:0] + #define LPIF_MR_OP_STORE_SHU_14_1_MR_OP_SET_SHU_14_5 Fld(8, 8) //[15:8] + #define LPIF_MR_OP_STORE_SHU_14_1_MR_OP_SET_SHU_14_6 Fld(8, 16) //[23:16] + #define LPIF_MR_OP_STORE_SHU_14_1_MR_OP_SET_SHU_14_7 Fld(8, 24) //[31:24] + +#define DDRPHY_MD32_REG_LPIF_MR_OP_STORE_SHU_14_2 (DDRPHY_MD32_BASE_ADDRESS + 0x7268) + #define LPIF_MR_OP_STORE_SHU_14_2_MR_OP_SET_SHU_14_8 Fld(8, 0) //[7:0] + #define LPIF_MR_OP_STORE_SHU_14_2_MR_OP_SET_SHU_14_9 Fld(8, 8) //[15:8] + #define LPIF_MR_OP_STORE_SHU_14_2_MR_OP_SET_SHU_14_10 Fld(8, 16) //[23:16] + #define LPIF_MR_OP_STORE_SHU_14_2_MR_OP_SET_SHU_14_11 Fld(8, 24) //[31:24] + +#define DDRPHY_MD32_REG_LPIF_MR_OP_STORE_SHU_14_3 (DDRPHY_MD32_BASE_ADDRESS + 0x726C) + #define LPIF_MR_OP_STORE_SHU_14_3_MR_OP_SET_SHU_14_12 Fld(8, 0) //[7:0] + #define LPIF_MR_OP_STORE_SHU_14_3_MR_OP_SET_SHU_14_13 Fld(8, 8) //[15:8] + #define LPIF_MR_OP_STORE_SHU_14_3_MR_OP_SET_SHU_14_14 Fld(8, 16) //[23:16] + #define LPIF_MR_OP_STORE_SHU_14_3_MR_OP_SET_SHU_14_15 Fld(8, 24) //[31:24] + +#define DDRPHY_MD32_REG_LPIF_MR_OP_STORE_SHU_15_0 (DDRPHY_MD32_BASE_ADDRESS + 0x7270) + #define LPIF_MR_OP_STORE_SHU_15_0_MR_OP_SET_SHU_15_0 Fld(8, 0) //[7:0] + #define LPIF_MR_OP_STORE_SHU_15_0_MR_OP_SET_SHU_15_1 Fld(8, 8) //[15:8] + #define LPIF_MR_OP_STORE_SHU_15_0_MR_OP_SET_SHU_15_2 Fld(8, 16) //[23:16] + #define LPIF_MR_OP_STORE_SHU_15_0_MR_OP_SET_SHU_15_3 Fld(8, 24) //[31:24] + +#define DDRPHY_MD32_REG_LPIF_MR_OP_STORE_SHU_15_1 (DDRPHY_MD32_BASE_ADDRESS + 0x7274) + #define LPIF_MR_OP_STORE_SHU_15_1_MR_OP_SET_SHU_15_4 Fld(8, 0) //[7:0] + #define LPIF_MR_OP_STORE_SHU_15_1_MR_OP_SET_SHU_15_5 Fld(8, 8) //[15:8] + #define LPIF_MR_OP_STORE_SHU_15_1_MR_OP_SET_SHU_15_6 Fld(8, 16) //[23:16] + #define LPIF_MR_OP_STORE_SHU_15_1_MR_OP_SET_SHU_15_7 Fld(8, 24) //[31:24] + +#define DDRPHY_MD32_REG_LPIF_MR_OP_STORE_SHU_15_2 (DDRPHY_MD32_BASE_ADDRESS + 0x7278) + #define LPIF_MR_OP_STORE_SHU_15_2_MR_OP_SET_SHU_15_8 Fld(8, 0) //[7:0] + #define LPIF_MR_OP_STORE_SHU_15_2_MR_OP_SET_SHU_15_9 Fld(8, 8) //[15:8] + #define LPIF_MR_OP_STORE_SHU_15_2_MR_OP_SET_SHU_15_10 Fld(8, 16) //[23:16] + #define LPIF_MR_OP_STORE_SHU_15_2_MR_OP_SET_SHU_15_11 Fld(8, 24) //[31:24] + +#define DDRPHY_MD32_REG_LPIF_MR_OP_STORE_SHU_15_3 (DDRPHY_MD32_BASE_ADDRESS + 0x727C) + #define LPIF_MR_OP_STORE_SHU_15_3_MR_OP_SET_SHU_15_12 Fld(8, 0) //[7:0] + #define LPIF_MR_OP_STORE_SHU_15_3_MR_OP_SET_SHU_15_13 Fld(8, 8) //[15:8] + #define LPIF_MR_OP_STORE_SHU_15_3_MR_OP_SET_SHU_15_14 Fld(8, 16) //[23:16] + #define LPIF_MR_OP_STORE_SHU_15_3_MR_OP_SET_SHU_15_15 Fld(8, 24) //[31:24] + +#define DDRPHY_MD32_REG_LPIF_INT_PSTA_0 (DDRPHY_MD32_BASE_ADDRESS + 0x7280) + #define LPIF_INT_PSTA_0_PSTA_CLK_26M_EN Fld(1, 0) //[0:0] + #define LPIF_INT_PSTA_0_PSTA_IN_SYNC_BYPASS Fld(1, 1) //[1:1] + #define LPIF_INT_PSTA_0_PSTA_TEST_TRIGGER_EN Fld(1, 2) //[2:2] + #define LPIF_INT_PSTA_0_PTA_ABORT_CASE_EN Fld(1, 3) //[3:3] + #define LPIF_INT_PSTA_0_PSTA_ABORT_TIME_RAND_EN Fld(1, 4) //[4:4] + #define LPIF_INT_PSTA_0_PSTA_PST_TO_REQ_TIME_RAND_EN Fld(1, 5) //[5:5] + #define LPIF_INT_PSTA_0_PSTA_REQ_TO_NXT_PST_TIME_RAND_EN Fld(1, 6) //[6:6] + #define LPIF_INT_PSTA_0_PSTA_ACK_TO_PST_REQ_LOW_TIME_RAND_EN Fld(1, 7) //[7:7] + #define LPIF_INT_PSTA_0_PSTA_LOOP_MODE_ENABLE Fld(1, 8) //[8:8] + #define LPIF_INT_PSTA_0_PSTA_TEST_CLR Fld(1, 9) //[9:9] + #define LPIF_INT_PSTA_0_RESERVED_XA0_11_10 Fld(2, 10) //[11:10] + #define LPIF_INT_PSTA_0_PSTA_HW_S1_TEST_EN Fld(1, 12) //[12:12] + #define LPIF_INT_PSTA_0_PSTA_HW_S1_HIGH_PERIOD_TIME_RAND_EN Fld(1, 13) //[13:13] + #define LPIF_INT_PSTA_0_PSTA_HW_S1_REQ_INTV_TIME_RAND_EN Fld(1, 14) //[14:14] + #define LPIF_INT_PSTA_0_PSTA_HW_S1_BYPASS_LOW_ACK_CHK Fld(1, 15) //[15:15] + #define LPIF_INT_PSTA_0_PSTA_TEST_CND_0_EN Fld(1, 16) //[16:16] + #define LPIF_INT_PSTA_0_PSTA_TEST_CND_1_EN Fld(1, 17) //[17:17] + #define LPIF_INT_PSTA_0_PSTA_TEST_CND_2_EN Fld(1, 18) //[18:18] + #define LPIF_INT_PSTA_0_PSTA_TEST_CND_3_EN Fld(1, 19) //[19:19] + #define LPIF_INT_PSTA_0_PSTA_TEST_CND_4_EN Fld(1, 20) //[20:20] + #define LPIF_INT_PSTA_0_PSTA_TEST_CND_5_EN Fld(1, 21) //[21:21] + #define LPIF_INT_PSTA_0_PSTA_TEST_CND_6_EN Fld(1, 22) //[22:22] + #define LPIF_INT_PSTA_0_PSTA_TEST_CND_7_EN Fld(1, 23) //[23:23] + #define LPIF_INT_PSTA_0_RESERVED_XA0_31_24 Fld(8, 24) //[31:24] + +#define DDRPHY_MD32_REG_LPIF_INT_PSTA_1 (DDRPHY_MD32_BASE_ADDRESS + 0x7284) + #define LPIF_INT_PSTA_1_PSTA_LOOP_MODE_TIME Fld(32, 0) //[31:0] + +#define DDRPHY_MD32_REG_LPIF_INT_PSTA_2 (DDRPHY_MD32_BASE_ADDRESS + 0x7288) + #define LPIF_INT_PSTA_2_PSTA_ABORT_TIME Fld(10, 0) //[9:0] + #define LPIF_INT_PSTA_2_PSTA_ABORT_TIME_MIN Fld(10, 10) //[19:10] + #define LPIF_INT_PSTA_2_PSTA_ABORT_TIME_MAX Fld(10, 20) //[29:20] + #define LPIF_INT_PSTA_2_RESERVED_XA2_31_30 Fld(2, 30) //[31:30] + +#define DDRPHY_MD32_REG_LPIF_INT_PSTA_3 (DDRPHY_MD32_BASE_ADDRESS + 0x728C) + #define LPIF_INT_PSTA_3_PSTA_PST_TO_REQ_TIME Fld(4, 0) //[3:0] + #define LPIF_INT_PSTA_3_PSTA_PST_TO_REQ_TIME_MIN Fld(4, 4) //[7:4] + #define LPIF_INT_PSTA_3_PSTA_PST_TO_REQ_TIME_MAX Fld(4, 8) //[11:8] + #define LPIF_INT_PSTA_3_RESERVED_XA3_15_12 Fld(4, 12) //[15:12] + #define LPIF_INT_PSTA_3_PSTA_ACK_TO_PST_REQ_LOW_TIME Fld(4, 16) //[19:16] + #define LPIF_INT_PSTA_3_PSTA_ACK_TO_PST_REQ_LOW_TIME_MIN Fld(4, 20) //[23:20] + #define LPIF_INT_PSTA_3_PSTA_ACK_TO_PST_REQ_LOW_TIME_MAX Fld(4, 24) //[27:24] + #define LPIF_INT_PSTA_3_RESERVED_XA3_31_28 Fld(4, 28) //[31:28] + +#define DDRPHY_MD32_REG_LPIF_INT_PSTA_4 (DDRPHY_MD32_BASE_ADDRESS + 0x7290) + #define LPIF_INT_PSTA_4_PSTA_REQ_TO_NXT_PST_TIME Fld(8, 0) //[7:0] + #define LPIF_INT_PSTA_4_PSTA_REQ_TO_NXT_PST_TIME_MIN Fld(8, 8) //[15:8] + #define LPIF_INT_PSTA_4_PSTA_REQ_TO_NXT_PST_TIME_MAX Fld(8, 16) //[23:16] + #define LPIF_INT_PSTA_4_RESERVED_XA4_31_24 Fld(8, 24) //[31:24] + +#define DDRPHY_MD32_REG_LPIF_INT_PSTA_5 (DDRPHY_MD32_BASE_ADDRESS + 0x7294) + #define LPIF_INT_PSTA_5_PSTA_CMD_PST_0 Fld(5, 0) //[4:0] + #define LPIF_INT_PSTA_5_RESERVED_XA5_7_5 Fld(3, 5) //[7:5] + #define LPIF_INT_PSTA_5_PSTA_CMD_PST_1 Fld(5, 8) //[12:8] + #define LPIF_INT_PSTA_5_RESERVED_XA5_15_13 Fld(3, 13) //[15:13] + #define LPIF_INT_PSTA_5_PSTA_CMD_PST_2 Fld(5, 16) //[20:16] + #define LPIF_INT_PSTA_5_RESERVED_XA5_23_21 Fld(3, 21) //[23:21] + #define LPIF_INT_PSTA_5_PSTA_CMD_PST_3 Fld(5, 24) //[28:24] + #define LPIF_INT_PSTA_5_RESERVED_XA5_31_29 Fld(3, 29) //[31:29] + +#define DDRPHY_MD32_REG_LPIF_INT_PSTA_6 (DDRPHY_MD32_BASE_ADDRESS + 0x7298) + #define LPIF_INT_PSTA_6_PSTA_CMD_PST_4 Fld(5, 0) //[4:0] + #define LPIF_INT_PSTA_6_RESERVED_XA6_7_5 Fld(3, 5) //[7:5] + #define LPIF_INT_PSTA_6_PSTA_CMD_PST_5 Fld(5, 8) //[12:8] + #define LPIF_INT_PSTA_6_RESERVED_XA6_15_13 Fld(3, 13) //[15:13] + #define LPIF_INT_PSTA_6_PSTA_CMD_PST_6 Fld(5, 16) //[20:16] + #define LPIF_INT_PSTA_6_RESERVED_XA6_23_21 Fld(3, 21) //[23:21] + #define LPIF_INT_PSTA_6_PSTA_CMD_PST_7 Fld(5, 24) //[28:24] + #define LPIF_INT_PSTA_6_RESERVED_XA6_31_29 Fld(3, 29) //[31:29] + +#define DDRPHY_MD32_REG_LPIF_INT_PSTA_7 (DDRPHY_MD32_BASE_ADDRESS + 0x729C) + #define LPIF_INT_PSTA_7_PSTA_ABORT_TIME_LSFR_POL Fld(20, 0) //[19:0] + #define LPIF_INT_PSTA_7_RESERVED_XA7_23_20 Fld(4, 20) //[23:20] + #define LPIF_INT_PSTA_7_PSTA_ACK_TO_PST_REQ_LOW_TIME_LSFR_POL Fld(8, 24) //[31:24] + +#define DDRPHY_MD32_REG_LPIF_INT_PSTA_8 (DDRPHY_MD32_BASE_ADDRESS + 0x72A0) + #define LPIF_INT_PSTA_8_PSTA_REQ_TO_NXT_PST_TIME_LSFR_POL Fld(16, 0) //[15:0] + #define LPIF_INT_PSTA_8_PSTA_PST_TO_REQ_TIME_LSFR_POL Fld(8, 16) //[23:16] + #define LPIF_INT_PSTA_8_RESERVED_XA8_31_24 Fld(8, 24) //[31:24] + +#define DDRPHY_MD32_REG_LPIF_INT_PSTA_9 (DDRPHY_MD32_BASE_ADDRESS + 0x72A4) + #define LPIF_INT_PSTA_9_PSTA_DDR_PST Fld(32, 0) //[31:0] + +#define DDRPHY_MD32_REG_LPIF_INT_PSTA_10 (DDRPHY_MD32_BASE_ADDRESS + 0x72A8) + #define LPIF_INT_PSTA_10_PSTA_DDR_PST_REQ Fld(1, 0) //[0:0] + #define LPIF_INT_PSTA_10_PSTA_DDR_PST_ABORT_REQ Fld(1, 1) //[1:1] + #define LPIF_INT_PSTA_10_RESERVED_XAA_3_2 Fld(2, 2) //[3:2] + #define LPIF_INT_PSTA_10_PSTA_DDR_FSM_DONE Fld(1, 4) //[4:4] + #define LPIF_INT_PSTA_10_PSTA_DDR_HW_S1_ACK Fld(1, 5) //[5:5] + #define LPIF_INT_PSTA_10_PSTA_FSM Fld(5, 8) //[12:8] + #define LPIF_INT_PSTA_10_CNT_PSTA_FSM Fld(12, 16) //[27:16] + #define LPIF_INT_PSTA_10_RESERVED_XAA_31_28 Fld(4, 28) //[31:28] + +#define DDRPHY_MD32_REG_LPIF_INT_PSTA_11 (DDRPHY_MD32_BASE_ADDRESS + 0x72AC) + #define LPIF_INT_PSTA_11_PSTA_HW_S1_REQ_INTV_TIME Fld(10, 0) //[9:0] + #define LPIF_INT_PSTA_11_PSTA_HW_S1_REQ_INTV_TIME_MIN Fld(10, 10) //[19:10] + #define LPIF_INT_PSTA_11_PSTA_HW_S1_REQ_INTV_TIME_MAX Fld(10, 20) //[29:20] + #define LPIF_INT_PSTA_11_RESERVED_XAB_31_30 Fld(2, 30) //[31:30] + +#define DDRPHY_MD32_REG_LPIF_INT_PSTA_12 (DDRPHY_MD32_BASE_ADDRESS + 0x72B0) + #define LPIF_INT_PSTA_12_PSTA_HW_S1_HIGH_PERIOD_TIME Fld(10, 0) //[9:0] + #define LPIF_INT_PSTA_12_PSTA_HW_S1_HIGH_PERIOD_TIME_MIN Fld(10, 10) //[19:10] + #define LPIF_INT_PSTA_12_PSTA_HW_S1_HIGH_PERIOD_TIME_MAX Fld(10, 20) //[29:20] + #define LPIF_INT_PSTA_12_RESERVED_XAC_31_30 Fld(2, 30) //[31:30] + +#define DDRPHY_MD32_REG_LPIF_INT_PSTA_13 (DDRPHY_MD32_BASE_ADDRESS + 0x72B4) + #define LPIF_INT_PSTA_13_PSTA_HW_S1_REQ_INTV_TIME_LSFR_POL Fld(20, 0) //[19:0] + #define LPIF_INT_PSTA_13_RESERVED_XAD_31_30 Fld(12, 20) //[31:20] + +#define DDRPHY_MD32_REG_LPIF_INT_PSTA_14 (DDRPHY_MD32_BASE_ADDRESS + 0x72B8) + #define LPIF_INT_PSTA_14_PSTA_HW_S1_HIGH_PERIOD_TIME_LSFR_POL Fld(20, 0) //[19:0] + #define LPIF_INT_PSTA_14_RESERVED_XAE_31_30 Fld(12, 20) //[31:20] + +#define DDRPHY_MD32_REG_LPIF_HW_S1_0 (DDRPHY_MD32_BASE_ADDRESS + 0x72C0) + #define LPIF_HW_S1_0_HW_S1_PS_CHK_RESULT_CLR Fld(1, 0) //[0:0] + #define LPIF_HW_S1_0_HW_S1_LATCH_CLR Fld(1, 1) //[1:1] + #define LPIF_HW_S1_0_HW_S1_TRIG_BY_FSM_EN Fld(1, 2) //[2:2] + #define LPIF_HW_S1_0_HW_S1_TRIG_BY_IRQ_EN Fld(1, 3) //[3:3] + #define LPIF_HW_S1_0_HW_S1_BYPASS_DMSUS_OFF Fld(1, 4) //[4:4] + #define LPIF_HW_S1_0_HW_S1_BYPASS_DPY_MODE_SW Fld(1, 5) //[5:5] + #define LPIF_HW_S1_0_HW_S1_BYPASS_DPY_DLL_EN Fld(1, 6) //[6:6] + #define LPIF_HW_S1_0_HW_S1_BYPASS_DPY_2ND_DLL_EN Fld(1, 7) //[7:7] + #define LPIF_HW_S1_0_HW_S1_BYPASS_DPY_DLL_CK_EN Fld(1, 8) //[8:8] + #define LPIF_HW_S1_0_HW_S1_BYPASS_DPY_VREF_EN Fld(1, 9) //[9:9] + #define LPIF_HW_S1_0_HW_S1_BYPASS_EMI_CLK_OFF_REQ Fld(1, 10) //[10:10] + #define LPIF_HW_S1_0_HW_S1_BYPASS_MEM_CK_OFF Fld(1, 11) //[11:11] + #define LPIF_HW_S1_0_HW_S1_BYPASS_DDRPHY_FB_CK_EN Fld(1, 12) //[12:12] + #define LPIF_HW_S1_0_HW_S1_BYPASS_TX_TRACKING_DIS Fld(1, 13) //[13:13] + #define LPIF_HW_S1_0_HW_S1_BYPASS_FHC_PAUSE_MPLL Fld(1, 14) //[14:14] + #define LPIF_HW_S1_0_HW_S1_BYPASS_FHC_PAUSE_MEM Fld(1, 15) //[15:15] + #define LPIF_HW_S1_0_HW_S1_BYPASS_DPY_MCK8X_EN Fld(1, 16) //[16:16] + #define LPIF_HW_S1_0_HW_S1_BYPASS_DPY_MIDPI_EN Fld(1, 17) //[17:17] + #define LPIF_HW_S1_0_HW_S1_BYPASS_DPY_PI_RESETB_EN Fld(1, 18) //[18:18] + #define LPIF_HW_S1_0_HW_S1_BYPASS_DR_GATE_RETRY_EN Fld(1, 19) //[19:19] + #define LPIF_HW_S1_0_HW_S1_BYPASS_DPHY_PRECAL_UP Fld(1, 20) //[20:20] + #define LPIF_HW_S1_0_HW_S1_BYPASS_TX_TRACKING_RETRY_EN Fld(1, 21) //[21:21] + #define LPIF_HW_S1_0_HW_S1_BYPASS_DPY_CS_PULL_DN_EN Fld(1, 22) //[22:22] + #define LPIF_HW_S1_0_HW_S1_BYPASS_DPY_EMI_S1_MODE_ASYNC Fld(1, 23) //[23:23] + #define LPIF_HW_S1_0_HW_S1_BYPASS_DPY_CA_PULL_DN_EN Fld(1, 24) //[24:24] + #define LPIF_HW_S1_0_HW_S1_BYPASS_DPY_PICG_FREE Fld(1, 25) //[25:25] + #define LPIF_HW_S1_0_RESERVED_XB0_31_26 Fld(6, 26) //[31:26] + +#define DDRPHY_MD32_REG_LPIF_HW_S1_1 (DDRPHY_MD32_BASE_ADDRESS + 0x72C4) + #define LPIF_HW_S1_1_HW_S1_PST_CHK Fld(32, 0) //[31:0] + +#define DDRPHY_MD32_REG_LPIF_HW_S1_2 (DDRPHY_MD32_BASE_ADDRESS + 0x72C8) + #define LPIF_HW_S1_2_HW_S1_PST_CHK_RESULT Fld(32, 0) //[31:0] + +#define DDRPHY_MD32_REG_LPIF_HW_S1_3 (DDRPHY_MD32_BASE_ADDRESS + 0x72CC) + #define LPIF_HW_S1_3_HW_S1_REQ Fld(1, 0) //[0:0] + #define LPIF_HW_S1_3_HW_S1_ACK Fld(1, 1) //[1:1] + #define LPIF_HW_S1_3_HW_S1_PST_REQ_CHK_RESULT Fld(1, 2) //[2:2] + #define LPIF_HW_S1_3_RESERVED_XB0_3_3 Fld(1, 3) //[3:3] + #define LPIF_HW_S1_3_RISING_HW_S1_REQ_LATCH Fld(1, 4) //[4:4] + #define LPIF_HW_S1_3_FALLING_HW_S1_REQ_LATCH Fld(1, 5) //[5:5] + #define LPIF_HW_S1_3_HW_S1_FSM Fld(6, 6) //[11:6] + #define LPIF_HW_S1_3_RESERVED_XB3_31_12 Fld(20, 12) //[31:12] + +#define DDRPHY_MD32_REG_LPIF_HW_S1_4 (DDRPHY_MD32_BASE_ADDRESS + 0x72D0) + #define LPIF_HW_S1_4_HW_S1_DRAMC_DPY_PI_RESETB_EN Fld(2, 0) //[1:0] + #define LPIF_HW_S1_4_HW_S1_DRAMC_DPY_MIDPI_EN Fld(2, 2) //[3:2] + #define LPIF_HW_S1_4_HW_S1_DRAMC_DPY_MCK8X_EN Fld(2, 4) //[5:4] + #define LPIF_HW_S1_4_HW_S1_DRAMC_TX_TRACKING_RETRY_EN Fld(2, 6) //[7:6] + #define LPIF_HW_S1_4_HW_S1_DRAMC_TX_TRACKING_DIS Fld(2, 8) //[9:8] + #define LPIF_HW_S1_4_HW_S1_DRAMC_DPHY_PRECAL_UP Fld(2, 10) //[11:10] + #define LPIF_HW_S1_4_HW_S1_DRAMC_DR_GATE_RETRY_EN Fld(2, 12) //[13:12] + #define LPIF_HW_S1_4_HW_S1_DRAMC_DDRPHY_FB_CK_EN Fld(2, 14) //[15:14] + #define LPIF_HW_S1_4_HW_S1_DRAMC_MEM_CK_OFF Fld(2, 16) //[17:16] + #define LPIF_HW_S1_4_HW_S1_DRAMC_EMI_CLK_OFF_REQ Fld(2, 18) //[19:18] + #define LPIF_HW_S1_4_HW_S1_DRAMC_DPY_VREF_EN Fld(2, 20) //[21:20] + #define LPIF_HW_S1_4_HW_S1_DRAMC_DPY_DLL_CK_EN Fld(2, 22) //[23:22] + #define LPIF_HW_S1_4_HW_S1_DRAMC_DPY_2ND_DLL_EN Fld(2, 24) //[25:24] + #define LPIF_HW_S1_4_HW_S1_DRAMC_DPY_DLL_EN Fld(2, 26) //[27:26] + #define LPIF_HW_S1_4_HW_S1_DRAMC_DPY_MODE_SW Fld(2, 28) //[29:28] + #define LPIF_HW_S1_4_HW_S1_DRAMC_DMSUS_OFF Fld(2, 30) //[31:30] + +#define DDRPHY_MD32_REG_LPIF_HW_S1_5 (DDRPHY_MD32_BASE_ADDRESS + 0x72D4) + #define LPIF_HW_S1_5_HW_S1_DRAMC_FHC_PAUSE_MPLL Fld(1, 0) //[0:0] + #define LPIF_HW_S1_5_HW_S1_DRAMC_FHC_PAUSE_MEM Fld(1, 1) //[1:1] + #define LPIF_HW_S1_5_HW_S1_DRAMC_DPY_CS_PULL_DN_EN Fld(2, 2) //[3:2] + #define LPIF_HW_S1_5_HW_S1_DRAMC_EMI_S1_MODE_ASYNC Fld(1, 4) //[4:4] + #define LPIF_HW_S1_5_HW_S1_DRAMC_DPY_CA_PULL_DN_EN Fld(2, 5) //[6:5] + #define LPIF_HW_S1_5_HW_S1_DRAMC_DPY_PICG_FREE Fld(2, 8) //[9:8] + #define LPIF_HW_S1_5_RESERVED_XB5_31_10 Fld(22, 10) //[31:10] + +#define DDRPHY_MD32_REG_LPIF_HW_S1_6 (DDRPHY_MD32_BASE_ADDRESS + 0x72D8) + #define LPIF_HW_S1_6_LOG_OPT_HWS1_DMSUS_OFF Fld(1, 0) //[0:0] + #define LPIF_HW_S1_6_LOG_OPT_HWS1_DPY_MODE_SW Fld(1, 1) //[1:1] + #define LPIF_HW_S1_6_LOG_OPT_HWS1_DPY_DLL_EN Fld(1, 2) //[2:2] + #define LPIF_HW_S1_6_LOG_OPT_HWS1_DPY_2ND_DLL_EN Fld(1, 3) //[3:3] + #define LPIF_HW_S1_6_LOG_OPT_HWS1_DPY_DLL_CK_EN Fld(1, 4) //[4:4] + #define LPIF_HW_S1_6_LOG_OPT_HWS1_DPY_VREF_EN Fld(1, 5) //[5:5] + #define LPIF_HW_S1_6_LOG_OPT_HWS1_EMI_CLK_OFF_REQ Fld(1, 6) //[6:6] + #define LPIF_HW_S1_6_LOG_OPT_HWS1_MEM_CK_OFF Fld(1, 7) //[7:7] + #define LPIF_HW_S1_6_LOG_OPT_HWS1_DDRPHY_FB_CK_EN Fld(1, 8) //[8:8] + #define LPIF_HW_S1_6_LOG_OPT_HWS1_TX_TRACKING_DIS Fld(1, 9) //[9:9] + #define LPIF_HW_S1_6_LOG_OPT_HWS1_FHC_PAUSE_MPLL Fld(1, 10) //[10:10] + #define LPIF_HW_S1_6_LOG_OPT_HWS1_FHC_PAUSE_MEM Fld(1, 11) //[11:11] + #define LPIF_HW_S1_6_LOG_OPT_HWS1_DPY_MCK8X_EN Fld(1, 12) //[12:12] + #define LPIF_HW_S1_6_LOG_OPT_HWS1_DPY_MIDPI_EN Fld(1, 13) //[13:13] + #define LPIF_HW_S1_6_LOG_OPT_HWS1_DPY_PI_RESETB_EN Fld(1, 14) //[14:14] + #define LPIF_HW_S1_6_LOG_OPT_HWS1_DR_GATE_RETRY_EN Fld(1, 15) //[15:15] + #define LPIF_HW_S1_6_LOG_OPT_HWS1_DPHY_PRECAL_UP Fld(1, 16) //[16:16] + #define LPIF_HW_S1_6_LOG_OPT_HWS1_TX_TRACKING_RETRY_EN Fld(1, 17) //[17:17] + #define LPIF_HW_S1_6_LOG_OPT_HWS1_DPY_CS_PULL_DN_EN Fld(1, 18) //[18:18] + #define LPIF_HW_S1_6_LOG_OPT_HWS1_DPY_CA_PULL_DN_EN Fld(1, 19) //[19:19] + #define LPIF_HW_S1_6_LOG_OPT_HWS1_EMI_S1_MODE_ASYNC Fld(1, 20) //[20:20] + #define LPIF_HW_S1_6_LOG_OPT_HWS1_DPY_PICG_FREE Fld(1, 21) //[21:21] + #define LPIF_HW_S1_6_RESERVED_XB6_31_22 Fld(10, 22) //[31:22] + +#define DDRPHY_MD32_REG_LPIF_DBG_LATCH0 (DDRPHY_MD32_BASE_ADDRESS + 0x7380) + #define LPIF_DBG_LATCH0_LPIF_DDR_PST Fld(32, 0) //[31:0] + +#define DDRPHY_MD32_REG_LPIF_DBG_LATCH1 (DDRPHY_MD32_BASE_ADDRESS + 0x7384) + #define LPIF_DBG_LATCH1_CUR_LPIF_DDR_PST_STA Fld(32, 0) //[31:0] + +#define DDRPHY_MD32_REG_LPIF_DBG_LATCH2 (DDRPHY_MD32_BASE_ADDRESS + 0x7388) + #define LPIF_DBG_LATCH2_EMI_CLK_OFF_REQ_ACK Fld(2, 0) //[1:0] + #define LPIF_DBG_LATCH2_RESERVED_XE2_3_2 Fld(2, 2) //[3:2] + #define LPIF_DBG_LATCH2_DRAMC_DFS_STA Fld(4, 4) //[7:4] + #define LPIF_DBG_LATCH2_DQSSOC_REQ Fld(2, 8) //[9:8] + #define LPIF_DBG_LATCH2_RESERVED_XE2_11_10 Fld(2, 10) //[11:10] + #define LPIF_DBG_LATCH2_DR_SHORT_QUEUE_ACK Fld(2, 12) //[13:12] + #define LPIF_DBG_LATCH2_DR_SHU_EN_ACK Fld(2, 14) //[15:14] + #define LPIF_DBG_LATCH2_DR_SRAM_PLL_LOAD_ACK Fld(2, 16) //[17:16] + #define LPIF_DBG_LATCH2_DR_SRAM_LOAD_ACK Fld(2, 18) //[19:18] + #define LPIF_DBG_LATCH2_DR_SRAM_RESTORE_ACK Fld(2, 20) //[21:20] + #define LPIF_DBG_LATCH2_TX_TRACKING_DIS_ACK Fld(2, 22) //[23:22] + #define LPIF_DBG_LATCH2_DDR_PST_ACK Fld(1, 24) //[24:24] + #define LPIF_DBG_LATCH2_DDR_PST_ABORT_ACK Fld(1, 25) //[25:25] + #define LPIF_DBG_LATCH2_EMI_SLEEP_IDLE Fld(1, 26) //[26:26] + #define LPIF_DBG_LATCH2_EMI_SLEEP_PROT_EN Fld(1, 27) //[27:27] + #define LPIF_DBG_LATCH2_DDR_PST_REQ Fld(1, 28) //[28:28] + #define LPIF_DBG_LATCH2_DDR_PST_ABORT_REQ Fld(1, 29) //[29:29] + #define LPIF_DBG_LATCH2_DDR_PST_ABORT_REQ_LATCH Fld(1, 30) //[30:30] + #define LPIF_DBG_LATCH2_LPC_INTERNAL_COUNTER_ABORT_FLAG Fld(1, 31) //[31:31] + +#define DDRPHY_MD32_REG_LPIF_DBG_LATCH3 (DDRPHY_MD32_BASE_ADDRESS + 0x738C) + #define LPIF_DBG_LATCH3_DDR_PST_STA_D0 Fld(6, 0) //[5:0] + #define LPIF_DBG_LATCH3_DDR_PST_ACK_D0 Fld(1, 6) //[6:6] + #define LPIF_DBG_LATCH3_DDR_PST_ABORT_ACK_D0 Fld(1, 7) //[7:7] + #define LPIF_DBG_LATCH3_DDR_PST_STA_D1 Fld(6, 8) //[13:8] + #define LPIF_DBG_LATCH3_DDR_PST_ACK_D1 Fld(1, 14) //[14:14] + #define LPIF_DBG_LATCH3_DDR_PST_ABORT_ACK_D1 Fld(1, 15) //[15:15] + #define LPIF_DBG_LATCH3_DDR_PST_STA_D2 Fld(6, 16) //[21:16] + #define LPIF_DBG_LATCH3_DDR_PST_ACK_D2 Fld(1, 22) //[22:22] + #define LPIF_DBG_LATCH3_DDR_PST_ABORT_ACK_D2 Fld(1, 23) //[23:23] + #define LPIF_DBG_LATCH3_DDR_PST_STA_D3 Fld(6, 24) //[29:24] + #define LPIF_DBG_LATCH3_DDR_PST_ACK_D3 Fld(1, 30) //[30:30] + #define LPIF_DBG_LATCH3_DDR_PST_ABORT_ACK_D3 Fld(1, 31) //[31:31] + +#define DDRPHY_MD32_REG_LPIF_DBG_LATCH4 (DDRPHY_MD32_BASE_ADDRESS + 0x7390) + #define LPIF_DBG_LATCH4_DDR_PST_STA_D4 Fld(6, 0) //[5:0] + #define LPIF_DBG_LATCH4_DDR_PST_ACK_D4 Fld(1, 6) //[6:6] + #define LPIF_DBG_LATCH4_DDR_PST_ABORT_ACK_D4 Fld(1, 7) //[7:7] + #define LPIF_DBG_LATCH4_DDR_PST_STA_D5 Fld(6, 8) //[13:8] + #define LPIF_DBG_LATCH4_DDR_PST_ACK_D5 Fld(1, 14) //[14:14] + #define LPIF_DBG_LATCH4_DDR_PST_ABORT_ACK_D5 Fld(1, 15) //[15:15] + #define LPIF_DBG_LATCH4_DDR_PST_STA_D6 Fld(6, 16) //[21:16] + #define LPIF_DBG_LATCH4_DDR_PST_ACK_D6 Fld(1, 22) //[22:22] + #define LPIF_DBG_LATCH4_DDR_PST_ABORT_ACK_D6 Fld(1, 23) //[23:23] + #define LPIF_DBG_LATCH4_DDR_PST_STA_D7 Fld(6, 24) //[29:24] + #define LPIF_DBG_LATCH4_DDR_PST_ACK_D7 Fld(1, 30) //[30:30] + #define LPIF_DBG_LATCH4_DDR_PST_ABORT_ACK_D7 Fld(1, 31) //[31:31] + +#define DDRPHY_MD32_REG_LPIF_DBG_LATCH5 (DDRPHY_MD32_BASE_ADDRESS + 0x7394) + #define LPIF_DBG_LATCH5_DDR_PST_STA_D8 Fld(6, 0) //[5:0] + #define LPIF_DBG_LATCH5_DDR_PST_ACK_D8 Fld(1, 6) //[6:6] + #define LPIF_DBG_LATCH5_DDR_PST_ABORT_ACK_D8 Fld(1, 7) //[7:7] + #define LPIF_DBG_LATCH5_DDR_PST_STA_D9 Fld(6, 8) //[13:8] + #define LPIF_DBG_LATCH5_DDR_PST_ACK_D9 Fld(1, 14) //[14:14] + #define LPIF_DBG_LATCH5_DDR_PST_ABORT_ACK_D9 Fld(1, 15) //[15:15] + #define LPIF_DBG_LATCH5_DDR_PST_STA_DA Fld(6, 16) //[21:16] + #define LPIF_DBG_LATCH5_DDR_PST_ACK_DA Fld(1, 22) //[22:22] + #define LPIF_DBG_LATCH5_DDR_PST_ABORT_ACK_DA Fld(1, 23) //[23:23] + #define LPIF_DBG_LATCH5_DDR_PST_STA_DB Fld(6, 24) //[29:24] + #define LPIF_DBG_LATCH5_DDR_PST_ACK_DB Fld(1, 30) //[30:30] + #define LPIF_DBG_LATCH5_DDR_PST_ABORT_ACK_DB Fld(1, 31) //[31:31] + +#define DDRPHY_MD32_REG_LPIF_DBG_LATCH6 (DDRPHY_MD32_BASE_ADDRESS + 0x7398) + #define LPIF_DBG_LATCH6_DDR_PST_STA_DC Fld(6, 0) //[5:0] + #define LPIF_DBG_LATCH6_DDR_PST_ACK_DC Fld(1, 6) //[6:6] + #define LPIF_DBG_LATCH6_DDR_PST_ABORT_ACK_DC Fld(1, 7) //[7:7] + #define LPIF_DBG_LATCH6_DDR_PST_STA_DD Fld(6, 8) //[13:8] + #define LPIF_DBG_LATCH6_DDR_PST_ACK_DD Fld(1, 14) //[14:14] + #define LPIF_DBG_LATCH6_DDR_PST_ABORT_ACK_DD Fld(1, 15) //[15:15] + #define LPIF_DBG_LATCH6_DDR_PST_STA_DE Fld(6, 16) //[21:16] + #define LPIF_DBG_LATCH6_DDR_PST_ACK_DE Fld(1, 22) //[22:22] + #define LPIF_DBG_LATCH6_DDR_PST_ABORT_ACK_DE Fld(1, 23) //[23:23] + #define LPIF_DBG_LATCH6_DDR_PST_STA_DF Fld(6, 24) //[29:24] + #define LPIF_DBG_LATCH6_DDR_PST_ACK_DF Fld(1, 30) //[30:30] + #define LPIF_DBG_LATCH6_DDR_PST_ABORT_ACK_DF Fld(1, 31) //[31:31] + +#define DDRPHY_MD32_REG_LPIF_DBG_LATCH7 (DDRPHY_MD32_BASE_ADDRESS + 0x739C) + #define LPIF_DBG_LATCH7_DRAMC_DMSUS_OFF Fld(2, 0) //[1:0] + #define LPIF_DBG_LATCH7_DRAMC_PHYPLL_EN Fld(2, 2) //[3:2] + #define LPIF_DBG_LATCH7_DRAMC_DPY_DLL_EN Fld(2, 4) //[5:4] + #define LPIF_DBG_LATCH7_DRAMC_DPY_2ND_DLL_EN Fld(2, 6) //[7:6] + #define LPIF_DBG_LATCH7_DRAMC_DPY_DLL_CK_EN Fld(2, 8) //[9:8] + #define LPIF_DBG_LATCH7_DRAMC_DPY_VREF_EN Fld(2, 10) //[11:10] + #define LPIF_DBG_LATCH7_DRAMC_EMI_CLK_OFF_REQ Fld(2, 12) //[13:12] + #define LPIF_DBG_LATCH7_DRAMC_MEM_CK_OFF Fld(2, 14) //[15:14] + #define LPIF_DBG_LATCH7_DRAMC_DDRPHY_FB_CK_EN Fld(2, 16) //[17:16] + #define LPIF_DBG_LATCH7_DRAMC_DR_GATE_RETRY_EN Fld(2, 18) //[19:18] + #define LPIF_DBG_LATCH7_DRAMC_PHYPLL_SHU_EN Fld(2, 20) //[21:20] + #define LPIF_DBG_LATCH7_DRAMC_PHYPLL_MODE_SW Fld(2, 22) //[23:22] + #define LPIF_DBG_LATCH7_DRAMC_PHYPLL2_SHU_EN Fld(2, 24) //[25:24] + #define LPIF_DBG_LATCH7_DRAMC_PHYPLL2_MODE_SW Fld(2, 26) //[27:26] + #define LPIF_DBG_LATCH7_DRAMC_DR_SHU_EN Fld(2, 28) //[29:28] + #define LPIF_DBG_LATCH7_DRAMC_DR_SHORT_QUEUE Fld(2, 30) //[31:30] + +#define DDRPHY_MD32_REG_LPIF_DBG_LATCH8 (DDRPHY_MD32_BASE_ADDRESS + 0x73A0) + #define LPIF_DBG_LATCH8_DRAMC_DR_SHU_LEVEL Fld(4, 0) //[3:0] + #define LPIF_DBG_LATCH8_DRAMC_DPY_BCLK_ENABLE Fld(2, 4) //[5:4] + #define LPIF_DBG_LATCH8_DRAMC_SHU_RESTORE Fld(2, 6) //[7:6] + #define LPIF_DBG_LATCH8_DRAMC_DPHY_PRECAL_UP Fld(2, 8) //[9:8] + #define LPIF_DBG_LATCH8_DRAMC_DPHY_RXDLY_TRACK_EN Fld(2, 10) //[11:10] + #define LPIF_DBG_LATCH8_DRAMC_DMY_EN_MOD_SEL Fld(2, 12) //[13:12] + #define LPIF_DBG_LATCH8_DRAMC_DMYRD_INTV_SEL Fld(2, 14) //[15:14] + #define LPIF_DBG_LATCH8_DRAMC_DMYRD_EN Fld(2, 16) //[17:16] + #define LPIF_DBG_LATCH8_DRAMC_TX_TRACKING_DIS Fld(2, 18) //[19:18] + #define LPIF_DBG_LATCH8_DRAMC_TX_TRACKING_RETRY_EN Fld(2, 20) //[21:20] + #define LPIF_DBG_LATCH8_DRAMC_DR_SHU_SRAM_LEVEL Fld(8, 22) //[29:22] + #define LPIF_DBG_LATCH8_DRAMC_DR_SRAM_LOAD Fld(2, 30) //[31:30] + +#define DDRPHY_MD32_REG_LPIF_DBG_LATCH9 (DDRPHY_MD32_BASE_ADDRESS + 0x73A4) + #define LPIF_DBG_LATCH9_DRAMC_DPY_MCK8X_EN Fld(2, 0) //[1:0] + #define LPIF_DBG_LATCH9_DRAMC_DPY_MIDPI_EN Fld(2, 2) //[3:2] + #define LPIF_DBG_LATCH9_DRAMC_DPY_PI_RESETB_EN Fld(2, 4) //[5:4] + #define LPIF_DBG_LATCH9_DRAMC_DVFS_MEM_CK_MUX_UPDATE Fld(2, 6) //[7:6] + #define LPIF_DBG_LATCH9_DRAMC_DVFS_MEM_CK_MUX_SEL Fld(4, 8) //[11:8] + #define LPIF_DBG_LATCH9_DRAMC_DPY_DSM_EN Fld(2, 12) //[13:12] + #define LPIF_DBG_LATCH9_DRAMC_DPY_FASTK_RDDQS_EN Fld(2, 14) //[15:14] + #define LPIF_DBG_LATCH9_DRAMC_DPY_CS_PULL_UP_EN Fld(2, 16) //[17:16] + #define LPIF_DBG_LATCH9_DRAMC_DPY_CS_PULL_DN_EN Fld(2, 18) //[19:18] + #define LPIF_DBG_LATCH9_DRAMC_DPY_CA_PULL_UP_EN Fld(2, 20) //[21:20] + #define LPIF_DBG_LATCH9_DRAMC_DPY_CA_PULL_DN_EN Fld(2, 22) //[23:22] + #define LPIF_DBG_LATCH9_DRAMC_FHC_PAUSE_MEM Fld(1, 24) //[24:24] + #define LPIF_DBG_LATCH9_DRAMC_FHC_PAUSE_MPLL Fld(1, 25) //[25:25] + #define LPIF_DBG_LATCH9_DRAMC_MPLL_S_OFF Fld(1, 26) //[26:26] + #define LPIF_DBG_LATCH9_DRAMC_MPLLOUT_OFF Fld(1, 27) //[27:27] + #define LPIF_DBG_LATCH9_DRAMC_EMI_S1_MODE_ASYNC Fld(1, 28) //[28:28] + #define LPIF_DBG_LATCH9_RESERVED_XE9_29_29 Fld(1, 29) //[29:29] + #define LPIF_DBG_LATCH9_DRAMC_DPY_PICG_FREE Fld(2, 30) //[31:30] + +#define DDRPHY_MD32_REG_LPIF_DBG_LATCH10 (DDRPHY_MD32_BASE_ADDRESS + 0x73A8) + #define LPIF_DBG_LATCH10_DRAMC_DR_SRAM_RESTORE Fld(2, 0) //[1:0] + #define LPIF_DBG_LATCH10_DRAMC_DR_SHU_LEVEL_SRAM_LATCH Fld(2, 2) //[3:2] + #define LPIF_DBG_LATCH10_DRAMC_DPY_MODE_SW Fld(2, 4) //[5:4] + #define LPIF_DBG_LATCH10_RESERVED_XEA_7_6 Fld(2, 6) //[7:6] + #define LPIF_DBG_LATCH10_DRAMC_DPY_RESERVED Fld(8, 8) //[15:8] + #define LPIF_DBG_LATCH10_DRAMC_DRAMC_DFS_CON Fld(13, 16) //[28:16] + #define LPIF_DBG_LATCH10_RESERVED_XEA_31_29 Fld(3, 29) //[31:29] + +#define DDRPHY_MD32_REG_LPIF_DBG_LATCH11 (DDRPHY_MD32_BASE_ADDRESS + 0x73AC) + #define LPIF_DBG_LATCH11_FSM_TIME_OUT_FLAG Fld(1, 0) //[0:0] + #define LPIF_DBG_LATCH11_EXP_FSM_JUMP Fld(1, 1) //[1:1] + #define LPIF_DBG_LATCH11_IRQ_LPIF_LOW_POWER Fld(1, 2) //[2:2] + #define LPIF_DBG_LATCH11_IRQ_LPIF_OTHERS_STATE Fld(1, 3) //[3:3] + #define LPIF_DBG_LATCH11_DFS_STATUS_RECORD Fld(4, 4) //[7:4] + #define LPIF_DBG_LATCH11_DVS_STATUS_RECORD Fld(1, 8) //[8:8] + #define LPIF_DBG_LATCH11_RUNTIME_STATUS_RECORD Fld(1, 9) //[9:9] + #define LPIF_DBG_LATCH11_RESERVED_XEB_11_10 Fld(2, 10) //[11:10] + #define LPIF_DBG_LATCH11_MUX_LPIF_DPHY_RXDLY_TRACK_EN Fld(1, 12) //[12:12] + #define LPIF_DBG_LATCH11_MUX_LPIF_DMYRD_EN Fld(1, 13) //[13:13] + #define LPIF_DBG_LATCH11_MUX_LPIF_TX_TRACKING_DIS Fld(1, 14) //[14:14] + #define LPIF_DBG_LATCH11_MUX_LPIF_DR_SRAM_RESTORE Fld(1, 15) //[15:15] + #define LPIF_DBG_LATCH11_MUX_LPIF_TX_TRACK_RETRY_EN Fld(1, 16) //[16:16] + #define LPIF_DBG_LATCH11_MUX_LPIF_RX_GATING_RETRY_EN Fld(1, 17) //[17:17] + #define LPIF_DBG_LATCH11_MUX_LPIF_DLL_ALL_SLAVE_EN Fld(1, 18) //[18:18] + #define LPIF_DBG_LATCH11_MUX_LPIF_IMPEDANCE_TRACKING_EN Fld(1, 19) //[19:19] + #define LPIF_DBG_LATCH11_MUX_LPIF_DPHY_RXDLY_TRACK_EN_PREV Fld(1, 20) //[20:20] + #define LPIF_DBG_LATCH11_MUX_LPIF_DMYRD_EN_PREV Fld(1, 21) //[21:21] + #define LPIF_DBG_LATCH11_MUX_LPIF_TX_TRACKING_DIS_PREV Fld(1, 22) //[22:22] + #define LPIF_DBG_LATCH11_MUX_LPIF_DR_SRAM_RESTORE_PREV Fld(1, 23) //[23:23] + #define LPIF_DBG_LATCH11_MUX_LPIF_TX_TRACK_RETRY_EN_PREV Fld(1, 24) //[24:24] + #define LPIF_DBG_LATCH11_MUX_LPIF_RX_GATING_RETRY_EN_PREV Fld(1, 25) //[25:25] + #define LPIF_DBG_LATCH11_MUX_LPIF_DLL_ALL_SLAVE_EN_PREV Fld(1, 26) //[26:26] + #define LPIF_DBG_LATCH11_MUX_LPIF_IMPEDANCE_TRACKING_EN_PREV Fld(1, 27) //[27:27] + #define LPIF_DBG_LATCH11_SHU_INDEX Fld(1, 28) //[28:28] + #define LPIF_DBG_LATCH11_RESERVED_XEB_31_29 Fld(3, 29) //[31:29] + +#define DDRPHY_MD32_REG_LPIF_DBG_LATCH12 (DDRPHY_MD32_BASE_ADDRESS + 0x73B0) + #define LPIF_DBG_LATCH12_DRAMC_PWR_RST_B Fld(2, 0) //[1:0] + #define LPIF_DBG_LATCH12_DRAMC_PWR_ISO Fld(2, 2) //[3:2] + #define LPIF_DBG_LATCH12_DRAMC_PWR_ON Fld(2, 4) //[5:4] + #define LPIF_DBG_LATCH12_DRAMC_PWR_ON_2ND Fld(2, 6) //[7:6] + #define LPIF_DBG_LATCH12_DRAMC_PWR_CLK_DIS Fld(2, 8) //[9:8] + #define LPIF_DBG_LATCH12_DRAMC_MPLL_OFF Fld(1, 12) //[12:12] + #define LPIF_DBG_LATCH12_DRAMC_PWR_SRAM_PDN Fld(4, 16) //[19:16] + #define LPIF_DBG_LATCH12_DRAMC_PWR_SC_SRAM_PDN_ACK Fld(1, 20) //[20:20] + #define LPIF_DBG_LATCH12_DRAMC_SHU_SRAM_SLEEP_B Fld(2, 24) //[25:24] + #define LPIF_DBG_LATCH12_DRAMC_SHU_SRAM_CKISO Fld(2, 26) //[27:26] + #define LPIF_DBG_LATCH12_DRAMC_SHU_SRAM_ISOINT_B Fld(2, 28) //[29:28] + #define LPIF_DBG_LATCH12_DRAMC_SHU_SRAM_PDN Fld(2, 30) //[31:30] + +#define DDRPHY_MD32_REG_LPIF_DBG_LATCH13 (DDRPHY_MD32_BASE_ADDRESS + 0x73B4) + #define LPIF_DBG_LATCH13_DRAMC_LPIF_COM Fld(32, 0) //[31:0] + +#define DDRPHY_MD32_REG_LPIF_DBG_LATCH14 (DDRPHY_MD32_BASE_ADDRESS + 0x73B8) + #define LPIF_DBG_LATCH14_HW_S1_DRAMC_DPY_PI_RESETB_EN Fld(2, 0) //[1:0] + #define LPIF_DBG_LATCH14_HW_S1_DRAMC_DPY_MIDPI_EN Fld(2, 2) //[3:2] + #define LPIF_DBG_LATCH14_HW_S1_DRAMC_DPY_MCK8X_EN Fld(2, 4) //[5:4] + #define LPIF_DBG_LATCH14_HW_S1_DRAMC_TX_TRACKING_RETRY_EN Fld(2, 6) //[7:6] + #define LPIF_DBG_LATCH14_HW_S1_DRAMC_TX_TRACKING_DIS Fld(2, 8) //[9:8] + #define LPIF_DBG_LATCH14_HW_S1_DRAMC_DPHY_PRECAL_UP Fld(2, 10) //[11:10] + #define LPIF_DBG_LATCH14_HW_S1_DRAMC_DR_GATE_RETRY_EN Fld(2, 12) //[13:12] + #define LPIF_DBG_LATCH14_HW_S1_DRAMC_DDRPHY_FB_CK_EN Fld(2, 14) //[15:14] + #define LPIF_DBG_LATCH14_HW_S1_DRAMC_MEM_CK_OFF Fld(2, 16) //[17:16] + #define LPIF_DBG_LATCH14_HW_S1_DRAMC_EMI_CLK_OFF_REQ Fld(2, 18) //[19:18] + #define LPIF_DBG_LATCH14_HW_S1_DRAMC_DPY_VREF_EN Fld(2, 20) //[21:20] + #define LPIF_DBG_LATCH14_HW_S1_DRAMC_DPY_DLL_CK_EN Fld(2, 22) //[23:22] + #define LPIF_DBG_LATCH14_HW_S1_DRAMC_DPY_2ND_DLL_EN Fld(2, 24) //[25:24] + #define LPIF_DBG_LATCH14_HW_S1_DRAMC_DPY_DLL_EN Fld(2, 26) //[27:26] + #define LPIF_DBG_LATCH14_HW_S1_DRAMC_DPY_MODE_SW Fld(2, 28) //[29:28] + #define LPIF_DBG_LATCH14_HW_S1_DRAMC_DMSUS_OFF Fld(2, 30) //[31:30] + +#define DDRPHY_MD32_REG_LPIF_DBG_LATCH15 (DDRPHY_MD32_BASE_ADDRESS + 0x73BC) + #define LPIF_DBG_LATCH15_HW_S1_DRAMC_FHC_PAUSE_MPLL Fld(1, 0) //[0:0] + #define LPIF_DBG_LATCH15_HW_S1_DRAMC_FHC_PAUSE_MEM Fld(1, 1) //[1:1] + #define LPIF_DBG_LATCH15_HW_S1_DRAMC_DPY_CS_PULL_DN_EN Fld(2, 2) //[3:2] + #define LPIF_DBG_LATCH15_HW_S1_DRAMC_EMI_S1_MODE_ASYNC Fld(1, 4) //[4:4] + #define LPIF_DBG_LATCH15_HW_S1_DRAMC_DPY_CA_PULL_DN_EN Fld(2, 5) //[6:5] + #define LPIF_DBG_LATCH15_HW_S1_DRAMC_DPY_PICG_FREE Fld(2, 8) //[9:8] + #define LPIF_DBG_LATCH15_PWR_ON_ACK Fld(2, 12) //[13:12] + #define LPIF_DBG_LATCH15_PWR_ON_2ND_ACK Fld(2, 14) //[15:14] + #define LPIF_DBG_LATCH15_SRAM_PDN_ACK Fld(4, 16) //[19:16] + #define LPIF_DBG_LATCH15_HW_S1_REQ Fld(1, 20) //[20:20] + #define LPIF_DBG_LATCH15_HW_S1_ACK Fld(1, 21) //[21:21] + #define LPIF_DBG_LATCH15_HW_S1_PST_REQ_CHK_RESULT Fld(1, 22) //[22:22] + #define LPIF_DBG_LATCH15_RESERVED_XEF_31_23 Fld(9, 23) //[31:23] + +#define DDRPHY_MD32_REG_LPIF_DBG_LATCH16 (DDRPHY_MD32_BASE_ADDRESS + 0x73C0) + #define LPIF_DBG_LATCH16_HW_S1_PST_CHK_RESULT Fld(32, 0) //[31:0] + +#define DDRPHY_MD32_REG_LPIF_DBG_LATCH17 (DDRPHY_MD32_BASE_ADDRESS + 0x73C4) + #define LPIF_DBG_LATCH17_MAX_CNT_SREF_REQ_HIGH_TO_SREF_ACK Fld(8, 0) //[7:0] + #define LPIF_DBG_LATCH17_MAX_CNT_SREF_REQ_LOW_TO_SREF_ACK Fld(8, 8) //[15:8] + #define LPIF_DBG_LATCH17_MAX_CNT_SHU_EN_HIGH_TO_ACK Fld(8, 16) //[23:16] + #define LPIF_DBG_LATCH17_MAX_CNT_HW_S1_REQ_LOW_TO_SREF_ACK_LOW Fld(8, 24) //[31:24] + +#endif // __DDRPHY_MD32_REGS_H__ diff --git a/src/vendorcode/mediatek/mt8192/include/Margaux_Register_DDRPHY_NAO.h b/src/vendorcode/mediatek/mt8192/include/Margaux_Register_DDRPHY_NAO.h new file mode 100644 index 000000000000..30c0c2a8f110 --- /dev/null +++ b/src/vendorcode/mediatek/mt8192/include/Margaux_Register_DDRPHY_NAO.h @@ -0,0 +1,1147 @@ +/* SPDX-License-Identifier: BSD-3-Clause */ + +#ifndef __DDRPHY_NAO_REGS_H__ +#define __DDRPHY_NAO_REGS_H__ + +#define Channel_A_DDRPHY_NAO_BASE_ADDRESS 0x10236000 +#define Channel_B_DDRPHY_NAO_BASE_ADDRESS 0x10246000 + +#define DDRPHY_NAO_BASE_ADDRESS Channel_A_DDRPHY_NAO_BASE_VIRTUAL + +#define DDRPHY_REG_MISC_STA_EXTLB0 (DDRPHY_NAO_BASE_ADDRESS + 0x0000) + #define MISC_STA_EXTLB0_STA_EXTLB_DONE Fld(32, 0) //[31:0] + +#define DDRPHY_REG_MISC_STA_EXTLB1 (DDRPHY_NAO_BASE_ADDRESS + 0x0004) + #define MISC_STA_EXTLB1_STA_EXTLB_FAIL Fld(32, 0) //[31:0] + +#define DDRPHY_REG_MISC_STA_EXTLB2 (DDRPHY_NAO_BASE_ADDRESS + 0x0008) + #define MISC_STA_EXTLB2_STA_EXTLB_DBG_INFO Fld(32, 0) //[31:0] + +#define DDRPHY_REG_MISC_DMA_DEBUG0 (DDRPHY_NAO_BASE_ADDRESS + 0x0010) + #define MISC_DMA_DEBUG0_WPTR Fld(2, 0) //[1:0] + #define MISC_DMA_DEBUG0_RPTR Fld(2, 2) //[3:2] + #define MISC_DMA_DEBUG0_CMD_CNT Fld(3, 4) //[6:4] + #define MISC_DMA_DEBUG0_DATA_CNT Fld(3, 8) //[10:8] + #define MISC_DMA_DEBUG0_FIFO_EMPTY Fld(1, 12) //[12:12] + #define MISC_DMA_DEBUG0_FIFO_FULL Fld(1, 13) //[13:13] + #define MISC_DMA_DEBUG0_DMA_FIRE Fld(1, 14) //[14:14] + #define MISC_DMA_DEBUG0_SHU_REG_PTR Fld(1, 15) //[15:15] + #define MISC_DMA_DEBUG0_SRAM_DONE Fld(1, 16) //[16:16] + #define MISC_DMA_DEBUG0_APB_DONE Fld(1, 17) //[17:17] + #define MISC_DMA_DEBUG0_SRAM_DONE_EARLY Fld(1, 18) //[18:18] + #define MISC_DMA_DEBUG0_APB_DONE_EARLY Fld(1, 19) //[19:19] + #define MISC_DMA_DEBUG0_SRAM_STEP Fld(4, 20) //[23:20] + #define MISC_DMA_DEBUG0_APB_STEP Fld(4, 24) //[27:24] + #define MISC_DMA_DEBUG0_SC_DR_SRAM_PLL_LOAD_ACK Fld(1, 28) //[28:28] + #define MISC_DMA_DEBUG0_SC_DR_SRAM_LOAD_ACK Fld(1, 29) //[29:29] + #define MISC_DMA_DEBUG0_SC_DR_SRAM_RESTORE_ACK Fld(1, 30) //[30:30] + +#define DDRPHY_REG_MISC_DMA_DEBUG1 (DDRPHY_NAO_BASE_ADDRESS + 0x0014) + #define MISC_DMA_DEBUG1_DMA_TIMER_EARLY Fld(6, 0) //[5:0] + #define MISC_DMA_DEBUG1_DMA_TIMER_ALL Fld(12, 8) //[19:8] + #define MISC_DMA_DEBUG1_PSEL_DDRPHY Fld(1, 20) //[20:20] + #define MISC_DMA_DEBUG1_PSEL_DRAMC Fld(1, 21) //[21:21] + #define MISC_DMA_DEBUG1_PSEL_DDRPHY2 Fld(1, 22) //[22:22] + #define MISC_DMA_DEBUG1_PSEL_DRAMC2 Fld(1, 23) //[23:23] + #define MISC_DMA_DEBUG1_DMA_PENABLE Fld(1, 24) //[24:24] + #define MISC_DMA_DEBUG1_PREADY Fld(1, 25) //[25:25] + #define MISC_DMA_DEBUG1_KEEP_APB_ARB Fld(1, 26) //[26:26] + #define MISC_DMA_DEBUG1_WR_APB Fld(1, 27) //[27:27] + #define MISC_DMA_DEBUG1_SRAM_CS Fld(1, 28) //[28:28] + #define MISC_DMA_DEBUG1_SRAM_GRANT Fld(1, 29) //[29:29] + #define MISC_DMA_DEBUG1_KEEP_SRAM_ARB Fld(1, 30) //[30:30] + #define MISC_DMA_DEBUG1_WR_SRAM Fld(1, 31) //[31:31] + +#define DDRPHY_REG_MISC_RETRY_DBG0 (DDRPHY_NAO_BASE_ADDRESS + 0x0018) + #define MISC_RETRY_DBG0_PRECAL_CONF_CAL_DONE_ALL Fld(1, 0) //[0:0] + #define MISC_RETRY_DBG0_RETRY_DONE_ALL Fld(1, 1) //[1:1] + #define MISC_RETRY_DBG0_RK0_RETRY_DONE0 Fld(1, 4) //[4:4] + #define MISC_RETRY_DBG0_RK0_RETRY_DONE1 Fld(1, 5) //[5:5] + #define MISC_RETRY_DBG0_RK0_RETRY_DONE2 Fld(1, 6) //[6:6] + #define MISC_RETRY_DBG0_RK0_RETRY_FAIL0 Fld(1, 8) //[8:8] + #define MISC_RETRY_DBG0_RK0_RETRY_FAIL1 Fld(1, 9) //[9:9] + #define MISC_RETRY_DBG0_RK0_RETRY_FAIL2 Fld(1, 10) //[10:10] + #define MISC_RETRY_DBG0_RK1_RETRY_DONE0 Fld(1, 12) //[12:12] + #define MISC_RETRY_DBG0_RK1_RETRY_DONE1 Fld(1, 13) //[13:13] + #define MISC_RETRY_DBG0_RK1_RETRY_DONE2 Fld(1, 14) //[14:14] + #define MISC_RETRY_DBG0_RK1_RETRY_FAIL0 Fld(1, 16) //[16:16] + #define MISC_RETRY_DBG0_RK1_RETRY_FAIL1 Fld(1, 17) //[17:17] + #define MISC_RETRY_DBG0_RK1_RETRY_FAIL2 Fld(1, 18) //[18:18] + +#define DDRPHY_REG_MISC_RETRY_DBG1 (DDRPHY_NAO_BASE_ADDRESS + 0x001C) + #define MISC_RETRY_DBG1_DQSG_RETRY_1ST_ST Fld(8, 0) //[7:0] + #define MISC_RETRY_DBG1_DQSG_RETRY_2ND_ST Fld(8, 8) //[15:8] + #define MISC_RETRY_DBG1_DQSG_RETRY_3RD_ST Fld(8, 16) //[23:16] + #define MISC_RETRY_DBG1_DQSG_RETRY_4TH_ST Fld(8, 24) //[31:24] + +#define DDRPHY_REG_MISC_RETRY_DBG2 (DDRPHY_NAO_BASE_ADDRESS + 0x0020) + #define MISC_RETRY_DBG2_DQSG_RETRY_5TH_ST Fld(8, 0) //[7:0] + +#define DDRPHY_REG_MISC_RDSEL_TRACK_DBG (DDRPHY_NAO_BASE_ADDRESS + 0x0024) + #define MISC_RDSEL_TRACK_DBG_RDSEL_TRK_SLOW_ST Fld(1, 2) //[2:2] + #define MISC_RDSEL_TRACK_DBG_RDSEL_TRK_FAST_ST Fld(1, 3) //[3:3] + #define MISC_RDSEL_TRACK_DBG_RDSEL_TRK_INI2SLOW Fld(1, 4) //[4:4] + #define MISC_RDSEL_TRACK_DBG_RDSEL_TRK_INI2FAST Fld(1, 5) //[5:5] + #define MISC_RDSEL_TRACK_DBG_RDSEL_TRK_SLOW2INI Fld(1, 6) //[6:6] + #define MISC_RDSEL_TRACK_DBG_RDSEL_TRK_FAST2INI Fld(1, 7) //[7:7] + +#define DDRPHY_REG_MISC_DQ_RXDLY_TRRO0 (DDRPHY_NAO_BASE_ADDRESS + 0x0080) + #define MISC_DQ_RXDLY_TRRO0_DVS_RKX_BX_SW_LAG_CNT_OUT_B0 Fld(8, 0) //[7:0] + #define MISC_DQ_RXDLY_TRRO0_DVS_RKX_BX_SW_LEAD_CNT_OUT_B0 Fld(8, 8) //[15:8] + #define MISC_DQ_RXDLY_TRRO0_DVS_RKX_BX_SW_LAG_CNT_OUT_B1 Fld(8, 16) //[23:16] + #define MISC_DQ_RXDLY_TRRO0_DVS_RKX_BX_SW_LEAD_CNT_OUT_B1 Fld(8, 24) //[31:24] + +#define DDRPHY_REG_MISC_DQ_RXDLY_TRRO1 (DDRPHY_NAO_BASE_ADDRESS + 0x0084) + #define MISC_DQ_RXDLY_TRRO1_DVS_RKX_BX_SW_LAG_CNT_OUT_B2 Fld(8, 0) //[7:0] + #define MISC_DQ_RXDLY_TRRO1_DVS_RKX_BX_SW_LEAD_CNT_OUT_B2 Fld(8, 8) //[15:8] + #define MISC_DQ_RXDLY_TRRO1_DVS_RKX_BX_SW_LAG_CNT_OUT_B3 Fld(8, 16) //[23:16] + #define MISC_DQ_RXDLY_TRRO1_DVS_RKX_BX_SW_LEAD_CNT_OUT_B3 Fld(8, 24) //[31:24] + +#define DDRPHY_REG_MISC_DQ_RXDLY_TRRO2 (DDRPHY_NAO_BASE_ADDRESS + 0x0088) + #define MISC_DQ_RXDLY_TRRO2_DVS_RKX_BX_SW_LAG_CNT_OUT_B4 Fld(8, 0) //[7:0] + #define MISC_DQ_RXDLY_TRRO2_DVS_RKX_BX_SW_LEAD_CNT_OUT_B4 Fld(8, 8) //[15:8] + #define MISC_DQ_RXDLY_TRRO2_DVS_RKX_BX_SW_LAG_CNT_OUT_B5 Fld(8, 16) //[23:16] + #define MISC_DQ_RXDLY_TRRO2_DVS_RKX_BX_SW_LEAD_CNT_OUT_B5 Fld(8, 24) //[31:24] + +#define DDRPHY_REG_MISC_DQ_RXDLY_TRRO3 (DDRPHY_NAO_BASE_ADDRESS + 0x008C) + #define MISC_DQ_RXDLY_TRRO3_DVS_RKX_BX_SW_LAG_CNT_OUT_B6 Fld(8, 0) //[7:0] + #define MISC_DQ_RXDLY_TRRO3_DVS_RKX_BX_SW_LEAD_CNT_OUT_B6 Fld(8, 8) //[15:8] + #define MISC_DQ_RXDLY_TRRO3_DVS_RKX_BX_SW_LAG_CNT_OUT_B7 Fld(8, 16) //[23:16] + #define MISC_DQ_RXDLY_TRRO3_DVS_RKX_BX_SW_LEAD_CNT_OUT_B7 Fld(8, 24) //[31:24] + +#define DDRPHY_REG_MISC_DQ_RXDLY_TRRO4 (DDRPHY_NAO_BASE_ADDRESS + 0x0090) + #define MISC_DQ_RXDLY_TRRO4_DVS_RKX_BX_LEAD_LAG_CNT_OUT_B0 Fld(8, 0) //[7:0] + #define MISC_DQ_RXDLY_TRRO4_DVS_RKX_BX_LEAD_LAG_CNT_OUT_B1 Fld(8, 8) //[15:8] + #define MISC_DQ_RXDLY_TRRO4_DVS_RKX_BX_LEAD_LAG_CNT_OUT_B2 Fld(8, 16) //[23:16] + #define MISC_DQ_RXDLY_TRRO4_DVS_RKX_BX_LEAD_LAG_CNT_OUT_B3 Fld(8, 24) //[31:24] + +#define DDRPHY_REG_MISC_DQ_RXDLY_TRRO5 (DDRPHY_NAO_BASE_ADDRESS + 0x0094) + #define MISC_DQ_RXDLY_TRRO5_DVS_RKX_BX_LEAD_LAG_CNT_OUT_B4 Fld(8, 0) //[7:0] + #define MISC_DQ_RXDLY_TRRO5_DVS_RKX_BX_LEAD_LAG_CNT_OUT_B5 Fld(8, 8) //[15:8] + #define MISC_DQ_RXDLY_TRRO5_DVS_RKX_BX_LEAD_LAG_CNT_OUT_B6 Fld(8, 16) //[23:16] + #define MISC_DQ_RXDLY_TRRO5_DVS_RKX_BX_LEAD_LAG_CNT_OUT_B7 Fld(8, 24) //[31:24] + +#define DDRPHY_REG_MISC_DQ_RXDLY_TRRO6 (DDRPHY_NAO_BASE_ADDRESS + 0x0098) + #define MISC_DQ_RXDLY_TRRO6_DVS_RKX_BX_SW_LAG_CNT_OUT_DQM0 Fld(8, 0) //[7:0] + #define MISC_DQ_RXDLY_TRRO6_DVS_RKX_BX_SW_LEAD_CNT_OUT_DQM0 Fld(8, 8) //[15:8] + #define MISC_DQ_RXDLY_TRRO6_DVS_RKX_BX_LEAD_LAG_CNT_OUT_DQM0 Fld(8, 24) //[31:24] + +#define DDRPHY_REG_MISC_DQ_RXDLY_TRRO7 (DDRPHY_NAO_BASE_ADDRESS + 0x009C) + #define MISC_DQ_RXDLY_TRRO7_DVS_RK0_B0_SW_UP_DONE Fld(1, 0) //[0:0] + #define MISC_DQ_RXDLY_TRRO7_DVS_RK0_B1_SW_UP_DONE Fld(1, 4) //[4:4] + #define MISC_DQ_RXDLY_TRRO7_DVS_RK1_B0_SW_UP_DONE Fld(1, 8) //[8:8] + #define MISC_DQ_RXDLY_TRRO7_DVS_RK1_B1_SW_UP_DONE Fld(1, 12) //[12:12] + #define MISC_DQ_RXDLY_TRRO7_DVS_RK2_B0_SW_UP_DONE Fld(1, 16) //[16:16] + #define MISC_DQ_RXDLY_TRRO7_DVS_RK2_B1_SW_UP_DONE Fld(1, 20) //[20:20] + +#define DDRPHY_REG_MISC_DQ_RXDLY_TRRO8 (DDRPHY_NAO_BASE_ADDRESS + 0x00A0) + #define MISC_DQ_RXDLY_TRRO8_DVS_RKX_BX_TH_CNT_OUT_B0 Fld(9, 0) //[8:0] + #define MISC_DQ_RXDLY_TRRO8_DVS_RKX_BX_TH_CNT_OUT_B1 Fld(9, 16) //[24:16] + +#define DDRPHY_REG_MISC_DQ_RXDLY_TRRO9 (DDRPHY_NAO_BASE_ADDRESS + 0x00A4) + #define MISC_DQ_RXDLY_TRRO9_DVS_RKX_BX_TH_CNT_OUT_B2 Fld(9, 0) //[8:0] + #define MISC_DQ_RXDLY_TRRO9_DVS_RKX_BX_TH_CNT_OUT_B3 Fld(9, 16) //[24:16] + +#define DDRPHY_REG_MISC_DQ_RXDLY_TRRO10 (DDRPHY_NAO_BASE_ADDRESS + 0x00A8) + #define MISC_DQ_RXDLY_TRRO10_DVS_RKX_BX_TH_CNT_OUT_B4 Fld(9, 0) //[8:0] + #define MISC_DQ_RXDLY_TRRO10_DVS_RKX_BX_TH_CNT_OUT_B5 Fld(9, 16) //[24:16] + +#define DDRPHY_REG_MISC_DQ_RXDLY_TRRO11 (DDRPHY_NAO_BASE_ADDRESS + 0x00AC) + #define MISC_DQ_RXDLY_TRRO11_DVS_RKX_BX_TH_CNT_OUT_B6 Fld(9, 0) //[8:0] + #define MISC_DQ_RXDLY_TRRO11_DVS_RKX_BX_TH_CNT_OUT_B7 Fld(9, 16) //[24:16] + +#define DDRPHY_REG_MISC_DQ_RXDLY_TRRO12 (DDRPHY_NAO_BASE_ADDRESS + 0x00B0) + #define MISC_DQ_RXDLY_TRRO12_DVS_RKX_BX_TH_CNT_OUT_DQM0 Fld(9, 0) //[8:0] + +#define DDRPHY_REG_MISC_DQ_RXDLY_TRRO13 (DDRPHY_NAO_BASE_ADDRESS + 0x00B4) + #define MISC_DQ_RXDLY_TRRO13_DA_RK0_DQX_B0_R_DLY Fld(6, 0) //[5:0] + #define MISC_DQ_RXDLY_TRRO13_DA_RK0_DQS0_R_DLY Fld(7, 8) //[14:8] + #define MISC_DQ_RXDLY_TRRO13_DA_RK0_DQX_B1_R_DLY Fld(6, 16) //[21:16] + #define MISC_DQ_RXDLY_TRRO13_DA_RK0_DQS1_R_DLY Fld(7, 24) //[30:24] + +#define DDRPHY_REG_MISC_DQ_RXDLY_TRRO14 (DDRPHY_NAO_BASE_ADDRESS + 0x00B8) + #define MISC_DQ_RXDLY_TRRO14_DA_RK1_DQX_B0_R_DLY Fld(6, 0) //[5:0] + #define MISC_DQ_RXDLY_TRRO14_DA_RK1_DQS0_R_DLY Fld(7, 8) //[14:8] + #define MISC_DQ_RXDLY_TRRO14_DA_RK1_DQX_B1_R_DLY Fld(6, 16) //[21:16] + #define MISC_DQ_RXDLY_TRRO14_DA_RK1_DQS1_R_DLY Fld(7, 24) //[30:24] + +#define DDRPHY_REG_MISC_DQ_RXDLY_TRRO15 (DDRPHY_NAO_BASE_ADDRESS + 0x00BC) + #define MISC_DQ_RXDLY_TRRO15_DA_RK2_DQX_B0_R_DLY Fld(6, 0) //[5:0] + #define MISC_DQ_RXDLY_TRRO15_DA_RK2_DQS0_R_DLY Fld(7, 8) //[14:8] + #define MISC_DQ_RXDLY_TRRO15_DA_RK2_DQX_B1_R_DLY Fld(6, 16) //[21:16] + #define MISC_DQ_RXDLY_TRRO15_DA_RK2_DQS1_R_DLY Fld(7, 24) //[30:24] + +#define DDRPHY_REG_MISC_DQ_RXDLY_TRRO16 (DDRPHY_NAO_BASE_ADDRESS + 0x00C0) + #define MISC_DQ_RXDLY_TRRO16_DVS_RXDLY_STS_ERR_CNT_ALL Fld(32, 0) //[31:0] + +#define DDRPHY_REG_MISC_DQ_RXDLY_TRRO17 (DDRPHY_NAO_BASE_ADDRESS + 0x00C4) + #define MISC_DQ_RXDLY_TRRO17_DVS_RXDLY_STS_ERR_CNT_ALL_47_32 Fld(16, 0) //[15:0] + #define MISC_DQ_RXDLY_TRRO17_PBYTE_LEADLAG_STUCK_B0 Fld(1, 16) //[16:16] + #define MISC_DQ_RXDLY_TRRO17_PBYTE_LEADLAG_STUCK_B1 Fld(1, 24) //[24:24] + +#define DDRPHY_REG_MISC_DQ_RXDLY_TRRO18 (DDRPHY_NAO_BASE_ADDRESS + 0x00C8) + #define MISC_DQ_RXDLY_TRRO18_RXDLY_DBG_MON_VALID Fld(1, 0) //[0:0] + #define MISC_DQ_RXDLY_TRRO18_RXDLY_RK0_FAIL_LAT Fld(1, 1) //[1:1] + #define MISC_DQ_RXDLY_TRRO18_RXDLY_RK1_FAIL_LAT Fld(1, 2) //[2:2] + #define MISC_DQ_RXDLY_TRRO18_RXDLY_RK2_FAIL_LAT Fld(1, 3) //[3:3] + #define MISC_DQ_RXDLY_TRRO18_DFS_SHU_GP_FAIL_LAT Fld(2, 4) //[5:4] + +#define DDRPHY_REG_MISC_DQ_RXDLY_TRRO19 (DDRPHY_NAO_BASE_ADDRESS + 0x00CC) + #define MISC_DQ_RXDLY_TRRO19_RESERVED_0X00C Fld(32, 0) //[31:0] + +#define DDRPHY_REG_MISC_DQ_RXDLY_TRRO20 (DDRPHY_NAO_BASE_ADDRESS + 0x00D0) + #define MISC_DQ_RXDLY_TRRO20_RESERVED_0X0D0 Fld(32, 0) //[31:0] + +#define DDRPHY_REG_MISC_DQ_RXDLY_TRRO21 (DDRPHY_NAO_BASE_ADDRESS + 0x00D4) + #define MISC_DQ_RXDLY_TRRO21_RESERVED_0X0D4 Fld(32, 0) //[31:0] + +#define DDRPHY_REG_MISC_DQ_RXDLY_TRRO22 (DDRPHY_NAO_BASE_ADDRESS + 0x00D8) + #define MISC_DQ_RXDLY_TRRO22_RESERVED_0X0D8 Fld(32, 0) //[31:0] + +#define DDRPHY_REG_MISC_DQ_RXDLY_TRRO23 (DDRPHY_NAO_BASE_ADDRESS + 0x00DC) + #define MISC_DQ_RXDLY_TRRO23_RESERVED_0X0DC Fld(32, 0) //[31:0] + +#define DDRPHY_REG_MISC_DQ_RXDLY_TRRO24 (DDRPHY_NAO_BASE_ADDRESS + 0x00E0) + #define MISC_DQ_RXDLY_TRRO24_RESERVED_0X0E0 Fld(32, 0) //[31:0] + +#define DDRPHY_REG_MISC_DQ_RXDLY_TRRO25 (DDRPHY_NAO_BASE_ADDRESS + 0x00E4) + #define MISC_DQ_RXDLY_TRRO25_RESERVED_0X0E4 Fld(32, 0) //[31:0] + +#define DDRPHY_REG_MISC_DQ_RXDLY_TRRO26 (DDRPHY_NAO_BASE_ADDRESS + 0x00E8) + #define MISC_DQ_RXDLY_TRRO26_RESERVED_0X0E8 Fld(32, 0) //[31:0] + +#define DDRPHY_REG_MISC_DQ_RXDLY_TRRO27 (DDRPHY_NAO_BASE_ADDRESS + 0x00EC) + #define MISC_DQ_RXDLY_TRRO27_RESERVED_0X0EC Fld(32, 0) //[31:0] + +#define DDRPHY_REG_MISC_DQ_RXDLY_TRRO28 (DDRPHY_NAO_BASE_ADDRESS + 0x00F0) + #define MISC_DQ_RXDLY_TRRO28_RESERVED_0X0F0 Fld(32, 0) //[31:0] + +#define DDRPHY_REG_MISC_DQ_RXDLY_TRRO29 (DDRPHY_NAO_BASE_ADDRESS + 0x00F4) + #define MISC_DQ_RXDLY_TRRO29_RESERVED_0X0F4 Fld(32, 0) //[31:0] + +#define DDRPHY_REG_MISC_DQ_RXDLY_TRRO30 (DDRPHY_NAO_BASE_ADDRESS + 0x00F8) + #define MISC_DQ_RXDLY_TRRO30_RESERVED_0X0F8 Fld(32, 0) //[31:0] + +#define DDRPHY_REG_MISC_DQ_RXDLY_TRRO31 (DDRPHY_NAO_BASE_ADDRESS + 0x00FC) + #define MISC_DQ_RXDLY_TRRO31_RESERVED_0X0FC Fld(32, 0) //[31:0] + +#define DDRPHY_REG_MISC_CA_RXDLY_TRRO20 (DDRPHY_NAO_BASE_ADDRESS + 0x0150) + #define MISC_CA_RXDLY_TRRO20_RESERVED_0X150 Fld(32, 0) //[31:0] + +#define DDRPHY_REG_MISC_CA_RXDLY_TRRO21 (DDRPHY_NAO_BASE_ADDRESS + 0x0154) + #define MISC_CA_RXDLY_TRRO21_RESERVED_0X154 Fld(32, 0) //[31:0] + +#define DDRPHY_REG_MISC_CA_RXDLY_TRRO22 (DDRPHY_NAO_BASE_ADDRESS + 0x0158) + #define MISC_CA_RXDLY_TRRO22_RESERVED_0X158 Fld(32, 0) //[31:0] + +#define DDRPHY_REG_MISC_CA_RXDLY_TRRO23 (DDRPHY_NAO_BASE_ADDRESS + 0x015C) + #define MISC_CA_RXDLY_TRRO23_RESERVED_0X15C Fld(32, 0) //[31:0] + +#define DDRPHY_REG_MISC_CA_RXDLY_TRRO24 (DDRPHY_NAO_BASE_ADDRESS + 0x0160) + #define MISC_CA_RXDLY_TRRO24_RESERVED_0X160 Fld(32, 0) //[31:0] + +#define DDRPHY_REG_MISC_CA_RXDLY_TRRO25 (DDRPHY_NAO_BASE_ADDRESS + 0x0164) + #define MISC_CA_RXDLY_TRRO25_RESERVED_0X164 Fld(32, 0) //[31:0] + +#define DDRPHY_REG_MISC_CA_RXDLY_TRRO26 (DDRPHY_NAO_BASE_ADDRESS + 0x0168) + #define MISC_CA_RXDLY_TRRO26_RESERVED_0X168 Fld(32, 0) //[31:0] + +#define DDRPHY_REG_MISC_CA_RXDLY_TRRO27 (DDRPHY_NAO_BASE_ADDRESS + 0x016C) + #define MISC_CA_RXDLY_TRRO27_RESERVED_0X16C Fld(32, 0) //[31:0] + +#define DDRPHY_REG_MISC_CA_RXDLY_TRRO28 (DDRPHY_NAO_BASE_ADDRESS + 0x0170) + #define MISC_CA_RXDLY_TRRO28_RESERVED_0X170 Fld(32, 0) //[31:0] + +#define DDRPHY_REG_MISC_CA_RXDLY_TRRO29 (DDRPHY_NAO_BASE_ADDRESS + 0x0174) + #define MISC_CA_RXDLY_TRRO29_RESERVED_0X174 Fld(32, 0) //[31:0] + +#define DDRPHY_REG_MISC_CA_RXDLY_TRRO30 (DDRPHY_NAO_BASE_ADDRESS + 0x0178) + #define MISC_CA_RXDLY_TRRO30_RESERVED_0X178 Fld(32, 0) //[31:0] + +#define DDRPHY_REG_MISC_CA_RXDLY_TRRO31 (DDRPHY_NAO_BASE_ADDRESS + 0x017C) + #define MISC_CA_RXDLY_TRRO31_RESERVED_0X17C Fld(32, 0) //[31:0] + +#define DDRPHY_REG_MISC_DQO1 (DDRPHY_NAO_BASE_ADDRESS + 0x0180) + #define MISC_DQO1_DQO1_RO Fld(32, 0) //[31:0] + +#define DDRPHY_REG_MISC_CAO1 (DDRPHY_NAO_BASE_ADDRESS + 0x0184) + #define MISC_CAO1_DQM0O1_RO Fld(1, 0) //[0:0] + #define MISC_CAO1_DQM1O1_RO Fld(1, 1) //[1:1] + #define MISC_CAO1_DQM2O1_RO Fld(1, 2) //[2:2] + #define MISC_CAO1_DQM3O1_RO Fld(1, 3) //[3:3] + +#define DDRPHY_REG_MISC_AD_RX_DQ_O1 (DDRPHY_NAO_BASE_ADDRESS + 0x0188) + #define MISC_AD_RX_DQ_O1_AD_RX_ARDQ_O1_B0 Fld(8, 0) //[7:0] + #define MISC_AD_RX_DQ_O1_AD_RX_ARDQM0_O1_B0 Fld(1, 8) //[8:8] + #define MISC_AD_RX_DQ_O1_AD_RX_ARDQ_O1_B1 Fld(8, 16) //[23:16] + #define MISC_AD_RX_DQ_O1_AD_RX_ARDQM0_O1_B1 Fld(1, 24) //[24:24] + +#define DDRPHY_REG_MISC_AD_RX_CMD_O1 (DDRPHY_NAO_BASE_ADDRESS + 0x018C) + #define MISC_AD_RX_CMD_O1_AD_RX_ARCA0_O1 Fld(1, 0) //[0:0] + #define MISC_AD_RX_CMD_O1_AD_RX_ARCA1_O1 Fld(1, 1) //[1:1] + #define MISC_AD_RX_CMD_O1_AD_RX_ARCA2_O1 Fld(1, 2) //[2:2] + #define MISC_AD_RX_CMD_O1_AD_RX_ARCA3_O1 Fld(1, 3) //[3:3] + #define MISC_AD_RX_CMD_O1_AD_RX_ARCA4_O1 Fld(1, 4) //[4:4] + #define MISC_AD_RX_CMD_O1_AD_RX_ARCA5_O1 Fld(1, 5) //[5:5] + #define MISC_AD_RX_CMD_O1_AD_RX_ARCA6_O1 Fld(1, 6) //[6:6] + #define MISC_AD_RX_CMD_O1_AD_RX_ARCA7_O1 Fld(1, 7) //[7:7] + #define MISC_AD_RX_CMD_O1_AD_RX_ARCA8_O1 Fld(1, 8) //[8:8] + #define MISC_AD_RX_CMD_O1_AD_RX_ARCA9_O1 Fld(1, 9) //[9:9] + #define MISC_AD_RX_CMD_O1_AD_RX_ARCKE0_O1 Fld(1, 10) //[10:10] + #define MISC_AD_RX_CMD_O1_AD_RX_ARCKE1_O1 Fld(1, 11) //[11:11] + #define MISC_AD_RX_CMD_O1_AD_RX_ARCKE2_O1 Fld(1, 12) //[12:12] + #define MISC_AD_RX_CMD_O1_AD_RX_ARCS0_O1 Fld(1, 13) //[13:13] + #define MISC_AD_RX_CMD_O1_AD_RX_ARCS1_O1 Fld(1, 14) //[14:14] + #define MISC_AD_RX_CMD_O1_AD_RX_ARCS2_O1 Fld(1, 15) //[15:15] + +#define DDRPHY_REG_MISC_PHY_RGS_DQ (DDRPHY_NAO_BASE_ADDRESS + 0x0190) + #define MISC_PHY_RGS_DQ_RGS_ARDQ_OFFSET_FLAG_B0 Fld(8, 0) //[7:0] + #define MISC_PHY_RGS_DQ_RGS_ARDQM0_OFFSET_FLAG_B0 Fld(1, 8) //[8:8] + #define MISC_PHY_RGS_DQ_RGS_RX_ARDQS0_RDY_EYE_B0 Fld(1, 9) //[9:9] + #define MISC_PHY_RGS_DQ_APB_ARB_M_DEBUG Fld(2, 12) //[13:12] + #define MISC_PHY_RGS_DQ_SRAM_ARB_M_DEBUG Fld(2, 14) //[15:14] + #define MISC_PHY_RGS_DQ_RGS_ARDQ_OFFSET_FLAG_B1 Fld(8, 16) //[23:16] + #define MISC_PHY_RGS_DQ_RGS_ARDQM0_OFFSET_FLAG_B1 Fld(1, 24) //[24:24] + #define MISC_PHY_RGS_DQ_RGS_RX_ARDQS0_RDY_EYE_B1 Fld(1, 25) //[25:25] + #define MISC_PHY_RGS_DQ_DA_RPHYPLLGP_CK_SEL Fld(1, 31) //[31:31] + +#define DDRPHY_REG_MISC_PHY_RGS_CMD (DDRPHY_NAO_BASE_ADDRESS + 0x0194) + #define MISC_PHY_RGS_CMD_RGS_ARCA0_OFFSET_FLAG Fld(1, 0) //[0:0] + #define MISC_PHY_RGS_CMD_RGS_ARCA1_OFFSET_FLAG Fld(1, 1) //[1:1] + #define MISC_PHY_RGS_CMD_RGS_ARCA2_OFFSET_FLAG Fld(1, 2) //[2:2] + #define MISC_PHY_RGS_CMD_RGS_ARCA3_OFFSET_FLAG Fld(1, 3) //[3:3] + #define MISC_PHY_RGS_CMD_RGS_ARCA4_OFFSET_FLAG Fld(1, 4) //[4:4] + #define MISC_PHY_RGS_CMD_RGS_ARCA5_OFFSET_FLAG Fld(1, 5) //[5:5] + #define MISC_PHY_RGS_CMD_RGS_ARCA6_OFFSET_FLAG Fld(1, 6) //[6:6] + #define MISC_PHY_RGS_CMD_RGS_ARCA7_OFFSET_FLAG Fld(1, 7) //[7:7] + #define MISC_PHY_RGS_CMD_RGS_ARCA8_OFFSET_FLAG Fld(1, 8) //[8:8] + #define MISC_PHY_RGS_CMD_RGS_ARCA9_OFFSET_FLAG Fld(1, 9) //[9:9] + #define MISC_PHY_RGS_CMD_RGS_ARCKE0_OFFSET_FLAG Fld(1, 10) //[10:10] + #define MISC_PHY_RGS_CMD_RGS_ARCKE1_OFFSET_FLAG Fld(1, 11) //[11:11] + #define MISC_PHY_RGS_CMD_RGS_ARCKE2_OFFSET_FLAG Fld(1, 12) //[12:12] + #define MISC_PHY_RGS_CMD_RGS_ARCS0_OFFSET_FLAG Fld(1, 13) //[13:13] + #define MISC_PHY_RGS_CMD_RGS_ARCS1_OFFSET_FLAG Fld(1, 14) //[14:14] + #define MISC_PHY_RGS_CMD_RGS_ARCS2_OFFSET_FLAG Fld(1, 15) //[15:15] + #define MISC_PHY_RGS_CMD_RGS_RX_ARCLK_RDY_EYE Fld(1, 16) //[16:16] + #define MISC_PHY_RGS_CMD_RGS_RIMPCALOUT Fld(1, 24) //[24:24] + +#define DDRPHY_REG_MISC_PHY_RGS_STBEN_B0 (DDRPHY_NAO_BASE_ADDRESS + 0x0198) + #define MISC_PHY_RGS_STBEN_B0_AD_RX_ARDQ0_STBEN_B0 Fld(9, 0) //[8:0] + #define MISC_PHY_RGS_STBEN_B0_AD_RX_ARDQS0_STBEN_LEAD_B0 Fld(1, 16) //[16:16] + #define MISC_PHY_RGS_STBEN_B0_AD_RX_ARDQS0_STBEN_LAG_B0 Fld(1, 17) //[17:17] + #define MISC_PHY_RGS_STBEN_B0_AD_ARDLL_PD_EN_B0 Fld(1, 18) //[18:18] + #define MISC_PHY_RGS_STBEN_B0_AD_ARDLL_MON_B0 Fld(8, 24) //[31:24] + +#define DDRPHY_REG_MISC_PHY_RGS_STBEN_B1 (DDRPHY_NAO_BASE_ADDRESS + 0x019C) + #define MISC_PHY_RGS_STBEN_B1_AD_RX_ARDQ0_STBEN_B1 Fld(9, 0) //[8:0] + #define MISC_PHY_RGS_STBEN_B1_AD_RX_ARDQS0_STBEN_LEAD_B1 Fld(1, 16) //[16:16] + #define MISC_PHY_RGS_STBEN_B1_AD_RX_ARDQS0_STBEN_LAG_B1 Fld(1, 17) //[17:17] + #define MISC_PHY_RGS_STBEN_B1_AD_ARDLL_PD_EN_B1 Fld(1, 18) //[18:18] + #define MISC_PHY_RGS_STBEN_B1_AD_ARDLL_MON_B1 Fld(8, 24) //[31:24] + +#define DDRPHY_REG_MISC_PHY_RGS_STBEN_CMD (DDRPHY_NAO_BASE_ADDRESS + 0x01A0) + #define MISC_PHY_RGS_STBEN_CMD_AD_RX_ARCA0_STBEN Fld(9, 0) //[8:0] + #define MISC_PHY_RGS_STBEN_CMD_AD_RX_ARCLK_STBEN_LEAD Fld(1, 16) //[16:16] + #define MISC_PHY_RGS_STBEN_CMD_AD_RX_ARCLK_STBEN_LAG Fld(1, 17) //[17:17] + #define MISC_PHY_RGS_STBEN_CMD_AD_ARDLL_PD_EN_CA Fld(1, 18) //[18:18] + #define MISC_PHY_RGS_STBEN_CMD_AD_ARDLL_MON_CA Fld(8, 24) //[31:24] + +#define DDRPHY_REG_MISC_PHY_PICG_MON_S0 (DDRPHY_NAO_BASE_ADDRESS + 0x01A4) + #define MISC_PHY_PICG_MON_S0_PICG_MON_S0 Fld(32, 0) //[31:0] + +#define DDRPHY_REG_MISC_PHY_PICG_MON_S1 (DDRPHY_NAO_BASE_ADDRESS + 0x01A8) + #define MISC_PHY_PICG_MON_S1_PICG_MON_S1 Fld(32, 0) //[31:0] + +#define DDRPHY_REG_MISC_PHY_PICG_MON_S2 (DDRPHY_NAO_BASE_ADDRESS + 0x01AC) + #define MISC_PHY_PICG_MON_S2_PICG_MON_S2 Fld(32, 0) //[31:0] + +#define DDRPHY_REG_MISC_PHY_PICG_MON_S3 (DDRPHY_NAO_BASE_ADDRESS + 0x01B0) + #define MISC_PHY_PICG_MON_S3_PICG_MON_S3 Fld(32, 0) //[31:0] + +#define DDRPHY_REG_MISC_PHY_PICG_MON_S4 (DDRPHY_NAO_BASE_ADDRESS + 0x01B4) + #define MISC_PHY_PICG_MON_S4_PICG_MON_S4 Fld(32, 0) //[31:0] + +#define DDRPHY_REG_MISC_PHY_PICG_MON_S5 (DDRPHY_NAO_BASE_ADDRESS + 0x01B8) + #define MISC_PHY_PICG_MON_S5_PICG_MON_S5 Fld(32, 0) //[31:0] + +#define DDRPHY_REG_MISC_PHY_PICG_MON_S6 (DDRPHY_NAO_BASE_ADDRESS + 0x01BC) + #define MISC_PHY_PICG_MON_S6_PICG_MON_S6 Fld(32, 0) //[31:0] + +#define DDRPHY_REG_MISC_PHY_PICG_MON_S7 (DDRPHY_NAO_BASE_ADDRESS + 0x01C0) + #define MISC_PHY_PICG_MON_S7_PICG_MON_S7 Fld(32, 0) //[31:0] + +#define DDRPHY_REG_MISC_PHY_PICG_MON_S8 (DDRPHY_NAO_BASE_ADDRESS + 0x01C4) + #define MISC_PHY_PICG_MON_S8_PICG_MON_S8 Fld(32, 0) //[31:0] + +#define DDRPHY_REG_MISC_MBIST_STATUS (DDRPHY_NAO_BASE_ADDRESS + 0x01C8) + #define MISC_MBIST_STATUS_MISC_MBIST_PRE_RP_FAIL Fld(1, 0) //[0:0] + #define MISC_MBIST_STATUS_MISC_MBIST_PRE_RP_OK Fld(1, 1) //[1:1] + #define MISC_MBIST_STATUS_MISC_MBIST_PRE_FUSE Fld(7, 2) //[8:2] + +#define DDRPHY_REG_MISC_MBIST_STATUS2 (DDRPHY_NAO_BASE_ADDRESS + 0x01CC) + #define MISC_MBIST_STATUS2_MISC_MBIST_FAIL Fld(1, 0) //[0:0] + #define MISC_MBIST_STATUS2_MISC_MBIST_DONE Fld(1, 1) //[1:1] + +#define DDRPHY_REG_MISC_IMPCAL_STATUS1 (DDRPHY_NAO_BASE_ADDRESS + 0x01D0) + #define MISC_IMPCAL_STATUS1_DRVNDQS_SAVE_1 Fld(5, 0) //[4:0] + #define MISC_IMPCAL_STATUS1_DRVPDQS_SAVE_1 Fld(5, 8) //[12:8] + #define MISC_IMPCAL_STATUS1_ODTNDQS_SAVE_1 Fld(5, 16) //[20:16] + +#define DDRPHY_REG_MISC_IMPCAL_STATUS2 (DDRPHY_NAO_BASE_ADDRESS + 0x01D4) + #define MISC_IMPCAL_STATUS2_DRVNDQS_SAVE_2 Fld(5, 0) //[4:0] + #define MISC_IMPCAL_STATUS2_DRVPDQS_SAVE_2 Fld(5, 8) //[12:8] + #define MISC_IMPCAL_STATUS2_ODTNDQS_SAVE_2 Fld(5, 16) //[20:16] + +#define DDRPHY_REG_MISC_IMPCAL_STATUS3 (DDRPHY_NAO_BASE_ADDRESS + 0x01D8) + #define MISC_IMPCAL_STATUS3_DRVNDQ_SAVE_1 Fld(5, 0) //[4:0] + #define MISC_IMPCAL_STATUS3_DRVPDQ_SAVE_1 Fld(5, 8) //[12:8] + #define MISC_IMPCAL_STATUS3_ODTNDQ_SAVE_1 Fld(5, 16) //[20:16] + +#define DDRPHY_REG_MISC_IMPCAL_STATUS4 (DDRPHY_NAO_BASE_ADDRESS + 0x01DC) + #define MISC_IMPCAL_STATUS4_DRVNDQ_SAVE_2 Fld(5, 0) //[4:0] + #define MISC_IMPCAL_STATUS4_DRVPDQ_SAVE_2 Fld(5, 8) //[12:8] + #define MISC_IMPCAL_STATUS4_ODTNDQ_SAVE_2 Fld(5, 16) //[20:16] + +#define DDRPHY_REG_MISC_IMPCAL_STATUS5 (DDRPHY_NAO_BASE_ADDRESS + 0x01E0) + #define MISC_IMPCAL_STATUS5_DRVNWCK_SAVE_1 Fld(5, 0) //[4:0] + #define MISC_IMPCAL_STATUS5_DRVPWCK_SAVE_1 Fld(5, 8) //[12:8] + #define MISC_IMPCAL_STATUS5_DRVNWCK_SAVE_2 Fld(5, 16) //[20:16] + #define MISC_IMPCAL_STATUS5_DRVPWCK_SAVE_2 Fld(5, 24) //[28:24] + +#define DDRPHY_REG_MISC_IMPCAL_STATUS6 (DDRPHY_NAO_BASE_ADDRESS + 0x01E4) + #define MISC_IMPCAL_STATUS6_DRVNCS_SAVE_1 Fld(5, 0) //[4:0] + #define MISC_IMPCAL_STATUS6_DRVPCS_SAVE_1 Fld(5, 8) //[12:8] + +#define DDRPHY_REG_MISC_IMPCAL_STATUS7 (DDRPHY_NAO_BASE_ADDRESS + 0x01E8) + #define MISC_IMPCAL_STATUS7_DRVNCMD_SAVE_1 Fld(5, 0) //[4:0] + #define MISC_IMPCAL_STATUS7_DRVPCMD_SAVE_1 Fld(5, 8) //[12:8] + #define MISC_IMPCAL_STATUS7_ODTNCMD_SAVE_1 Fld(5, 16) //[20:16] + +#define DDRPHY_REG_MISC_IMPCAL_STATUS8 (DDRPHY_NAO_BASE_ADDRESS + 0x01EC) + #define MISC_IMPCAL_STATUS8_DRVNCMD_SAVE_2 Fld(5, 0) //[4:0] + #define MISC_IMPCAL_STATUS8_DRVPCMD_SAVE_2 Fld(5, 8) //[12:8] + #define MISC_IMPCAL_STATUS8_ODTNCMD_SAVE_2 Fld(5, 16) //[20:16] + +#define DDRPHY_REG_MISC_IMPCAL_STATUS9 (DDRPHY_NAO_BASE_ADDRESS + 0x01F4) + #define MISC_IMPCAL_STATUS9_IMPCAL_N_ERROR Fld(1, 0) //[0:0] + #define MISC_IMPCAL_STATUS9_IMPCAL_P_ERROR Fld(1, 1) //[1:1] + #define MISC_IMPCAL_STATUS9_DRVNDQC_SAVE_1 Fld(5, 10) //[14:10] + #define MISC_IMPCAL_STATUS9_DRVPDQC_SAVE_1 Fld(5, 15) //[19:15] + #define MISC_IMPCAL_STATUS9_DRVNDQC_SAVE_2 Fld(5, 20) //[24:20] + #define MISC_IMPCAL_STATUS9_DRVPDQC_SAVE_2 Fld(5, 25) //[29:25] + +#define DDRPHY_REG_MISC_STA_TOGLB0 (DDRPHY_NAO_BASE_ADDRESS + 0x01F8) + #define MISC_STA_TOGLB0_STA_TOGLB_DONE Fld(32, 0) //[31:0] + +#define DDRPHY_REG_MISC_STA_TOGLB1 (DDRPHY_NAO_BASE_ADDRESS + 0x01FC) + #define MISC_STA_TOGLB1_STA_TOGLB_FAIL Fld(32, 0) //[31:0] + +#define DDRPHY_REG_MISC_STA_EXTLB_DBG0 (DDRPHY_NAO_BASE_ADDRESS + 0x0214) + #define MISC_STA_EXTLB_DBG0_STA_EXTLB_DVS_LEAD_0TO1 Fld(32, 0) //[31:0] + +#define DDRPHY_REG_MISC_STA_EXTLB_DBG1 (DDRPHY_NAO_BASE_ADDRESS + 0x0218) + #define MISC_STA_EXTLB_DBG1_STA_EXTLB_DVS_LEAD_1TO0 Fld(32, 0) //[31:0] + +#define DDRPHY_REG_MISC_STA_EXTLB_DBG2 (DDRPHY_NAO_BASE_ADDRESS + 0x021C) + #define MISC_STA_EXTLB_DBG2_STA_EXTLB_DVS_LAG_0TO1 Fld(32, 0) //[31:0] + +#define DDRPHY_REG_MISC_STA_EXTLB_DBG3 (DDRPHY_NAO_BASE_ADDRESS + 0x0220) + #define MISC_STA_EXTLB_DBG3_STA_EXTLB_DVS_LAG_1TO0 Fld(32, 0) //[31:0] + +#define DDRPHY_REG_MISC_DUTY_TOGGLE_CNT (DDRPHY_NAO_BASE_ADDRESS + 0x0224) + #define MISC_DUTY_TOGGLE_CNT_TOGGLE_CNT Fld(32, 0) //[31:0] + +#define DDRPHY_REG_MISC_DUTY_DQS0_ERR_CNT (DDRPHY_NAO_BASE_ADDRESS + 0x0228) + #define MISC_DUTY_DQS0_ERR_CNT_DQS0_ERR_CNT Fld(32, 0) //[31:0] + +#define DDRPHY_REG_MISC_DUTY_DQ_ERR_CNT0 (DDRPHY_NAO_BASE_ADDRESS + 0x022C) + #define MISC_DUTY_DQ_ERR_CNT0_DQ_ERR_CNT0 Fld(32, 0) //[31:0] + +#define DDRPHY_REG_MISC_DUTY_DQS1_ERR_CNT (DDRPHY_NAO_BASE_ADDRESS + 0x0230) + #define MISC_DUTY_DQS1_ERR_CNT_DQS1_ERR_CNT Fld(32, 0) //[31:0] + +#define DDRPHY_REG_MISC_DUTY_DQ_ERR_CNT1 (DDRPHY_NAO_BASE_ADDRESS + 0x0234) + #define MISC_DUTY_DQ_ERR_CNT1_DQ_ERR_CNT1 Fld(32, 0) //[31:0] + +#define DDRPHY_REG_MISC_DUTY_DQS2_ERR_CNT (DDRPHY_NAO_BASE_ADDRESS + 0x0238) + #define MISC_DUTY_DQS2_ERR_CNT_DQS2_ERR_CNT Fld(32, 0) //[31:0] + +#define DDRPHY_REG_MISC_DUTY_DQ_ERR_CNT2 (DDRPHY_NAO_BASE_ADDRESS + 0x023C) + #define MISC_DUTY_DQ_ERR_CNT2_DQ_ERR_CNT2 Fld(32, 0) //[31:0] + +#define DDRPHY_REG_MISC_DUTY_DQS3_ERR_CNT (DDRPHY_NAO_BASE_ADDRESS + 0x0240) + #define MISC_DUTY_DQS3_ERR_CNT_DQS3_ERR_CNT Fld(32, 0) //[31:0] + +#define DDRPHY_REG_MISC_DUTY_DQ_ERR_CNT3 (DDRPHY_NAO_BASE_ADDRESS + 0x0244) + #define MISC_DUTY_DQ_ERR_CNT3_DQ_ERR_CNT3 Fld(32, 0) //[31:0] + +#define DDRPHY_REG_MISC_JMETER_ST0 (DDRPHY_NAO_BASE_ADDRESS + 0x0248) + #define MISC_JMETER_ST0_JMTR_DONE Fld(1, 31) //[31:31] + +#define DDRPHY_REG_MISC_JMETER_ST1 (DDRPHY_NAO_BASE_ADDRESS + 0x024C) + #define MISC_JMETER_ST1_ZEROS_CNT Fld(16, 0) //[15:0] + #define MISC_JMETER_ST1_ONES_CNT Fld(16, 16) //[31:16] + +#define DDRPHY_REG_MISC_EMI_LPBK0 (DDRPHY_NAO_BASE_ADDRESS + 0x0250) + #define MISC_EMI_LPBK0_RDATA_DQ0_B0 Fld(16, 0) //[15:0] + #define MISC_EMI_LPBK0_RDATA_DQ1_B0 Fld(16, 16) //[31:16] + +#define DDRPHY_REG_MISC_EMI_LPBK1 (DDRPHY_NAO_BASE_ADDRESS + 0x0254) + #define MISC_EMI_LPBK1_RDATA_DQ2_B0 Fld(16, 0) //[15:0] + #define MISC_EMI_LPBK1_RDATA_DQ3_B0 Fld(16, 16) //[31:16] + +#define DDRPHY_REG_MISC_EMI_LPBK2 (DDRPHY_NAO_BASE_ADDRESS + 0x0258) + #define MISC_EMI_LPBK2_RDATA_DQ4_B0 Fld(16, 0) //[15:0] + #define MISC_EMI_LPBK2_RDATA_DQ5_B0 Fld(16, 16) //[31:16] + +#define DDRPHY_REG_MISC_EMI_LPBK3 (DDRPHY_NAO_BASE_ADDRESS + 0x025C) + #define MISC_EMI_LPBK3_RDATA_DQ6_B0 Fld(16, 0) //[15:0] + #define MISC_EMI_LPBK3_RDATA_DQ7_B0 Fld(16, 16) //[31:16] + +#define DDRPHY_REG_MISC_EMI_LPBK4 (DDRPHY_NAO_BASE_ADDRESS + 0x0260) + #define MISC_EMI_LPBK4_RDATA_DQ0_B1 Fld(16, 0) //[15:0] + #define MISC_EMI_LPBK4_RDATA_DQ1_B1 Fld(16, 16) //[31:16] + +#define DDRPHY_REG_MISC_EMI_LPBK5 (DDRPHY_NAO_BASE_ADDRESS + 0x0264) + #define MISC_EMI_LPBK5_RDATA_DQ2_B1 Fld(16, 0) //[15:0] + #define MISC_EMI_LPBK5_RDATA_DQ3_B1 Fld(16, 16) //[31:16] + +#define DDRPHY_REG_MISC_EMI_LPBK6 (DDRPHY_NAO_BASE_ADDRESS + 0x0268) + #define MISC_EMI_LPBK6_RDATA_DQ4_B1 Fld(16, 0) //[15:0] + #define MISC_EMI_LPBK6_RDATA_DQ5_B1 Fld(16, 16) //[31:16] + +#define DDRPHY_REG_MISC_EMI_LPBK7 (DDRPHY_NAO_BASE_ADDRESS + 0x026C) + #define MISC_EMI_LPBK7_RDATA_DQ6_B1 Fld(16, 0) //[15:0] + #define MISC_EMI_LPBK7_RDATA_DQ7_B1 Fld(16, 16) //[31:16] + +#define DDRPHY_REG_MISC_FT_STATUS0 (DDRPHY_NAO_BASE_ADDRESS + 0x0270) + #define MISC_FT_STATUS0_AD_RX_ARDQ_DVS_R_LAG_B1 Fld(8, 0) //[7:0] + #define MISC_FT_STATUS0_AD_RX_ARDQ_DVS_R_LEAD_B1 Fld(8, 8) //[15:8] + #define MISC_FT_STATUS0_AD_RX_ARDQ_DVS_R_LAG_B0 Fld(8, 16) //[23:16] + #define MISC_FT_STATUS0_AD_RX_ARDQ_DVS_R_LEAD_B0 Fld(8, 24) //[31:24] + +#define DDRPHY_REG_MISC_FT_STATUS1 (DDRPHY_NAO_BASE_ADDRESS + 0x0274) + #define MISC_FT_STATUS1_AD_RX_ARDQ_DVS_F_LAG_B1 Fld(8, 0) //[7:0] + #define MISC_FT_STATUS1_AD_RX_ARDQ_DVS_F_LEAD_B1 Fld(8, 8) //[15:8] + #define MISC_FT_STATUS1_AD_RX_ARDQ_DVS_F_LAG_B0 Fld(8, 16) //[23:16] + #define MISC_FT_STATUS1_AD_RX_ARDQ_DVS_F_LEAD_B0 Fld(8, 24) //[31:24] + +#define DDRPHY_REG_MISC_FT_STATUS2 (DDRPHY_NAO_BASE_ADDRESS + 0x0278) + #define MISC_FT_STATUS2_AD_RRESETB_O Fld(1, 0) //[0:0] + +#define DDRPHY_REG_MISC_FT_STATUS3 (DDRPHY_NAO_BASE_ADDRESS + 0x027C) + #define MISC_FT_STATUS3_AD_RX_ARCA0_DVS_R_LAG Fld(1, 0) //[0:0] + #define MISC_FT_STATUS3_AD_RX_ARCA1_DVS_R_LAG Fld(1, 1) //[1:1] + #define MISC_FT_STATUS3_AD_RX_ARCA2_DVS_R_LAG Fld(1, 2) //[2:2] + #define MISC_FT_STATUS3_AD_RX_ARCA3_DVS_R_LAG Fld(1, 3) //[3:3] + #define MISC_FT_STATUS3_AD_RX_ARCA4_DVS_R_LAG Fld(1, 4) //[4:4] + #define MISC_FT_STATUS3_AD_RX_ARCA5_DVS_R_LAG Fld(1, 5) //[5:5] + #define MISC_FT_STATUS3_AD_RX_ARCKE0_DVS_R_LAG Fld(1, 6) //[6:6] + #define MISC_FT_STATUS3_AD_RX_ARCKE1_DVS_R_LAG Fld(1, 7) //[7:7] + #define MISC_FT_STATUS3_AD_RX_ARCS0_DVS_R_LAG Fld(1, 8) //[8:8] + #define MISC_FT_STATUS3_AD_RX_ARCS1_DVS_R_LAG Fld(1, 9) //[9:9] + #define MISC_FT_STATUS3_AD_RX_ARCA0_DVS_R_LEAD Fld(1, 16) //[16:16] + #define MISC_FT_STATUS3_AD_RX_ARCA1_DVS_R_LEAD Fld(1, 17) //[17:17] + #define MISC_FT_STATUS3_AD_RX_ARCA2_DVS_R_LEAD Fld(1, 18) //[18:18] + #define MISC_FT_STATUS3_AD_RX_ARCA3_DVS_R_LEAD Fld(1, 19) //[19:19] + #define MISC_FT_STATUS3_AD_RX_ARCA4_DVS_R_LEAD Fld(1, 20) //[20:20] + #define MISC_FT_STATUS3_AD_RX_ARCA5_DVS_R_LEAD Fld(1, 21) //[21:21] + #define MISC_FT_STATUS3_AD_RX_ARCKE0_DVS_R_LEAD Fld(1, 22) //[22:22] + #define MISC_FT_STATUS3_AD_RX_ARCKE1_DVS_R_LEAD Fld(1, 23) //[23:23] + #define MISC_FT_STATUS3_AD_RX_ARCS0_DVS_R_LEAD Fld(1, 24) //[24:24] + #define MISC_FT_STATUS3_AD_RX_ARCS1_DVS_R_LEAD Fld(1, 25) //[25:25] + +#define DDRPHY_REG_MISC_FT_STATUS4 (DDRPHY_NAO_BASE_ADDRESS + 0x0280) + #define MISC_FT_STATUS4_AD_RX_ARCA0_DVS_F_LAG Fld(1, 0) //[0:0] + #define MISC_FT_STATUS4_AD_RX_ARCA1_DVS_F_LAG Fld(1, 1) //[1:1] + #define MISC_FT_STATUS4_AD_RX_ARCA2_DVS_F_LAG Fld(1, 2) //[2:2] + #define MISC_FT_STATUS4_AD_RX_ARCA3_DVS_F_LAG Fld(1, 3) //[3:3] + #define MISC_FT_STATUS4_AD_RX_ARCA4_DVS_F_LAG Fld(1, 4) //[4:4] + #define MISC_FT_STATUS4_AD_RX_ARCA5_DVS_F_LAG Fld(1, 5) //[5:5] + #define MISC_FT_STATUS4_AD_RX_ARCKE0_DVS_F_LAG Fld(1, 6) //[6:6] + #define MISC_FT_STATUS4_AD_RX_ARCKE1_DVS_F_LAG Fld(1, 7) //[7:7] + #define MISC_FT_STATUS4_AD_RX_ARCS0_DVS_F_LAG Fld(1, 8) //[8:8] + #define MISC_FT_STATUS4_AD_RX_ARCS1_DVS_F_LAG Fld(1, 9) //[9:9] + #define MISC_FT_STATUS4_AD_RX_ARCA0_DVS_F_LEAD Fld(1, 16) //[16:16] + #define MISC_FT_STATUS4_AD_RX_ARCA1_DVS_F_LEAD Fld(1, 17) //[17:17] + #define MISC_FT_STATUS4_AD_RX_ARCA2_DVS_F_LEAD Fld(1, 18) //[18:18] + #define MISC_FT_STATUS4_AD_RX_ARCA3_DVS_F_LEAD Fld(1, 19) //[19:19] + #define MISC_FT_STATUS4_AD_RX_ARCA4_DVS_F_LEAD Fld(1, 20) //[20:20] + #define MISC_FT_STATUS4_AD_RX_ARCA5_DVS_F_LEAD Fld(1, 21) //[21:21] + #define MISC_FT_STATUS4_AD_RX_ARCKE0_DVS_F_LEAD Fld(1, 22) //[22:22] + #define MISC_FT_STATUS4_AD_RX_ARCKE1_DVS_F_LEAD Fld(1, 23) //[23:23] + #define MISC_FT_STATUS4_AD_RX_ARCS0_DVS_F_LEAD Fld(1, 24) //[24:24] + #define MISC_FT_STATUS4_AD_RX_ARCS1_DVS_F_LEAD Fld(1, 25) //[25:25] + +#define DDRPHY_REG_MISC_STA_TOGLB2 (DDRPHY_NAO_BASE_ADDRESS + 0x0284) + #define MISC_STA_TOGLB2_STA_TOGLB_PUHI_TIMEOUT Fld(32, 0) //[31:0] + +#define DDRPHY_REG_MISC_STA_TOGLB3 (DDRPHY_NAO_BASE_ADDRESS + 0x0288) + #define MISC_STA_TOGLB3_STA_TOGLB_PULO_TIMEOUT Fld(32, 0) //[31:0] + +#define DDRPHY_REG_MISC_STA_EXTLB3 (DDRPHY_NAO_BASE_ADDRESS + 0x028C) + #define MISC_STA_EXTLB3_STA_EXTLB_RISING_FAIL Fld(32, 0) //[31:0] + +#define DDRPHY_REG_MISC_STA_EXTLB4 (DDRPHY_NAO_BASE_ADDRESS + 0x0290) + #define MISC_STA_EXTLB4_STA_EXTLB_FALLING_FAIL Fld(32, 0) //[31:0] + +#define DDRPHY_REG_MISC_STA_EXTLB5 (DDRPHY_NAO_BASE_ADDRESS + 0x0294) + #define MISC_STA_EXTLB5_STA_EXTLB_DBG_INFO2 Fld(32, 0) //[31:0] + +#define DDRPHY_REG_DEBUG_APHY_RX_CTL (DDRPHY_NAO_BASE_ADDRESS + 0x0400) + #define DEBUG_APHY_RX_CTL_DEBUG_STATUS_APHY_RX_CTL Fld(32, 0) //[31:0] + +#define DDRPHY_REG_GATING_ERR_INFOR (DDRPHY_NAO_BASE_ADDRESS + 0x0410) + #define GATING_ERR_INFOR_STB_GATING_ERR Fld(1, 0) //[0:0] + #define GATING_ERR_INFOR_STBUPD_STOP Fld(1, 1) //[1:1] + #define GATING_ERR_INFOR_R_OTHER_SHU_GP_GATING_ERR Fld(2, 4) //[5:4] + #define GATING_ERR_INFOR_R_MPDIV_SHU_GP_GATING_ERR Fld(3, 8) //[10:8] + #define GATING_ERR_INFOR_GATING_ERR_INF_STATUS Fld(4, 16) //[19:16] + #define GATING_ERR_INFOR_GATING_ERR_PRE_SHU_ST Fld(4, 20) //[23:20] + #define GATING_ERR_INFOR_GATING_ERR_CUR_SHU_ST Fld(4, 24) //[27:24] + +#define DDRPHY_REG_DEBUG_DQSIEN_B0 (DDRPHY_NAO_BASE_ADDRESS + 0x0414) + #define DEBUG_DQSIEN_B0_DQSIEN_PICG_HEAD_ERR_FLAG_B0_RK0 Fld(1, 0) //[0:0] + #define DEBUG_DQSIEN_B0_STB_CNT_SHU_ST_ERR_FLAG_B0_RK0 Fld(1, 1) //[1:1] + #define DEBUG_DQSIEN_B0_DQSIEN_PICG_HEAD_ERR_FLAG_B0_RK1 Fld(1, 16) //[16:16] + #define DEBUG_DQSIEN_B0_STB_CNT_SHU_ST_ERR_FLAG_B0_RK1 Fld(1, 17) //[17:17] + +#define DDRPHY_REG_DEBUG_DQSIEN_B1 (DDRPHY_NAO_BASE_ADDRESS + 0x0418) + #define DEBUG_DQSIEN_B1_DQSIEN_PICG_HEAD_ERR_FLAG_B1_RK0 Fld(1, 0) //[0:0] + #define DEBUG_DQSIEN_B1_STB_CNT_SHU_ST_ERR_FLAG_B1_RK0 Fld(1, 1) //[1:1] + #define DEBUG_DQSIEN_B1_DQSIEN_PICG_HEAD_ERR_FLAG_B1_RK1 Fld(1, 16) //[16:16] + #define DEBUG_DQSIEN_B1_STB_CNT_SHU_ST_ERR_FLAG_B1_RK1 Fld(1, 17) //[17:17] + +#define DDRPHY_REG_DEBUG_DQSIEN_CA (DDRPHY_NAO_BASE_ADDRESS + 0x041C) + #define DEBUG_DQSIEN_CA_DQSIEN_PICG_HEAD_ERR_FLAG_CA_RK0 Fld(1, 0) //[0:0] + #define DEBUG_DQSIEN_CA_STB_CNT_SHU_ST_ERR_FLAG_CA_RK0 Fld(1, 1) //[1:1] + #define DEBUG_DQSIEN_CA_DQSIEN_PICG_HEAD_ERR_FLAG_CA_RK1 Fld(1, 16) //[16:16] + #define DEBUG_DQSIEN_CA_STB_CNT_SHU_ST_ERR_FLAG_CA_RK1 Fld(1, 17) //[17:17] + +#define DDRPHY_REG_GATING_ERR_LATCH_DLY_B0_RK0 (DDRPHY_NAO_BASE_ADDRESS + 0x0420) + #define GATING_ERR_LATCH_DLY_B0_RK0_DQSIEN0_PI_DLY_RK0 Fld(7, 0) //[6:0] + #define GATING_ERR_LATCH_DLY_B0_RK0_DQSIEN0_UI_P0_DLY_RK0 Fld(8, 16) //[23:16] + #define GATING_ERR_LATCH_DLY_B0_RK0_DQSIEN0_UI_P1_DLY_RK0 Fld(8, 24) //[31:24] + +#define DDRPHY_REG_GATING_ERR_LATCH_DLY_B1_RK0 (DDRPHY_NAO_BASE_ADDRESS + 0x0424) + #define GATING_ERR_LATCH_DLY_B1_RK0_DQSIEN1_PI_DLY_RK0 Fld(7, 0) //[6:0] + #define GATING_ERR_LATCH_DLY_B1_RK0_DQSIEN1_UI_P0_DLY_RK0 Fld(8, 16) //[23:16] + #define GATING_ERR_LATCH_DLY_B1_RK0_DQSIEN1_UI_P1_DLY_RK0 Fld(8, 24) //[31:24] + +#define DDRPHY_REG_GATING_ERR_LATCH_DLY_CA_RK0 (DDRPHY_NAO_BASE_ADDRESS + 0x0428) + #define GATING_ERR_LATCH_DLY_CA_RK0_DQSIEN2_PI_DLY_RK0 Fld(7, 0) //[6:0] + #define GATING_ERR_LATCH_DLY_CA_RK0_DQSIEN2_UI_P0_DLY_RK0 Fld(8, 16) //[23:16] + #define GATING_ERR_LATCH_DLY_CA_RK0_DQSIEN2_UI_P1_DLY_RK0 Fld(8, 24) //[31:24] + +#define DDRPHY_REG_GATING_ERR_LATCH_DLY_B0_RK1 (DDRPHY_NAO_BASE_ADDRESS + 0x0430) + #define GATING_ERR_LATCH_DLY_B0_RK1_DQSIEN0_PI_DLY_RK1 Fld(7, 0) //[6:0] + #define GATING_ERR_LATCH_DLY_B0_RK1_DQSIEN0_UI_P0_DLY_RK1 Fld(8, 16) //[23:16] + #define GATING_ERR_LATCH_DLY_B0_RK1_DQSIEN0_UI_P1_DLY_RK1 Fld(8, 24) //[31:24] + +#define DDRPHY_REG_GATING_ERR_LATCH_DLY_B1_RK1 (DDRPHY_NAO_BASE_ADDRESS + 0x0434) + #define GATING_ERR_LATCH_DLY_B1_RK1_DQSIEN1_PI_DLY_RK1 Fld(7, 0) //[6:0] + #define GATING_ERR_LATCH_DLY_B1_RK1_DQSIEN1_UI_P0_DLY_RK1 Fld(8, 16) //[23:16] + #define GATING_ERR_LATCH_DLY_B1_RK1_DQSIEN1_UI_P1_DLY_RK1 Fld(8, 24) //[31:24] + +#define DDRPHY_REG_GATING_ERR_LATCH_DLY_CA_RK1 (DDRPHY_NAO_BASE_ADDRESS + 0x0438) + #define GATING_ERR_LATCH_DLY_CA_RK1_DQSIEN2_PI_DLY_RK1 Fld(7, 0) //[6:0] + #define GATING_ERR_LATCH_DLY_CA_RK1_DQSIEN2_UI_P0_DLY_RK1 Fld(8, 16) //[23:16] + #define GATING_ERR_LATCH_DLY_CA_RK1_DQSIEN2_UI_P1_DLY_RK1 Fld(8, 24) //[31:24] + +#define DDRPHY_REG_DEBUG_RODT_CTL (DDRPHY_NAO_BASE_ADDRESS + 0x0440) + #define DEBUG_RODT_CTL_DEBUG_STATUS_RODTCTL Fld(32, 0) //[31:0] + +#define DDRPHY_REG_CAL_DQSG_CNT_B0 (DDRPHY_NAO_BASE_ADDRESS + 0x0500) + #define CAL_DQSG_CNT_B0_DQS_B0_F_GATING_COUNTER Fld(8, 0) //[7:0] + #define CAL_DQSG_CNT_B0_DQS_B0_R_GATING_COUNTER Fld(8, 8) //[15:8] + +#define DDRPHY_REG_CAL_DQSG_CNT_B1 (DDRPHY_NAO_BASE_ADDRESS + 0x0504) + #define CAL_DQSG_CNT_B1_DQS_B1_F_GATING_COUNTER Fld(8, 0) //[7:0] + #define CAL_DQSG_CNT_B1_DQS_B1_R_GATING_COUNTER Fld(8, 8) //[15:8] + +#define DDRPHY_REG_CAL_DQSG_CNT_CA (DDRPHY_NAO_BASE_ADDRESS + 0x0508) + #define CAL_DQSG_CNT_CA_DQS_CA_F_GATING_COUNTER Fld(8, 0) //[7:0] + #define CAL_DQSG_CNT_CA_DQS_CA_R_GATING_COUNTER Fld(8, 8) //[15:8] + +#define DDRPHY_REG_DVFS_STATUS (DDRPHY_NAO_BASE_ADDRESS + 0x050C) + #define DVFS_STATUS_CUT_PHY_ST_SHU Fld(8, 0) //[7:0] + #define DVFS_STATUS_PLL_SEL Fld(1, 8) //[8:8] + #define DVFS_STATUS_MPDIV_SHU_GP Fld(3, 12) //[14:12] + #define DVFS_STATUS_OTHER_SHU_GP Fld(2, 16) //[17:16] + #define DVFS_STATUS_PICG_SHUFFLE Fld(1, 20) //[20:20] + #define DVFS_STATUS_SHUFFLE_PHY_STATE_START Fld(1, 21) //[21:21] + #define DVFS_STATUS_SHUFFLE_PHY_STATE_DONE Fld(1, 22) //[22:22] + #define DVFS_STATUS_SHUFFLE_PERIOD Fld(1, 23) //[23:23] + +#define DDRPHY_REG_RX_AUTOK_STATUS0 (DDRPHY_NAO_BASE_ADDRESS + 0x0510) + #define RX_AUTOK_STATUS0_RO_RX_CAL_FAIL Fld(1, 0) //[0:0] + #define RX_AUTOK_STATUS0_RO_RX_CAL_PASS Fld(1, 1) //[1:1] + #define RX_AUTOK_STATUS0_RO_RX_CAL_DONE Fld(1, 2) //[2:2] + #define RX_AUTOK_STATUS0_RO_RX_CAL_OUT_WIN1_LEN_ARDQX Fld(10, 4) //[13:4] + #define RX_AUTOK_STATUS0_RO_RX_CAL_OUT_WIN1_BEGIN_ARDQX Fld(11, 16) //[26:16] + +#define DDRPHY_REG_RX_AUTOK_STATUS1 (DDRPHY_NAO_BASE_ADDRESS + 0x0514) + #define RX_AUTOK_STATUS1_RO_RX_CAL_OUT_WIN2_LEN_ARDQX Fld(10, 4) //[13:4] + #define RX_AUTOK_STATUS1_RO_RX_CAL_OUT_WIN2_BEGIN_ARDQX Fld(11, 16) //[26:16] + +#define DDRPHY_REG_RX_AUTOK_STATUS2 (DDRPHY_NAO_BASE_ADDRESS + 0x0518) + #define RX_AUTOK_STATUS2_RO_RX_CAL_OUT_WIN3_LEN_ARDQX Fld(10, 4) //[13:4] + #define RX_AUTOK_STATUS2_RO_RX_CAL_OUT_WIN3_BEGIN_ARDQX Fld(11, 16) //[26:16] + +#define DDRPHY_REG_RX_AUTOK_STATUS3 (DDRPHY_NAO_BASE_ADDRESS + 0x051C) + #define RX_AUTOK_STATUS3_RO_RX_CAL_OUT_WIN4_LEN_ARDQX Fld(10, 4) //[13:4] + #define RX_AUTOK_STATUS3_RO_RX_CAL_OUT_WIN4_BEGIN_ARDQX Fld(11, 16) //[26:16] + +#define DDRPHY_REG_RX_AUTOK_STATUS4 (DDRPHY_NAO_BASE_ADDRESS + 0x0520) + #define RX_AUTOK_STATUS4_RO_RX_CAL_OUT_WIN5_LEN_ARDQX Fld(10, 4) //[13:4] + #define RX_AUTOK_STATUS4_RO_RX_CAL_OUT_WIN5_BEGIN_ARDQX Fld(11, 16) //[26:16] + +#define DDRPHY_REG_RX_AUTOK_STATUS5 (DDRPHY_NAO_BASE_ADDRESS + 0x0524) + #define RX_AUTOK_STATUS5_RO_RX_CAL_OUT_MAX_WIN_LEN_ARDQ0 Fld(10, 4) //[13:4] + #define RX_AUTOK_STATUS5_RO_RX_CAL_OUT_MAX_WIN_BEGIN_ARDQ0 Fld(11, 16) //[26:16] + +#define DDRPHY_REG_RX_AUTOK_STATUS6 (DDRPHY_NAO_BASE_ADDRESS + 0x0528) + #define RX_AUTOK_STATUS6_RO_RX_CAL_OUT_MAX_WIN_LEN_ARDQ1 Fld(10, 4) //[13:4] + #define RX_AUTOK_STATUS6_RO_RX_CAL_OUT_MAX_WIN_BEGIN_ARDQ1 Fld(11, 16) //[26:16] + +#define DDRPHY_REG_RX_AUTOK_STATUS7 (DDRPHY_NAO_BASE_ADDRESS + 0x052C) + #define RX_AUTOK_STATUS7_RO_RX_CAL_OUT_MAX_WIN_LEN_ARDQ2 Fld(10, 4) //[13:4] + #define RX_AUTOK_STATUS7_RO_RX_CAL_OUT_MAX_WIN_BEGIN_ARDQ2 Fld(11, 16) //[26:16] + +#define DDRPHY_REG_RX_AUTOK_STATUS8 (DDRPHY_NAO_BASE_ADDRESS + 0x0530) + #define RX_AUTOK_STATUS8_RO_RX_CAL_OUT_MAX_WIN_LEN_ARDQ3 Fld(10, 4) //[13:4] + #define RX_AUTOK_STATUS8_RO_RX_CAL_OUT_MAX_WIN_BEGIN_ARDQ3 Fld(11, 16) //[26:16] + +#define DDRPHY_REG_RX_AUTOK_STATUS9 (DDRPHY_NAO_BASE_ADDRESS + 0x0534) + #define RX_AUTOK_STATUS9_RO_RX_CAL_OUT_MAX_WIN_LEN_ARDQ4 Fld(10, 4) //[13:4] + #define RX_AUTOK_STATUS9_RO_RX_CAL_OUT_MAX_WIN_BEGIN_ARDQ4 Fld(11, 16) //[26:16] + +#define DDRPHY_REG_RX_AUTOK_STATUS10 (DDRPHY_NAO_BASE_ADDRESS + 0x0538) + #define RX_AUTOK_STATUS10_RO_RX_CAL_OUT_MAX_WIN_LEN_ARDQ5 Fld(10, 4) //[13:4] + #define RX_AUTOK_STATUS10_RO_RX_CAL_OUT_MAX_WIN_BEGIN_ARDQ5 Fld(11, 16) //[26:16] + +#define DDRPHY_REG_RX_AUTOK_STATUS11 (DDRPHY_NAO_BASE_ADDRESS + 0x053C) + #define RX_AUTOK_STATUS11_RO_RX_CAL_OUT_MAX_WIN_LEN_ARDQ6 Fld(10, 4) //[13:4] + #define RX_AUTOK_STATUS11_RO_RX_CAL_OUT_MAX_WIN_BEGIN_ARDQ6 Fld(11, 16) //[26:16] + +#define DDRPHY_REG_RX_AUTOK_STATUS12 (DDRPHY_NAO_BASE_ADDRESS + 0x0540) + #define RX_AUTOK_STATUS12_RO_RX_CAL_OUT_MAX_WIN_LEN_ARDQ7 Fld(10, 4) //[13:4] + #define RX_AUTOK_STATUS12_RO_RX_CAL_OUT_MAX_WIN_BEGIN_ARDQ7 Fld(11, 16) //[26:16] + +#define DDRPHY_REG_RX_AUTOK_STATUS13 (DDRPHY_NAO_BASE_ADDRESS + 0x0544) + #define RX_AUTOK_STATUS13_RO_RX_CAL_OUT_MAX_WIN_LEN_ARDQ8 Fld(10, 4) //[13:4] + #define RX_AUTOK_STATUS13_RO_RX_CAL_OUT_MAX_WIN_BEGIN_ARDQ8 Fld(11, 16) //[26:16] + +#define DDRPHY_REG_RX_AUTOK_STATUS14 (DDRPHY_NAO_BASE_ADDRESS + 0x0548) + #define RX_AUTOK_STATUS14_RO_RX_CAL_OUT_MAX_WIN_LEN_ARDQ9 Fld(10, 4) //[13:4] + #define RX_AUTOK_STATUS14_RO_RX_CAL_OUT_MAX_WIN_BEGIN_ARDQ9 Fld(11, 16) //[26:16] + +#define DDRPHY_REG_RX_AUTOK_STATUS15 (DDRPHY_NAO_BASE_ADDRESS + 0x054C) + #define RX_AUTOK_STATUS15_RO_RX_CAL_OUT_MAX_WIN_LEN_ARDQ10 Fld(10, 4) //[13:4] + #define RX_AUTOK_STATUS15_RO_RX_CAL_OUT_MAX_WIN_BEGIN_ARDQ10 Fld(11, 16) //[26:16] + +#define DDRPHY_REG_RX_AUTOK_STATUS16 (DDRPHY_NAO_BASE_ADDRESS + 0x0550) + #define RX_AUTOK_STATUS16_RO_RX_CAL_OUT_MAX_WIN_LEN_ARDQ11 Fld(10, 4) //[13:4] + #define RX_AUTOK_STATUS16_RO_RX_CAL_OUT_MAX_WIN_BEGIN_ARDQ11 Fld(11, 16) //[26:16] + +#define DDRPHY_REG_RX_AUTOK_STATUS17 (DDRPHY_NAO_BASE_ADDRESS + 0x0554) + #define RX_AUTOK_STATUS17_RO_RX_CAL_OUT_MAX_WIN_LEN_ARDQ12 Fld(10, 4) //[13:4] + #define RX_AUTOK_STATUS17_RO_RX_CAL_OUT_MAX_WIN_BEGIN_ARDQ12 Fld(11, 16) //[26:16] + +#define DDRPHY_REG_RX_AUTOK_STATUS18 (DDRPHY_NAO_BASE_ADDRESS + 0x0558) + #define RX_AUTOK_STATUS18_RO_RX_CAL_OUT_MAX_WIN_LEN_ARDQ13 Fld(10, 4) //[13:4] + #define RX_AUTOK_STATUS18_RO_RX_CAL_OUT_MAX_WIN_BEGIN_ARDQ13 Fld(11, 16) //[26:16] + +#define DDRPHY_REG_RX_AUTOK_STATUS19 (DDRPHY_NAO_BASE_ADDRESS + 0x055C) + #define RX_AUTOK_STATUS19_RO_RX_CAL_OUT_MAX_WIN_LEN_ARDQ14 Fld(10, 4) //[13:4] + #define RX_AUTOK_STATUS19_RO_RX_CAL_OUT_MAX_WIN_BEGIN_ARDQ14 Fld(11, 16) //[26:16] + +#define DDRPHY_REG_RX_AUTOK_STATUS20 (DDRPHY_NAO_BASE_ADDRESS + 0x0560) + #define RX_AUTOK_STATUS20_RO_RX_CAL_OUT_MAX_WIN_LEN_ARDQ15 Fld(10, 4) //[13:4] + #define RX_AUTOK_STATUS20_RO_RX_CAL_OUT_MAX_WIN_BEGIN_ARDQ15 Fld(11, 16) //[26:16] + +#define DDRPHY_REG_DQSIEN_AUTOK_B0_RK0_STATUS0 (DDRPHY_NAO_BASE_ADDRESS + 0x0600) + #define DQSIEN_AUTOK_B0_RK0_STATUS0_DQSIEN_AUTOK_C__PI_B0_RK0 Fld(7, 0) //[6:0] + #define DQSIEN_AUTOK_B0_RK0_STATUS0_DQSIEN_AUTOK_C__UI_B0_RK0 Fld(4, 8) //[11:8] + #define DQSIEN_AUTOK_B0_RK0_STATUS0_DQSIEN_AUTOK_C_MCK_B0_RK0 Fld(4, 12) //[15:12] + #define DQSIEN_AUTOK_B0_RK0_STATUS0_AUTOK_DONE_B0_RK0 Fld(1, 16) //[16:16] + #define DQSIEN_AUTOK_B0_RK0_STATUS0_AUTOK_ERR_B0_RK0 Fld(1, 17) //[17:17] + +#define DDRPHY_REG_DQSIEN_AUTOK_B0_RK0_STATUS1 (DDRPHY_NAO_BASE_ADDRESS + 0x0604) + #define DQSIEN_AUTOK_B0_RK0_STATUS1_DQSIEN_AUTOK_R__PI_B0_RK0 Fld(7, 0) //[6:0] + #define DQSIEN_AUTOK_B0_RK0_STATUS1_DQSIEN_AUTOK_R__UI_B0_RK0 Fld(4, 8) //[11:8] + #define DQSIEN_AUTOK_B0_RK0_STATUS1_DQSIEN_AUTOK_R_MCK_B0_RK0 Fld(4, 12) //[15:12] + #define DQSIEN_AUTOK_B0_RK0_STATUS1_DQSIEN_AUTOK_L__PI_B0_RK0 Fld(7, 16) //[22:16] + #define DQSIEN_AUTOK_B0_RK0_STATUS1_DQSIEN_AUTOK_L__UI_B0_RK0 Fld(4, 24) //[27:24] + #define DQSIEN_AUTOK_B0_RK0_STATUS1_DQSIEN_AUTOK_L_MCK_B0_RK0 Fld(4, 28) //[31:28] + +#define DDRPHY_REG_DQSIEN_AUTOK_B0_RK0_DBG_STATUS0 (DDRPHY_NAO_BASE_ADDRESS + 0x0608) + #define DQSIEN_AUTOK_B0_RK0_DBG_STATUS0_DBG_GATING_STATUS_0_B0_RK0 Fld(32, 0) //[31:0] + +#define DDRPHY_REG_DQSIEN_AUTOK_B0_RK0_DBG_STATUS1 (DDRPHY_NAO_BASE_ADDRESS + 0x060C) + #define DQSIEN_AUTOK_B0_RK0_DBG_STATUS1_DBG_GATING_STATUS_1_B0_RK0 Fld(32, 0) //[31:0] + +#define DDRPHY_REG_DQSIEN_AUTOK_B0_RK0_DBG_STATUS2 (DDRPHY_NAO_BASE_ADDRESS + 0x0610) + #define DQSIEN_AUTOK_B0_RK0_DBG_STATUS2_DBG_GATING_STATUS_2_B0_RK0 Fld(32, 0) //[31:0] + +#define DDRPHY_REG_DQSIEN_AUTOK_B0_RK0_DBG_STATUS3 (DDRPHY_NAO_BASE_ADDRESS + 0x0614) + #define DQSIEN_AUTOK_B0_RK0_DBG_STATUS3_DBG_GATING_STATUS_3_B0_RK0 Fld(32, 0) //[31:0] + +#define DDRPHY_REG_DQSIEN_AUTOK_B0_RK0_DBG_STATUS4 (DDRPHY_NAO_BASE_ADDRESS + 0x0618) + #define DQSIEN_AUTOK_B0_RK0_DBG_STATUS4_DBG_GATING_STATUS_4_B0_RK0 Fld(32, 0) //[31:0] + +#define DDRPHY_REG_DQSIEN_AUTOK_B0_RK0_DBG_STATUS5 (DDRPHY_NAO_BASE_ADDRESS + 0x061C) + #define DQSIEN_AUTOK_B0_RK0_DBG_STATUS5_DBG_GATING_STATUS_5_B0_RK0 Fld(32, 0) //[31:0] + +#define DDRPHY_REG_DQSIEN_AUTOK_B0_RK1_STATUS0 (DDRPHY_NAO_BASE_ADDRESS + 0x0620) + #define DQSIEN_AUTOK_B0_RK1_STATUS0_DQSIEN_AUTOK_C__PI_B0_RK1 Fld(7, 0) //[6:0] + #define DQSIEN_AUTOK_B0_RK1_STATUS0_DQSIEN_AUTOK_C__UI_B0_RK1 Fld(4, 8) //[11:8] + #define DQSIEN_AUTOK_B0_RK1_STATUS0_DQSIEN_AUTOK_C_MCK_B0_RK1 Fld(4, 12) //[15:12] + #define DQSIEN_AUTOK_B0_RK1_STATUS0_AUTOK_DONE_B0_RK1 Fld(1, 16) //[16:16] + #define DQSIEN_AUTOK_B0_RK1_STATUS0_AUTOK_ERR_B0_RK1 Fld(1, 17) //[17:17] + +#define DDRPHY_REG_DQSIEN_AUTOK_B0_RK1_STATUS1 (DDRPHY_NAO_BASE_ADDRESS + 0x0624) + #define DQSIEN_AUTOK_B0_RK1_STATUS1_DQSIEN_AUTOK_R__PI_B0_RK1 Fld(7, 0) //[6:0] + #define DQSIEN_AUTOK_B0_RK1_STATUS1_DQSIEN_AUTOK_R__UI_B0_RK1 Fld(4, 8) //[11:8] + #define DQSIEN_AUTOK_B0_RK1_STATUS1_DQSIEN_AUTOK_R_MCK_B0_RK1 Fld(4, 12) //[15:12] + #define DQSIEN_AUTOK_B0_RK1_STATUS1_DQSIEN_AUTOK_L__PI_B0_RK1 Fld(7, 16) //[22:16] + #define DQSIEN_AUTOK_B0_RK1_STATUS1_DQSIEN_AUTOK_L__UI_B0_RK1 Fld(4, 24) //[27:24] + #define DQSIEN_AUTOK_B0_RK1_STATUS1_DQSIEN_AUTOK_L_MCK_B0_RK1 Fld(4, 28) //[31:28] + +#define DDRPHY_REG_DQSIEN_AUTOK_B0_RK1_DBG_STATUS0 (DDRPHY_NAO_BASE_ADDRESS + 0x0628) + #define DQSIEN_AUTOK_B0_RK1_DBG_STATUS0_DBG_GATING_STATUS_0_B0_RK1 Fld(32, 0) //[31:0] + +#define DDRPHY_REG_DQSIEN_AUTOK_B0_RK1_DBG_STATUS1 (DDRPHY_NAO_BASE_ADDRESS + 0x062C) + #define DQSIEN_AUTOK_B0_RK1_DBG_STATUS1_DBG_GATING_STATUS_1_B0_RK1 Fld(32, 0) //[31:0] + +#define DDRPHY_REG_DQSIEN_AUTOK_B0_RK1_DBG_STATUS2 (DDRPHY_NAO_BASE_ADDRESS + 0x0630) + #define DQSIEN_AUTOK_B0_RK1_DBG_STATUS2_DBG_GATING_STATUS_2_B0_RK1 Fld(32, 0) //[31:0] + +#define DDRPHY_REG_DQSIEN_AUTOK_B0_RK1_DBG_STATUS3 (DDRPHY_NAO_BASE_ADDRESS + 0x0634) + #define DQSIEN_AUTOK_B0_RK1_DBG_STATUS3_DBG_GATING_STATUS_3_B0_RK1 Fld(32, 0) //[31:0] + +#define DDRPHY_REG_DQSIEN_AUTOK_B0_RK1_DBG_STATUS4 (DDRPHY_NAO_BASE_ADDRESS + 0x0638) + #define DQSIEN_AUTOK_B0_RK1_DBG_STATUS4_DBG_GATING_STATUS_4_B0_RK1 Fld(32, 0) //[31:0] + +#define DDRPHY_REG_DQSIEN_AUTOK_B0_RK1_DBG_STATUS5 (DDRPHY_NAO_BASE_ADDRESS + 0x063C) + #define DQSIEN_AUTOK_B0_RK1_DBG_STATUS5_DBG_GATING_STATUS_5_B0_RK1 Fld(32, 0) //[31:0] + +#define DDRPHY_REG_DQSIEN_AUTOK_B1_RK0_STATUS0 (DDRPHY_NAO_BASE_ADDRESS + 0x0640) + #define DQSIEN_AUTOK_B1_RK0_STATUS0_DQSIEN_AUTOK_C__PI_B1_RK0 Fld(7, 0) //[6:0] + #define DQSIEN_AUTOK_B1_RK0_STATUS0_DQSIEN_AUTOK_C__UI_B1_RK0 Fld(4, 8) //[11:8] + #define DQSIEN_AUTOK_B1_RK0_STATUS0_DQSIEN_AUTOK_C_MCK_B1_RK0 Fld(4, 12) //[15:12] + #define DQSIEN_AUTOK_B1_RK0_STATUS0_AUTOK_DONE_B1_RK0 Fld(1, 16) //[16:16] + #define DQSIEN_AUTOK_B1_RK0_STATUS0_AUTOK_ERR_B1_RK0 Fld(1, 17) //[17:17] + +#define DDRPHY_REG_DQSIEN_AUTOK_B1_RK0_STATUS1 (DDRPHY_NAO_BASE_ADDRESS + 0x0644) + #define DQSIEN_AUTOK_B1_RK0_STATUS1_DQSIEN_AUTOK_R__PI_B1_RK0 Fld(7, 0) //[6:0] + #define DQSIEN_AUTOK_B1_RK0_STATUS1_DQSIEN_AUTOK_R__UI_B1_RK0 Fld(4, 8) //[11:8] + #define DQSIEN_AUTOK_B1_RK0_STATUS1_DQSIEN_AUTOK_R_MCK_B1_RK0 Fld(4, 12) //[15:12] + #define DQSIEN_AUTOK_B1_RK0_STATUS1_DQSIEN_AUTOK_L__PI_B1_RK0 Fld(7, 16) //[22:16] + #define DQSIEN_AUTOK_B1_RK0_STATUS1_DQSIEN_AUTOK_L__UI_B1_RK0 Fld(4, 24) //[27:24] + #define DQSIEN_AUTOK_B1_RK0_STATUS1_DQSIEN_AUTOK_L_MCK_B1_RK0 Fld(4, 28) //[31:28] + +#define DDRPHY_REG_DQSIEN_AUTOK_B1_RK0_DBG_STATUS0 (DDRPHY_NAO_BASE_ADDRESS + 0x0648) + #define DQSIEN_AUTOK_B1_RK0_DBG_STATUS0_DBG_GATING_STATUS_0_B1_RK0 Fld(32, 0) //[31:0] + +#define DDRPHY_REG_DQSIEN_AUTOK_B1_RK0_DBG_STATUS1 (DDRPHY_NAO_BASE_ADDRESS + 0x064C) + #define DQSIEN_AUTOK_B1_RK0_DBG_STATUS1_DBG_GATING_STATUS_1_B1_RK0 Fld(32, 0) //[31:0] + +#define DDRPHY_REG_DQSIEN_AUTOK_B1_RK0_DBG_STATUS2 (DDRPHY_NAO_BASE_ADDRESS + 0x0650) + #define DQSIEN_AUTOK_B1_RK0_DBG_STATUS2_DBG_GATING_STATUS_2_B1_RK0 Fld(32, 0) //[31:0] + +#define DDRPHY_REG_DQSIEN_AUTOK_B1_RK0_DBG_STATUS3 (DDRPHY_NAO_BASE_ADDRESS + 0x0654) + #define DQSIEN_AUTOK_B1_RK0_DBG_STATUS3_DBG_GATING_STATUS_3_B1_RK0 Fld(32, 0) //[31:0] + +#define DDRPHY_REG_DQSIEN_AUTOK_B1_RK0_DBG_STATUS4 (DDRPHY_NAO_BASE_ADDRESS + 0x0658) + #define DQSIEN_AUTOK_B1_RK0_DBG_STATUS4_DBG_GATING_STATUS_4_B1_RK0 Fld(32, 0) //[31:0] + +#define DDRPHY_REG_DQSIEN_AUTOK_B1_RK0_DBG_STATUS5 (DDRPHY_NAO_BASE_ADDRESS + 0x065C) + #define DQSIEN_AUTOK_B1_RK0_DBG_STATUS5_DBG_GATING_STATUS_5_B1_RK0 Fld(32, 0) //[31:0] + +#define DDRPHY_REG_DQSIEN_AUTOK_B1_RK1_STATUS0 (DDRPHY_NAO_BASE_ADDRESS + 0x0660) + #define DQSIEN_AUTOK_B1_RK1_STATUS0_DQSIEN_AUTOK_C__PI_B1_RK1 Fld(7, 0) //[6:0] + #define DQSIEN_AUTOK_B1_RK1_STATUS0_DQSIEN_AUTOK_C__UI_B1_RK1 Fld(4, 8) //[11:8] + #define DQSIEN_AUTOK_B1_RK1_STATUS0_DQSIEN_AUTOK_C_MCK_B1_RK1 Fld(4, 12) //[15:12] + #define DQSIEN_AUTOK_B1_RK1_STATUS0_AUTOK_DONE_B1_RK1 Fld(1, 16) //[16:16] + #define DQSIEN_AUTOK_B1_RK1_STATUS0_AUTOK_ERR_B1_RK1 Fld(1, 17) //[17:17] + +#define DDRPHY_REG_DQSIEN_AUTOK_B1_RK1_STATUS1 (DDRPHY_NAO_BASE_ADDRESS + 0x0664) + #define DQSIEN_AUTOK_B1_RK1_STATUS1_DQSIEN_AUTOK_R__PI_B1_RK1 Fld(7, 0) //[6:0] + #define DQSIEN_AUTOK_B1_RK1_STATUS1_DQSIEN_AUTOK_R__UI_B1_RK1 Fld(4, 8) //[11:8] + #define DQSIEN_AUTOK_B1_RK1_STATUS1_DQSIEN_AUTOK_R_MCK_B1_RK1 Fld(4, 12) //[15:12] + #define DQSIEN_AUTOK_B1_RK1_STATUS1_DQSIEN_AUTOK_L__PI_B1_RK1 Fld(7, 16) //[22:16] + #define DQSIEN_AUTOK_B1_RK1_STATUS1_DQSIEN_AUTOK_L__UI_B1_RK1 Fld(4, 24) //[27:24] + #define DQSIEN_AUTOK_B1_RK1_STATUS1_DQSIEN_AUTOK_L_MCK_B1_RK1 Fld(4, 28) //[31:28] + +#define DDRPHY_REG_DQSIEN_AUTOK_B1_RK1_DBG_STATUS0 (DDRPHY_NAO_BASE_ADDRESS + 0x0668) + #define DQSIEN_AUTOK_B1_RK1_DBG_STATUS0_DBG_GATING_STATUS_0_B1_RK1 Fld(32, 0) //[31:0] + +#define DDRPHY_REG_DQSIEN_AUTOK_B1_RK1_DBG_STATUS1 (DDRPHY_NAO_BASE_ADDRESS + 0x066C) + #define DQSIEN_AUTOK_B1_RK1_DBG_STATUS1_DBG_GATING_STATUS_1_B1_RK1 Fld(32, 0) //[31:0] + +#define DDRPHY_REG_DQSIEN_AUTOK_B1_RK1_DBG_STATUS2 (DDRPHY_NAO_BASE_ADDRESS + 0x0670) + #define DQSIEN_AUTOK_B1_RK1_DBG_STATUS2_DBG_GATING_STATUS_2_B1_RK1 Fld(32, 0) //[31:0] + +#define DDRPHY_REG_DQSIEN_AUTOK_B1_RK1_DBG_STATUS3 (DDRPHY_NAO_BASE_ADDRESS + 0x0674) + #define DQSIEN_AUTOK_B1_RK1_DBG_STATUS3_DBG_GATING_STATUS_3_B1_RK1 Fld(32, 0) //[31:0] + +#define DDRPHY_REG_DQSIEN_AUTOK_B1_RK1_DBG_STATUS4 (DDRPHY_NAO_BASE_ADDRESS + 0x0678) + #define DQSIEN_AUTOK_B1_RK1_DBG_STATUS4_DBG_GATING_STATUS_4_B1_RK1 Fld(32, 0) //[31:0] + +#define DDRPHY_REG_DQSIEN_AUTOK_B1_RK1_DBG_STATUS5 (DDRPHY_NAO_BASE_ADDRESS + 0x067C) + #define DQSIEN_AUTOK_B1_RK1_DBG_STATUS5_DBG_GATING_STATUS_5_B1_RK1 Fld(32, 0) //[31:0] + +#define DDRPHY_REG_DQSIEN_AUTOK_CA_RK0_STATUS0 (DDRPHY_NAO_BASE_ADDRESS + 0x0680) + #define DQSIEN_AUTOK_CA_RK0_STATUS0_DQSIEN_AUTOK_C__PI_CA_RK0 Fld(7, 0) //[6:0] + #define DQSIEN_AUTOK_CA_RK0_STATUS0_DQSIEN_AUTOK_C__UI_CA_RK0 Fld(4, 8) //[11:8] + #define DQSIEN_AUTOK_CA_RK0_STATUS0_DQSIEN_AUTOK_C_MCK_CA_RK0 Fld(4, 12) //[15:12] + #define DQSIEN_AUTOK_CA_RK0_STATUS0_AUTOK_DONE_CA_RK0 Fld(1, 16) //[16:16] + #define DQSIEN_AUTOK_CA_RK0_STATUS0_AUTOK_ERR_CA_RK0 Fld(1, 17) //[17:17] + +#define DDRPHY_REG_DQSIEN_AUTOK_CA_RK0_STATUS1 (DDRPHY_NAO_BASE_ADDRESS + 0x0684) + #define DQSIEN_AUTOK_CA_RK0_STATUS1_DQSIEN_AUTOK_R__PI_CA_RK0 Fld(7, 0) //[6:0] + #define DQSIEN_AUTOK_CA_RK0_STATUS1_DQSIEN_AUTOK_R__UI_CA_RK0 Fld(4, 8) //[11:8] + #define DQSIEN_AUTOK_CA_RK0_STATUS1_DQSIEN_AUTOK_R_MCK_CA_RK0 Fld(4, 12) //[15:12] + #define DQSIEN_AUTOK_CA_RK0_STATUS1_DQSIEN_AUTOK_L__PI_CA_RK0 Fld(7, 16) //[22:16] + #define DQSIEN_AUTOK_CA_RK0_STATUS1_DQSIEN_AUTOK_L__UI_CA_RK0 Fld(4, 24) //[27:24] + #define DQSIEN_AUTOK_CA_RK0_STATUS1_DQSIEN_AUTOK_L_MCK_CA_RK0 Fld(4, 28) //[31:28] + +#define DDRPHY_REG_DQSIEN_AUTOK_CA_RK0_DBG_STATUS0 (DDRPHY_NAO_BASE_ADDRESS + 0x0688) + #define DQSIEN_AUTOK_CA_RK0_DBG_STATUS0_DBG_GATING_STATUS_0_CA_RK0 Fld(32, 0) //[31:0] + +#define DDRPHY_REG_DQSIEN_AUTOK_CA_RK0_DBG_STATUS1 (DDRPHY_NAO_BASE_ADDRESS + 0x068C) + #define DQSIEN_AUTOK_CA_RK0_DBG_STATUS1_DBG_GATING_STATUS_1_CA_RK0 Fld(32, 0) //[31:0] + +#define DDRPHY_REG_DQSIEN_AUTOK_CA_RK0_DBG_STATUS2 (DDRPHY_NAO_BASE_ADDRESS + 0x0690) + #define DQSIEN_AUTOK_CA_RK0_DBG_STATUS2_DBG_GATING_STATUS_2_CA_RK0 Fld(32, 0) //[31:0] + +#define DDRPHY_REG_DQSIEN_AUTOK_CA_RK0_DBG_STATUS3 (DDRPHY_NAO_BASE_ADDRESS + 0x0694) + #define DQSIEN_AUTOK_CA_RK0_DBG_STATUS3_DBG_GATING_STATUS_3_CA_RK0 Fld(32, 0) //[31:0] + +#define DDRPHY_REG_DQSIEN_AUTOK_CA_RK0_DBG_STATUS4 (DDRPHY_NAO_BASE_ADDRESS + 0x0698) + #define DQSIEN_AUTOK_CA_RK0_DBG_STATUS4_DBG_GATING_STATUS_4_CA_RK0 Fld(32, 0) //[31:0] + +#define DDRPHY_REG_DQSIEN_AUTOK_CA_RK0_DBG_STATUS5 (DDRPHY_NAO_BASE_ADDRESS + 0x069C) + #define DQSIEN_AUTOK_CA_RK0_DBG_STATUS5_DBG_GATING_STATUS_5_CA_RK0 Fld(32, 0) //[31:0] + +#define DDRPHY_REG_DQSIEN_AUTOK_CA_RK1_STATUS0 (DDRPHY_NAO_BASE_ADDRESS + 0x0700) + #define DQSIEN_AUTOK_CA_RK1_STATUS0_DQSIEN_AUTOK_C__PI_CA_RK1 Fld(7, 0) //[6:0] + #define DQSIEN_AUTOK_CA_RK1_STATUS0_DQSIEN_AUTOK_C__UI_CA_RK1 Fld(4, 8) //[11:8] + #define DQSIEN_AUTOK_CA_RK1_STATUS0_DQSIEN_AUTOK_C_MCK_CA_RK1 Fld(4, 12) //[15:12] + #define DQSIEN_AUTOK_CA_RK1_STATUS0_AUTOK_DONE_CA_RK1 Fld(1, 16) //[16:16] + #define DQSIEN_AUTOK_CA_RK1_STATUS0_AUTOK_ERR_CA_RK1 Fld(1, 17) //[17:17] + +#define DDRPHY_REG_DQSIEN_AUTOK_CA_RK1_STATUS1 (DDRPHY_NAO_BASE_ADDRESS + 0x0704) + #define DQSIEN_AUTOK_CA_RK1_STATUS1_DQSIEN_AUTOK_R__PI_CA_RK1 Fld(7, 0) //[6:0] + #define DQSIEN_AUTOK_CA_RK1_STATUS1_DQSIEN_AUTOK_R__UI_CA_RK1 Fld(4, 8) //[11:8] + #define DQSIEN_AUTOK_CA_RK1_STATUS1_DQSIEN_AUTOK_R_MCK_CA_RK1 Fld(4, 12) //[15:12] + #define DQSIEN_AUTOK_CA_RK1_STATUS1_DQSIEN_AUTOK_L__PI_CA_RK1 Fld(7, 16) //[22:16] + #define DQSIEN_AUTOK_CA_RK1_STATUS1_DQSIEN_AUTOK_L__UI_CA_RK1 Fld(4, 24) //[27:24] + #define DQSIEN_AUTOK_CA_RK1_STATUS1_DQSIEN_AUTOK_L_MCK_CA_RK1 Fld(4, 28) //[31:28] + +#define DDRPHY_REG_DQSIEN_AUTOK_CA_RK1_DBG_STATUS0 (DDRPHY_NAO_BASE_ADDRESS + 0x0708) + #define DQSIEN_AUTOK_CA_RK1_DBG_STATUS0_DBG_GATING_STATUS_0_CA_RK1 Fld(32, 0) //[31:0] + +#define DDRPHY_REG_DQSIEN_AUTOK_CA_RK1_DBG_STATUS1 (DDRPHY_NAO_BASE_ADDRESS + 0x070C) + #define DQSIEN_AUTOK_CA_RK1_DBG_STATUS1_DBG_GATING_STATUS_1_CA_RK1 Fld(32, 0) //[31:0] + +#define DDRPHY_REG_DQSIEN_AUTOK_CA_RK1_DBG_STATUS2 (DDRPHY_NAO_BASE_ADDRESS + 0x0710) + #define DQSIEN_AUTOK_CA_RK1_DBG_STATUS2_DBG_GATING_STATUS_2_CA_RK1 Fld(32, 0) //[31:0] + +#define DDRPHY_REG_DQSIEN_AUTOK_CA_RK1_DBG_STATUS3 (DDRPHY_NAO_BASE_ADDRESS + 0x0714) + #define DQSIEN_AUTOK_CA_RK1_DBG_STATUS3_DBG_GATING_STATUS_3_CA_RK1 Fld(32, 0) //[31:0] + +#define DDRPHY_REG_DQSIEN_AUTOK_CA_RK1_DBG_STATUS4 (DDRPHY_NAO_BASE_ADDRESS + 0x0718) + #define DQSIEN_AUTOK_CA_RK1_DBG_STATUS4_DBG_GATING_STATUS_4_CA_RK1 Fld(32, 0) //[31:0] + +#define DDRPHY_REG_DQSIEN_AUTOK_CA_RK1_DBG_STATUS5 (DDRPHY_NAO_BASE_ADDRESS + 0x071C) + #define DQSIEN_AUTOK_CA_RK1_DBG_STATUS5_DBG_GATING_STATUS_5_CA_RK1 Fld(32, 0) //[31:0] + +#define DDRPHY_REG_DQSIEN_AUTOK_CTRL_STATUS (DDRPHY_NAO_BASE_ADDRESS + 0x0720) + #define DQSIEN_AUTOK_CTRL_STATUS_DQSIEN_AUTOK_DONE_RK0 Fld(1, 0) //[0:0] + #define DQSIEN_AUTOK_CTRL_STATUS_DQSIEN_AUTOK_DONE_RK1 Fld(1, 1) //[1:1] + #define DQSIEN_AUTOK_CTRL_STATUS_DQSIEN_AUTOK_DLE_TIMEOUT_ERROR Fld(1, 2) //[2:2] + #define DQSIEN_AUTOK_CTRL_STATUS_DQSIEN_AUTOK_FSM_ST Fld(3, 4) //[6:4] + #define DQSIEN_AUTOK_CTRL_STATUS_DQSIEN_AUTOK_FSM_CUR_EDGE Fld(1, 8) //[8:8] + +#define DDRPHY_REG_AD_DLINE_MON (DDRPHY_NAO_BASE_ADDRESS + 0x0724) + #define AD_DLINE_MON_AD_RPLLGP_DLINE_MON Fld(24, 0) //[23:0] + +#define DDRPHY_REG_DLINE_MON_TRACK_DBG (DDRPHY_NAO_BASE_ADDRESS + 0x0728) + #define DLINE_MON_TRACK_DBG_DLINE_MON_TRACK_DBG Fld(32, 0) //[31:0] + +#define DDRPHY_REG_MISC_DUTYCAL_STATUS (DDRPHY_NAO_BASE_ADDRESS + 0x072C) + #define MISC_DUTYCAL_STATUS_RGS_RX_ARDQ_DUTY_VCAL_CMP_OUT_B0 Fld(1, 0) //[0:0] + #define MISC_DUTYCAL_STATUS_RGS_RX_ARDQ_DUTY_VCAL_CMP_OUT_B1 Fld(1, 1) //[1:1] + #define MISC_DUTYCAL_STATUS_RGS_RX_ARCA_DUTY_VCAL_CMP_OUT_C0 Fld(1, 2) //[2:2] + +#define DDRPHY_REG_MISC_DBG_DB_IMP_MESSAGE0 (DDRPHY_NAO_BASE_ADDRESS + 0x0730) + #define MISC_DBG_DB_IMP_MESSAGE0_DBG_DB_DQS0_DRVP_MAX Fld(5, 0) //[4:0] + #define MISC_DBG_DB_IMP_MESSAGE0_DBG_DB_DQS0_DRVP_MAX_ERR Fld(1, 7) //[7:7] + #define MISC_DBG_DB_IMP_MESSAGE0_DBG_DB_DQS0_DRVN_MAX Fld(5, 8) //[12:8] + #define MISC_DBG_DB_IMP_MESSAGE0_DBG_DB_DQS0_DRVN_MAX_ERR Fld(1, 15) //[15:15] + #define MISC_DBG_DB_IMP_MESSAGE0_DBG_DB_DQS0_ODTN_MAX Fld(5, 16) //[20:16] + #define MISC_DBG_DB_IMP_MESSAGE0_DBG_DB_DQS0_ODTN_MAX_ERR Fld(1, 23) //[23:23] + #define MISC_DBG_DB_IMP_MESSAGE0_DBG_DB_WCK0_DRVP_MAX Fld(5, 24) //[28:24] + #define MISC_DBG_DB_IMP_MESSAGE0_DBG_DB_WCK0_DRVP_MAX_ERR Fld(1, 31) //[31:31] + +#define DDRPHY_REG_MISC_DBG_DB_IMP_MESSAGE1 (DDRPHY_NAO_BASE_ADDRESS + 0x0734) + #define MISC_DBG_DB_IMP_MESSAGE1_DBG_DB_DQS1_DRVP_MAX Fld(5, 0) //[4:0] + #define MISC_DBG_DB_IMP_MESSAGE1_DBG_DB_DQS1_DRVP_MAX_ERR Fld(1, 7) //[7:7] + #define MISC_DBG_DB_IMP_MESSAGE1_DBG_DB_DQS1_DRVN_MAX Fld(5, 8) //[12:8] + #define MISC_DBG_DB_IMP_MESSAGE1_DBG_DB_DQS1_DRVN_MAX_ERR Fld(1, 15) //[15:15] + #define MISC_DBG_DB_IMP_MESSAGE1_DBG_DB_DQS1_ODTN_MAX Fld(5, 16) //[20:16] + #define MISC_DBG_DB_IMP_MESSAGE1_DBG_DB_DQS1_ODTN_MAX_ERR Fld(1, 23) //[23:23] + #define MISC_DBG_DB_IMP_MESSAGE1_DBG_DB_WCK0_DRVN_MAX Fld(5, 24) //[28:24] + #define MISC_DBG_DB_IMP_MESSAGE1_DBG_DB_WCK0_DRVN_MAX_ERR Fld(1, 31) //[31:31] + +#define DDRPHY_REG_MISC_DBG_DB_IMP_MESSAGE2 (DDRPHY_NAO_BASE_ADDRESS + 0x0738) + #define MISC_DBG_DB_IMP_MESSAGE2_DBG_DB_DQ0_DRVP_MAX Fld(5, 0) //[4:0] + #define MISC_DBG_DB_IMP_MESSAGE2_DBG_DB_DQ0_DRVP_MAX_ERR Fld(1, 7) //[7:7] + #define MISC_DBG_DB_IMP_MESSAGE2_DBG_DB_DQ0_DRVN_MAX Fld(5, 8) //[12:8] + #define MISC_DBG_DB_IMP_MESSAGE2_DBG_DB_DQ0_DRVN_MAX_ERR Fld(1, 15) //[15:15] + #define MISC_DBG_DB_IMP_MESSAGE2_DBG_DB_DQ0_ODTN_MAX Fld(5, 16) //[20:16] + #define MISC_DBG_DB_IMP_MESSAGE2_DBG_DB_DQ0_ODTN_MAX_ERR Fld(1, 23) //[23:23] + #define MISC_DBG_DB_IMP_MESSAGE2_DBG_DB_WCK1_DRVP_MAX Fld(5, 24) //[28:24] + #define MISC_DBG_DB_IMP_MESSAGE2_DBG_DB_WCK1_DRVP_MAX_ERR Fld(1, 31) //[31:31] + +#define DDRPHY_REG_MISC_DBG_DB_IMP_MESSAGE3 (DDRPHY_NAO_BASE_ADDRESS + 0x073C) + #define MISC_DBG_DB_IMP_MESSAGE3_DBG_DB_DQ1_DRVP_MAX Fld(5, 0) //[4:0] + #define MISC_DBG_DB_IMP_MESSAGE3_DBG_DB_DQ1_DRVP_MAX_ERR Fld(1, 7) //[7:7] + #define MISC_DBG_DB_IMP_MESSAGE3_DBG_DB_DQ1_DRVN_MAX Fld(5, 8) //[12:8] + #define MISC_DBG_DB_IMP_MESSAGE3_DBG_DB_DQ1_DRVN_MAX_ERR Fld(1, 15) //[15:15] + #define MISC_DBG_DB_IMP_MESSAGE3_DBG_DB_DQ1_ODTN_MAX Fld(5, 16) //[20:16] + #define MISC_DBG_DB_IMP_MESSAGE3_DBG_DB_DQ1_ODTN_MAX_ERR Fld(1, 23) //[23:23] + #define MISC_DBG_DB_IMP_MESSAGE3_DBG_DB_WCK1_DRVN_MAX Fld(5, 24) //[28:24] + #define MISC_DBG_DB_IMP_MESSAGE3_DBG_DB_WCK1_DRVN_MAX_ERR Fld(1, 31) //[31:31] + +#define DDRPHY_REG_MISC_DBG_DB_IMP_MESSAGE4 (DDRPHY_NAO_BASE_ADDRESS + 0x0740) + #define MISC_DBG_DB_IMP_MESSAGE4_DBG_DB_CMD_DRVP_MAX Fld(5, 0) //[4:0] + #define MISC_DBG_DB_IMP_MESSAGE4_DBG_DB_CMD_DRVP_MAX_ERR Fld(1, 7) //[7:7] + #define MISC_DBG_DB_IMP_MESSAGE4_DBG_DB_CMD_DRVN_MAX Fld(5, 8) //[12:8] + #define MISC_DBG_DB_IMP_MESSAGE4_DBG_DB_CMD_DRVN_MAX_ERR Fld(1, 15) //[15:15] + #define MISC_DBG_DB_IMP_MESSAGE4_DBG_DB_CMD_ODTN_MAX Fld(5, 16) //[20:16] + #define MISC_DBG_DB_IMP_MESSAGE4_DBG_DB_CMD_ODTN_MAX_ERR Fld(1, 23) //[23:23] + #define MISC_DBG_DB_IMP_MESSAGE4_DBG_DB_CS_DRVP_MAX Fld(5, 24) //[28:24] + #define MISC_DBG_DB_IMP_MESSAGE4_DBG_DB_CS_DRVP_MAX_ERR Fld(1, 31) //[31:31] + +#define DDRPHY_REG_MISC_DBG_DB_IMP_MESSAGE5 (DDRPHY_NAO_BASE_ADDRESS + 0x0744) + #define MISC_DBG_DB_IMP_MESSAGE5_DBG_DB_CLK_DRVP_MAX Fld(5, 0) //[4:0] + #define MISC_DBG_DB_IMP_MESSAGE5_DBG_DB_CLK_DRVP_MAX_ERR Fld(1, 7) //[7:7] + #define MISC_DBG_DB_IMP_MESSAGE5_DBG_DB_CLK_DRVN_MAX Fld(5, 8) //[12:8] + #define MISC_DBG_DB_IMP_MESSAGE5_DBG_DB_CLK_DRVN_MAX_ERR Fld(1, 15) //[15:15] + #define MISC_DBG_DB_IMP_MESSAGE5_DBG_DB_CLK_ODTN_MAX Fld(5, 16) //[20:16] + #define MISC_DBG_DB_IMP_MESSAGE5_DBG_DB_CLK_ODTN_MAX_ERR Fld(1, 23) //[23:23] + #define MISC_DBG_DB_IMP_MESSAGE5_DBG_DB_CS_DRVN_MAX Fld(5, 24) //[28:24] + #define MISC_DBG_DB_IMP_MESSAGE5_DBG_DB_CS_DRVN_MAX_ERR Fld(1, 31) //[31:31] + +#define DDRPHY_REG_MISC_DBG_DB_IMP_MESSAGE6 (DDRPHY_NAO_BASE_ADDRESS + 0x0748) + #define MISC_DBG_DB_IMP_MESSAGE6_DBG_DB_DQS0_DRVP_MIN Fld(5, 0) //[4:0] + #define MISC_DBG_DB_IMP_MESSAGE6_DBG_DB_DQS0_DRVP_MIN_ERR Fld(1, 7) //[7:7] + #define MISC_DBG_DB_IMP_MESSAGE6_DBG_DB_DQS0_DRVN_MIN Fld(5, 8) //[12:8] + #define MISC_DBG_DB_IMP_MESSAGE6_DBG_DB_DQS0_DRVN_MIN_ERR Fld(1, 15) //[15:15] + #define MISC_DBG_DB_IMP_MESSAGE6_DBG_DB_DQS0_ODTN_MIN Fld(5, 16) //[20:16] + #define MISC_DBG_DB_IMP_MESSAGE6_DBG_DB_DQS0_ODTN_MIN_ERR Fld(1, 23) //[23:23] + #define MISC_DBG_DB_IMP_MESSAGE6_DBG_DB_WCK0_DRVP_MIN Fld(5, 24) //[28:24] + #define MISC_DBG_DB_IMP_MESSAGE6_DBG_DB_WCK0_DRVP_MIN_ERR Fld(1, 31) //[31:31] + +#define DDRPHY_REG_MISC_DBG_DB_IMP_MESSAGE7 (DDRPHY_NAO_BASE_ADDRESS + 0x074C) + #define MISC_DBG_DB_IMP_MESSAGE7_DBG_DB_DQS1_DRVP_MIN Fld(5, 0) //[4:0] + #define MISC_DBG_DB_IMP_MESSAGE7_DBG_DB_DQS1_DRVP_MIN_ERR Fld(1, 7) //[7:7] + #define MISC_DBG_DB_IMP_MESSAGE7_DBG_DB_DQS1_DRVN_MIN Fld(5, 8) //[12:8] + #define MISC_DBG_DB_IMP_MESSAGE7_DBG_DB_DQS1_DRVN_MIN_ERR Fld(1, 15) //[15:15] + #define MISC_DBG_DB_IMP_MESSAGE7_DBG_DB_DQS1_ODTN_MIN Fld(5, 16) //[20:16] + #define MISC_DBG_DB_IMP_MESSAGE7_DBG_DB_DQS1_ODTN_MIN_ERR Fld(1, 23) //[23:23] + #define MISC_DBG_DB_IMP_MESSAGE7_DBG_DB_WCK0_DRVN_MIN Fld(5, 24) //[28:24] + #define MISC_DBG_DB_IMP_MESSAGE7_DBG_DB_WCK0_DRVN_MIN_ERR Fld(1, 31) //[31:31] + +#define DDRPHY_REG_MISC_DBG_DB_IMP_MESSAGE8 (DDRPHY_NAO_BASE_ADDRESS + 0x0750) + #define MISC_DBG_DB_IMP_MESSAGE8_DBG_DB_DQ0_DRVP_MIN Fld(5, 0) //[4:0] + #define MISC_DBG_DB_IMP_MESSAGE8_DBG_DB_DQ0_DRVP_MIN_ERR Fld(1, 7) //[7:7] + #define MISC_DBG_DB_IMP_MESSAGE8_DBG_DB_DQ0_DRVN_MIN Fld(5, 8) //[12:8] + #define MISC_DBG_DB_IMP_MESSAGE8_DBG_DB_DQ0_DRVN_MIN_ERR Fld(1, 15) //[15:15] + #define MISC_DBG_DB_IMP_MESSAGE8_DBG_DB_DQ0_ODTN_MIN Fld(5, 16) //[20:16] + #define MISC_DBG_DB_IMP_MESSAGE8_DBG_DB_DQ0_ODTN_MIN_ERR Fld(1, 23) //[23:23] + #define MISC_DBG_DB_IMP_MESSAGE8_DBG_DB_WCK1_DRVP_MIN Fld(5, 24) //[28:24] + #define MISC_DBG_DB_IMP_MESSAGE8_DBG_DB_WCK1_DRVP_MIN_ERR Fld(1, 31) //[31:31] + +#define DDRPHY_REG_MISC_DBG_DB_IMP_MESSAGE9 (DDRPHY_NAO_BASE_ADDRESS + 0x0754) + #define MISC_DBG_DB_IMP_MESSAGE9_DBG_DB_DQ1_DRVP_MIN Fld(5, 0) //[4:0] + #define MISC_DBG_DB_IMP_MESSAGE9_DBG_DB_DQ1_DRVP_MIN_ERR Fld(1, 7) //[7:7] + #define MISC_DBG_DB_IMP_MESSAGE9_DBG_DB_DQ1_DRVN_MIN Fld(5, 8) //[12:8] + #define MISC_DBG_DB_IMP_MESSAGE9_DBG_DB_DQ1_DRVN_MIN_ERR Fld(1, 15) //[15:15] + #define MISC_DBG_DB_IMP_MESSAGE9_DBG_DB_DQ1_ODTN_MIN Fld(5, 16) //[20:16] + #define MISC_DBG_DB_IMP_MESSAGE9_DBG_DB_DQ1_ODTN_MIN_ERR Fld(1, 23) //[23:23] + #define MISC_DBG_DB_IMP_MESSAGE9_DBG_DB_WCK1_DRVN_MIN Fld(5, 24) //[28:24] + #define MISC_DBG_DB_IMP_MESSAGE9_DBG_DB_WCK1_DRVN_MIN_ERR Fld(1, 31) //[31:31] + +#define DDRPHY_REG_MISC_DBG_DB_IMP_MESSAGE10 (DDRPHY_NAO_BASE_ADDRESS + 0x0758) + #define MISC_DBG_DB_IMP_MESSAGE10_DBG_DB_CMD_DRVP_MIN Fld(5, 0) //[4:0] + #define MISC_DBG_DB_IMP_MESSAGE10_DBG_DB_CMD_DRVP_MIN_ERR Fld(1, 7) //[7:7] + #define MISC_DBG_DB_IMP_MESSAGE10_DBG_DB_CMD_DRVN_MIN Fld(5, 8) //[12:8] + #define MISC_DBG_DB_IMP_MESSAGE10_DBG_DB_CMD_DRVN_MIN_ERR Fld(1, 15) //[15:15] + #define MISC_DBG_DB_IMP_MESSAGE10_DBG_DB_CMD_ODTN_MIN Fld(5, 16) //[20:16] + #define MISC_DBG_DB_IMP_MESSAGE10_DBG_DB_CMD_ODTN_MIN_ERR Fld(1, 23) //[23:23] + #define MISC_DBG_DB_IMP_MESSAGE10_DBG_DB_CS_DRVP_MIN Fld(5, 24) //[28:24] + #define MISC_DBG_DB_IMP_MESSAGE10_DBG_DB_CS_DRVP_MIN_ERR Fld(1, 31) //[31:31] + +#define DDRPHY_REG_MISC_DBG_DB_IMP_MESSAGE11 (DDRPHY_NAO_BASE_ADDRESS + 0x075C) + #define MISC_DBG_DB_IMP_MESSAGE11_DBG_DB_CLK_DRVP_MIN Fld(5, 0) //[4:0] + #define MISC_DBG_DB_IMP_MESSAGE11_DBG_DB_CLK_DRVP_MIN_ERR Fld(1, 7) //[7:7] + #define MISC_DBG_DB_IMP_MESSAGE11_DBG_DB_CLK_DRVN_MIN Fld(5, 8) //[12:8] + #define MISC_DBG_DB_IMP_MESSAGE11_DBG_DB_CLK_DRVN_MIN_ERR Fld(1, 15) //[15:15] + #define MISC_DBG_DB_IMP_MESSAGE11_DBG_DB_CLK_ODTN_MIN Fld(5, 16) //[20:16] + #define MISC_DBG_DB_IMP_MESSAGE11_DBG_DB_CLK_ODTN_MIN_ERR Fld(1, 23) //[23:23] + #define MISC_DBG_DB_IMP_MESSAGE11_DBG_DB_CS_DRVN_MIN Fld(5, 24) //[28:24] + #define MISC_DBG_DB_IMP_MESSAGE11_DBG_DB_CS_DRVN_MIN_ERR Fld(1, 31) //[31:31] + +#define DDRPHY_REG_MISC_DMA_SRAM_MBIST (DDRPHY_NAO_BASE_ADDRESS + 0x0800) + #define MISC_DMA_SRAM_MBIST_DRAMC_MBIST_MBIST_PRE_FUSE Fld(8, 0) //[7:0] + +#define DDRPHY_REG_MISC_APHY_OBS0 (DDRPHY_NAO_BASE_ADDRESS + 0x0820) + #define MISC_APHY_OBS0_AD_RX_ARDQ1_RCNT_B0 Fld(9, 0) //[8:0] + #define MISC_APHY_OBS0_AD_RX_ARDQ2_RCNT_B0 Fld(9, 9) //[17:9] + #define MISC_APHY_OBS0_AD_RX_ARDQ3_RCNT_B0 Fld(9, 18) //[26:18] + +#define DDRPHY_REG_MISC_APHY_OBS1 (DDRPHY_NAO_BASE_ADDRESS + 0x0824) + #define MISC_APHY_OBS1_AD_RX_ARDQ5_RCNT_B0 Fld(9, 0) //[8:0] + #define MISC_APHY_OBS1_AD_RX_ARDQ6_RCNT_B0 Fld(9, 9) //[17:9] + #define MISC_APHY_OBS1_AD_RX_ARDQ7_RCNT_B0 Fld(9, 18) //[26:18] + +#define DDRPHY_REG_MISC_APHY_OBS2 (DDRPHY_NAO_BASE_ADDRESS + 0x0828) + #define MISC_APHY_OBS2_AD_RX_ARDQ1_RCNT_B1 Fld(9, 0) //[8:0] + #define MISC_APHY_OBS2_AD_RX_ARDQ2_RCNT_B1 Fld(9, 9) //[17:9] + #define MISC_APHY_OBS2_AD_RX_ARDQ3_RCNT_B1 Fld(9, 18) //[26:18] + +#define DDRPHY_REG_MISC_APHY_OBS3 (DDRPHY_NAO_BASE_ADDRESS + 0x082C) + #define MISC_APHY_OBS3_AD_RX_ARDQ5_RCNT_B1 Fld(9, 0) //[8:0] + #define MISC_APHY_OBS3_AD_RX_ARDQ6_RCNT_B1 Fld(9, 9) //[17:9] + #define MISC_APHY_OBS3_AD_RX_ARDQ7_RCNT_B1 Fld(9, 18) //[26:18] + +#define DDRPHY_REG_MISC_APHY_OBS4 (DDRPHY_NAO_BASE_ADDRESS + 0x0830) + #define MISC_APHY_OBS4_AD_RX_ARDQM_RCNT_B0 Fld(9, 0) //[8:0] + #define MISC_APHY_OBS4_AD_RX_ARDQM_RCNT_B1 Fld(9, 9) //[17:9] + +#define DDRPHY_REG_MISC_APHY_OBS5 (DDRPHY_NAO_BASE_ADDRESS + 0x0834) + #define MISC_APHY_OBS5_AD_RX_ARCA1_RCNT_C0 Fld(9, 0) //[8:0] + #define MISC_APHY_OBS5_AD_RX_ARCA2_RCNT_C0 Fld(9, 9) //[17:9] + #define MISC_APHY_OBS5_AD_RX_ARCA3_RCNT_C0 Fld(9, 18) //[26:18] + +#define DDRPHY_REG_MISC_APHY_OBS6 (DDRPHY_NAO_BASE_ADDRESS + 0x0838) + #define MISC_APHY_OBS6_AD_RX_ARCA5_RCNT_C0 Fld(9, 0) //[8:0] + #define MISC_APHY_OBS6_AD_RX_ARCS0_RCNT_C0 Fld(9, 9) //[17:9] + #define MISC_APHY_OBS6_AD_RX_ARCS1_RCNT_C0 Fld(9, 18) //[26:18] + +#define DDRPHY_REG_MISC_APHY_OBS7 (DDRPHY_NAO_BASE_ADDRESS + 0x083C) + #define MISC_APHY_OBS7_AD_RX_ARCKE0_RCNT_C0 Fld(9, 0) //[8:0] + #define MISC_APHY_OBS7_AD_RX_ARCKE1_RCNT_C0 Fld(9, 9) //[17:9] + +#define DDRPHY_REG_MISC_APHY_OBS8 (DDRPHY_NAO_BASE_ADDRESS + 0x0840) + #define MISC_APHY_OBS8_RGS_ARDLL_ULCK_B0 Fld(2, 0) //[1:0] + #define MISC_APHY_OBS8_RGS_ARDLL_ULCK_B1 Fld(2, 2) //[3:2] + #define MISC_APHY_OBS8_RGS_ARDLL_ULCK_C0 Fld(2, 4) //[5:4] + #define MISC_APHY_OBS8_RGS_RPHYPLL_DET_RSTB Fld(1, 6) //[6:6] + #define MISC_APHY_OBS8_RGS_RCLRPLL_DET_RSTB Fld(1, 7) //[7:7] + +#endif // __DDRPHY_NAO_REGS_H__ diff --git a/src/vendorcode/mediatek/mt8192/include/Margaux_Register_DRAMC_AO.h b/src/vendorcode/mediatek/mt8192/include/Margaux_Register_DRAMC_AO.h new file mode 100644 index 000000000000..7fc3b2f0a8b6 --- /dev/null +++ b/src/vendorcode/mediatek/mt8192/include/Margaux_Register_DRAMC_AO.h @@ -0,0 +1,1624 @@ +/* SPDX-License-Identifier: BSD-3-Clause */ + +#ifndef __DRAMC_AO_REGS_H__ +#define __DRAMC_AO_REGS_H__ + +#define Channel_A_DRAMC_AO_BASE_ADDRESS 0x10230000 +#define Channel_B_DRAMC_AO_BASE_ADDRESS 0x10240000 + +#define DRAMC_AO_BASE_ADDRESS Channel_A_DRAMC_AO_BASE_VIRTUAL + +#define DRAMC_REG_DDRCOMMON0 (DRAMC_AO_BASE_ADDRESS + 0x0000) + #define DDRCOMMON0_DISSTOP26M Fld(1, 0) //[0:0] + #define DDRCOMMON0_RANK_ASYM Fld(1, 1) //[1:1] + #define DDRCOMMON0_DM16BITFULL Fld(1, 2) //[2:2] + #define DDRCOMMON0_TRCDEARLY Fld(1, 3) //[3:3] + #define DDRCOMMON0_BK8EN Fld(1, 8) //[8:8] + #define DDRCOMMON0_BG4EN Fld(1, 11) //[11:11] + #define DDRCOMMON0_GDDR3EN Fld(1, 16) //[16:16] + #define DDRCOMMON0_LPDDR2EN Fld(1, 17) //[17:17] + #define DDRCOMMON0_LPDDR3EN Fld(1, 18) //[18:18] + #define DDRCOMMON0_LPDDR4EN Fld(1, 19) //[19:19] + #define DDRCOMMON0_LPDDR5EN Fld(1, 20) //[20:20] + #define DDRCOMMON0_DDR2EN Fld(1, 22) //[22:22] + #define DDRCOMMON0_DDR3EN Fld(1, 23) //[23:23] + #define DDRCOMMON0_DDR4EN Fld(1, 24) //[24:24] + #define DDRCOMMON0_DRAMC_SW_RST Fld(1, 31) //[31:31] + +#define DRAMC_REG_SA_RESERVE (DRAMC_AO_BASE_ADDRESS + 0x000C) + #define SA_RESERVE_SINGLE_RANK Fld(1, 0) //[0:0] + #define SA_RESERVE_DFS_FSP_RTMRW Fld(2, 1) //[2:1] + #define SA_RESERVE_SUPPORT_4266 Fld(1, 3) //[3:3] + #define SA_RESERVE_SA_RESERVE Fld(20, 4) //[23:4] + #define SA_RESERVE_MODE_RK1 Fld(4, 24) //[27:24] + #define SA_RESERVE_MODE_RK0 Fld(4, 28) //[31:28] + +#define DRAMC_REG_NONSHU_RSV (DRAMC_AO_BASE_ADDRESS + 0x00FC) + #define NONSHU_RSV_NONSHU_RSV Fld(32, 0) //[31:0] + +#define DRAMC_REG_TEST2_A0 (DRAMC_AO_BASE_ADDRESS + 0x0100) + #define TEST2_A0_TEST2_PAT1 Fld(8, 0) //[7:0] + #define TEST2_A0_TEST2_PAT0 Fld(8, 8) //[15:8] + #define TEST2_A0_LOOP_NV_END Fld(1, 16) //[16:16] + #define TEST2_A0_ERR_BREAK_EN Fld(1, 17) //[17:17] + #define TEST2_A0_TA2_LOOP_EN Fld(1, 18) //[18:18] + #define TEST2_A0_TA2_CG_FR Fld(1, 19) //[19:19] + #define TEST2_A0_LOOP_CNT_INDEX Fld(4, 20) //[23:20] + #define TEST2_A0_WDT_BY_DRAMC_DIS Fld(1, 24) //[24:24] + +#define DRAMC_REG_TEST2_A2 (DRAMC_AO_BASE_ADDRESS + 0x0104) + #define TEST2_A2_TEST2_OFF Fld(28, 4) //[31:4] + +#define DRAMC_REG_TEST2_A3 (DRAMC_AO_BASE_ADDRESS + 0x0108) + #define TEST2_A3_TESTCNT Fld(4, 0) //[3:0] + #define TEST2_A3_TESTWRHIGH Fld(1, 4) //[4:4] + #define TEST2_A3_ADRDECEN_TARKMODE Fld(1, 5) //[5:5] + #define TEST2_A3_PSTWR2 Fld(1, 6) //[6:6] + #define TEST2_A3_TESTAUDPAT Fld(1, 7) //[7:7] + #define TEST2_A3_TESTCLKRUN Fld(1, 8) //[8:8] + #define TEST2_A3_ERRFLAG_BYTE_SEL Fld(2, 9) //[10:9] + #define TEST2_A3_PAT_SHIFT_SW_EN Fld(1, 11) //[11:11] + #define TEST2_A3_PAT_SHIFT_OFFSET Fld(3, 12) //[14:12] + #define TEST2_A3_TEST2_PAT_SHIFT Fld(1, 15) //[15:15] + #define TEST2_A3_TEST_AID_EN Fld(1, 16) //[16:16] + #define TEST2_A3_HFIDPAT Fld(1, 17) //[17:17] + #define TEST2_A3_AUTO_GEN_PAT Fld(1, 18) //[18:18] + #define TEST2_A3_LBSELFCMP Fld(1, 19) //[19:19] + #define TEST2_A3_DMPAT32 Fld(1, 24) //[24:24] + #define TEST2_A3_TESTADR_SHIFT Fld(1, 25) //[25:25] + #define TEST2_A3_TAHPRI_B Fld(1, 26) //[26:26] + #define TEST2_A3_TESTLP Fld(1, 27) //[27:27] + #define TEST2_A3_TEST2WREN2_HW_EN Fld(1, 28) //[28:28] + #define TEST2_A3_TEST1 Fld(1, 29) //[29:29] + #define TEST2_A3_TEST2R Fld(1, 30) //[30:30] + #define TEST2_A3_TEST2W Fld(1, 31) //[31:31] + +#define DRAMC_REG_TEST2_A4 (DRAMC_AO_BASE_ADDRESS + 0x010C) + #define TEST2_A4_TESTAUDINC Fld(5, 0) //[4:0] + #define TEST2_A4_TEST2DISSCRAM Fld(1, 5) //[5:5] + #define TEST2_A4_TESTSSOPAT Fld(1, 6) //[6:6] + #define TEST2_A4_TESTSSOXTALKPAT Fld(1, 7) //[7:7] + #define TEST2_A4_TESTAUDINIT Fld(5, 8) //[12:8] + #define TEST2_A4_TEST2_EN1ARB_DIS Fld(1, 13) //[13:13] + #define TEST2_A4_TESTAUDBITINV Fld(1, 14) //[14:14] + #define TEST2_A4_TESTAUDMODE Fld(1, 15) //[15:15] + #define TEST2_A4_TESTXTALKPAT Fld(1, 16) //[16:16] + #define TEST2_A4_TEST_REQ_LEN1 Fld(1, 17) //[17:17] + #define TEST2_A4_TEST2EN1_OPT2 Fld(1, 18) //[18:18] + #define TEST2_A4_TEST2EN1_OPT1_DIS Fld(1, 19) //[19:19] + #define TEST2_A4_TEST2_DQMTGL Fld(1, 21) //[21:21] + #define TEST2_A4_TESTAGENTRK Fld(2, 24) //[25:24] + #define TEST2_A4_TESTDMITGLPAT Fld(1, 26) //[26:26] + #define TEST2_A4_TEST1TO4LEN1_DIS Fld(1, 27) //[27:27] + #define TEST2_A4_TESTAGENTRKSEL Fld(3, 28) //[30:28] + #define TEST2_A4_TESTAGENT_DMYRD_OPT Fld(1, 31) //[31:31] + +#define DRAMC_REG_DUMMY_RD (DRAMC_AO_BASE_ADDRESS + 0x0110) + #define DUMMY_RD_SREF_DMYRD_MASK Fld(1, 0) //[0:0] + #define DUMMY_RD_DMYRDOFOEN Fld(1, 1) //[1:1] + #define DUMMY_RD_DUMMY_RD_SW Fld(1, 4) //[4:4] + #define DUMMY_RD_DMYWR_LPRI_EN Fld(1, 5) //[5:5] + #define DUMMY_RD_DMY_WR_DBG Fld(1, 6) //[6:6] + #define DUMMY_RD_DMY_RD_DBG Fld(1, 7) //[7:7] + #define DUMMY_RD_DRS_CNTX Fld(7, 8) //[14:8] + #define DUMMY_RD_DRS_SELFWAKE_DMYRD_DIS Fld(1, 15) //[15:15] + #define DUMMY_RD_RANK_NUM Fld(2, 16) //[17:16] + #define DUMMY_RD_DUMMY_RD_EN Fld(1, 20) //[20:20] + #define DUMMY_RD_SREF_DMYRD_EN Fld(1, 21) //[21:21] + #define DUMMY_RD_DQSG_DMYRD_EN Fld(1, 22) //[22:22] + #define DUMMY_RD_DQSG_DMYWR_EN Fld(1, 23) //[23:23] + #define DUMMY_RD_DUMMY_RD_PA_OPT Fld(1, 24) //[24:24] + #define DUMMY_RD_DMY_RD_RX_TRACK Fld(1, 25) //[25:25] + #define DUMMY_RD_DMYRD_HPRI_DIS Fld(1, 26) //[26:26] + #define DUMMY_RD_DMYRD_REORDER_DIS Fld(1, 27) //[27:27] + #define DUMMY_RD_RETRY_SP_RK_DIS Fld(1, 28) //[28:28] + +#define DRAMC_REG_DUMMY_RD_INTV (DRAMC_AO_BASE_ADDRESS + 0x0114) + #define DUMMY_RD_INTV_DUMMY_RD_CNT0 Fld(1, 0) //[0:0] + #define DUMMY_RD_INTV_DUMMY_RD_CNT1 Fld(1, 1) //[1:1] + #define DUMMY_RD_INTV_DUMMY_RD_CNT2 Fld(1, 2) //[2:2] + #define DUMMY_RD_INTV_DUMMY_RD_CNT3 Fld(1, 3) //[3:3] + #define DUMMY_RD_INTV_DUMMY_RD_CNT4 Fld(1, 4) //[4:4] + #define DUMMY_RD_INTV_DUMMY_RD_CNT5 Fld(1, 5) //[5:5] + #define DUMMY_RD_INTV_DUMMY_RD_CNT6 Fld(1, 6) //[6:6] + #define DUMMY_RD_INTV_DUMMY_RD_CNT7 Fld(1, 7) //[7:7] + #define DUMMY_RD_INTV_DUMMY_RD_1_CNT0 Fld(1, 16) //[16:16] + #define DUMMY_RD_INTV_DUMMY_RD_1_CNT1 Fld(1, 17) //[17:17] + #define DUMMY_RD_INTV_DUMMY_RD_1_CNT2 Fld(1, 18) //[18:18] + #define DUMMY_RD_INTV_DUMMY_RD_1_CNT3 Fld(1, 19) //[19:19] + #define DUMMY_RD_INTV_DUMMY_RD_1_CNT4 Fld(1, 20) //[20:20] + #define DUMMY_RD_INTV_DUMMY_RD_1_CNT5 Fld(1, 21) //[21:21] + #define DUMMY_RD_INTV_DUMMY_RD_1_CNT6 Fld(1, 22) //[22:22] + #define DUMMY_RD_INTV_DUMMY_RD_1_CNT7 Fld(1, 23) //[23:23] + +#define DRAMC_REG_BUS_MON1 (DRAMC_AO_BASE_ADDRESS + 0x0118) + #define BUS_MON1_WRBYTE_CNT_OPT Fld(1, 0) //[0:0] + +#define DRAMC_REG_DRAMC_DBG_SEL1 (DRAMC_AO_BASE_ADDRESS + 0x011C) + #define DRAMC_DBG_SEL1_DEBUG_SEL_0 Fld(16, 0) //[15:0] + #define DRAMC_DBG_SEL1_DEBUG_SEL_1 Fld(16, 16) //[31:16] + +#define DRAMC_REG_DRAMC_DBG_SEL2 (DRAMC_AO_BASE_ADDRESS + 0x0120) + #define DRAMC_DBG_SEL2_DEBUG_SEL_2 Fld(16, 0) //[15:0] + #define DRAMC_DBG_SEL2_DEBUG_SEL_3 Fld(16, 16) //[31:16] + +#define DRAMC_REG_SWCMD_EN (DRAMC_AO_BASE_ADDRESS + 0x0124) + #define SWCMD_EN_MPRWEN Fld(1, 0) //[0:0] + #define SWCMD_EN_STESTEN Fld(1, 1) //[1:1] + #define SWCMD_EN_MPCMANEN Fld(1, 2) //[2:2] + #define SWCMD_EN_PREAEN Fld(1, 3) //[3:3] + #define SWCMD_EN_ACTEN Fld(1, 4) //[4:4] + #define SWCMD_EN_RDDQCEN Fld(1, 5) //[5:5] + #define SWCMD_EN_WRFIFOEN Fld(1, 6) //[6:6] + #define SWCMD_EN_RDFIFOEN Fld(1, 7) //[7:7] + #define SWCMD_EN_DQSOSCDISEN Fld(1, 8) //[8:8] + #define SWCMD_EN_DQSOSCENEN Fld(1, 9) //[9:9] + #define SWCMD_EN_ZQLATEN Fld(1, 10) //[10:10] + #define SWCMD_EN_MRWEN Fld(1, 11) //[11:11] + #define SWCMD_EN_MRREN Fld(1, 12) //[12:12] + #define SWCMD_EN_AREFEN Fld(1, 13) //[13:13] + #define SWCMD_EN_ZQCEN Fld(1, 14) //[14:14] + #define SWCMD_EN_SPREA_EN Fld(1, 15) //[15:15] + #define SWCMD_EN_ZQCEN_SWTRIG Fld(1, 16) //[16:16] + #define SWCMD_EN_ZQLATEN_SWTRIG Fld(1, 17) //[17:17] + #define SWCMD_EN_WCK2DQI_START_SWTRIG Fld(1, 18) //[18:18] + #define SWCMD_EN_WCK2DQO_START_SWTRIG Fld(1, 19) //[19:19] + #define SWCMD_EN_ZQ_SW Fld(1, 20) //[20:20] + #define SWCMD_EN_WCK2DQ_SW Fld(1, 21) //[21:21] + #define SWCMD_EN_SWCMDEN_RESERVED87 Fld(2, 22) //[23:22] + #define SWCMD_EN_RTMRWEN Fld(1, 24) //[24:24] + #define SWCMD_EN_RTSWCMDEN Fld(1, 25) //[25:25] + #define SWCMD_EN_RTSWCMD_SEL Fld(6, 26) //[31:26] + +#define DRAMC_REG_SWCMD_CTRL0 (DRAMC_AO_BASE_ADDRESS + 0x0128) + #define SWCMD_CTRL0_MRSOP Fld(8, 0) //[7:0] + #define SWCMD_CTRL0_MRSMA Fld(13, 8) //[20:8] + #define SWCMD_CTRL0_MRSBA Fld(3, 21) //[23:21] + #define SWCMD_CTRL0_MRSRK Fld(2, 24) //[25:24] + #define SWCMD_CTRL0_MRRRK Fld(2, 26) //[27:26] + #define SWCMD_CTRL0_MRSBG Fld(2, 28) //[29:28] + #define SWCMD_CTRL0_SWTRIG_ZQ_RK Fld(1, 30) //[30:30] + +#define DRAMC_REG_SWCMD_CTRL1 (DRAMC_AO_BASE_ADDRESS + 0x012C) + #define SWCMD_CTRL1_RDDQC_LP_INTV Fld(2, 0) //[1:0] + #define SWCMD_CTRL1_RDDQC_LP_ENB Fld(1, 2) //[2:2] + #define SWCMD_CTRL1_ACTEN_BK Fld(3, 3) //[5:3] + #define SWCMD_CTRL1_ACTEN_ROW_R17_R16 Fld(2, 22) //[22:23] //Lewis add for ppr + #define SWCMD_CTRL1_ACTEN_ROW Fld(18, 6) //[23:6] + #define SWCMD_CTRL1_WRFIFO_MODE2 Fld(1, 31) //[31:31] + +#define DRAMC_REG_SWCMD_CTRL2 (DRAMC_AO_BASE_ADDRESS + 0x0130) + #define SWCMD_CTRL2_RTSWCMD_AGE Fld(10, 0) //[9:0] + #define SWCMD_CTRL2_RTSWCMD_RK Fld(2, 10) //[11:10] + #define SWCMD_CTRL2_RTSWCMD_MA Fld(8, 12) //[19:12] + #define SWCMD_CTRL2_RTSWCMD_OP Fld(8, 20) //[27:20] + #define SWCMD_CTRL2_RTSWCMD_ALLTYPE_OPT Fld(1, 28) //[28:28] + +#define DRAMC_REG_RDDQCGOLDEN1 (DRAMC_AO_BASE_ADDRESS + 0x0134) + #define RDDQCGOLDEN1_LP5_MR20_6_GOLDEN Fld(1, 0) //[0:0] + #define RDDQCGOLDEN1_LP5_MR20_7_GOLDEN Fld(1, 1) //[1:1] + +#define DRAMC_REG_RDDQCGOLDEN (DRAMC_AO_BASE_ADDRESS + 0x0138) + #define RDDQCGOLDEN_MR20_GOLDEN Fld(8, 0) //[7:0] + #define RDDQCGOLDEN_MR15_GOLDEN Fld(8, 8) //[15:8] + #define RDDQCGOLDEN_MR40_GOLDEN Fld(8, 16) //[23:16] + #define RDDQCGOLDEN_MR32_GOLDEN Fld(8, 24) //[31:24] + +#define DRAMC_REG_RTMRW_CTRL0 (DRAMC_AO_BASE_ADDRESS + 0x013C) + #define RTMRW_CTRL0_RTMRW0_RK Fld(2, 0) //[1:0] + #define RTMRW_CTRL0_RTMRW1_RK Fld(2, 2) //[3:2] + #define RTMRW_CTRL0_RTMRW2_RK Fld(2, 4) //[5:4] + #define RTMRW_CTRL0_RTMRW3_RK Fld(2, 6) //[7:6] + #define RTMRW_CTRL0_RTMRW4_RK Fld(2, 8) //[9:8] + #define RTMRW_CTRL0_RTMRW5_RK Fld(2, 10) //[11:10] + #define RTMRW_CTRL0_RTMRW_LEN Fld(3, 12) //[14:12] + #define RTMRW_CTRL0_RTMRW_AGE Fld(10, 15) //[24:15] + #define RTMRW_CTRL0_RTMRW_LAT Fld(7, 25) //[31:25] + +#define DRAMC_REG_RTMRW_CTRL1 (DRAMC_AO_BASE_ADDRESS + 0x0140) + #define RTMRW_CTRL1_RTMRW0_MA Fld(8, 0) //[7:0] + #define RTMRW_CTRL1_RTMRW1_MA Fld(8, 8) //[15:8] + #define RTMRW_CTRL1_RTMRW2_MA Fld(8, 16) //[23:16] + #define RTMRW_CTRL1_RTMRW3_MA Fld(8, 24) //[31:24] + +#define DRAMC_REG_RTMRW_CTRL2 (DRAMC_AO_BASE_ADDRESS + 0x0144) + #define RTMRW_CTRL2_RTMRW0_OP Fld(8, 0) //[7:0] + #define RTMRW_CTRL2_RTMRW1_OP Fld(8, 8) //[15:8] + #define RTMRW_CTRL2_RTMRW2_OP Fld(8, 16) //[23:16] + #define RTMRW_CTRL2_RTMRW3_OP Fld(8, 24) //[31:24] + +#define DRAMC_REG_RTMRW_CTRL3 (DRAMC_AO_BASE_ADDRESS + 0x0148) + #define RTMRW_CTRL3_RTMRW4_MA Fld(8, 0) //[7:0] + #define RTMRW_CTRL3_RTMRW5_MA Fld(8, 8) //[15:8] + #define RTMRW_CTRL3_RTMRW4_OP Fld(8, 16) //[23:16] + #define RTMRW_CTRL3_RTMRW5_OP Fld(8, 24) //[31:24] + +#define DRAMC_REG_CBT_WLEV_CTRL0 (DRAMC_AO_BASE_ADDRESS + 0x014C) + #define CBT_WLEV_CTRL0_CBT_CAPATEN Fld(1, 0) //[0:0] + #define CBT_WLEV_CTRL0_TCMDEN Fld(1, 1) //[1:1] + #define CBT_WLEV_CTRL0_BYTEMODECBTEN Fld(1, 2) //[2:2] + #define CBT_WLEV_CTRL0_WRITE_LEVEL_EN Fld(1, 3) //[3:3] + #define CBT_WLEV_CTRL0_DQSOEAOEN Fld(1, 4) //[4:4] + #define CBT_WLEV_CTRL0_CBTMASKDQSOE Fld(1, 5) //[5:5] + #define CBT_WLEV_CTRL0_WLEV_DQSPATEN Fld(1, 6) //[6:6] + #define CBT_WLEV_CTRL0_CBT_WLEV_DQS_TRIG Fld(1, 7) //[7:7] + #define CBT_WLEV_CTRL0_CBT_WLEV_DQS_SEL Fld(4, 8) //[11:8] + #define CBT_WLEV_CTRL0_WLEV_DQSPAT_LAT Fld(8, 12) //[19:12] + #define CBT_WLEV_CTRL0_WLEV_MCK_NUM Fld(2, 20) //[21:20] + #define CBT_WLEV_CTRL0_WLEV_WCK_HR Fld(1, 22) //[22:22] + #define CBT_WLEV_CTRL0_CBT_WLEV_WCKAO Fld(1, 23) //[23:23] + #define CBT_WLEV_CTRL0_CBT_SW_DQM_B0_LP5 Fld(1, 24) //[24:24] + #define CBT_WLEV_CTRL0_CBT_SW_DQM_B1_LP5 Fld(1, 25) //[25:25] + #define CBT_WLEV_CTRL0_CBT_DQBYTE_OEAO_EN Fld(4, 26) //[29:26] + #define CBT_WLEV_CTRL0_CBT_CMP_BYTEMODE Fld(1, 30) //[30:30] + +#define DRAMC_REG_CBT_WLEV_CTRL1 (DRAMC_AO_BASE_ADDRESS + 0x0150) + #define CBT_WLEV_CTRL1_CATRAINCSEXT Fld(1, 0) //[0:0] + #define CBT_WLEV_CTRL1_CATRAINMRS Fld(1, 1) //[1:1] + #define CBT_WLEV_CTRL1_CATRAINEN Fld(1, 2) //[2:2] + #define CBT_WLEV_CTRL1_CATRAINLAT Fld(4, 11) //[14:11] + #define CBT_WLEV_CTRL1_CATRAIN_INTV Fld(8, 15) //[22:15] + #define CBT_WLEV_CTRL1_TCMDO1LAT Fld(8, 23) //[30:23] + +#define DRAMC_REG_CBT_WLEV_CTRL2 (DRAMC_AO_BASE_ADDRESS + 0x0154) + #define CBT_WLEV_CTRL2_CATRAINCA Fld(16, 0) //[15:0] + #define CBT_WLEV_CTRL2_CATRAINCA_Y Fld(16, 16) //[31:16] + +#define DRAMC_REG_CBT_WLEV_CTRL3 (DRAMC_AO_BASE_ADDRESS + 0x0158) + #define CBT_WLEV_CTRL3_CATRAIN_PAT_STOP0 Fld(4, 0) //[3:0] + #define CBT_WLEV_CTRL3_CATRAIN_PAT_STOP1 Fld(3, 4) //[6:4] + #define CBT_WLEV_CTRL3_CATRAIN_1PAT_SEL0 Fld(4, 7) //[10:7] + #define CBT_WLEV_CTRL3_CATRAIN_1PAT_SEL1 Fld(3, 11) //[13:11] + #define CBT_WLEV_CTRL3_DQSBX_G Fld(4, 14) //[17:14] + #define CBT_WLEV_CTRL3_DQSBY_G Fld(4, 18) //[21:18] + #define CBT_WLEV_CTRL3_DQSBX1_G Fld(4, 22) //[25:22] + #define CBT_WLEV_CTRL3_DQSBY1_G Fld(4, 26) //[29:26] + +#define DRAMC_REG_CBT_WLEV_CTRL4 (DRAMC_AO_BASE_ADDRESS + 0x015C) + #define CBT_WLEV_CTRL4_CBT_TXDQ_B0 Fld(8, 0) //[7:0] + #define CBT_WLEV_CTRL4_CBT_TXDQ_B1 Fld(8, 8) //[15:8] + +#define DRAMC_REG_CBT_WLEV_ATK_CTRL0 (DRAMC_AO_BASE_ADDRESS + 0x0160) + #define CBT_WLEV_ATK_CTRL0_ARPICS_SW Fld(1, 0) //[0:0] + #define CBT_WLEV_ATK_CTRL0_ARPICA_SW Fld(1, 1) //[1:1] + #define CBT_WLEV_ATK_CTRL0_ARPIDQS_SW Fld(1, 2) //[2:2] + #define CBT_WLEV_ATK_CTRL0_CSTRAIN_ATKEN Fld(1, 3) //[3:3] + #define CBT_WLEV_ATK_CTRL0_CATRAIN_ATKEN Fld(1, 4) //[4:4] + #define CBT_WLEV_ATK_CTRL0_WLEV_ATKEN Fld(1, 5) //[5:5] + #define CBT_WLEV_ATK_CTRL0_CBT_WLEV_ATK_INTV Fld(5, 6) //[10:6] + #define CBT_WLEV_ATK_CTRL0_CBT_WLEV_ATK_LENPI Fld(6, 11) //[16:11] + #define CBT_WLEV_ATK_CTRL0_CBT_WLEV_ATK_RESPI Fld(2, 17) //[18:17] + #define CBT_WLEV_ATK_CTRL0_CBT_WLEV_ATK_INITPI Fld(6, 19) //[24:19] + #define CBT_WLEV_ATK_CTRL0_CBT_ATK_CABITDBG Fld(3, 25) //[27:25] + +#define DRAMC_REG_CBT_WLEV_ATK_CTRL1 (DRAMC_AO_BASE_ADDRESS + 0x0164) + #define CBT_WLEV_ATK_CTRL1_UICS_SW Fld(2, 0) //[1:0] + #define CBT_WLEV_ATK_CTRL1_UICA_SW Fld(7, 2) //[8:2] + #define CBT_WLEV_ATK_CTRL1_UIDQS_SW Fld(4, 9) //[12:9] + #define CBT_WLEV_ATK_CTRL1_UIWCK_FS_B1_RK0_SW Fld(1, 13) //[13:13] + #define CBT_WLEV_ATK_CTRL1_UIWCK_FS_B0_RK0_SW Fld(1, 14) //[14:14] + #define CBT_WLEV_ATK_CTRL1_UIWCK_FS_B1_RK1_SW Fld(1, 15) //[15:15] + #define CBT_WLEV_ATK_CTRL1_UIWCK_FS_B0_RK1_SW Fld(1, 16) //[16:16] + #define CBT_WLEV_ATK_CTRL1_CBT_ATK_CA1UI64PI Fld(1, 17) //[17:17] + +#define DRAMC_REG_SREF_DPD_CTRL (DRAMC_AO_BASE_ADDRESS + 0x0168) + #define SREF_DPD_CTRL_LPSM_BYPASS_B Fld(1, 7) //[7:7] + #define SREF_DPD_CTRL_DPDWOSC Fld(1, 8) //[8:8] + #define SREF_DPD_CTRL_CLR_EN Fld(1, 9) //[9:9] + #define SREF_DPD_CTRL_SELFREF_AUTOSAVE_EN Fld(1, 10) //[10:10] + #define SREF_DPD_CTRL_SREF_PRD_OPT Fld(1, 11) //[11:11] + #define SREF_DPD_CTRL_SREF_CG_OPT Fld(1, 12) //[12:12] + #define SREF_DPD_CTRL_SRFPD_DIS Fld(1, 13) //[13:13] + #define SREF_DPD_CTRL_SREF3_OPTION Fld(1, 14) //[14:14] + #define SREF_DPD_CTRL_SREF2_OPTION Fld(1, 15) //[15:15] + #define SREF_DPD_CTRL_SREFDLY Fld(4, 16) //[19:16] + #define SREF_DPD_CTRL_DSM_HW_EN Fld(1, 20) //[20:20] + #define SREF_DPD_CTRL_DSM_TRIGGER Fld(1, 21) //[21:21] + #define SREF_DPD_CTRL_SREF_HW_EN Fld(1, 22) //[22:22] + #define SREF_DPD_CTRL_SELFREF Fld(1, 23) //[23:23] + #define SREF_DPD_CTRL_DPDWAKEDCMCKE Fld(1, 25) //[25:25] + #define SREF_DPD_CTRL_CMDCKAR Fld(1, 26) //[26:26] + #define SREF_DPD_CTRL_GTDMW_SYNC_MASK Fld(1, 28) //[28:28] + #define SREF_DPD_CTRL_GT_SYNC_MASK Fld(1, 29) //[29:29] + #define SREF_DPD_CTRL_DAT_SYNC_MASK Fld(1, 30) //[30:30] + #define SREF_DPD_CTRL_PHY_SYNC_MASK Fld(1, 31) //[31:31] + +#define DRAMC_REG_CFC_CTRL (DRAMC_AO_BASE_ADDRESS + 0x016C) + #define CFC_CTRL_CFC_CTRL_RESERVED Fld(1, 0) //[0:0] + +#define DRAMC_REG_DLLFRZ_CTRL (DRAMC_AO_BASE_ADDRESS + 0x0170) + #define DLLFRZ_CTRL_INPUTRXTRACK_BLOCK Fld(1, 0) //[0:0] + #define DLLFRZ_CTRL_DLLFRZ_MON_PBREF_OPT Fld(1, 1) //[1:1] + #define DLLFRZ_CTRL_DLLFRZ_BLOCKLONG Fld(1, 2) //[2:2] + #define DLLFRZ_CTRL_DLLFRZIDLE4XUPD Fld(1, 3) //[3:3] + #define DLLFRZ_CTRL_FASTDQSG2X Fld(1, 4) //[4:4] + #define DLLFRZ_CTRL_FASTDQSGUPD Fld(1, 5) //[5:5] + #define DLLFRZ_CTRL_MANUDLLFRZ Fld(1, 6) //[6:6] + #define DLLFRZ_CTRL_DLLFRZ Fld(1, 7) //[7:7] + #define DLLFRZ_CTRL_UPDBYWR Fld(1, 8) //[8:8] + +#define DRAMC_REG_MPC_CTRL (DRAMC_AO_BASE_ADDRESS + 0x0174) + #define MPC_CTRL_MPC_BLOCKALE_OPT Fld(1, 0) //[0:0] + #define MPC_CTRL_MPC_BLOCKALE_OPT1 Fld(1, 1) //[1:1] + #define MPC_CTRL_MPC_BLOCKALE_OPT2 Fld(1, 2) //[2:2] + #define MPC_CTRL_ZQ_BLOCKALE_OPT Fld(1, 3) //[3:3] + #define MPC_CTRL_RW2ZQLAT_OPT Fld(1, 4) //[4:4] + #define MPC_CTRL_REFR_BLOCKEN Fld(1, 5) //[5:5] + #define MPC_CTRL_RTMRW_HPRI_EN Fld(1, 6) //[6:6] + #define MPC_CTRL_RTSWCMD_HPRI_EN Fld(1, 7) //[7:7] + +#define DRAMC_REG_HW_MRR_FUN (DRAMC_AO_BASE_ADDRESS + 0x0178) + #define HW_MRR_FUN_TMRR_ENA Fld(1, 0) //[0:0] + #define HW_MRR_FUN_TRCDMRR_EN Fld(1, 1) //[1:1] + #define HW_MRR_FUN_TRPMRR_EN Fld(1, 2) //[2:2] + #define HW_MRR_FUN_MANTMRR_EN Fld(1, 3) //[3:3] + #define HW_MRR_FUN_TR2MRR_ENA Fld(1, 4) //[4:4] + #define HW_MRR_FUN_R2MRRHPRICTL Fld(1, 5) //[5:5] + #define HW_MRR_FUN_BUFEN_RFC_OPT Fld(1, 8) //[8:8] + #define HW_MRR_FUN_MRR_REQNOPUSH_DIS Fld(1, 9) //[9:9] + #define HW_MRR_FUN_MRR_BLOCK_NOR_DIS Fld(1, 10) //[10:10] + #define HW_MRR_FUN_MRR_HW_HIPRI Fld(1, 11) //[11:11] + #define HW_MRR_FUN_MRR_SPCMD_WAKE_DIS Fld(1, 12) //[12:12] + #define HW_MRR_FUN_TMRR_OE_OPT_DIS Fld(1, 13) //[13:13] + #define HW_MRR_FUN_MRR_SBR_OPT_DIS Fld(1, 14) //[14:14] + #define HW_MRR_FUN_MRR_INT_TIE0_DIS Fld(1, 15) //[15:15] + #define HW_MRR_FUN_MRR_PUSH2POP_ENA Fld(1, 16) //[16:16] + #define HW_MRR_FUN_MRR_PUSH2POP_CLR Fld(1, 17) //[17:17] + #define HW_MRR_FUN_MRR_PUSH2POP_ST_CLR Fld(1, 18) //[18:18] + #define HW_MRR_FUN_MRR_MADIS Fld(1, 19) //[19:19] + #define HW_MRR_FUN_MRR_PUSH2POP_SEL Fld(3, 20) //[22:20] + #define HW_MRR_FUN_MRR_SBR3_BKVA_DIS Fld(1, 23) //[23:23] + #define HW_MRR_FUN_MRR_DDRCLKCOMB_DIS Fld(1, 24) //[24:24] + #define HW_MRR_FUN_TRPRCD_DIS_OPT1 Fld(1, 25) //[25:25] + #define HW_MRR_FUN_TRPRCD_OPT2 Fld(1, 26) //[26:26] + #define HW_MRR_FUN_MRR_SBR2_QHIT_DIS Fld(1, 27) //[27:27] + #define HW_MRR_FUN_MRR_INPUT_BANK Fld(3, 28) //[30:28] + #define HW_MRR_FUN_MRR_TZQCS_DIS Fld(1, 31) //[31:31] + +#define DRAMC_REG_SCHEDULER_COM (DRAMC_AO_BASE_ADDRESS + 0x017C) + #define SCHEDULER_COM_RWOFOEN Fld(1, 0) //[0:0] + #define SCHEDULER_COM_RWHPRICTL Fld(1, 4) //[4:4] + #define SCHEDULER_COM_RWSPLIT Fld(1, 5) //[5:5] + #define SCHEDULER_COM_MWHPRIEN Fld(1, 6) //[6:6] + #define SCHEDULER_COM_SPEC_MODE Fld(1, 7) //[7:7] + #define SCHEDULER_COM_DISRDPHASE1 Fld(1, 8) //[8:8] + #define SCHEDULER_COM_PBR2PBR_OPT Fld(1, 9) //[9:9] + +#define DRAMC_REG_ACTIMING_CTRL (DRAMC_AO_BASE_ADDRESS + 0x0190) + #define ACTIMING_CTRL_SEQCLKRUN3 Fld(1, 0) //[0:0] + #define ACTIMING_CTRL_SEQCLKRUN2 Fld(1, 1) //[1:1] + #define ACTIMING_CTRL_SEQCLKRUN Fld(1, 2) //[2:2] + #define ACTIMING_CTRL_TMRR2WDIS Fld(1, 4) //[4:4] + #define ACTIMING_CTRL_MRRSWUPD Fld(1, 5) //[5:5] + #define ACTIMING_CTRL_REFNA_OPT Fld(1, 6) //[6:6] + #define ACTIMING_CTRL_REFBW_FREN Fld(1, 8) //[8:8] + #define ACTIMING_CTRL_CLKWITRFC Fld(1, 9) //[9:9] + #define ACTIMING_CTRL_CHKFORPRE Fld(1, 10) //[10:10] + #define ACTIMING_CTRL_BC4OTF_OPT Fld(1, 11) //[11:11] + #define ACTIMING_CTRL_TMRRICHKDIS Fld(1, 21) //[21:21] + #define ACTIMING_CTRL_TMRRIBYRK_DIS Fld(1, 22) //[22:22] + #define ACTIMING_CTRL_MRRIOPT Fld(1, 23) //[23:23] + #define ACTIMING_CTRL_FASTW2R Fld(1, 24) //[24:24] + #define ACTIMING_CTRL_APBL2 Fld(1, 25) //[25:25] + #define ACTIMING_CTRL_LPDDR2_NO_INT Fld(1, 27) //[27:27] + +#define DRAMC_REG_ZQ_SET0 (DRAMC_AO_BASE_ADDRESS + 0x01A0) + #define ZQ_SET0_ZQCSOP Fld(8, 0) //[7:0] + #define ZQ_SET0_ZQCSAD Fld(8, 8) //[15:8] + #define ZQ_SET0_ZQCS_MASK_SEL Fld(3, 16) //[18:16] + #define ZQ_SET0_ZQCS_MASK_SEL_CGAR Fld(1, 19) //[19:19] + #define ZQ_SET0_ZQMASK_CGAR Fld(1, 20) //[20:20] + #define ZQ_SET0_ZQCSMASK_OPT Fld(1, 21) //[21:21] + #define ZQ_SET0_ZQ_SRF_OPT Fld(1, 22) //[22:22] + #define ZQ_SET0_DM3RANK Fld(1, 23) //[23:23] + #define ZQ_SET0_ZQCSMASK Fld(1, 29) //[29:29] + #define ZQ_SET0_ZQCSDUAL Fld(1, 30) //[30:30] + #define ZQ_SET0_ZQCALL Fld(1, 31) //[31:31] + +#define DRAMC_REG_ZQ_SET1 (DRAMC_AO_BASE_ADDRESS + 0x01A4) + #define ZQ_SET1_ZQCS_NONMASK_CLR Fld(1, 20) //[20:20] + #define ZQ_SET1_ZQCS_MASK_FIX Fld(1, 21) //[21:21] + #define ZQ_SET1_ZQCS_MASK_VALUE Fld(1, 22) //[22:22] + #define ZQ_SET1_ZQCALDISB Fld(1, 30) //[30:30] + #define ZQ_SET1_ZQCSDISB Fld(1, 31) //[31:31] + +#define DRAMC_REG_TX_TRACKING_SET0 (DRAMC_AO_BASE_ADDRESS + 0x01B0) + #define TX_TRACKING_SET0_TX_TRACKING_OPT Fld(1, 15) //[15:15] + #define TX_TRACKING_SET0_SW_UP_TX_NOW_CASE Fld(1, 16) //[16:16] + #define TX_TRACKING_SET0_TXUIPI_CAL_CGAR Fld(1, 17) //[17:17] + #define TX_TRACKING_SET0_SHU_PRELOAD_TX_START Fld(1, 18) //[18:18] + #define TX_TRACKING_SET0_SHU_PRELOAD_TX_HW Fld(1, 19) //[19:19] + #define TX_TRACKING_SET0_APHY_CG_OPT1 Fld(1, 20) //[20:20] + #define TX_TRACKING_SET0_HMRRSEL_CGAR Fld(1, 21) //[21:21] + #define TX_TRACKING_SET0_RDDQSOSC_CGAR Fld(1, 22) //[22:22] + #define TX_TRACKING_SET0_DQSOSC_THRD_OPT Fld(1, 23) //[23:23] + #define TX_TRACKING_SET0_TX_PRECAL_RELOAD_OPT Fld(1, 24) //[24:24] + #define TX_TRACKING_SET0_DQSOSC_C2R_OPT Fld(1, 31) //[31:31] + +#define DRAMC_REG_TX_RETRY_SET0 (DRAMC_AO_BASE_ADDRESS + 0x01C0) + #define TX_RETRY_SET0_XSR_TX_RETRY_BLOCK_ALE_MASK Fld(1, 0) //[0:0] + #define TX_RETRY_SET0_XSR_TX_RETRY_OPT Fld(1, 1) //[1:1] + #define TX_RETRY_SET0_XSR_TX_RETRY_EN Fld(1, 2) //[2:2] + #define TX_RETRY_SET0_XSR_TX_RETRY_SPM_MODE Fld(1, 3) //[3:3] + #define TX_RETRY_SET0_XSR_TX_RETRY_SW_EN Fld(1, 4) //[4:4] + #define TX_RETRY_SET0_TX_RETRY_UPDPI_CG_OPT Fld(1, 5) //[5:5] + #define TX_RETRY_SET0_TX_RETRY_SHU_RESP_OPT Fld(1, 6) //[6:6] + +#define DRAMC_REG_MPC_OPTION (DRAMC_AO_BASE_ADDRESS + 0x01C8) + #define MPC_OPTION_MPCOP Fld(7, 8) //[14:8] + #define MPC_OPTION_MPCMAN_CAS2EN Fld(1, 16) //[16:16] + #define MPC_OPTION_MPCRKEN Fld(1, 17) //[17:17] + +#define DRAMC_REG_MRR_BIT_MUX1 (DRAMC_AO_BASE_ADDRESS + 0x01D0) + #define MRR_BIT_MUX1_MRR_BIT0_SEL Fld(5, 0) //[4:0] + #define MRR_BIT_MUX1_MRR_BIT1_SEL Fld(5, 8) //[12:8] + #define MRR_BIT_MUX1_MRR_BIT2_SEL Fld(5, 16) //[20:16] + #define MRR_BIT_MUX1_MRR_BIT3_SEL Fld(5, 24) //[28:24] + +#define DRAMC_REG_MRR_BIT_MUX2 (DRAMC_AO_BASE_ADDRESS + 0x01D4) + #define MRR_BIT_MUX2_MRR_BIT4_SEL Fld(5, 0) //[4:0] + #define MRR_BIT_MUX2_MRR_BIT5_SEL Fld(5, 8) //[12:8] + #define MRR_BIT_MUX2_MRR_BIT6_SEL Fld(5, 16) //[20:16] + #define MRR_BIT_MUX2_MRR_BIT7_SEL Fld(5, 24) //[28:24] + +#define DRAMC_REG_MRR_BIT_MUX3 (DRAMC_AO_BASE_ADDRESS + 0x01D8) + #define MRR_BIT_MUX3_MRR_BIT8_SEL Fld(5, 0) //[4:0] + #define MRR_BIT_MUX3_MRR_BIT9_SEL Fld(5, 8) //[12:8] + #define MRR_BIT_MUX3_MRR_BIT10_SEL Fld(5, 16) //[20:16] + #define MRR_BIT_MUX3_MRR_BIT11_SEL Fld(5, 24) //[28:24] + +#define DRAMC_REG_MRR_BIT_MUX4 (DRAMC_AO_BASE_ADDRESS + 0x01DC) + #define MRR_BIT_MUX4_MRR_BIT12_SEL Fld(5, 0) //[4:0] + #define MRR_BIT_MUX4_MRR_BIT13_SEL Fld(5, 8) //[12:8] + #define MRR_BIT_MUX4_MRR_BIT14_SEL Fld(5, 16) //[20:16] + #define MRR_BIT_MUX4_MRR_BIT15_SEL Fld(5, 24) //[28:24] + +#define DRAMC_REG_SHUCTRL (DRAMC_AO_BASE_ADDRESS + 0x01F8) + #define SHUCTRL_R_DVFS_FSM_CLR Fld(1, 0) //[0:0] + #define SHUCTRL_DMSHU_DRAMC Fld(1, 4) //[4:4] + +#define DRAMC_REG_DRAMC_PD_CTRL (DRAMC_AO_BASE_ADDRESS + 0x01FC) + #define DRAMC_PD_CTRL_DCMEN Fld(1, 0) //[0:0] + #define DRAMC_PD_CTRL_DCMEN2 Fld(1, 1) //[1:1] + #define DRAMC_PD_CTRL_DCMENNOTRFC Fld(1, 2) //[2:2] + #define DRAMC_PD_CTRL_PHYGLUECLKRUN Fld(1, 3) //[3:3] + #define DRAMC_PD_CTRL_PHYCLK_REFWKEN Fld(1, 4) //[4:4] + #define DRAMC_PD_CTRL_COMBPHY_CLKENSAME Fld(1, 5) //[5:5] + #define DRAMC_PD_CTRL_MIOCKCTRLOFF Fld(1, 6) //[6:6] + #define DRAMC_PD_CTRL_DRAMC_IDLE_DCM_FIXON Fld(1, 7) //[7:7] + #define DRAMC_PD_CTRL_PG_DCM_OPT Fld(1, 9) //[9:9] + #define DRAMC_PD_CTRL_COMB_DCM Fld(1, 10) //[10:10] + #define DRAMC_PD_CTRL_APHYCKCG_FIXOFF Fld(1, 12) //[12:12] + #define DRAMC_PD_CTRL_TCKFIXON Fld(1, 13) //[13:13] + #define DRAMC_PD_CTRL_PHYCLKDYNGEN Fld(1, 30) //[30:30] + #define DRAMC_PD_CTRL_COMBCLKCTRL Fld(1, 31) //[31:31] + +#define DRAMC_REG_DCM_CTRL0 (DRAMC_AO_BASE_ADDRESS + 0x0200) + #define DCM_CTRL0_BCLKAR Fld(1, 2) //[2:2] + #define DCM_CTRL0_DBG_CKE1FIXON Fld(1, 4) //[4:4] + #define DCM_CTRL0_DBG_CKE1FIXOFF Fld(1, 5) //[5:5] + #define DCM_CTRL0_DBG_CKEFIXON Fld(1, 6) //[6:6] + #define DCM_CTRL0_DBG_CKEFIXOFF Fld(1, 7) //[7:7] + #define DCM_CTRL0_DISDMOEDIS Fld(1, 8) //[8:8] + #define DCM_CTRL0_IDLE_CNT_OPT Fld(1, 16) //[16:16] + #define DCM_CTRL0_IDLEDCM_CNT_OPT Fld(1, 17) //[17:17] + #define DCM_CTRL0_IDLE_COND_OPT Fld(1, 18) //[18:18] + +#define DRAMC_REG_CKECTRL (DRAMC_AO_BASE_ADDRESS + 0x0204) + #define CKECTRL_CKE2RANK_OPT3 Fld(1, 1) //[1:1] + #define CKECTRL_CKE2FIXON Fld(1, 2) //[2:2] + #define CKECTRL_CKE2FIXOFF Fld(1, 3) //[3:3] + #define CKECTRL_CKE1FIXON Fld(1, 4) //[4:4] + #define CKECTRL_CKE1FIXOFF Fld(1, 5) //[5:5] + #define CKECTRL_CKEFIXON Fld(1, 6) //[6:6] + #define CKECTRL_CKEFIXOFF Fld(1, 7) //[7:7] + #define CKECTRL_CKE2RANK_OPT5 Fld(1, 8) //[8:8] + #define CKECTRL_CKE2RANK_OPT6 Fld(1, 9) //[9:9] + #define CKECTRL_CKE2RANK_OPT7 Fld(1, 10) //[10:10] + #define CKECTRL_CKE2RANK_OPT8 Fld(1, 11) //[11:11] + #define CKECTRL_CKEEXTEND Fld(1, 12) //[12:12] + #define CKECTRL_CKETIMER_SEL Fld(1, 13) //[13:13] + #define CKECTRL_FASTWAKE_SEL Fld(1, 14) //[14:14] + #define CKECTRL_CKEWAKE_SEL Fld(1, 15) //[15:15] + #define CKECTRL_CKEWAKE_SEL2 Fld(1, 16) //[16:16] + #define CKECTRL_CKE2RANK_OPT9 Fld(1, 17) //[17:17] + #define CKECTRL_CKE2RANK_OPT10 Fld(1, 18) //[18:18] + #define CKECTRL_CKE2RANK_OPT11 Fld(1, 19) //[19:19] + #define CKECTRL_CKE2RANK_OPT12 Fld(1, 20) //[20:20] + #define CKECTRL_CKE2RANK_OPT13 Fld(1, 21) //[21:21] + #define CKECTRL_CKEPBDIS Fld(1, 22) //[22:22] + #define CKECTRL_CKELCKFIX Fld(1, 23) //[23:23] + #define CKECTRL_CKE2RANK_OPT2 Fld(1, 24) //[24:24] + #define CKECTRL_CKE2RANK_OPT Fld(1, 25) //[25:25] + #define CKECTRL_RUNTIMEMRRCKEFIX Fld(1, 27) //[27:27] + #define CKECTRL_RUNTIMEMRRMIODIS Fld(1, 28) //[28:28] + #define CKECTRL_CKEON Fld(1, 31) //[31:31] + +#define DRAMC_REG_DVFS_CTRL0 (DRAMC_AO_BASE_ADDRESS + 0x0208) + #define DVFS_CTRL0_R_DRAMC_CHA Fld(1, 0) //[0:0] + #define DVFS_CTRL0_SHU_PHYRST_SEL Fld(1, 1) //[1:1] + #define DVFS_CTRL0_R_DVFS_SREF_OPT Fld(1, 5) //[5:5] + #define DVFS_CTRL0_HWSET_WLRL Fld(1, 8) //[8:8] + #define DVFS_CTRL0_MR13_SHU_EN Fld(1, 9) //[9:9] + #define DVFS_CTRL0_VRCG_EN Fld(1, 10) //[10:10] + #define DVFS_CTRL0_SHU_CLK_MASK Fld(1, 12) //[12:12] + #define DVFS_CTRL0_DVFS_RXFIFOST_SKIP Fld(1, 13) //[13:13] + #define DVFS_CTRL0_DVFS_MR2_SKIP Fld(1, 14) //[14:14] + #define DVFS_CTRL0_DVFS_NOQUEFLUSH_EN Fld(1, 15) //[15:15] + #define DVFS_CTRL0_DVFS_CKE_OPT Fld(1, 16) //[16:16] + #define DVFS_CTRL0_R_SHUFFLE_BLOCK_OPT Fld(2, 17) //[18:17] + #define DVFS_CTRL0_DVFS_CG_OPT Fld(1, 19) //[19:19] + #define DVFS_CTRL0_SCARB_PRI_OPT Fld(1, 20) //[20:20] + #define DVFS_CTRL0_R_DMDVFSMRW_EN Fld(1, 21) //[21:21] + #define DVFS_CTRL0_MRWWOPRA Fld(1, 22) //[22:22] + #define DVFS_CTRL0_SHU2RKOPT Fld(1, 23) //[23:23] + #define DVFS_CTRL0_R_DMSHU_RDATRST_MASK Fld(1, 25) //[25:25] + #define DVFS_CTRL0_DVFS_SYNC_MASK Fld(1, 27) //[27:27] + +#define DRAMC_REG_SHUCTRL1 (DRAMC_AO_BASE_ADDRESS + 0x020C) + #define SHUCTRL1_FC_PRDCNT Fld(8, 0) //[7:0] + #define SHUCTRL1_CKFSPE_PRDCNT Fld(8, 8) //[15:8] + #define SHUCTRL1_CKFSPX_PRDCNT Fld(8, 16) //[23:16] + #define SHUCTRL1_VRCGEN_PRDCNT Fld(8, 24) //[31:24] + +#define DRAMC_REG_DVFS_TIMING_CTRL1 (DRAMC_AO_BASE_ADDRESS + 0x0210) + #define DVFS_TIMING_CTRL1_SHU_PERIOD_GO_ZERO_CNT Fld(8, 0) //[7:0] + #define DVFS_TIMING_CTRL1_DMSHU_CNT Fld(6, 16) //[21:16] + +#define DRAMC_REG_SHUCTRL3 (DRAMC_AO_BASE_ADDRESS + 0x0214) + #define SHUCTRL3_VRCGDIS_MRSMA Fld(13, 0) //[12:0] + #define SHUCTRL3_VRCGDISOP Fld(8, 16) //[23:16] + +#define DRAMC_REG_DVFS_TIMING_CTRL3 (DRAMC_AO_BASE_ADDRESS + 0x0218) + #define DVFS_TIMING_CTRL3_PREA_INTV Fld(5, 0) //[4:0] + #define DVFS_TIMING_CTRL3_MRW_INTV Fld(5, 8) //[12:8] + #define DVFS_TIMING_CTRL3_RTMRW_MRW1_SKIP Fld(1, 16) //[16:16] + #define DVFS_TIMING_CTRL3_RTMRW_MRW2_SKIP Fld(1, 17) //[17:17] + #define DVFS_TIMING_CTRL3_RTMRW_MRW3_SKIP Fld(1, 18) //[18:18] + #define DVFS_TIMING_CTRL3_RTMRW_MRW1_PAUSE Fld(1, 19) //[19:19] + #define DVFS_TIMING_CTRL3_RTMRW_MRW2_PAUSE Fld(1, 20) //[20:20] + #define DVFS_TIMING_CTRL3_RTMRW_MRW3_PAUSE Fld(1, 21) //[21:21] + #define DVFS_TIMING_CTRL3_RTMRW_MRW3_PRDCNT Fld(8, 24) //[31:24] + +#define DRAMC_REG_CMD_DEC_CTRL0 (DRAMC_AO_BASE_ADDRESS + 0x021C) + #define CMD_DEC_CTRL0_GDDR3RST Fld(1, 0) //[0:0] + #define CMD_DEC_CTRL0_SELPH_CMD_CG_DIS Fld(1, 4) //[4:4] + #define CMD_DEC_CTRL0_RA15TOCS1 Fld(1, 27) //[27:27] + #define CMD_DEC_CTRL0_RKMODE Fld(3, 8) //[10:8] + #define CMD_DEC_CTRL0_RKSWAP Fld(1, 11) //[11:11] + #define CMD_DEC_CTRL0_CS1FIXOFF Fld(1, 12) //[12:12] + #define CMD_DEC_CTRL0_PHYPIPE1EN Fld(1, 15) //[15:15] + #define CMD_DEC_CTRL0_PHYPIPE2EN Fld(1, 16) //[16:16] + #define CMD_DEC_CTRL0_PHYPIPE3EN Fld(1, 17) //[17:17] + #define CMD_DEC_CTRL0_DQCMD Fld(1, 19) //[19:19] + +#define DRAMC_REG_HMR4 (DRAMC_AO_BASE_ADDRESS + 0x0220) + #define HMR4_DRS_MR4_OPT_B Fld(1, 0) //[0:0] + #define HMR4_HMR4_TOG_OPT Fld(1, 1) //[1:1] + #define HMR4_SPDR_MR4_OPT Fld(1, 2) //[2:2] + #define HMR4_SRFMR4_CNTKEEP_B Fld(1, 3) //[3:3] + #define HMR4_MRRREFUPD_B Fld(1, 4) //[4:4] + #define HMR4_HMR4_BYTEMODE_EN Fld(1, 5) //[5:5] + #define HMR4_MR4INT_LIMITEN Fld(1, 6) //[6:6] + #define HMR4_REFR_PERIOD_OPT Fld(1, 7) //[7:7] + #define HMR4_REFRDIS Fld(1, 8) //[8:8] + #define HMR4_REFRCNT_OPT Fld(1, 9) //[9:9] + +#define DRAMC_REG_BYPASS_FSPOP (DRAMC_AO_BASE_ADDRESS + 0x0224) + #define BYPASS_FSPOP_BPFSP_SET_SHU0 Fld(1, 0) //[0:0] + #define BYPASS_FSPOP_BPFSP_SET_SHU1 Fld(1, 1) //[1:1] + #define BYPASS_FSPOP_BPFSP_SET_SHU2 Fld(1, 2) //[2:2] + #define BYPASS_FSPOP_BPFSP_SET_SHU3 Fld(1, 3) //[3:3] + #define BYPASS_FSPOP_BPFSP_SET_SHU4 Fld(1, 4) //[4:4] + #define BYPASS_FSPOP_BPFSP_SET_SHU5 Fld(1, 5) //[5:5] + #define BYPASS_FSPOP_BPFSP_SET_SHU6 Fld(1, 6) //[6:6] + #define BYPASS_FSPOP_BPFSP_SET_SHU7 Fld(1, 7) //[7:7] + #define BYPASS_FSPOP_BPFSP_SET_SHU8 Fld(1, 8) //[8:8] + #define BYPASS_FSPOP_BPFSP_SET_SHU9 Fld(1, 9) //[9:9] + #define BYPASS_FSPOP_BPFSP_OPT Fld(1, 16) //[16:16] + +#define DRAMC_REG_RKCFG (DRAMC_AO_BASE_ADDRESS + 0x0228) + #define RKCFG_MRS2RK Fld(1, 10) //[10:10] + #define RKCFG_CKE2RANK Fld(1, 12) //[12:12] + +#define DRAMC_REG_SLP4_TESTMODE (DRAMC_AO_BASE_ADDRESS + 0x022C) + #define SLP4_TESTMODE_CA0_TEST Fld(4, 0) //[3:0] + #define SLP4_TESTMODE_CA1_TEST Fld(4, 4) //[7:4] + #define SLP4_TESTMODE_CA2_TEST Fld(4, 8) //[11:8] + #define SLP4_TESTMODE_CA3_TEST Fld(4, 12) //[15:12] + #define SLP4_TESTMODE_CA4_TEST Fld(4, 16) //[19:16] + #define SLP4_TESTMODE_CA5_TEST Fld(4, 20) //[23:20] + +#define DRAMC_REG_DQ_MUX_SET0 (DRAMC_AO_BASE_ADDRESS + 0x0230) + #define DQ_MUX_SET0_SRF_ENTER_MASK_OPT Fld(1, 30) //[30:30] + #define DQ_MUX_SET0_DQ4BMUX Fld(1, 31) //[31:31] + +#define DRAMC_REG_DBIWR_PROTECT (DRAMC_AO_BASE_ADDRESS + 0x0234) + #define DBIWR_PROTECT_DBIWR_IMP_EN Fld(1, 0) //[0:0] + #define DBIWR_PROTECT_DBIWR_PINMUX_EN Fld(1, 1) //[1:1] + #define DBIWR_PROTECT_DBIWR_OPT_B0 Fld(8, 16) //[23:16] + #define DBIWR_PROTECT_DBIWR_OPT_B1 Fld(8, 24) //[31:24] + +#define DRAMC_REG_TX_SET0 (DRAMC_AO_BASE_ADDRESS + 0x0238) + #define TX_SET0_TXRANK Fld(2, 0) //[1:0] + #define TX_SET0_TXRANKFIX Fld(1, 2) //[2:2] + #define TX_SET0_DDRPHY_COMB_CG_SEL Fld(1, 3) //[3:3] + #define TX_SET0_TX_DQM_DEFAULT Fld(1, 4) //[4:4] + #define TX_SET0_DQBUS_X32 Fld(1, 5) //[5:5] + #define TX_SET0_OE_DOWNGRADE Fld(1, 6) //[6:6] + #define TX_SET0_DQ16COM1 Fld(1, 21) //[21:21] + #define TX_SET0_WPRE2T Fld(1, 22) //[22:22] + #define TX_SET0_DRSCLR_EN Fld(1, 24) //[24:24] + #define TX_SET0_DRSCLR_RK0_EN Fld(1, 25) //[25:25] + #define TX_SET0_ARPI_CAL_E2OPT Fld(1, 26) //[26:26] + #define TX_SET0_TX_DLY_CAL_E2OPT Fld(1, 27) //[27:27] + #define TX_SET0_DQS_OE_OP1_DIS Fld(1, 28) //[28:28] + #define TX_SET0_DQS_OE_OP2_EN Fld(1, 29) //[29:29] + #define TX_SET0_RK_SCINPUT_OPT Fld(1, 30) //[30:30] + #define TX_SET0_DRAMOEN Fld(1, 31) //[31:31] + +#define DRAMC_REG_TX_CG_SET0 (DRAMC_AO_BASE_ADDRESS + 0x023C) + #define TX_CG_SET0_SELPH_4LCG_DIS Fld(1, 0) //[0:0] + #define TX_CG_SET0_SELPH_CG_DIS Fld(1, 1) //[1:1] + #define TX_CG_SET0_DWCLKRUN Fld(1, 2) //[2:2] + #define TX_CG_SET0_WDATA_CG_DIS Fld(1, 3) //[3:3] + #define TX_CG_SET0_TX_ATK_CLKRUN Fld(1, 4) //[4:4] + #define TX_CG_SET0_PSEL_OPT3 Fld(1, 22) //[22:22] + #define TX_CG_SET0_PSEL_OPT2 Fld(1, 23) //[23:23] + #define TX_CG_SET0_PSEL_OPT1 Fld(1, 24) //[24:24] + #define TX_CG_SET0_PSEL_CNT Fld(6, 25) //[30:25] + #define TX_CG_SET0_PSELAR Fld(1, 31) //[31:31] + +#define DRAMC_REG_RX_SET0 (DRAMC_AO_BASE_ADDRESS + 0x0240) + #define RX_SET0_RDATRST Fld(1, 0) //[0:0] + #define RX_SET0_PRE_DLE_VLD_OPT Fld(1, 1) //[1:1] + #define RX_SET0_DATLAT_PDLE_TH Fld(3, 2) //[4:2] + #define RX_SET0_RANKRDY_OPT Fld(1, 5) //[5:5] + #define RX_SET0_SMRR_UPD_OLD Fld(1, 6) //[6:6] + #define RX_SET0_EBG_DLE_SKIP_SPEC_RID Fld(1, 29) //[29:29] + #define RX_SET0_DM32BIT_RDSEL_OPT Fld(1, 30) //[30:30] + #define RX_SET0_DM4TO1MODE Fld(1, 31) //[31:31] + +#define DRAMC_REG_RX_CG_SET0 (DRAMC_AO_BASE_ADDRESS + 0x0244) + #define RX_CG_SET0_RDPERIODON Fld(1, 29) //[29:29] + #define RX_CG_SET0_RDATCKAR Fld(1, 30) //[30:30] + #define RX_CG_SET0_RDYCKAR Fld(1, 31) //[31:31] + +#define DRAMC_REG_DQSOSCR (DRAMC_AO_BASE_ADDRESS + 0x0248) + #define DQSOSCR_DQSOSC_INTEN Fld(1, 0) //[0:0] + #define DQSOSCR_DQSOSC2RK Fld(1, 1) //[1:1] + #define DQSOSCR_TXUPD_BLOCK_SEL Fld(2, 2) //[3:2] + #define DQSOSCR_TXUPD_BLOCK_OPT Fld(1, 4) //[4:4] + #define DQSOSCR_TXUPDMODE Fld(1, 5) //[5:5] + #define DQSOSCR_MANUTXUPD Fld(1, 6) //[6:6] + #define DQSOSCR_ARUIDQ_SW Fld(1, 7) //[7:7] + #define DQSOSCR_DQS2DQ_UPD_BLOCK_CNT Fld(5, 8) //[12:8] + #define DQSOSCR_TDQS2DQ_UPD_BLOCKING Fld(1, 13) //[13:13] + #define DQSOSCR_DQS2DQ_UPD_MON_OPT Fld(1, 14) //[14:14] + #define DQSOSCR_DQS2DQ_UPD_MON_CNT_SEL Fld(2, 15) //[16:15] + #define DQSOSCR_TXUPD_IDLE_SEL Fld(2, 17) //[18:17] + #define DQSOSCR_TXUPD_ABREF_SEL Fld(2, 19) //[20:19] + #define DQSOSCR_TXUPD_IDLE_OPT Fld(1, 21) //[21:21] + #define DQSOSCR_DQS2DQ_SHU_HW_CAL_DIS Fld(1, 22) //[22:22] + #define DQSOSCR_SREF_TXUI_RELOAD_OPT Fld(1, 23) //[23:23] + #define DQSOSCR_DQSOSCRDIS Fld(1, 24) //[24:24] + #define DQSOSCR_DQS2DQ_WARN_OPT Fld(1, 25) //[25:25] + #define DQSOSCR_R_DMDQS2DQ_FILT_OPT Fld(1, 26) //[26:26] + #define DQSOSCR_SREF_TXPI_RELOAD_OPT Fld(1, 27) //[27:27] + #define DQSOSCR_EMPTY_WRITE_OPT Fld(1, 28) //[28:28] + #define DQSOSCR_TXUPD_ABREF_OPT Fld(1, 29) //[29:29] + #define DQSOSCR_DQSOSCLOPAD Fld(1, 30) //[30:30] + #define DQSOSCR_DQSOSC_CALEN Fld(1, 31) //[31:31] + +#define DRAMC_REG_DRAMCTRL (DRAMC_AO_BASE_ADDRESS + 0x024C) + #define DRAMCTRL_CTOREQ_HPRI_OPT Fld(1, 0) //[0:0] + #define DRAMCTRL_MATAB_LP5_MODE Fld(1, 1) //[1:1] + #define DRAMCTRL_ADRDECEN Fld(1, 2) //[2:2] + #define DRAMCTRL_ADRBIT3DEC Fld(1, 3) //[3:3] + #define DRAMCTRL_ADRDEN_1TO4_OPT Fld(1, 5) //[5:5] + #define DRAMCTRL_ALL_BLOCK_CTO_ALE_DBG_EN Fld(1, 8) //[8:8] + #define DRAMCTRL_SELFREF_BLOCK_CTO_ALE_DBG_EN Fld(1, 9) //[9:9] + #define DRAMCTRL_DVFS_BLOCK_CTO_ALE_DBG_EN Fld(1, 10) //[10:10] + #define DRAMCTRL_AG0MWR Fld(1, 12) //[12:12] + #define DRAMCTRL_DYNMWREN Fld(1, 13) //[13:13] + #define DRAMCTRL_ALEBLOCK Fld(1, 14) //[14:14] + #define DRAMCTRL_PREALL_OPTION Fld(1, 19) //[19:19] + #define DRAMCTRL_REQQUE_DEPTH_UPD Fld(1, 25) //[25:25] + #define DRAMCTRL_REQQUE_THD_EN Fld(1, 26) //[26:26] + #define DRAMCTRL_REQQUE_MAXCNT_CHG Fld(1, 27) //[27:27] + #define DRAMCTRL_PREA_RK Fld(2, 28) //[29:28] + #define DRAMCTRL_SHORTQ_OPT Fld(1, 31) //[31:31] + +#define DRAMC_REG_MISCTL0 (DRAMC_AO_BASE_ADDRESS + 0x0250) + #define MISCTL0_REFP_ARBMASK_PBR2PBR_ENA Fld(1, 0) //[0:0] + #define MISCTL0_REFP_ARBMASK_PBR2PBR_PA_DIS Fld(1, 1) //[1:1] + #define MISCTL0_WDLE_DVFS_NO_FLUSH_OPT_DIS Fld(1, 4) //[4:4] + #define MISCTL0_GROUP_A_REV Fld(4, 8) //[11:8] + #define MISCTL0_PG_WAKEUP_OPT Fld(2, 14) //[15:14] + #define MISCTL0_PAGDIS Fld(1, 17) //[17:17] + #define MISCTL0_REFA_ARB_EN2 Fld(1, 19) //[19:19] + #define MISCTL0_REFA_ARB_EN_OPTION Fld(1, 21) //[21:21] + #define MISCTL0_REORDER_MASK_E1T Fld(1, 22) //[22:22] + #define MISCTL0_PBC_ARB_E1T Fld(1, 23) //[23:23] + #define MISCTL0_PBC_ARB_EN Fld(1, 24) //[24:24] + #define MISCTL0_REFA_ARB_EN Fld(1, 25) //[25:25] + #define MISCTL0_REFP_ARB_EN Fld(1, 26) //[26:26] + #define MISCTL0_EMIPREEN Fld(1, 27) //[27:27] + #define MISCTL0_REFP_ARB_EN2 Fld(1, 31) //[31:31] + +#define DRAMC_REG_PERFCTL0 (DRAMC_AO_BASE_ADDRESS + 0x0254) + #define PERFCTL0_EBG_EN Fld(1, 0) //[0:0] + #define PERFCTL0_AIDCHKEN Fld(1, 3) //[3:3] + #define PERFCTL0_RWHPRIEN Fld(1, 8) //[8:8] + #define PERFCTL0_RWLLATEN Fld(1, 9) //[9:9] + #define PERFCTL0_RWAGEEN Fld(1, 10) //[10:10] + #define PERFCTL0_EMILLATEN Fld(1, 11) //[11:11] + #define PERFCTL0_WFLUSHEN Fld(1, 14) //[14:14] + #define PERFCTL0_REORDER_MODE Fld(1, 18) //[18:18] + #define PERFCTL0_REORDEREN Fld(1, 19) //[19:19] + #define PERFCTL0_SBR_MASK_OPT Fld(1, 20) //[20:20] + #define PERFCTL0_SBR_MASK_OPT2 Fld(1, 21) //[21:21] + #define PERFCTL0_MAFIXHIGH Fld(1, 22) //[22:22] + #define PERFCTL0_RECORDER_MASK_OPT Fld(1, 24) //[24:24] + #define PERFCTL0_MDMCU_MASK_EN Fld(1, 25) //[25:25] + +#define DRAMC_REG_ARBCTL (DRAMC_AO_BASE_ADDRESS + 0x0258) + #define ARBCTL_MAXPENDCNT Fld(8, 0) //[7:0] + #define ARBCTL_RDATACNTDIS Fld(1, 8) //[8:8] + #define ARBCTL_WDATACNTDIS Fld(1, 9) //[9:9] + +#define DRAMC_REG_DATASCR (DRAMC_AO_BASE_ADDRESS + 0x025C) + #define DATASCR_WDATKEY0 Fld(1, 0) //[0:0] + #define DATASCR_WDATKEY1 Fld(1, 1) //[1:1] + #define DATASCR_WDATKEY2 Fld(1, 2) //[2:2] + #define DATASCR_WDATKEY3 Fld(1, 3) //[3:3] + #define DATASCR_WDATKEY4 Fld(1, 4) //[4:4] + #define DATASCR_WDATKEY5 Fld(1, 5) //[5:5] + #define DATASCR_WDATKEY6 Fld(1, 6) //[6:6] + #define DATASCR_WDATKEY7 Fld(1, 7) //[7:7] + #define DATASCR_WDATITLV Fld(1, 8) //[8:8] + +#define DRAMC_REG_CLKAR (DRAMC_AO_BASE_ADDRESS + 0x0260) + #define CLKAR_REQQUE_PACG_DIS Fld(15, 0) //[14:0] + #define CLKAR_SRF_CLKRUN Fld(1, 17) //[17:17] + #define CLKAR_IDLE_OPT Fld(1, 18) //[18:18] + #define CLKAR_RKSIZE Fld(3, 20) //[22:20] + #define CLKAR_DCMREF_OPT Fld(1, 24) //[24:24] + #define CLKAR_REQQUECLKRUN Fld(1, 27) //[27:27] + +#define DRAMC_REG_REFCTRL0 (DRAMC_AO_BASE_ADDRESS + 0x0264) + #define REFCTRL0_PBREF_BK_REFA_NUM Fld(3, 0) //[2:0] + #define REFCTRL0_PBREF_BK_REFA_ENA Fld(1, 3) //[3:3] + #define REFCTRL0_RFRINTCTL Fld(1, 5) //[5:5] + #define REFCTRL0_RFRINTEN Fld(1, 6) //[6:6] + #define REFCTRL0_REFOVERCNT_RST Fld(1, 7) //[7:7] + #define REFCTRL0_DMPGVLD_IG Fld(1, 8) //[8:8] + #define REFCTRL0_KEEP_PBREF_OPT Fld(1, 9) //[9:9] + #define REFCTRL0_KEEP_PBREF Fld(1, 10) //[10:10] + #define REFCTRL0_DISBYREFNUM Fld(3, 12) //[14:12] + #define REFCTRL0_PBREF_DISBYREFNUM Fld(1, 16) //[16:16] + #define REFCTRL0_PBREF_DISBYRATE Fld(1, 17) //[17:17] + #define REFCTRL0_SREF3_OPTION1 Fld(1, 19) //[19:19] + #define REFCTRL0_ADVREF_CNT Fld(4, 20) //[23:20] + #define REFCTRL0_REF_PREGATE_CNT Fld(4, 24) //[27:24] + #define REFCTRL0_REFDIS Fld(1, 29) //[29:29] + +#define DRAMC_REG_REFCTRL1 (DRAMC_AO_BASE_ADDRESS + 0x0268) + #define REFCTRL1_PB2AB_OPT Fld(1, 0) //[0:0] + #define REFCTRL1_PB2AB_OPT1 Fld(1, 1) //[1:1] + #define REFCTRL1_PBREF_DISBYMODREF Fld(1, 2) //[2:2] + #define REFCTRL1_REFPENDINGINT_OPT1 Fld(1, 3) //[3:3] + #define REFCTRL1_PRE8REF Fld(1, 4) //[4:4] + #define REFCTRL1_REF_QUE_AUTOSAVE_EN Fld(1, 5) //[5:5] + #define REFCTRL1_REFPEND_OPT1 Fld(1, 6) //[6:6] + #define REFCTRL1_REFPEND_OPT2 Fld(1, 7) //[7:7] + #define REFCTRL1_REFPB2AB_IGZQCS Fld(1, 8) //[8:8] + #define REFCTRL1_REFRATE_MON_CLR Fld(1, 11) //[11:11] + #define REFCTRL1_REF_OVERHEAD_PBR2PB_ENA Fld(1, 13) //[13:13] + #define REFCTRL1_REF_OVERHEAD_RATE_REFAL_ENA Fld(1, 14) //[14:14] + #define REFCTRL1_REF_OVERHEAD_RATE_REFPB_ENA Fld(1, 15) //[15:15] + #define REFCTRL1_REFRATE_MANUAL Fld(5, 16) //[20:16] + #define REFCTRL1_REF_OVERHEAD_SLOW_REFAL_ENA Fld(1, 24) //[24:24] + #define REFCTRL1_REF_OVERHEAD_SLOW_REFPB_ENA Fld(1, 25) //[25:25] + #define REFCTRL1_REF_OVERHEAD_ALL_REFAL_ENA Fld(1, 26) //[26:26] + #define REFCTRL1_REF_OVERHEAD_ALL_REFPB_ENA Fld(1, 27) //[27:27] + #define REFCTRL1_REFRATE_MANUAL_RATE_TRIG Fld(1, 31) //[31:31] + +#define DRAMC_REG_REF_BOUNCE1 (DRAMC_AO_BASE_ADDRESS + 0x026C) + #define REF_BOUNCE1_REFRATE_DEBOUNCE_COUNT Fld(8, 0) //[7:0] + #define REF_BOUNCE1_REFRATE_DEBOUNCE_TH Fld(5, 8) //[12:8] + #define REF_BOUNCE1_REFRATE_DEBOUNCE_OPT Fld(1, 13) //[13:13] + #define REF_BOUNCE1_REFRATE_DEBOUNCE_DIS Fld(16, 16) //[31:16] + +#define DRAMC_REG_REF_BOUNCE2 (DRAMC_AO_BASE_ADDRESS + 0x0270) + #define REF_BOUNCE2_PRE_MR4INT_TH Fld(5, 0) //[4:0] + +#define DRAMC_REG_REFPEND1 (DRAMC_AO_BASE_ADDRESS + 0x0278) + #define REFPEND1_MPENDREFCNT_TH0 Fld(4, 0) //[3:0] + #define REFPEND1_MPENDREFCNT_TH1 Fld(4, 4) //[7:4] + #define REFPEND1_MPENDREFCNT_TH2 Fld(4, 8) //[11:8] + #define REFPEND1_MPENDREFCNT_TH3 Fld(4, 12) //[15:12] + #define REFPEND1_MPENDREFCNT_TH4 Fld(4, 16) //[19:16] + #define REFPEND1_MPENDREFCNT_TH5 Fld(4, 20) //[23:20] + #define REFPEND1_MPENDREFCNT_TH6 Fld(4, 24) //[27:24] + #define REFPEND1_MPENDREFCNT_TH7 Fld(4, 28) //[31:28] + +#define DRAMC_REG_REFPEND2 (DRAMC_AO_BASE_ADDRESS + 0x027C) + #define REFPEND2_MPENDREFCNT_TH8 Fld(4, 0) //[3:0] + #define REFPEND2_MPENDREFCNT_TH9 Fld(4, 4) //[7:4] + #define REFPEND2_MPENDREFCNT_TH10 Fld(4, 8) //[11:8] + #define REFPEND2_MPENDREFCNT_TH11 Fld(4, 12) //[15:12] + #define REFPEND2_MPENDREFCNT_TH12 Fld(4, 16) //[19:16] + #define REFPEND2_MPENDREFCNT_TH13 Fld(4, 20) //[23:20] + #define REFPEND2_MPENDREFCNT_TH14 Fld(4, 24) //[27:24] + #define REFPEND2_MPENDREFCNT_TH15 Fld(4, 28) //[31:28] + +#define DRAMC_REG_REFQUE_CNT (DRAMC_AO_BASE_ADDRESS + 0x0280) + #define REFQUE_CNT_REFRESH_QUEUE_CNT_FROM_AO Fld(4, 0) //[3:0] + +#define DRAMC_REG_SCSMCTRL (DRAMC_AO_BASE_ADDRESS + 0x0284) + #define SCSMCTRL_SC_PG_UPD_OPT Fld(1, 0) //[0:0] + #define SCSMCTRL_SC_PG_MAN_DIS Fld(1, 1) //[1:1] + #define SCSMCTRL_SC_PG_OPT2_DIS Fld(1, 8) //[8:8] + #define SCSMCTRL_SC_PG_STCMD_AREF_DIS Fld(1, 9) //[9:9] + #define SCSMCTRL_SC_PG_MPRW_DIS Fld(1, 10) //[10:10] + #define SCSMCTRL_SCPRE Fld(1, 19) //[19:19] + +#define DRAMC_REG_SCSMCTRL_CG (DRAMC_AO_BASE_ADDRESS + 0x0288) + #define SCSMCTRL_CG_SCARB_SM_CGAR Fld(1, 30) //[30:30] + #define SCSMCTRL_CG_SCSM_CGAR Fld(1, 31) //[31:31] + +#define DRAMC_REG_REFCTRL2 (DRAMC_AO_BASE_ADDRESS + 0x028C) + #define REFCTRL2_MR4INT_TH Fld(5, 0) //[4:0] + #define REFCTRL2_PB2AB_THD Fld(3, 8) //[10:8] + #define REFCTRL2_REF_OVERHEAD_RATE Fld(16, 16) //[31:16] + +#define DRAMC_REG_TX_FREQ_RATIO_OLD_MODE0 (DRAMC_AO_BASE_ADDRESS + 0x0290) + #define TX_FREQ_RATIO_OLD_MODE0_FREQ_RATIO_TX_8 Fld(5, 0) //[4:0] + #define TX_FREQ_RATIO_OLD_MODE0_FREQ_RATIO_TX_9 Fld(5, 8) //[12:8] + #define TX_FREQ_RATIO_OLD_MODE0_FREQ_RATIO_TX_10 Fld(5, 16) //[20:16] + #define TX_FREQ_RATIO_OLD_MODE0_FREQ_RATIO_TX_11 Fld(5, 24) //[28:24] + #define TX_FREQ_RATIO_OLD_MODE0_SHUFFLE_LEVEL_MODE_SELECT Fld(1, 31) //[31:31] + +#define DRAMC_REG_TX_FREQ_RATIO_OLD_MODE1 (DRAMC_AO_BASE_ADDRESS + 0x0294) + #define TX_FREQ_RATIO_OLD_MODE1_FREQ_RATIO_TX_4 Fld(5, 0) //[4:0] + #define TX_FREQ_RATIO_OLD_MODE1_FREQ_RATIO_TX_5 Fld(5, 8) //[12:8] + #define TX_FREQ_RATIO_OLD_MODE1_FREQ_RATIO_TX_6 Fld(5, 16) //[20:16] + #define TX_FREQ_RATIO_OLD_MODE1_FREQ_RATIO_TX_7 Fld(5, 24) //[28:24] + +#define DRAMC_REG_TX_FREQ_RATIO_OLD_MODE2 (DRAMC_AO_BASE_ADDRESS + 0x0298) + #define TX_FREQ_RATIO_OLD_MODE2_FREQ_RATIO_TX_0 Fld(5, 0) //[4:0] + #define TX_FREQ_RATIO_OLD_MODE2_FREQ_RATIO_TX_1 Fld(5, 8) //[12:8] + #define TX_FREQ_RATIO_OLD_MODE2_FREQ_RATIO_TX_2 Fld(5, 16) //[20:16] + #define TX_FREQ_RATIO_OLD_MODE2_FREQ_RATIO_TX_3 Fld(5, 24) //[28:24] + +#define DRAMC_REG_WDT_RST (DRAMC_AO_BASE_ADDRESS + 0x029C) + #define WDT_RST_WDT_DBG_RST Fld(1, 0) //[0:0] + +#define DRAMC_REG_SEDA_LOOP_BAK_ERR_PAT_B01 (DRAMC_AO_BASE_ADDRESS + 0x02A0) + #define SEDA_LOOP_BAK_ERR_PAT_B01_SEDA_LOOP_BAK_ERR_PAT0 Fld(32, 0) //[31:0] + +#define DRAMC_REG_SEDA_LOOP_BAK_ERR_PAT_B23 (DRAMC_AO_BASE_ADDRESS + 0x02A4) + #define SEDA_LOOP_BAK_ERR_PAT_B23_SEDA_LOOP_BAK_ERR_PAT1 Fld(32, 0) //[31:0] + +#define DRAMC_REG_SEDA_LOOP_BAK_ERR_PAT_B45 (DRAMC_AO_BASE_ADDRESS + 0x02A8) + #define SEDA_LOOP_BAK_ERR_PAT_B45_SEDA_LOOP_BAK_ERR_PAT2 Fld(32, 0) //[31:0] + +#define DRAMC_REG_SEDA_LOOP_BAK_ERR_PAT_B67 (DRAMC_AO_BASE_ADDRESS + 0x02AC) + #define SEDA_LOOP_BAK_ERR_PAT_B67_SEDA_LOOP_BAK_ERR_PAT3 Fld(32, 0) //[31:0] + +#define DRAMC_REG_SEDA_LOOP_BAK_SET (DRAMC_AO_BASE_ADDRESS + 0x02B0) + #define SEDA_LOOP_BAK_SET_WPRE0T Fld(1, 0) //[0:0] + #define SEDA_LOOP_BAK_SET_DRAMC_LOOP_BAK_EN Fld(1, 1) //[1:1] + #define SEDA_LOOP_BAK_SET_DRAMC_LOOP_BAK_CMP_EN Fld(1, 2) //[2:2] + #define SEDA_LOOP_BAK_SET_LOOP_BAK_WDAT_SEL Fld(3, 4) //[6:4] + +#define DRAMC_REG_DBG_CMDDEC_CMDSEL0 (DRAMC_AO_BASE_ADDRESS + 0x02C0) + #define DBG_CMDDEC_CMDSEL0_RANK0_10GBEN Fld(1, 0) //[0:0] + #define DBG_CMDDEC_CMDSEL0_RANK1_10GBEN Fld(1, 1) //[1:1] + #define DBG_CMDDEC_CMDSEL0_DBG_CMDDEC_CMDSEL Fld(1, 4) //[4:4] + #define DBG_CMDDEC_CMDSEL0_DBG_CMDDEC_CMDTYPE Fld(16, 16) //[31:16] + +#define DRAMC_REG_DBG_CMDDEC_CMDSEL1 (DRAMC_AO_BASE_ADDRESS + 0x02C4) + #define DBG_CMDDEC_CMDSEL1_DBG_CMDDEC_CMDSEL_OP Fld(8, 0) //[7:0] + #define DBG_CMDDEC_CMDSEL1_DBG_CMDDEC_CMDSEL_MA Fld(8, 8) //[15:8] + #define DBG_CMDDEC_CMDSEL1_DBG_CMDDEC_CMDSEL_C Fld(12, 16) //[27:16] + #define DBG_CMDDEC_CMDSEL1_DBG_CMDDEC_CMDSEL_RK Fld(2, 28) //[29:28] + #define DBG_CMDDEC_CMDSEL1_DBG_CMDDEC_CMDSEL_SINGLE Fld(1, 30) //[30:30] + +#define DRAMC_REG_DBG_CMDDEC_CMDSEL2 (DRAMC_AO_BASE_ADDRESS + 0x02C8) + #define DBG_CMDDEC_CMDSEL2_DBG_CMDDEC_CMDSEL_R Fld(17, 0) //[16:0] + #define DBG_CMDDEC_CMDSEL2_DBG_CMDDEC_CMDSEL_BA Fld(3, 17) //[19:17] + #define DBG_CMDDEC_CMDSEL2_DBG_CMDDEC_CMDSEL_BL Fld(1, 20) //[20:20] + #define DBG_CMDDEC_CMDSEL2_DBG_CMDDEC_CMDSEL_AP Fld(1, 21) //[21:21] + #define DBG_CMDDEC_CMDSEL2_DBG_CMDDEC_CMDSEL_AB Fld(1, 22) //[22:22] + +#define DRAMC_REG_DBG_CMDDEC_CMDSEL3 (DRAMC_AO_BASE_ADDRESS + 0x02CC) + #define DBG_CMDDEC_CMDSEL3_DBG_CMDDEC_CMDSEL_CA0 Fld(8, 0) //[7:0] + #define DBG_CMDDEC_CMDSEL3_DBG_CMDDEC_CMDSEL_CA1 Fld(8, 8) //[15:8] + #define DBG_CMDDEC_CMDSEL3_DBG_CMDDEC_CMDSEL_CA2 Fld(8, 16) //[23:16] + #define DBG_CMDDEC_CMDSEL3_DBG_CMDDEC_CMDSEL_CA3 Fld(8, 24) //[31:24] + +#define DRAMC_REG_DBG_CMDDEC_CMDSEL4 (DRAMC_AO_BASE_ADDRESS + 0x02D0) + #define DBG_CMDDEC_CMDSEL4_DBG_CMDDEC_CMDSEL_CA4 Fld(8, 0) //[7:0] + #define DBG_CMDDEC_CMDSEL4_DBG_CMDDEC_CMDSEL_CA5 Fld(8, 8) //[15:8] + +#define DRAMC_REG_RTSWCMD_CNT (DRAMC_AO_BASE_ADDRESS + 0x02D4) + #define RTSWCMD_CNT_RTSWCMD_CNT Fld(32, 0) //[31:0] + +#define DRAMC_REG_REFCTRL3 (DRAMC_AO_BASE_ADDRESS + 0x02D8) + #define REFCTRL3_REF_DERATING_EN Fld(16, 0) //[15:0] + +#define DRAMC_REG_DRAMC_IRQ_EN (DRAMC_AO_BASE_ADDRESS + 0x02E0) + #define DRAMC_IRQ_EN_MR4INT_EN Fld(1, 0) //[0:0] + #define DRAMC_IRQ_EN_REFPENDINGINT_EN Fld(1, 1) //[1:1] + #define DRAMC_IRQ_EN_PRE_MR4INT_EN Fld(1, 2) //[2:2] + #define DRAMC_IRQ_EN_RTMRWINT_EN Fld(1, 3) //[3:3] + #define DRAMC_IRQ_EN_INT_SREF_REQ_NO_ACK_EN Fld(1, 6) //[6:6] + #define DRAMC_IRQ_EN_INT_SREF_REQ_SHORT_EN Fld(1, 7) //[7:7] + #define DRAMC_IRQ_EN_INT_SREF_REQ_DTRIG_EN Fld(1, 8) //[8:8] + #define DRAMC_IRQ_EN_RTSWCMDINT_EN Fld(1, 12) //[12:12] + #define DRAMC_IRQ_EN_TX_TRACKING_INT1_EN Fld(1, 16) //[16:16] + #define DRAMC_IRQ_EN_TX_TRACKING_INT2_EN Fld(1, 17) //[17:17] + #define DRAMC_IRQ_EN_DRAMC_IRQ_EN_RSV Fld(14, 18) //[31:18] + +#define DRAMC_REG_DRAMC_IRQ_CLEAR (DRAMC_AO_BASE_ADDRESS + 0x02E4) + #define DRAMC_IRQ_CLEAR_MR4INT_CLR Fld(1, 0) //[0:0] + #define DRAMC_IRQ_CLEAR_REFPENDINGINT_CLR Fld(1, 1) //[1:1] + #define DRAMC_IRQ_CLEAR_PRE_MR4INT_CLR Fld(1, 2) //[2:2] + #define DRAMC_IRQ_CLEAR_RTMRWINT_CLR Fld(1, 3) //[3:3] + #define DRAMC_IRQ_CLEAR_INT_SREF_REQ_NO_ACK_CLR Fld(1, 6) //[6:6] + #define DRAMC_IRQ_CLEAR_INT_SREF_REQ_SHORT_CLR Fld(1, 7) //[7:7] + #define DRAMC_IRQ_CLEAR_INT_SREF_REQ_DTRIG_CLR Fld(1, 8) //[8:8] + #define DRAMC_IRQ_CLEAR_RTSWCMDINT_CLR Fld(1, 12) //[12:12] + #define DRAMC_IRQ_CLEAR_DRAMC_IRQ_CLEAR_RSV Fld(19, 13) //[31:13] + +#define DRAMC_REG_IRQ_RSV1 (DRAMC_AO_BASE_ADDRESS + 0x02E8) + #define IRQ_RSV1_IRQ_RSV1 Fld(32, 0) //[31:0] + +#define DRAMC_REG_IRQ_RSV2 (DRAMC_AO_BASE_ADDRESS + 0x02EC) + #define IRQ_RSV2_IRQ_RSV2 Fld(32, 0) //[31:0] + +#define DRAMC_REG_REFCNT_FR_CLK1 (DRAMC_AO_BASE_ADDRESS + 0x02F0) + #define REFCNT_FR_CLK1_REFCNT_FR_CLK_1X Fld(11, 0) //[10:0] + #define REFCNT_FR_CLK1_REFCNT_FR_CLK_2X Fld(11, 16) //[26:16] + +#define DRAMC_REG_REFCNT_FR_CLK2 (DRAMC_AO_BASE_ADDRESS + 0x02F4) + #define REFCNT_FR_CLK2_REFCNT_FR_CLK_4X Fld(11, 0) //[10:0] + #define REFCNT_FR_CLK2_REFCNT_FR_CLK_8X Fld(11, 16) //[26:16] + +#define DRAMC_REG_REFCNT_FR_CLK3 (DRAMC_AO_BASE_ADDRESS + 0x02F8) + #define REFCNT_FR_CLK3_REFCNT_FR_CLK_0P25X Fld(11, 0) //[10:0] + #define REFCNT_FR_CLK3_REFCNT_FR_CLK_0P5X Fld(11, 16) //[26:16] + +#define DRAMC_REG_REFCNT_FR_CLK4 (DRAMC_AO_BASE_ADDRESS + 0x02FC) + #define REFCNT_FR_CLK4_REFCNT_FR_CLK_1P3X Fld(11, 0) //[10:0] + #define REFCNT_FR_CLK4_REFCNT_FR_CLK_1P7X Fld(11, 16) //[26:16] + +#define DRAMC_REG_REFCNT_FR_CLK5 (DRAMC_AO_BASE_ADDRESS + 0x0300) + #define REFCNT_FR_CLK5_REFCNT_FR_CLK_2P5X Fld(11, 0) //[10:0] + #define REFCNT_FR_CLK5_REFCNT_FR_CLK_3P3X Fld(11, 16) //[26:16] + +#define DRAMC_REG_REFCNT_FR_CLK6 (DRAMC_AO_BASE_ADDRESS + 0x0304) + #define REFCNT_FR_CLK6_REFCNT_FR_CLK_6X Fld(11, 0) //[10:0] + #define REFCNT_FR_CLK6_REFCNT_FR_CLK_0P7X Fld(11, 16) //[26:16] + +#define DRAMC_REG_REFCNT_FR_CLK7 (DRAMC_AO_BASE_ADDRESS + 0x0308) + #define REFCNT_FR_CLK7_REFCNT_FR_CLK_0P125X Fld(11, 0) //[10:0] + +#define DRAMC_REG_DCM_SUB_CTRL (DRAMC_AO_BASE_ADDRESS + 0x0310) + #define DCM_SUB_CTRL_SUBCLK_CTRL_ZQ_CAL Fld(1, 0) //[0:0] + #define DCM_SUB_CTRL_SUBCLK_CTRL_TX_TRACKING Fld(1, 1) //[1:1] + #define DCM_SUB_CTRL_SUBCLK_CTRL_TEST2 Fld(1, 2) //[2:2] + #define DCM_SUB_CTRL_SUBCLK_CTRL_SWCMD Fld(1, 3) //[3:3] + #define DCM_SUB_CTRL_SUBCLK_CTRL_SREF Fld(1, 4) //[4:4] + #define DCM_SUB_CTRL_SUBCLK_CTRL_SHUFFLE_SM Fld(1, 5) //[5:5] + #define DCM_SUB_CTRL_SUBCLK_CTRL_REF Fld(1, 6) //[6:6] + #define DCM_SUB_CTRL_SUBCLK_CTRL_PD_NEW Fld(1, 7) //[7:7] + #define DCM_SUB_CTRL_SUBCLK_CTRL_HMR4 Fld(1, 8) //[8:8] + #define DCM_SUB_CTRL_SUBCLK_CTRL_DUMMY_READ Fld(1, 9) //[9:9] + #define DCM_SUB_CTRL_SUBCLK_CTRL_DPD Fld(1, 10) //[10:10] + #define DCM_SUB_CTRL_SUBCLK_CTRL_CBT_WLEV Fld(1, 11) //[11:11] + #define DCM_SUB_CTRL_SUBCLK_CTRL_TX_AUTOK Fld(1, 12) //[12:12] + +#define DRAMC_REG_CBT_WLEV_CTRL5 (DRAMC_AO_BASE_ADDRESS + 0x0320) + #define CBT_WLEV_CTRL5_NEW_CBT_CAPATEN Fld(1, 0) //[0:0] + #define CBT_WLEV_CTRL5_NEW_CBT_CAGOLDEN_SEL Fld(3, 1) //[3:1] + #define CBT_WLEV_CTRL5_NEW_CBT_PAT_INTV Fld(8, 4) //[11:4] + #define CBT_WLEV_CTRL5_NEW_CBT_INVERT_NUM Fld(1, 12) //[12:12] + #define CBT_WLEV_CTRL5_NEW_CBT_PAT_NUM Fld(3, 13) //[15:13] + #define CBT_WLEV_CTRL5_NEW_CBT_CA_NUM Fld(4, 16) //[19:16] + #define CBT_WLEV_CTRL5_NEW_CBT_PAT_RKSEL Fld(2, 20) //[21:20] + #define CBT_WLEV_CTRL5_CBT_NEW_MODE Fld(1, 22) //[22:22] + +#define DRAMC_REG_DRAM_CLK_CTRL (DRAMC_AO_BASE_ADDRESS + 0x0330) + #define DRAM_CLK_CTRL_CLK_EN Fld(1, 0) //[0:0] + +#define DRAMC_REG_RK_TEST2_A1 (DRAMC_AO_BASE_ADDRESS + 0x0500) + #define RK_TEST2_A1_TEST2_BASE Fld(29, 3) //[31:3] + +#define DRAMC_REG_RK_DUMMY_RD_WDATA0 (DRAMC_AO_BASE_ADDRESS + 0x0504) + #define RK_DUMMY_RD_WDATA0_DMY_RD_WDATA0 Fld(32, 0) //[31:0] + +#define DRAMC_REG_RK_DUMMY_RD_WDATA1 (DRAMC_AO_BASE_ADDRESS + 0x0508) + #define RK_DUMMY_RD_WDATA1_DMY_RD_WDATA1 Fld(32, 0) //[31:0] + +#define DRAMC_REG_RK_DUMMY_RD_WDATA2 (DRAMC_AO_BASE_ADDRESS + 0x050C) + #define RK_DUMMY_RD_WDATA2_DMY_RD_WDATA2 Fld(32, 0) //[31:0] + +#define DRAMC_REG_RK_DUMMY_RD_WDATA3 (DRAMC_AO_BASE_ADDRESS + 0x0510) + #define RK_DUMMY_RD_WDATA3_DMY_RD_WDATA3 Fld(32, 0) //[31:0] + +#define DRAMC_REG_RK_DUMMY_RD_ADR (DRAMC_AO_BASE_ADDRESS + 0x0514) + #define RK_DUMMY_RD_ADR_DMY_RD_COL_ADR Fld(11, 17) //[27:17] + #define RK_DUMMY_RD_ADR_DMY_RD_LEN Fld(4, 28) //[31:28] + +#define DRAMC_REG_RK_DUMMY_RD_ADR2 (DRAMC_AO_BASE_ADDRESS + 0x0554) + #define RK_DUMMY_RD_ADR2_DMY_RD_BK Fld(4, 0) //[3:0] + #define RK_DUMMY_RD_ADR2_DMY_RD_ROW_ADR Fld(18, 4) //[21:4] + +#define DRAMC_REG_RK_SREF_DPD_TCK_RK_CTRL (DRAMC_AO_BASE_ADDRESS + 0x0568) + #define RK_SREF_DPD_TCK_RK_CTRL_DPD_EN Fld(1, 29) //[29:29] + #define RK_SREF_DPD_TCK_RK_CTRL_DPDX_EN Fld(1, 30) //[30:30] + #define RK_SREF_DPD_TCK_RK_CTRL_SRF_EN Fld(1, 31) //[31:31] + +#define DRAMC_REG_RK_DQSOSC (DRAMC_AO_BASE_ADDRESS + 0x0590) + #define RK_DQSOSC_RK0_BYTE_MODE Fld(1, 29) //[29:29] + #define RK_DQSOSC_DQSOSCR_RK0EN Fld(1, 30) //[30:30] + #define RK_DQSOSC_DQSOSC_RK0INTCLR Fld(1, 31) //[31:31] + +#define DRAMC_REG_WDT_DBG_SIGNAL (DRAMC_AO_BASE_ADDRESS + 0x0D00) + #define WDT_DBG_SIGNAL_LATCH_RD_TEST_DM_CMP_CPT2_RK0_FROM_AO Fld(1, 0) //[0:0] + #define WDT_DBG_SIGNAL_LATCH_RD_TEST_DM_CMP_CPT2_RK1_FROM_AO Fld(1, 1) //[1:1] + #define WDT_DBG_SIGNAL_LATCH_RD_TEST_DM_CMP_ERR2_RK0_FROM_AO Fld(1, 2) //[2:2] + #define WDT_DBG_SIGNAL_LATCH_RD_TEST_DM_CMP_ERR2_RK1_FROM_AO Fld(1, 3) //[3:3] + #define WDT_DBG_SIGNAL_LATCH_RD_TEST_DLE_CNT_OK2_RK0_FROM_AO Fld(1, 4) //[4:4] + #define WDT_DBG_SIGNAL_LATCH_RD_TEST_DLE_CNT_OK2_RK1_FROM_AO Fld(1, 5) //[5:5] + #define WDT_DBG_SIGNAL_LATCH_RDWR_TEST_DM_CMP_CPT2_RK0_FROM_AO Fld(1, 8) //[8:8] + #define WDT_DBG_SIGNAL_LATCH_RDWR_TEST_DM_CMP_CPT2_RK1_FROM_AO Fld(1, 9) //[9:9] + #define WDT_DBG_SIGNAL_LATCH_RDWR_TEST_DM_CMP_ERR2_RK0_FROM_AO Fld(1, 10) //[10:10] + #define WDT_DBG_SIGNAL_LATCH_RDWR_TEST_DM_CMP_ERR2_RK1_FROM_AO Fld(1, 11) //[11:11] + #define WDT_DBG_SIGNAL_LATCH_RDWR_TEST_DLE_CNT_OK2_RK0_FROM_AO Fld(1, 12) //[12:12] + #define WDT_DBG_SIGNAL_LATCH_RDWR_TEST_DLE_CNT_OK2_RK1_FROM_AO Fld(1, 13) //[13:13] + #define WDT_DBG_SIGNAL_LATCH_DRAMC_GATING_ERROR_FROM_AO Fld(1, 14) //[14:14] + +#define DRAMC_REG_SELFREF_HWSAVE_FLAG (DRAMC_AO_BASE_ADDRESS + 0x0D08) + #define SELFREF_HWSAVE_FLAG_SELFREF_HWSAVE_FLAG_FROM_AO Fld(1, 0) //[0:0] + +#define DRAMC_REG_DRAMC_IRQ_STATUS1 (DRAMC_AO_BASE_ADDRESS + 0x0F00) + #define DRAMC_IRQ_STATUS1_DRAMC_IRQ_STATUS1_X0 Fld(32, 0) //[31:0] + +#define DRAMC_REG_DRAMC_IRQ_STATUS2 (DRAMC_AO_BASE_ADDRESS + 0x0F04) + #define DRAMC_IRQ_STATUS2_DRAMC_IRQ_STATUS2_X0 Fld(32, 0) //[31:0] + +#define DRAMC_REG_DRAMC_IRQ_INFO1 (DRAMC_AO_BASE_ADDRESS + 0x0F10) + #define DRAMC_IRQ_INFO1_REFRESH_RATE_FOR_INT_X0 Fld(5, 0) //[4:0] + #define DRAMC_IRQ_INFO1_REFRESH_QUEUE_CNT_FOR_INT_X0 Fld(4, 8) //[11:8] + #define DRAMC_IRQ_INFO1_REFRESH_RATE_CHG_QUEUE_CNT_FOR_INT_X0 Fld(4, 12) //[15:12] + +#define DRAMC_REG_DRAMC_IRQ_INFO1A (DRAMC_AO_BASE_ADDRESS + 0x0F14) + #define DRAMC_IRQ_INFO1A_PRE_REFRESH_RATE_RK0_FOR_INT_X0 Fld(5, 0) //[4:0] + #define DRAMC_IRQ_INFO1A_PRE_REFRESH_RATE_RK1_FOR_INT_X0 Fld(5, 8) //[12:8] + #define DRAMC_IRQ_INFO1A_PRE_REFRESH_RATE_RK0_B1_FOR_INT_X0 Fld(5, 16) //[20:16] + #define DRAMC_IRQ_INFO1A_PRE_REFRESH_RATE_RK1_B1_FOR_INT_X0 Fld(5, 24) //[28:24] + +#define DRAMC_REG_DRAMC_IRQ_INFO2 (DRAMC_AO_BASE_ADDRESS + 0x0F20) + #define DRAMC_IRQ_INFO2_RK0_MR18_INT1_X0 Fld(16, 0) //[15:0] + #define DRAMC_IRQ_INFO2_RK0_MR19_INT1_X0 Fld(16, 16) //[31:16] + +#define DRAMC_REG_DRAMC_IRQ_INFO3 (DRAMC_AO_BASE_ADDRESS + 0x0F24) + #define DRAMC_IRQ_INFO3_RK1_MR18_INT1_X0 Fld(16, 0) //[15:0] + #define DRAMC_IRQ_INFO3_RK1_MR19_INT1_X0 Fld(16, 16) //[31:16] + +#define DRAMC_REG_DRAMC_IRQ_INFO4 (DRAMC_AO_BASE_ADDRESS + 0x0F28) + #define DRAMC_IRQ_INFO4_RK0_MR18_INT2_X0 Fld(16, 0) //[15:0] + #define DRAMC_IRQ_INFO4_RK0_MR19_INT2_X0 Fld(16, 16) //[31:16] + +#define DRAMC_REG_DRAMC_IRQ_INFO5 (DRAMC_AO_BASE_ADDRESS + 0x0F2C) + #define DRAMC_IRQ_INFO5_RK1_MR18_INT2_X0 Fld(16, 0) //[15:0] + #define DRAMC_IRQ_INFO5_RK1_MR19_INT2_X0 Fld(16, 16) //[31:16] + +#define DRAMC_REG_SHURK_SELPH_DQ0 (DRAMC_AO_BASE_ADDRESS + 0x1200) + #define SHURK_SELPH_DQ0_TXDLY_DQ0 Fld(3, 0) //[2:0] + #define SHURK_SELPH_DQ0_TXDLY_DQ1 Fld(3, 4) //[6:4] + #define SHURK_SELPH_DQ0_TXDLY_DQ2 Fld(3, 8) //[10:8] + #define SHURK_SELPH_DQ0_TXDLY_DQ3 Fld(3, 12) //[14:12] + #define SHURK_SELPH_DQ0_TXDLY_OEN_DQ0 Fld(3, 16) //[18:16] + #define SHURK_SELPH_DQ0_TXDLY_OEN_DQ1 Fld(3, 20) //[22:20] + #define SHURK_SELPH_DQ0_TXDLY_OEN_DQ2 Fld(3, 24) //[26:24] + #define SHURK_SELPH_DQ0_TXDLY_OEN_DQ3 Fld(3, 28) //[30:28] + +#define DRAMC_REG_SHURK_SELPH_DQ1 (DRAMC_AO_BASE_ADDRESS + 0x1204) + #define SHURK_SELPH_DQ1_TXDLY_DQM0 Fld(3, 0) //[2:0] + #define SHURK_SELPH_DQ1_TXDLY_DQM1 Fld(3, 4) //[6:4] + #define SHURK_SELPH_DQ1_TXDLY_DQM2 Fld(3, 8) //[10:8] + #define SHURK_SELPH_DQ1_TXDLY_DQM3 Fld(3, 12) //[14:12] + #define SHURK_SELPH_DQ1_TXDLY_OEN_DQM0 Fld(3, 16) //[18:16] + #define SHURK_SELPH_DQ1_TXDLY_OEN_DQM1 Fld(3, 20) //[22:20] + #define SHURK_SELPH_DQ1_TXDLY_OEN_DQM2 Fld(3, 24) //[26:24] + #define SHURK_SELPH_DQ1_TXDLY_OEN_DQM3 Fld(3, 28) //[30:28] + +#define DRAMC_REG_SHURK_SELPH_DQ2 (DRAMC_AO_BASE_ADDRESS + 0x1208) + #define SHURK_SELPH_DQ2_DLY_DQ0 Fld(4, 0) //[3:0] + #define SHURK_SELPH_DQ2_DLY_DQ1 Fld(4, 4) //[7:4] + #define SHURK_SELPH_DQ2_DLY_DQ2 Fld(4, 8) //[11:8] + #define SHURK_SELPH_DQ2_DLY_DQ3 Fld(4, 12) //[15:12] + #define SHURK_SELPH_DQ2_DLY_OEN_DQ0 Fld(4, 16) //[19:16] + #define SHURK_SELPH_DQ2_DLY_OEN_DQ1 Fld(4, 20) //[23:20] + #define SHURK_SELPH_DQ2_DLY_OEN_DQ2 Fld(4, 24) //[27:24] + #define SHURK_SELPH_DQ2_DLY_OEN_DQ3 Fld(4, 28) //[31:28] + +#define DRAMC_REG_SHURK_SELPH_DQ3 (DRAMC_AO_BASE_ADDRESS + 0x120C) + #define SHURK_SELPH_DQ3_DLY_DQM0 Fld(4, 0) //[3:0] + #define SHURK_SELPH_DQ3_DLY_DQM1 Fld(4, 4) //[7:4] + #define SHURK_SELPH_DQ3_DLY_DQM2 Fld(4, 8) //[11:8] + #define SHURK_SELPH_DQ3_DLY_DQM3 Fld(4, 12) //[15:12] + #define SHURK_SELPH_DQ3_DLY_OEN_DQM0 Fld(4, 16) //[19:16] + #define SHURK_SELPH_DQ3_DLY_OEN_DQM1 Fld(4, 20) //[23:20] + #define SHURK_SELPH_DQ3_DLY_OEN_DQM2 Fld(4, 24) //[27:24] + #define SHURK_SELPH_DQ3_DLY_OEN_DQM3 Fld(4, 28) //[31:28] + +#define DRAMC_REG_SHURK_DQS2DQ_CAL1 (DRAMC_AO_BASE_ADDRESS + 0x1210) + #define SHURK_DQS2DQ_CAL1_BOOT_ORIG_UI_RK0_DQ0 Fld(11, 0) //[10:0] + #define SHURK_DQS2DQ_CAL1_BOOT_ORIG_UI_RK0_DQ1 Fld(11, 16) //[26:16] + +#define DRAMC_REG_SHURK_DQS2DQ_CAL2 (DRAMC_AO_BASE_ADDRESS + 0x1214) + #define SHURK_DQS2DQ_CAL2_BOOT_TARG_UI_RK0_DQ0 Fld(11, 0) //[10:0] + #define SHURK_DQS2DQ_CAL2_BOOT_TARG_UI_RK0_DQ1 Fld(11, 16) //[26:16] + +#define DRAMC_REG_SHURK_DQS2DQ_CAL3 (DRAMC_AO_BASE_ADDRESS + 0x1218) + #define SHURK_DQS2DQ_CAL3_BOOT_TARG_UI_RK0_OEN_DQ0 Fld(6, 0) //[5:0] + #define SHURK_DQS2DQ_CAL3_BOOT_TARG_UI_RK0_OEN_DQ1 Fld(6, 6) //[11:6] + #define SHURK_DQS2DQ_CAL3_BOOT_TARG_UI_RK0_OEN_DQ0_B4TO0 Fld(5, 12) //[16:12] + #define SHURK_DQS2DQ_CAL3_BOOT_TARG_UI_RK0_OEN_DQ1_B4TO0 Fld(5, 17) //[21:17] + +#define DRAMC_REG_SHURK_DQS2DQ_CAL4 (DRAMC_AO_BASE_ADDRESS + 0x121C) + #define SHURK_DQS2DQ_CAL4_BOOT_TARG_UI_RK0_OEN_DQM0 Fld(6, 0) //[5:0] + #define SHURK_DQS2DQ_CAL4_BOOT_TARG_UI_RK0_OEN_DQM1 Fld(6, 6) //[11:6] + #define SHURK_DQS2DQ_CAL4_BOOT_TARG_UI_RK0_OEN_DQM0_B4TO0 Fld(5, 12) //[16:12] + #define SHURK_DQS2DQ_CAL4_BOOT_TARG_UI_RK0_OEN_DQM1_B4TO0 Fld(5, 17) //[21:17] + +#define DRAMC_REG_SHURK_DQS2DQ_CAL5 (DRAMC_AO_BASE_ADDRESS + 0x1220) + #define SHURK_DQS2DQ_CAL5_BOOT_TARG_UI_RK0_DQM0 Fld(11, 0) //[10:0] + #define SHURK_DQS2DQ_CAL5_BOOT_TARG_UI_RK0_DQM1 Fld(11, 16) //[26:16] + +#define DRAMC_REG_SHURK_PI (DRAMC_AO_BASE_ADDRESS + 0x1224) + #define SHURK_PI_RK0_ARPI_DQ_B1 Fld(6, 0) //[5:0] + #define SHURK_PI_RK0_ARPI_DQ_B0 Fld(6, 8) //[13:8] + #define SHURK_PI_RK0_ARPI_DQM_B1 Fld(6, 16) //[21:16] + #define SHURK_PI_RK0_ARPI_DQM_B0 Fld(6, 24) //[29:24] + +#define DRAMC_REG_SHURK_DQSOSC (DRAMC_AO_BASE_ADDRESS + 0x1228) + #define SHURK_DQSOSC_DQSOSC_BASE_RK0 Fld(16, 0) //[15:0] + #define SHURK_DQSOSC_DQSOSC_BASE_RK0_B1 Fld(16, 16) //[31:16] + +#define DRAMC_REG_SHURK_DQSOSC_THRD (DRAMC_AO_BASE_ADDRESS + 0x122C) + #define SHURK_DQSOSC_THRD_DQSOSCTHRD_INC Fld(12, 0) //[11:0] + #define SHURK_DQSOSC_THRD_DQSOSCTHRD_DEC Fld(12, 16) //[27:16] + +#define DRAMC_REG_SHURK_APHY_TX_PICG_CTRL (DRAMC_AO_BASE_ADDRESS + 0x1230) + #define SHURK_APHY_TX_PICG_CTRL_DDRPHY_CLK_EN_COMB_TX_DQ_RK_SEL_P1 Fld(3, 0) //[2:0] + #define SHURK_APHY_TX_PICG_CTRL_DDRPHY_CLK_EN_COMB_TX_DQ_RK_SEL_P0 Fld(3, 4) //[6:4] + +#define DRAMC_REG_SHURK_WCK_WR_MCK (DRAMC_AO_BASE_ADDRESS + 0x1240) + #define SHURK_WCK_WR_MCK_WCK_WR_B0_MCK Fld(4, 0) //[3:0] + #define SHURK_WCK_WR_MCK_WCK_WR_B1_MCK Fld(4, 4) //[7:4] + +#define DRAMC_REG_SHURK_WCK_RD_MCK (DRAMC_AO_BASE_ADDRESS + 0x1244) + #define SHURK_WCK_RD_MCK_WCK_RD_B0_MCK Fld(4, 0) //[3:0] + #define SHURK_WCK_RD_MCK_WCK_RD_B1_MCK Fld(4, 4) //[7:4] + +#define DRAMC_REG_SHURK_WCK_FS_MCK (DRAMC_AO_BASE_ADDRESS + 0x1248) + #define SHURK_WCK_FS_MCK_WCK_FS_B0_MCK Fld(4, 0) //[3:0] + #define SHURK_WCK_FS_MCK_WCK_FS_B1_MCK Fld(4, 4) //[7:4] + +#define DRAMC_REG_SHURK_WCK_WR_UI (DRAMC_AO_BASE_ADDRESS + 0x124C) + #define SHURK_WCK_WR_UI_WCK_WR_B0_UI Fld(4, 0) //[3:0] + #define SHURK_WCK_WR_UI_WCK_WR_B1_UI Fld(4, 4) //[7:4] + +#define DRAMC_REG_SHURK_WCK_RD_UI (DRAMC_AO_BASE_ADDRESS + 0x1250) + #define SHURK_WCK_RD_UI_WCK_RD_B0_UI Fld(4, 0) //[3:0] + #define SHURK_WCK_RD_UI_WCK_RD_B1_UI Fld(4, 4) //[7:4] + +#define DRAMC_REG_SHURK_WCK_FS_UI (DRAMC_AO_BASE_ADDRESS + 0x1254) + #define SHURK_WCK_FS_UI_WCK_FS_B0_UI Fld(4, 0) //[3:0] + #define SHURK_WCK_FS_UI_WCK_FS_B1_UI Fld(4, 4) //[7:4] + +#define DRAMC_REG_SHURK_CKE_CTRL (DRAMC_AO_BASE_ADDRESS + 0x1260) + #define SHURK_CKE_CTRL_CKE_DBE_CNT Fld(4, 0) //[3:0] + +#define DRAMC_REG_SHU_MATYPE (DRAMC_AO_BASE_ADDRESS + 0x1600) + #define SHU_MATYPE_MATYPE Fld(2, 0) //[1:0] + #define SHU_MATYPE_NORMPOP_LEN Fld(3, 4) //[6:4] + +#define DRAMC_REG_SHU_COMMON0 (DRAMC_AO_BASE_ADDRESS + 0x1604) + #define SHU_COMMON0_FREQDIV4 Fld(1, 0) //[0:0] + #define SHU_COMMON0_FDIV2 Fld(1, 1) //[1:1] + #define SHU_COMMON0_FREQDIV8 Fld(1, 2) //[2:2] + #define SHU_COMMON0_DM64BITEN Fld(1, 4) //[4:4] + #define SHU_COMMON0_DLE256EN Fld(1, 5) //[5:5] + #define SHU_COMMON0_LP5BGEN Fld(1, 6) //[6:6] + #define SHU_COMMON0_LP5WCKON Fld(1, 7) //[7:7] + #define SHU_COMMON0_CL2 Fld(1, 8) //[8:8] + #define SHU_COMMON0_BL2 Fld(1, 9) //[9:9] + #define SHU_COMMON0_BL4 Fld(1, 10) //[10:10] + #define SHU_COMMON0_LP5BGOTF Fld(1, 11) //[11:11] + #define SHU_COMMON0_BC4OTF Fld(1, 12) //[12:12] + #define SHU_COMMON0_LP5HEFF_MODE Fld(1, 13) //[13:13] + #define SHU_COMMON0_LP5WRAPEN Fld(1, 14) //[14:14] + #define SHU_COMMON0_SHU_COMMON0_RSV Fld(17, 15) //[31:15] + +#define DRAMC_REG_SHU_SREF_CTRL (DRAMC_AO_BASE_ADDRESS + 0x1608) + #define SHU_SREF_CTRL_CKEHCMD Fld(2, 4) //[5:4] + #define SHU_SREF_CTRL_SREF_CK_DLY Fld(2, 28) //[29:28] + +#define DRAMC_REG_SHU_SCHEDULER (DRAMC_AO_BASE_ADDRESS + 0x160C) + #define SHU_SCHEDULER_DUALSCHEN Fld(1, 2) //[2:2] + +#define DRAMC_REG_SHU_DCM_CTRL0 (DRAMC_AO_BASE_ADDRESS + 0x1610) + #define SHU_DCM_CTRL0_DDRPHY_CLK_EN_OPT Fld(1, 7) //[7:7] + #define SHU_DCM_CTRL0_DPHY_CMD_CLKEN_EXTCNT Fld(3, 8) //[10:8] + #define SHU_DCM_CTRL0_DDRPHY_CLK_DYN_GATING_SEL Fld(4, 12) //[15:12] + #define SHU_DCM_CTRL0_APHYPI_CKCGL_CNT Fld(4, 16) //[19:16] + #define SHU_DCM_CTRL0_APHYPI_CKCGH_CNT Fld(4, 20) //[23:20] + #define SHU_DCM_CTRL0_FASTWAKE2 Fld(1, 29) //[29:29] + #define SHU_DCM_CTRL0_FASTWAKE Fld(1, 31) //[31:31] + +#define DRAMC_REG_SHU_HMR4_DVFS_CTRL0 (DRAMC_AO_BASE_ADDRESS + 0x1614) + #define SHU_HMR4_DVFS_CTRL0_FSPCHG_PRDCNT Fld(8, 8) //[15:8] + #define SHU_HMR4_DVFS_CTRL0_REFRCNT Fld(12, 16) //[27:16] + +#define DRAMC_REG_SHU_SELPH_CA1 (DRAMC_AO_BASE_ADDRESS + 0x1618) + #define SHU_SELPH_CA1_TXDLY_CS Fld(3, 0) //[2:0] + #define SHU_SELPH_CA1_TXDLY_CKE Fld(3, 4) //[6:4] + #define SHU_SELPH_CA1_TXDLY_ODT Fld(3, 8) //[10:8] + #define SHU_SELPH_CA1_TXDLY_RESET Fld(3, 12) //[14:12] + #define SHU_SELPH_CA1_TXDLY_WE Fld(3, 16) //[18:16] + #define SHU_SELPH_CA1_TXDLY_CAS Fld(3, 20) //[22:20] + #define SHU_SELPH_CA1_TXDLY_RAS Fld(3, 24) //[26:24] + #define SHU_SELPH_CA1_TXDLY_CS1 Fld(3, 28) //[30:28] + +#define DRAMC_REG_SHU_SELPH_CA2 (DRAMC_AO_BASE_ADDRESS + 0x161C) + #define SHU_SELPH_CA2_TXDLY_BA0 Fld(3, 0) //[2:0] + #define SHU_SELPH_CA2_TXDLY_BA1 Fld(3, 4) //[6:4] + #define SHU_SELPH_CA2_TXDLY_BA2 Fld(3, 8) //[10:8] + #define SHU_SELPH_CA2_TXDLY_CMD Fld(5, 16) //[20:16] + #define SHU_SELPH_CA2_TXDLY_CKE1 Fld(3, 24) //[26:24] + +#define DRAMC_REG_SHU_SELPH_CA3 (DRAMC_AO_BASE_ADDRESS + 0x1620) + #define SHU_SELPH_CA3_TXDLY_RA0 Fld(3, 0) //[2:0] + #define SHU_SELPH_CA3_TXDLY_RA1 Fld(3, 4) //[6:4] + #define SHU_SELPH_CA3_TXDLY_RA2 Fld(3, 8) //[10:8] + #define SHU_SELPH_CA3_TXDLY_RA3 Fld(3, 12) //[14:12] + #define SHU_SELPH_CA3_TXDLY_RA4 Fld(3, 16) //[18:16] + #define SHU_SELPH_CA3_TXDLY_RA5 Fld(3, 20) //[22:20] + #define SHU_SELPH_CA3_TXDLY_RA6 Fld(3, 24) //[26:24] + #define SHU_SELPH_CA3_TXDLY_RA7 Fld(3, 28) //[30:28] + +#define DRAMC_REG_SHU_SELPH_CA4 (DRAMC_AO_BASE_ADDRESS + 0x1624) + #define SHU_SELPH_CA4_TXDLY_RA8 Fld(3, 0) //[2:0] + #define SHU_SELPH_CA4_TXDLY_RA9 Fld(3, 4) //[6:4] + #define SHU_SELPH_CA4_TXDLY_RA10 Fld(3, 8) //[10:8] + #define SHU_SELPH_CA4_TXDLY_RA11 Fld(3, 12) //[14:12] + #define SHU_SELPH_CA4_TXDLY_RA12 Fld(3, 16) //[18:16] + #define SHU_SELPH_CA4_TXDLY_RA13 Fld(3, 20) //[22:20] + #define SHU_SELPH_CA4_TXDLY_RA14 Fld(3, 24) //[26:24] + #define SHU_SELPH_CA4_TXDLY_RA15 Fld(3, 28) //[30:28] + +#define DRAMC_REG_SHU_SELPH_CA5 (DRAMC_AO_BASE_ADDRESS + 0x1628) + #define SHU_SELPH_CA5_DLY_CS Fld(3, 0) //[2:0] + #define SHU_SELPH_CA5_DLY_CKE Fld(3, 4) //[6:4] + #define SHU_SELPH_CA5_DLY_ODT Fld(3, 8) //[10:8] + #define SHU_SELPH_CA5_DLY_RESET Fld(3, 12) //[14:12] + #define SHU_SELPH_CA5_DLY_WE Fld(3, 16) //[18:16] + #define SHU_SELPH_CA5_DLY_CAS Fld(3, 20) //[22:20] + #define SHU_SELPH_CA5_DLY_RAS Fld(3, 24) //[26:24] + #define SHU_SELPH_CA5_DLY_CS1 Fld(3, 28) //[30:28] + +#define DRAMC_REG_SHU_SELPH_CA6 (DRAMC_AO_BASE_ADDRESS + 0x162C) + #define SHU_SELPH_CA6_DLY_BA0 Fld(3, 0) //[2:0] + #define SHU_SELPH_CA6_DLY_BA1 Fld(3, 4) //[6:4] + #define SHU_SELPH_CA6_DLY_BA2 Fld(3, 8) //[10:8] + #define SHU_SELPH_CA6_DLY_CKE1 Fld(3, 24) //[26:24] + +#define DRAMC_REG_SHU_SELPH_CA7 (DRAMC_AO_BASE_ADDRESS + 0x1630) + #define SHU_SELPH_CA7_DLY_RA0 Fld(3, 0) //[2:0] + #define SHU_SELPH_CA7_DLY_RA1 Fld(3, 4) //[6:4] + #define SHU_SELPH_CA7_DLY_RA2 Fld(3, 8) //[10:8] + #define SHU_SELPH_CA7_DLY_RA3 Fld(3, 12) //[14:12] + #define SHU_SELPH_CA7_DLY_RA4 Fld(3, 16) //[18:16] + #define SHU_SELPH_CA7_DLY_RA5 Fld(3, 20) //[22:20] + #define SHU_SELPH_CA7_DLY_RA6 Fld(3, 24) //[26:24] + #define SHU_SELPH_CA7_DLY_RA7 Fld(3, 28) //[30:28] + +#define DRAMC_REG_SHU_SELPH_CA8 (DRAMC_AO_BASE_ADDRESS + 0x1634) + #define SHU_SELPH_CA8_DLY_RA8 Fld(3, 0) //[2:0] + #define SHU_SELPH_CA8_DLY_RA9 Fld(3, 4) //[6:4] + #define SHU_SELPH_CA8_DLY_RA10 Fld(3, 8) //[10:8] + #define SHU_SELPH_CA8_DLY_RA11 Fld(3, 12) //[14:12] + #define SHU_SELPH_CA8_DLY_RA12 Fld(3, 16) //[18:16] + #define SHU_SELPH_CA8_DLY_RA13 Fld(3, 20) //[22:20] + #define SHU_SELPH_CA8_DLY_RA14 Fld(3, 24) //[26:24] + #define SHU_SELPH_CA8_DLY_RA15 Fld(3, 28) //[30:28] + +#define DRAMC_REG_SHU_HWSET_MR2 (DRAMC_AO_BASE_ADDRESS + 0x1638) + #define SHU_HWSET_MR2_HWSET_MR2_MRSMA Fld(13, 0) //[12:0] + #define SHU_HWSET_MR2_HWSET_MR2_OP Fld(8, 16) //[23:16] + +#define DRAMC_REG_SHU_HWSET_MR13 (DRAMC_AO_BASE_ADDRESS + 0x163C) + #define SHU_HWSET_MR13_HWSET_MR13_MRSMA Fld(13, 0) //[12:0] + #define SHU_HWSET_MR13_HWSET_MR13_OP Fld(8, 16) //[23:16] + +#define DRAMC_REG_SHU_HWSET_VRCG (DRAMC_AO_BASE_ADDRESS + 0x1640) + #define SHU_HWSET_VRCG_HWSET_VRCG_MRSMA Fld(13, 0) //[12:0] + #define SHU_HWSET_VRCG_HWSET_VRCG_OP Fld(8, 16) //[23:16] + #define SHU_HWSET_VRCG_VRCGDIS_PRDCNT Fld(8, 24) //[31:24] + +#define DRAMC_REG_SHU_ACTIM0 (DRAMC_AO_BASE_ADDRESS + 0x1644) + #define SHU_ACTIM0_TWTR Fld(6, 0) //[5:0] + #define SHU_ACTIM0_TWR Fld(8, 8) //[15:8] + #define SHU_ACTIM0_TRRD Fld(3, 16) //[18:16] + #define SHU_ACTIM0_TRCD Fld(4, 24) //[27:24] + #define SHU_ACTIM0_CKELCKCNT Fld(4, 28) //[31:28] + +#define DRAMC_REG_SHU_ACTIM1 (DRAMC_AO_BASE_ADDRESS + 0x1648) + #define SHU_ACTIM1_TRPAB Fld(4, 0) //[3:0] + #define SHU_ACTIM1_TMRWCKEL Fld(4, 4) //[7:4] + #define SHU_ACTIM1_TRP Fld(4, 8) //[11:8] + #define SHU_ACTIM1_TRAS Fld(6, 16) //[21:16] + #define SHU_ACTIM1_TRC Fld(5, 24) //[28:24] + +#define DRAMC_REG_SHU_ACTIM2 (DRAMC_AO_BASE_ADDRESS + 0x164C) + #define SHU_ACTIM2_TXP Fld(4, 0) //[3:0] + #define SHU_ACTIM2_TMRRI Fld(5, 4) //[8:4] + #define SHU_ACTIM2_TRTP Fld(3, 12) //[14:12] + #define SHU_ACTIM2_TR2W Fld(6, 16) //[21:16] + #define SHU_ACTIM2_TFAW Fld(5, 24) //[28:24] + +#define DRAMC_REG_SHU_ACTIM3 (DRAMC_AO_BASE_ADDRESS + 0x1650) + #define SHU_ACTIM3_TRFCPB Fld(8, 0) //[7:0] + #define SHU_ACTIM3_MANTMRR Fld(4, 8) //[11:8] + #define SHU_ACTIM3_TR2MRR Fld(4, 12) //[15:12] + #define SHU_ACTIM3_TRFC Fld(8, 16) //[23:16] + #define SHU_ACTIM3_TWTR_L Fld(6, 24) //[29:24] + +#define DRAMC_REG_SHU_ACTIM4 (DRAMC_AO_BASE_ADDRESS + 0x1654) + #define SHU_ACTIM4_TXREFCNT Fld(10, 0) //[9:0] + #define SHU_ACTIM4_TMRR2MRW Fld(6, 10) //[15:10] + #define SHU_ACTIM4_TMRR2W Fld(6, 16) //[21:16] + #define SHU_ACTIM4_TZQCS Fld(8, 24) //[31:24] + +#define DRAMC_REG_SHU_ACTIM5 (DRAMC_AO_BASE_ADDRESS + 0x1658) + #define SHU_ACTIM5_TR2PD Fld(7, 0) //[6:0] + #define SHU_ACTIM5_TWTPD Fld(7, 8) //[14:8] + #define SHU_ACTIM5_TPBR2PBR Fld(8, 16) //[23:16] + #define SHU_ACTIM5_TPBR2ACT Fld(2, 28) //[29:28] + +#define DRAMC_REG_SHU_ACTIM6 (DRAMC_AO_BASE_ADDRESS + 0x165C) + #define SHU_ACTIM6_TZQLAT2 Fld(5, 0) //[4:0] + #define SHU_ACTIM6_TMRD Fld(4, 8) //[11:8] + #define SHU_ACTIM6_TMRW Fld(4, 12) //[15:12] + #define SHU_ACTIM6_TW2MRW Fld(6, 20) //[25:20] + #define SHU_ACTIM6_TR2MRW Fld(6, 26) //[31:26] + +#define DRAMC_REG_SHU_ACTIM_XRT (DRAMC_AO_BASE_ADDRESS + 0x1660) + #define SHU_ACTIM_XRT_XRTR2R Fld(5, 0) //[4:0] + #define SHU_ACTIM_XRT_XRTR2W Fld(6, 8) //[13:8] + #define SHU_ACTIM_XRT_XRTW2R Fld(4, 16) //[19:16] + #define SHU_ACTIM_XRT_XRTW2W Fld(5, 24) //[28:24] + +#define DRAMC_REG_SHU_AC_TIME_05T (DRAMC_AO_BASE_ADDRESS + 0x1664) + #define SHU_AC_TIME_05T_TRC_05T Fld(1, 0) //[0:0] + #define SHU_AC_TIME_05T_TRFCPB_05T Fld(1, 1) //[1:1] + #define SHU_AC_TIME_05T_TRFC_05T Fld(1, 2) //[2:2] + #define SHU_AC_TIME_05T_TPBR2PBR_05T Fld(1, 3) //[3:3] + #define SHU_AC_TIME_05T_TXP_05T Fld(1, 4) //[4:4] + #define SHU_AC_TIME_05T_TRTP_05T Fld(1, 5) //[5:5] + #define SHU_AC_TIME_05T_TRCD_05T Fld(1, 6) //[6:6] + #define SHU_AC_TIME_05T_TRP_05T Fld(1, 7) //[7:7] + #define SHU_AC_TIME_05T_TRPAB_05T Fld(1, 8) //[8:8] + #define SHU_AC_TIME_05T_TRAS_05T Fld(1, 9) //[9:9] + #define SHU_AC_TIME_05T_TWR_M05T Fld(1, 10) //[10:10] + #define SHU_AC_TIME_05T_TRRD_05T Fld(1, 12) //[12:12] + #define SHU_AC_TIME_05T_TFAW_05T Fld(1, 13) //[13:13] + #define SHU_AC_TIME_05T_TCKEPRD_05T Fld(1, 14) //[14:14] + #define SHU_AC_TIME_05T_TR2PD_05T Fld(1, 15) //[15:15] + #define SHU_AC_TIME_05T_TWTPD_M05T Fld(1, 16) //[16:16] + #define SHU_AC_TIME_05T_TMRRI_05T Fld(1, 17) //[17:17] + #define SHU_AC_TIME_05T_TMRWCKEL_05T Fld(1, 18) //[18:18] + #define SHU_AC_TIME_05T_BGTRRD_05T Fld(1, 19) //[19:19] + #define SHU_AC_TIME_05T_BGTCCD_05T Fld(1, 20) //[20:20] + #define SHU_AC_TIME_05T_BGTWTR_M05T Fld(1, 21) //[21:21] + #define SHU_AC_TIME_05T_TR2W_05T Fld(1, 22) //[22:22] + #define SHU_AC_TIME_05T_TWTR_M05T Fld(1, 23) //[23:23] + #define SHU_AC_TIME_05T_XRTR2W_05T Fld(1, 24) //[24:24] + #define SHU_AC_TIME_05T_TMRD_05T Fld(1, 25) //[25:25] + #define SHU_AC_TIME_05T_TMRW_05T Fld(1, 26) //[26:26] + #define SHU_AC_TIME_05T_TMRR2MRW_05T Fld(1, 27) //[27:27] + #define SHU_AC_TIME_05T_TW2MRW_05T Fld(1, 28) //[28:28] + #define SHU_AC_TIME_05T_TR2MRW_05T Fld(1, 29) //[29:29] + #define SHU_AC_TIME_05T_TPBR2ACT_05T Fld(1, 30) //[30:30] + #define SHU_AC_TIME_05T_XRTW2R_M05T Fld(1, 31) //[31:31] + +#define DRAMC_REG_SHU_AC_DERATING0 (DRAMC_AO_BASE_ADDRESS + 0x1668) + #define SHU_AC_DERATING0_ACDERATEEN Fld(1, 0) //[0:0] + #define SHU_AC_DERATING0_TRRD_DERATE Fld(3, 16) //[18:16] + #define SHU_AC_DERATING0_TRCD_DERATE Fld(4, 24) //[27:24] + +#define DRAMC_REG_SHU_AC_DERATING1 (DRAMC_AO_BASE_ADDRESS + 0x166C) + #define SHU_AC_DERATING1_TRPAB_DERATE Fld(4, 0) //[3:0] + #define SHU_AC_DERATING1_TRP_DERATE Fld(4, 8) //[11:8] + #define SHU_AC_DERATING1_TRAS_DERATE Fld(6, 16) //[21:16] + #define SHU_AC_DERATING1_TRC_DERATE Fld(5, 24) //[28:24] + +#define DRAMC_REG_SHU_AC_DERATING_05T (DRAMC_AO_BASE_ADDRESS + 0x1670) + #define SHU_AC_DERATING_05T_TRC_05T_DERATE Fld(1, 0) //[0:0] + #define SHU_AC_DERATING_05T_TRCD_05T_DERATE Fld(1, 6) //[6:6] + #define SHU_AC_DERATING_05T_TRP_05T_DERATE Fld(1, 7) //[7:7] + #define SHU_AC_DERATING_05T_TRPAB_05T_DERATE Fld(1, 8) //[8:8] + #define SHU_AC_DERATING_05T_TRAS_05T_DERATE Fld(1, 9) //[9:9] + #define SHU_AC_DERATING_05T_TRRD_05T_DERATE Fld(1, 12) //[12:12] + +#define DRAMC_REG_SHU_ACTIMING_CONF (DRAMC_AO_BASE_ADDRESS + 0x1674) + #define SHU_ACTIMING_CONF_SCINTV Fld(6, 0) //[5:0] + #define SHU_ACTIMING_CONF_TRFCPBIG Fld(1, 8) //[8:8] + #define SHU_ACTIMING_CONF_REFBW_FR Fld(10, 16) //[25:16] + #define SHU_ACTIMING_CONF_TREFBWIG Fld(1, 31) //[31:31] + +#define DRAMC_REG_SHU_CKECTRL (DRAMC_AO_BASE_ADDRESS + 0x1678) + #define SHU_CKECTRL_TPDE_05T Fld(1, 0) //[0:0] + #define SHU_CKECTRL_TPDX_05T Fld(1, 1) //[1:1] + #define SHU_CKECTRL_TPDE Fld(3, 12) //[14:12] + #define SHU_CKECTRL_TPDX Fld(3, 16) //[18:16] + #define SHU_CKECTRL_TCKEPRD Fld(3, 20) //[22:20] + #define SHU_CKECTRL_TCKESRX Fld(2, 24) //[25:24] + +#define DRAMC_REG_SHU_SELPH_DQS0 (DRAMC_AO_BASE_ADDRESS + 0x167C) + #define SHU_SELPH_DQS0_TXDLY_DQS0 Fld(3, 0) //[2:0] + #define SHU_SELPH_DQS0_TXDLY_DQS1 Fld(3, 4) //[6:4] + #define SHU_SELPH_DQS0_TXDLY_DQS2 Fld(3, 8) //[10:8] + #define SHU_SELPH_DQS0_TXDLY_DQS3 Fld(3, 12) //[14:12] + #define SHU_SELPH_DQS0_TXDLY_OEN_DQS0 Fld(3, 16) //[18:16] + #define SHU_SELPH_DQS0_TXDLY_OEN_DQS1 Fld(3, 20) //[22:20] + #define SHU_SELPH_DQS0_TXDLY_OEN_DQS2 Fld(3, 24) //[26:24] + #define SHU_SELPH_DQS0_TXDLY_OEN_DQS3 Fld(3, 28) //[30:28] + +#define DRAMC_REG_SHU_SELPH_DQS1 (DRAMC_AO_BASE_ADDRESS + 0x1680) + #define SHU_SELPH_DQS1_DLY_DQS0 Fld(4, 0) //[3:0] + #define SHU_SELPH_DQS1_DLY_DQS1 Fld(4, 4) //[7:4] + #define SHU_SELPH_DQS1_DLY_DQS2 Fld(4, 8) //[11:8] + #define SHU_SELPH_DQS1_DLY_DQS3 Fld(4, 12) //[15:12] + #define SHU_SELPH_DQS1_DLY_OEN_DQS0 Fld(4, 16) //[19:16] + #define SHU_SELPH_DQS1_DLY_OEN_DQS1 Fld(4, 20) //[23:20] + #define SHU_SELPH_DQS1_DLY_OEN_DQS2 Fld(4, 24) //[27:24] + #define SHU_SELPH_DQS1_DLY_OEN_DQS3 Fld(4, 28) //[31:28] + +#define DRAMC_REG_SHU_WODT (DRAMC_AO_BASE_ADDRESS + 0x1684) + #define SHU_WODT_DISWODT Fld(3, 0) //[2:0] + #define SHU_WODT_WODTFIX Fld(1, 3) //[3:3] + #define SHU_WODT_WODTFIXOFF Fld(1, 4) //[4:4] + #define SHU_WODT_DISWODTE Fld(1, 5) //[5:5] + #define SHU_WODT_DISWODTE2 Fld(1, 6) //[6:6] + #define SHU_WODT_WODTPDEN Fld(1, 7) //[7:7] + #define SHU_WODT_WOEN Fld(1, 8) //[8:8] + #define SHU_WODT_DQS2DQ_WARN_PITHRD Fld(6, 9) //[14:9] + #define SHU_WODT_TWODT Fld(7, 16) //[22:16] + +#define DRAMC_REG_SHU_TX_SET0 (DRAMC_AO_BASE_ADDRESS + 0x1688) + #define SHU_TX_SET0_DQOE_CNT Fld(4, 0) //[3:0] + #define SHU_TX_SET0_DQOE_OPT Fld(1, 4) //[4:4] + #define SHU_TX_SET0_WR_NEW_OPT Fld(1, 5) //[5:5] + #define SHU_TX_SET0_TXUPD_SEL Fld(2, 6) //[7:6] + #define SHU_TX_SET0_TXUPD_W2R_SEL Fld(3, 8) //[10:8] + #define SHU_TX_SET0_WECC_EN Fld(1, 11) //[11:11] + #define SHU_TX_SET0_DBIWR Fld(1, 12) //[12:12] + #define SHU_TX_SET0_WDATRGO Fld(1, 13) //[13:13] + #define SHU_TX_SET0_TXUPD_W2R_OPT Fld(1, 14) //[14:14] + #define SHU_TX_SET0_WPST1P5T Fld(1, 15) //[15:15] + #define SHU_TX_SET0_TXOEN_AUTOSET_OFFSET Fld(4, 16) //[19:16] + #define SHU_TX_SET0_TWCKPST Fld(2, 20) //[21:20] + #define SHU_TX_SET0_OE_EXT2UI Fld(3, 22) //[24:22] + #define SHU_TX_SET0_DQS2DQ_FILT_PITHRD Fld(6, 25) //[30:25] + #define SHU_TX_SET0_TXOEN_AUTOSET_EN Fld(1, 31) //[31:31] + +#define DRAMC_REG_SHU_RX_CG_SET0 (DRAMC_AO_BASE_ADDRESS + 0x168C) + #define SHU_RX_CG_SET0_DLE_LAST_EXTEND3 Fld(1, 0) //[0:0] + #define SHU_RX_CG_SET0_READ_START_EXTEND3 Fld(1, 1) //[1:1] + #define SHU_RX_CG_SET0_DLE_LAST_EXTEND2 Fld(1, 2) //[2:2] + #define SHU_RX_CG_SET0_READ_START_EXTEND2 Fld(1, 3) //[3:3] + #define SHU_RX_CG_SET0_DLE_LAST_EXTEND1 Fld(1, 4) //[4:4] + #define SHU_RX_CG_SET0_READ_START_EXTEND1 Fld(1, 5) //[5:5] + +#define DRAMC_REG_SHU_DQSOSC_SET0 (DRAMC_AO_BASE_ADDRESS + 0x1690) + #define SHU_DQSOSC_SET0_DQSOSCENDIS Fld(1, 0) //[0:0] + #define SHU_DQSOSC_SET0_DQSOSC_PRDCNT Fld(10, 4) //[13:4] + #define SHU_DQSOSC_SET0_DQSOSCENCNT Fld(16, 16) //[31:16] + +#define DRAMC_REG_SHU_DQSOSCR (DRAMC_AO_BASE_ADDRESS + 0x1694) + #define SHU_DQSOSCR_DQSOSCRCNT Fld(8, 0) //[7:0] + #define SHU_DQSOSCR_DQSOSC_ADV_SEL Fld(2, 8) //[9:8] + #define SHU_DQSOSCR_DQSOSC_DRS_ADV_SEL Fld(2, 10) //[11:10] + #define SHU_DQSOSCR_TX_SW_FORCE_UPD_SEL Fld(3, 12) //[14:12] + #define SHU_DQSOSCR_DQSOSC_DELTA Fld(16, 16) //[31:16] + +#define DRAMC_REG_SHU_TX_RANKCTL (DRAMC_AO_BASE_ADDRESS + 0x1698) + #define SHU_TX_RANKCTL_TXRANKINCTL_TXDLY Fld(4, 0) //[3:0] + #define SHU_TX_RANKCTL_TXRANKINCTL Fld(4, 4) //[7:4] + #define SHU_TX_RANKCTL_TXRANKINCTL_ROOT Fld(4, 8) //[11:8] + +#define DRAMC_REG_SHU_ZQ_SET0 (DRAMC_AO_BASE_ADDRESS + 0x169C) + #define SHU_ZQ_SET0_ZQCSCNT Fld(16, 0) //[15:0] + #define SHU_ZQ_SET0_TZQLAT Fld(5, 27) //[31:27] + +#define DRAMC_REG_SHU_CONF0 (DRAMC_AO_BASE_ADDRESS + 0x16A0) + #define SHU_CONF0_DMPGTIM Fld(7, 0) //[6:0] + #define SHU_CONF0_ADVPREEN Fld(1, 7) //[7:7] + #define SHU_CONF0_PBREFEN Fld(1, 8) //[8:8] + #define SHU_CONF0_REFTHD Fld(4, 12) //[15:12] + #define SHU_CONF0_REQQUE_DEPTH Fld(4, 16) //[19:16] + #define SHU_CONF0_ADVREFEN Fld(1, 31) //[31:31] + +#define DRAMC_REG_SHU_MISC (DRAMC_AO_BASE_ADDRESS + 0x16A4) + #define SHU_MISC_REQQUE_MAXCNT Fld(4, 0) //[3:0] + #define SHU_MISC_DCMDLYREF Fld(3, 16) //[18:16] + #define SHU_MISC_DAREFEN Fld(1, 30) //[30:30] + +#define DRAMC_REG_SHU_NEW_XRW2W_CTRL (DRAMC_AO_BASE_ADDRESS + 0x16A8) + #define SHU_NEW_XRW2W_CTRL_TX_PI_UPDCTL_B0 Fld(3, 16) //[18:16] + #define SHU_NEW_XRW2W_CTRL_TX_PI_UPDCTL_B1 Fld(3, 24) //[26:24] + #define SHU_NEW_XRW2W_CTRL_TXPI_UPD_MODE Fld(1, 31) //[31:31] + +#define DRAMC_REG_SHU_APHY_TX_PICG_CTRL (DRAMC_AO_BASE_ADDRESS + 0x16AC) + #define SHU_APHY_TX_PICG_CTRL_DDRPHY_CLK_EN_COMB_TX_PICG_CNT Fld(4, 0) //[3:0] + #define SHU_APHY_TX_PICG_CTRL_DDRPHY_CLK_EN_COMB_TX_DQS_SEL_P1 Fld(3, 4) //[6:4] + #define SHU_APHY_TX_PICG_CTRL_DDRPHY_CLK_EN_COMB_TX_DQS_SEL_P0 Fld(3, 8) //[10:8] + #define SHU_APHY_TX_PICG_CTRL_DPHY_TX_DCM_EXTCNT Fld(4, 12) //[15:12] + #define SHU_APHY_TX_PICG_CTRL_DDRPHY_CLK_EN_COMB_TX_OPT Fld(1, 31) //[31:31] + +#define DRAMC_REG_SHU_FREQ_RATIO_SET0 (DRAMC_AO_BASE_ADDRESS + 0x16B0) + #define SHU_FREQ_RATIO_SET0_TDQSCK_JUMP_RATIO3 Fld(8, 0) //[7:0] + #define SHU_FREQ_RATIO_SET0_TDQSCK_JUMP_RATIO2 Fld(8, 8) //[15:8] + #define SHU_FREQ_RATIO_SET0_TDQSCK_JUMP_RATIO1 Fld(8, 16) //[23:16] + #define SHU_FREQ_RATIO_SET0_TDQSCK_JUMP_RATIO0 Fld(8, 24) //[31:24] + +#define DRAMC_REG_SHU_FREQ_RATIO_SET1 (DRAMC_AO_BASE_ADDRESS + 0x16B4) + #define SHU_FREQ_RATIO_SET1_TDQSCK_JUMP_RATIO7 Fld(8, 0) //[7:0] + #define SHU_FREQ_RATIO_SET1_TDQSCK_JUMP_RATIO6 Fld(8, 8) //[15:8] + #define SHU_FREQ_RATIO_SET1_TDQSCK_JUMP_RATIO5 Fld(8, 16) //[23:16] + #define SHU_FREQ_RATIO_SET1_TDQSCK_JUMP_RATIO4 Fld(8, 24) //[31:24] + +#define DRAMC_REG_SHU_FREQ_RATIO_SET2 (DRAMC_AO_BASE_ADDRESS + 0x16B8) + #define SHU_FREQ_RATIO_SET2_TDQSCK_JUMP_RATIO9 Fld(8, 16) //[23:16] + #define SHU_FREQ_RATIO_SET2_TDQSCK_JUMP_RATIO8 Fld(8, 24) //[31:24] + +#define DRAMC_REG_SHUREG_RSV (DRAMC_AO_BASE_ADDRESS + 0x16BC) + #define SHUREG_RSV_SHUREG_RSV Fld(32, 0) //[31:0] + +#define DRAMC_REG_SHU_WCKCTRL (DRAMC_AO_BASE_ADDRESS + 0x16C0) + #define SHU_WCKCTRL_WCKRDOFF Fld(6, 0) //[5:0] + #define SHU_WCKCTRL_WCKRDOFF_05T Fld(1, 7) //[7:7] + #define SHU_WCKCTRL_WCKWROFF Fld(6, 8) //[13:8] + #define SHU_WCKCTRL_WCKWROFF_05T Fld(1, 15) //[15:15] + #define SHU_WCKCTRL_WCKDUAL Fld(1, 16) //[16:16] + +#define DRAMC_REG_SHU_WCKCTRL_1 (DRAMC_AO_BASE_ADDRESS + 0x16C4) + #define SHU_WCKCTRL_1_WCKSYNC_PRE_MODE Fld(1, 0) //[0:0] + +#define DRAMC_REG_SHU_RX_SET0 (DRAMC_AO_BASE_ADDRESS + 0x16D0) + #define SHU_RX_SET0_RECC_EN Fld(1, 31) //[31:31] + +#define DRAMC_REG_SHU_REF0 (DRAMC_AO_BASE_ADDRESS + 0x16D4) + #define SHU_REF0_MPENDREF_CNT Fld(3, 0) //[2:0] + +#define DRAMC_REG_SHU_LP5_CMD (DRAMC_AO_BASE_ADDRESS + 0x16E0) + #define SHU_LP5_CMD_LP5_CMD1TO2EN Fld(1, 0) //[0:0] + #define SHU_LP5_CMD_TCSH Fld(4, 4) //[7:4] + +#define DRAMC_REG_SHU_LP5_SACT (DRAMC_AO_BASE_ADDRESS + 0x16E4) + #define SHU_LP5_SACT_LP5_SEPARATE_ACT Fld(1, 0) //[0:0] + +#define DRAMC_REG_SHU_ACTIM7 (DRAMC_AO_BASE_ADDRESS + 0x16E8) + #define SHU_ACTIM7_TCSH_CSCAL Fld(4, 0) //[3:0] + #define SHU_ACTIM7_TCACSH Fld(4, 4) //[7:4] + +#endif // __DRAMC_AO_REGS_H__ diff --git a/src/vendorcode/mediatek/mt8192/include/Margaux_Register_DRAMC_NAO.h b/src/vendorcode/mediatek/mt8192/include/Margaux_Register_DRAMC_NAO.h new file mode 100644 index 000000000000..f3a1342ab3f5 --- /dev/null +++ b/src/vendorcode/mediatek/mt8192/include/Margaux_Register_DRAMC_NAO.h @@ -0,0 +1,1081 @@ +/* SPDX-License-Identifier: BSD-3-Clause */ + +#ifndef __DRAMC_NAO_REGS_H__ +#define __DRAMC_NAO_REGS_H__ + +#define Channel_A_DRAMC_NAO_BASE_ADDRESS 0x10234000 +#define Channel_B_DRAMC_NAO_BASE_ADDRESS 0x10244000 + +#define DRAMC_NAO_BASE_ADDRESS Channel_A_DRAMC_NAO_BASE_VIRTUAL + +#define DRAMC_REG_TESTMODE (DRAMC_NAO_BASE_ADDRESS + 0x0000) + #define TESTMODE_TESTM_PAT0 Fld(8, 24) //[31:24] + +#define DRAMC_REG_RDQC_CMP (DRAMC_NAO_BASE_ADDRESS + 0x0014) + #define RDQC_CMP_RDDQC_CMP0_ERR Fld(16, 0) //[15:0] + #define RDQC_CMP_RDDQC_CMP1_ERR Fld(16, 16) //[31:16] + +#define DRAMC_REG_RDQC_DQM_CMP (DRAMC_NAO_BASE_ADDRESS + 0x0018) + #define RDQC_DQM_CMP_RDDQC_DQM_CMP0_ERR Fld(2, 0) //[1:0] + #define RDQC_DQM_CMP_RDDQC_DQM_CMP1_ERR Fld(2, 2) //[3:2] + +#define DRAMC_REG_DMMONITOR (DRAMC_NAO_BASE_ADDRESS + 0x0024) + #define DMMONITOR_MONPAUSE_SW Fld(1, 2) //[2:2] + #define DMMONITOR_BUSMONEN_SW Fld(1, 3) //[3:3] + #define DMMONITOR_WDQ_MON_OPT Fld(1, 4) //[4:4] + #define DMMONITOR_REQQUE_MON_SREF_DIS Fld(1, 8) //[8:8] + #define DMMONITOR_REQQUE_MON_SREF_REOR Fld(1, 9) //[9:9] + #define DMMONITOR_REQQUE_MON_SREF_LLAT Fld(1, 10) //[10:10] + #define DMMONITOR_REQQUE_MON_SREF_HPRI Fld(1, 11) //[11:11] + #define DMMONITOR_REQQUE_MON_SREF_RW Fld(1, 12) //[12:12] + #define DMMONITOR_EBG_PGHIT_COUNTER_CLR Fld(1, 16) //[16:16] + +#define DRAMC_REG_INITK_PAT0 (DRAMC_NAO_BASE_ADDRESS + 0x0030) + #define INITK_PAT0_INITK_PAT0 Fld(32, 0) //[31:0] + +#define DRAMC_REG_INITK_PAT1 (DRAMC_NAO_BASE_ADDRESS + 0x0034) + #define INITK_PAT1_INITK_PAT1 Fld(32, 0) //[31:0] + +#define DRAMC_REG_INITK_PAT2 (DRAMC_NAO_BASE_ADDRESS + 0x0038) + #define INITK_PAT2_INITK_PAT2 Fld(32, 0) //[31:0] + +#define DRAMC_REG_INITK_PAT3 (DRAMC_NAO_BASE_ADDRESS + 0x003C) + #define INITK_PAT3_INITK_PAT3 Fld(32, 0) //[31:0] + +#define DRAMC_REG_INITK_PAT4 (DRAMC_NAO_BASE_ADDRESS + 0x0040) + #define INITK_PAT4_INITK_PAT4 Fld(32, 0) //[31:0] + +#define DRAMC_REG_SPCMDRESP3 (DRAMC_NAO_BASE_ADDRESS + 0x0050) + #define SPCMDRESP3_RTSWCMD_RESPONSE Fld(1, 0) //[0:0] + #define SPCMDRESP3_ZQC_SWTRIG_RESPONSE Fld(1, 1) //[1:1] + #define SPCMDRESP3_ZQLAT_SWTRIG_RESPONSE Fld(1, 2) //[2:2] + #define SPCMDRESP3_WCK2DQI_START_SWTRIG_RESPONSE Fld(1, 3) //[3:3] + #define SPCMDRESP3_WCK2DQO_START_SWTRIG_RESPONSE Fld(1, 4) //[4:4] + #define SPCMDRESP3_DVFS_RTMRW_RESPONSE Fld(1, 5) //[5:5] + +#define DRAMC_REG_CBT_WLEV_STATUS2 (DRAMC_NAO_BASE_ADDRESS + 0x0054) + #define CBT_WLEV_STATUS2_CBT_PAT_CMP_CPT Fld(1, 0) //[0:0] + #define CBT_WLEV_STATUS2_CBT_PAT_CMP_ERR_B0 Fld(7, 1) //[7:1] + #define CBT_WLEV_STATUS2_CBT_PAT_RDAT_B0 Fld(7, 8) //[14:8] + #define CBT_WLEV_STATUS2_CBT_PAT_CMP_ERR_B1 Fld(7, 15) //[21:15] + #define CBT_WLEV_STATUS2_CBT_PAT_RDAT_B1 Fld(7, 22) //[28:22] + +#define DRAMC_REG_MISC_STATUSA (DRAMC_NAO_BASE_ADDRESS + 0x0080) + #define MISC_STATUSA_WAIT_DLE Fld(1, 0) //[0:0] + #define MISC_STATUSA_WRITE_DATA_BUFFER_EMPTY Fld(1, 1) //[1:1] + #define MISC_STATUSA_REQQ_EMPTY Fld(1, 2) //[2:2] + #define MISC_STATUSA_PG_VLD Fld(1, 3) //[3:3] + #define MISC_STATUSA_REQQUE_DEPTH Fld(4, 4) //[7:4] + #define MISC_STATUSA_REFRESH_RATE Fld(5, 8) //[12:8] + #define MISC_STATUSA_CKEO_PRE Fld(1, 13) //[13:13] + #define MISC_STATUSA_CKE1O_PRE Fld(1, 14) //[14:14] + #define MISC_STATUSA_SREF_STATE Fld(1, 16) //[16:16] + #define MISC_STATUSA_SELFREF_SM Fld(3, 17) //[19:17] + #define MISC_STATUSA_REFRESH_OVER_CNT Fld(4, 20) //[23:20] + #define MISC_STATUSA_REFRESH_QUEUE_CNT Fld(4, 24) //[27:24] + #define MISC_STATUSA_REQDEPTH_UPD_DONE Fld(1, 28) //[28:28] + #define MISC_STATUSA_DRAMC_IDLE_STATUS Fld(1, 30) //[30:30] + #define MISC_STATUSA_DRAMC_IDLE_DCM Fld(1, 31) //[31:31] + +#define DRAMC_REG_SPECIAL_STATUS (DRAMC_NAO_BASE_ADDRESS + 0x0084) + #define SPECIAL_STATUS_SPECIAL_COMMAND_ENABLE Fld(1, 0) //[0:0] + #define SPECIAL_STATUS_H_ZQLAT_REQ Fld(1, 1) //[1:1] + #define SPECIAL_STATUS_H_ZQLCAL_REQ Fld(1, 2) //[2:2] + #define SPECIAL_STATUS_TX_RETRY_PERIOD Fld(1, 3) //[3:3] + #define SPECIAL_STATUS_H_DQSOSCEN_REQ Fld(1, 4) //[4:4] + #define SPECIAL_STATUS_DQSOSCEN_PERIOD Fld(1, 5) //[5:5] + #define SPECIAL_STATUS_H_ZQCS_REQ Fld(1, 6) //[6:6] + #define SPECIAL_STATUS_H_REFR_REQ Fld(1, 7) //[7:7] + #define SPECIAL_STATUS_HW_ZQLAT_REQ Fld(1, 9) //[9:9] + #define SPECIAL_STATUS_HW_ZQCAL_REQ Fld(1, 10) //[10:10] + #define SPECIAL_STATUS_SPECIAL_STATUS Fld(1, 11) //[11:11] + #define SPECIAL_STATUS_SCSM Fld(5, 12) //[16:12] + #define SPECIAL_STATUS_XSR_TX_RETRY_SM Fld(3, 17) //[19:17] + #define SPECIAL_STATUS_SCARB_SM Fld(5, 20) //[24:20] + #define SPECIAL_STATUS_TX_RETRY_PERIOD_WO_RX_RETRY Fld(1, 25) //[25:25] + #define SPECIAL_STATUS_DSM_REQ_2Q Fld(1, 26) //[26:26] + #define SPECIAL_STATUS_DSM_REQ Fld(1, 27) //[27:27] + #define SPECIAL_STATUS_SC_DRAMC_QUEUE_ACK Fld(1, 28) //[28:28] + #define SPECIAL_STATUS_SREF_REQ_2Q Fld(1, 30) //[30:30] + #define SPECIAL_STATUS_SREF_REQ Fld(1, 31) //[31:31] + +#define DRAMC_REG_SPCMDRESP (DRAMC_NAO_BASE_ADDRESS + 0x0088) + #define SPCMDRESP_MRW_RESPONSE Fld(1, 0) //[0:0] + #define SPCMDRESP_MRR_RESPONSE Fld(1, 1) //[1:1] + #define SPCMDRESP_PREA_RESPONSE Fld(1, 2) //[2:2] + #define SPCMDRESP_AREF_RESPONSE Fld(1, 3) //[3:3] + #define SPCMDRESP_ZQC_RESPONSE Fld(1, 4) //[4:4] + #define SPCMDRESP_TCMD_RESPONSE Fld(1, 5) //[5:5] + #define SPCMDRESP_ZQLAT_RESPONSE Fld(1, 6) //[6:6] + #define SPCMDRESP_RDDQC_RESPONSE Fld(1, 7) //[7:7] + #define SPCMDRESP_STEST_RESPONSE Fld(1, 8) //[8:8] + #define SPCMDRESP_MPCMAN_RESPONSE Fld(1, 9) //[9:9] + #define SPCMDRESP_DQSOSCEN_RESPONSE Fld(1, 10) //[10:10] + #define SPCMDRESP_DQSOSCDIS_RESPONSE Fld(1, 11) //[11:11] + #define SPCMDRESP_ACT_RESPONSE Fld(1, 12) //[12:12] + #define SPCMDRESP_MPRW_RESPONSE Fld(1, 13) //[13:13] + #define SPCMDRESP_TX_RETRY_DONE_RESPONSE Fld(1, 15) //[15:15] + #define SPCMDRESP_DVFS_RESPONSE Fld(1, 16) //[16:16] + #define SPCMDRESP_HW_ZQLAT_POP Fld(1, 17) //[17:17] + #define SPCMDRESP_HW_ZQCAL_POP Fld(1, 18) //[18:18] + #define SPCMDRESP_RTMRW_RESPONSE Fld(1, 19) //[19:19] + #define SPCMDRESP_RTMRW_REQ_CNT Fld(3, 20) //[22:20] + #define SPCMDRESP_RTMRW_ACK_CNT Fld(3, 23) //[25:23] + #define SPCMDRESP_RTMRW_POP_CNT Fld(3, 26) //[28:26] + #define SPCMDRESP_RDFIFO_RESPONSE Fld(1, 30) //[30:30] + #define SPCMDRESP_WRFIFO_RESPONSE Fld(1, 31) //[31:31] + +#define DRAMC_REG_MRR_STATUS (DRAMC_NAO_BASE_ADDRESS + 0x008C) + #define MRR_STATUS_MRR_REG Fld(16, 0) //[15:0] + #define MRR_STATUS_MRR_SW_REG Fld(16, 16) //[31:16] + +#define DRAMC_REG_MRR_STATUS2 (DRAMC_NAO_BASE_ADDRESS + 0x0090) + #define MRR_STATUS2_MR4_REG Fld(16, 0) //[15:0] + #define MRR_STATUS2_SHUFFLE_MRW_VRCG_NORMAL_OK Fld(1, 16) //[16:16] + #define MRR_STATUS2_TFC_OK Fld(1, 17) //[17:17] + #define MRR_STATUS2_TCKFSPX_OK Fld(1, 18) //[18:18] + #define MRR_STATUS2_TVRCG_EN_OK Fld(1, 19) //[19:19] + #define MRR_STATUS2_TCKFSPE_OK Fld(1, 20) //[20:20] + #define MRR_STATUS2_TVRCG_DIS_OK Fld(1, 21) //[21:21] + #define MRR_STATUS2_PHY_SHUFFLE_PERIOD_GO_ZERO_OK Fld(1, 22) //[22:22] + #define MRR_STATUS2_DVFS_STATE Fld(8, 24) //[31:24] + +#define DRAMC_REG_MRRDATA0 (DRAMC_NAO_BASE_ADDRESS + 0x0094) + #define MRRDATA0_MRR_DATA0 Fld(32, 0) //[31:0] + +#define DRAMC_REG_MRRDATA1 (DRAMC_NAO_BASE_ADDRESS + 0x0098) + #define MRRDATA1_MRR_DATA1 Fld(32, 0) //[31:0] + +#define DRAMC_REG_MRRDATA2 (DRAMC_NAO_BASE_ADDRESS + 0x009C) + #define MRRDATA2_MRR_DATA2 Fld(32, 0) //[31:0] + +#define DRAMC_REG_MRRDATA3 (DRAMC_NAO_BASE_ADDRESS + 0x00A0) + #define MRRDATA3_MRR_DATA3 Fld(32, 0) //[31:0] + +#define DRAMC_REG_REF_STATUS (DRAMC_NAO_BASE_ADDRESS + 0x00A4) + #define REF_STATUS_REFRATE_INT_TRIGGER1 Fld(1, 0) //[0:0] + #define REF_STATUS_REFRATE_INT_TRIGGER2 Fld(1, 1) //[1:1] + #define REF_STATUS_PRE_REFRATE_INT_TRIGGER1 Fld(1, 2) //[2:2] + #define REF_STATUS_REFPENDING_INT_TRIGGER_1 Fld(1, 3) //[3:3] + #define REF_STATUS_REFPENDING_INT_TRIGGER_2 Fld(1, 4) //[4:4] + +#define DRAMC_REG_WCK_STATUS (DRAMC_NAO_BASE_ADDRESS + 0x00B0) + #define WCK_STATUS_WCKEN_RK0_SM Fld(2, 0) //[1:0] + #define WCK_STATUS_WCKEN_RK1_SM Fld(2, 2) //[3:2] + +#define DRAMC_REG_TCMDO1LAT (DRAMC_NAO_BASE_ADDRESS + 0x00C0) + #define TCMDO1LAT_MANUTXUPD_B0_DONE Fld(1, 6) //[6:6] + #define TCMDO1LAT_MANUTXUPD_B1_DONE Fld(1, 7) //[7:7] + +#define DRAMC_REG_CBT_WLEV_STATUS1 (DRAMC_NAO_BASE_ADDRESS + 0x00C4) + #define CBT_WLEV_STATUS1_CATRAIN_CMP_CPT Fld(1, 0) //[0:0] + #define CBT_WLEV_STATUS1_CATRAIN_CMP_ERR_B0 Fld(7, 1) //[7:1] + #define CBT_WLEV_STATUS1_CATRAIN_RDAT_B0 Fld(7, 8) //[14:8] + #define CBT_WLEV_STATUS1_CATRAIN_CMP_ERR_B1 Fld(7, 15) //[21:15] + #define CBT_WLEV_STATUS1_CATRAIN_RDAT_B1 Fld(7, 22) //[28:22] + +#define DRAMC_REG_CBT_WLEV_STATUS (DRAMC_NAO_BASE_ADDRESS + 0x00C8) + #define CBT_WLEV_STATUS_WLEV_CMP_CPT Fld(1, 0) //[0:0] + #define CBT_WLEV_STATUS_WLEV_CMP_ERR Fld(2, 1) //[2:1] + #define CBT_WLEV_STATUS_TCMD_CMP_ERR_B0 Fld(1, 3) //[3:3] + #define CBT_WLEV_STATUS_TCMD_CMP_ERR_B1 Fld(1, 4) //[4:4] + #define CBT_WLEV_STATUS_TCMD_O1_LATCH_DATA_B0 Fld(7, 5) //[11:5] + #define CBT_WLEV_STATUS_TCMD_O1_LATCH_DATA_B1 Fld(7, 12) //[18:12] + #define CBT_WLEV_STATUS_CBT_WLEV_ATK_CNT Fld(6, 19) //[24:19] + #define CBT_WLEV_STATUS_CBT_WLEV_ATK_RESPONSE Fld(1, 25) //[25:25] + +#define DRAMC_REG_SPCMDRESP2 (DRAMC_NAO_BASE_ADDRESS + 0x00CC) + #define SPCMDRESP2_RTMRW_ABNORMAL_STOP Fld(1, 0) //[0:0] + +#define DRAMC_REG_CBT_WLEV_ATK_RESULT0 (DRAMC_NAO_BASE_ADDRESS + 0x00D0) + #define CBT_WLEV_ATK_RESULT0_CBT_WLEV_ATK_CMP_ERR0 Fld(32, 0) //[31:0] + +#define DRAMC_REG_CBT_WLEV_ATK_RESULT1 (DRAMC_NAO_BASE_ADDRESS + 0x00D4) + #define CBT_WLEV_ATK_RESULT1_CBT_WLEV_ATK_CMP_ERR1 Fld(32, 0) //[31:0] + +#define DRAMC_REG_CBT_WLEV_ATK_RESULT2 (DRAMC_NAO_BASE_ADDRESS + 0x00D8) + #define CBT_WLEV_ATK_RESULT2_CBT_WLEV_ATK_CMP_ERR2 Fld(32, 0) //[31:0] + +#define DRAMC_REG_CBT_WLEV_ATK_RESULT3 (DRAMC_NAO_BASE_ADDRESS + 0x00DC) + #define CBT_WLEV_ATK_RESULT3_CBT_WLEV_ATK_CMP_ERR3 Fld(32, 0) //[31:0] + +#define DRAMC_REG_CBT_WLEV_ATK_RESULT4 (DRAMC_NAO_BASE_ADDRESS + 0x00E0) + #define CBT_WLEV_ATK_RESULT4_CBT_WLEV_ATK_CMP_ERR4 Fld(32, 0) //[31:0] + +#define DRAMC_REG_CBT_WLEV_ATK_RESULT5 (DRAMC_NAO_BASE_ADDRESS + 0x00E4) + #define CBT_WLEV_ATK_RESULT5_CBT_WLEV_ATK_CMP_ERR5 Fld(32, 0) //[31:0] + +#define DRAMC_REG_CBT_WLEV_ATK_RESULT6 (DRAMC_NAO_BASE_ADDRESS + 0x00E8) + #define CBT_WLEV_ATK_RESULT6_CBT_WLEV_ATK_CMP_ERR6 Fld(32, 0) //[31:0] + +#define DRAMC_REG_CBT_WLEV_ATK_RESULT7 (DRAMC_NAO_BASE_ADDRESS + 0x00EC) + #define CBT_WLEV_ATK_RESULT7_CBT_WLEV_ATK_CMP_ERR7 Fld(32, 0) //[31:0] + +#define DRAMC_REG_CBT_WLEV_ATK_RESULT8 (DRAMC_NAO_BASE_ADDRESS + 0x00F0) + #define CBT_WLEV_ATK_RESULT8_CBT_WLEV_ATK_CMP_ERR8 Fld(32, 0) //[31:0] + +#define DRAMC_REG_CBT_WLEV_ATK_RESULT9 (DRAMC_NAO_BASE_ADDRESS + 0x00F4) + #define CBT_WLEV_ATK_RESULT9_CBT_WLEV_ATK_CMP_ERR9 Fld(32, 0) //[31:0] + +#define DRAMC_REG_CBT_WLEV_ATK_RESULT10 (DRAMC_NAO_BASE_ADDRESS + 0x00F8) + #define CBT_WLEV_ATK_RESULT10_CBT_WLEV_ATK_CMP_ERR10 Fld(32, 0) //[31:0] + +#define DRAMC_REG_CBT_WLEV_ATK_RESULT11 (DRAMC_NAO_BASE_ADDRESS + 0x00FC) + #define CBT_WLEV_ATK_RESULT11_CBT_WLEV_ATK_CMP_ERR11 Fld(32, 0) //[31:0] + +#define DRAMC_REG_CBT_WLEV_ATK_RESULT12 (DRAMC_NAO_BASE_ADDRESS + 0x0100) + #define CBT_WLEV_ATK_RESULT12_CBT_WLEV_ATK_CMP_ERR12 Fld(32, 0) //[31:0] + +#define DRAMC_REG_CBT_WLEV_ATK_RESULT13 (DRAMC_NAO_BASE_ADDRESS + 0x0104) + #define CBT_WLEV_ATK_RESULT13_CBT_WLEV_ATK_CMP_ERR13 Fld(32, 0) //[31:0] + +#define DRAMC_REG_HWMRR_PUSH2POP_CNT (DRAMC_NAO_BASE_ADDRESS + 0x010C) + #define HWMRR_PUSH2POP_CNT_HWMRR_PUSH2POP_CNT Fld(32, 0) //[31:0] + +#define DRAMC_REG_HWMRR_STATUS (DRAMC_NAO_BASE_ADDRESS + 0x0110) + #define HWMRR_STATUS_OV_P2P_CNT Fld(8, 0) //[7:0] + #define HWMRR_STATUS_MRR_CNT_UNDER_FULL Fld(1, 30) //[30:30] + #define HWMRR_STATUS_MRR_CNT_OVER_FULL Fld(1, 31) //[31:31] + +#define DRAMC_REG_HW_REFRATE_MON (DRAMC_NAO_BASE_ADDRESS + 0x0114) + #define HW_REFRATE_MON_REFRESH_RATE_MIN_MON Fld(5, 0) //[4:0] + #define HW_REFRATE_MON_REFRESH_RATE_MAX_MON Fld(5, 8) //[12:8] + +#define DRAMC_REG_HW_REFRATE_MON2 (DRAMC_NAO_BASE_ADDRESS + 0x0118) + #define HW_REFRATE_MON2_REFRESH_RATE_MIN_MON_RK1_B1 Fld(5, 0) //[4:0] + #define HW_REFRATE_MON2_REFRESH_RATE_MAX_MON_RK1_B1 Fld(5, 8) //[12:8] + #define HW_REFRATE_MON2_REFRESH_RATE_MIN_MON_RK0_B1 Fld(5, 16) //[20:16] + #define HW_REFRATE_MON2_REFRESH_RATE_MAX_MON_RK0_B1 Fld(5, 24) //[28:24] + +#define DRAMC_REG_HW_REFRATE_MON3 (DRAMC_NAO_BASE_ADDRESS + 0x011C) + #define HW_REFRATE_MON3_REFRESH_RATE_MIN_MON_RK1_B0 Fld(5, 0) //[4:0] + #define HW_REFRATE_MON3_REFRESH_RATE_MAX_MON_RK1_B0 Fld(5, 8) //[12:8] + #define HW_REFRATE_MON3_REFRESH_RATE_MIN_MON_RK0_B0 Fld(5, 16) //[20:16] + #define HW_REFRATE_MON3_REFRESH_RATE_MAX_MON_RK0_B0 Fld(5, 24) //[28:24] + +#define DRAMC_REG_TESTRPT (DRAMC_NAO_BASE_ADDRESS + 0x0120) + #define TESTRPT_DM_CMP_CPT_RK0 Fld(1, 0) //[0:0] + #define TESTRPT_DM_CMP_CPT_RK1 Fld(1, 1) //[1:1] + #define TESTRPT_DM_CMP_ERR_RK0 Fld(1, 4) //[4:4] + #define TESTRPT_DM_CMP_ERR_RK1 Fld(1, 5) //[5:5] + #define TESTRPT_DLE_CNT_OK_RK0 Fld(1, 8) //[8:8] + #define TESTRPT_DLE_CNT_OK_RK1 Fld(1, 9) //[9:9] + #define TESTRPT_LPBK_CMP_ERR Fld(1, 12) //[12:12] + #define TESTRPT_TESTSTAT Fld(3, 20) //[22:20] + +#define DRAMC_REG_CMP_ERR (DRAMC_NAO_BASE_ADDRESS + 0x0124) + #define CMP_ERR_CMP_ERR Fld(32, 0) //[31:0] + +#define DRAMC_REG_TEST_ABIT_STATUS1 (DRAMC_NAO_BASE_ADDRESS + 0x0128) + #define TEST_ABIT_STATUS1_TEST_ABIT_ERR1 Fld(32, 0) //[31:0] + +#define DRAMC_REG_TEST_ABIT_STATUS2 (DRAMC_NAO_BASE_ADDRESS + 0x012C) + #define TEST_ABIT_STATUS2_TEST_ABIT_ERR2 Fld(32, 0) //[31:0] + +#define DRAMC_REG_TEST_ABIT_STATUS3 (DRAMC_NAO_BASE_ADDRESS + 0x0130) + #define TEST_ABIT_STATUS3_TEST_ABIT_ERR3 Fld(32, 0) //[31:0] + +#define DRAMC_REG_TEST_ABIT_STATUS4 (DRAMC_NAO_BASE_ADDRESS + 0x0134) + #define TEST_ABIT_STATUS4_TEST_ABIT_ERR4 Fld(32, 0) //[31:0] + +#define DRAMC_REG_TEST_ABIT_STATUS5 (DRAMC_NAO_BASE_ADDRESS + 0x0138) + #define TEST_ABIT_STATUS5_TEST_ABIT_ERR5 Fld(32, 0) //[31:0] + +#define DRAMC_REG_TEST_ABIT_STATUS6 (DRAMC_NAO_BASE_ADDRESS + 0x013C) + #define TEST_ABIT_STATUS6_TEST_ABIT_ERR6 Fld(32, 0) //[31:0] + +#define DRAMC_REG_TEST_ABIT_STATUS7 (DRAMC_NAO_BASE_ADDRESS + 0x0140) + #define TEST_ABIT_STATUS7_TEST_ABIT_ERR7 Fld(32, 0) //[31:0] + +#define DRAMC_REG_TEST_ABIT_STATUS8 (DRAMC_NAO_BASE_ADDRESS + 0x0144) + #define TEST_ABIT_STATUS8_TEST_ABIT_ERR8 Fld(32, 0) //[31:0] + +#define DRAMC_REG_TEST_RF_ERROR_FLAG0 (DRAMC_NAO_BASE_ADDRESS + 0x0148) + #define TEST_RF_ERROR_FLAG0_TEST_RF_ERROR_FLAG0 Fld(32, 0) //[31:0] + +#define DRAMC_REG_TEST_RF_ERROR_FLAG1 (DRAMC_NAO_BASE_ADDRESS + 0x014C) + #define TEST_RF_ERROR_FLAG1_TEST_RF_ERROR_FLAG1 Fld(32, 0) //[31:0] + +#define DRAMC_REG_TEST_RF_ERROR_CNT1 (DRAMC_NAO_BASE_ADDRESS + 0x0150) + #define TEST_RF_ERROR_CNT1_DQ0F_ERR_CNT Fld(11, 16) //[26:16] + #define TEST_RF_ERROR_CNT1_DQ0R_ERR_CNT Fld(11, 0) //[10:0] + +#define DRAMC_REG_TEST_RF_ERROR_CNT2 (DRAMC_NAO_BASE_ADDRESS + 0x0154) + #define TEST_RF_ERROR_CNT2_DQ1F_ERR_CNT Fld(11, 16) //[26:16] + #define TEST_RF_ERROR_CNT2_DQ1R_ERR_CNT Fld(11, 0) //[10:0] + +#define DRAMC_REG_TEST_RF_ERROR_CNT3 (DRAMC_NAO_BASE_ADDRESS + 0x0158) + #define TEST_RF_ERROR_CNT3_DQ2F_ERR_CNT Fld(11, 16) //[26:16] + #define TEST_RF_ERROR_CNT3_DQ2R_ERR_CNT Fld(11, 0) //[10:0] + +#define DRAMC_REG_TEST_RF_ERROR_CNT4 (DRAMC_NAO_BASE_ADDRESS + 0x015C) + #define TEST_RF_ERROR_CNT4_DQ3F_ERR_CNT Fld(11, 16) //[26:16] + #define TEST_RF_ERROR_CNT4_DQ3R_ERR_CNT Fld(11, 0) //[10:0] + +#define DRAMC_REG_TEST_RF_ERROR_CNT5 (DRAMC_NAO_BASE_ADDRESS + 0x0160) + #define TEST_RF_ERROR_CNT5_DQ4F_ERR_CNT Fld(11, 16) //[26:16] + #define TEST_RF_ERROR_CNT5_DQ4R_ERR_CNT Fld(11, 0) //[10:0] + +#define DRAMC_REG_TEST_RF_ERROR_CNT6 (DRAMC_NAO_BASE_ADDRESS + 0x0164) + #define TEST_RF_ERROR_CNT6_DQ5F_ERR_CNT Fld(11, 16) //[26:16] + #define TEST_RF_ERROR_CNT6_DQ5R_ERR_CNT Fld(11, 0) //[10:0] + +#define DRAMC_REG_TEST_RF_ERROR_CNT7 (DRAMC_NAO_BASE_ADDRESS + 0x0168) + #define TEST_RF_ERROR_CNT7_DQ6F_ERR_CNT Fld(11, 16) //[26:16] + #define TEST_RF_ERROR_CNT7_DQ6R_ERR_CNT Fld(11, 0) //[10:0] + +#define DRAMC_REG_TEST_RF_ERROR_CNT8 (DRAMC_NAO_BASE_ADDRESS + 0x016C) + #define TEST_RF_ERROR_CNT8_DQ7F_ERR_CNT Fld(11, 16) //[26:16] + #define TEST_RF_ERROR_CNT8_DQ7R_ERR_CNT Fld(11, 0) //[10:0] + +#define DRAMC_REG_TEST_LOOP_CNT (DRAMC_NAO_BASE_ADDRESS + 0x0170) + #define TEST_LOOP_CNT_LOOP_CNT Fld(16, 0) //[15:0] + +#define DRAMC_REG_SREF_DLY_CNT (DRAMC_NAO_BASE_ADDRESS + 0x0180) + #define SREF_DLY_CNT_SREF_DLY_CNT Fld(16, 0) //[15:0] + #define SREF_DLY_CNT_SREF_DLY_CNT_ECO Fld(16, 16) //[31:16] + +#define DRAMC_REG_TX_ATK_SET0 (DRAMC_NAO_BASE_ADDRESS + 0x0200) + #define TX_ATK_SET0_TX_ATK_DQ_B0_PI_INIT Fld(6, 0) //[5:0] + #define TX_ATK_SET0_TX_ATK_DQ_B1_PI_INIT Fld(6, 8) //[13:8] + #define TX_ATK_SET0_TX_ATK_DQM_B0_PI_INIT Fld(6, 16) //[21:16] + #define TX_ATK_SET0_TX_ATK_DQM_B1_PI_INIT Fld(6, 24) //[29:24] + +#define DRAMC_REG_TX_ATK_SET1 (DRAMC_NAO_BASE_ADDRESS + 0x0204) + #define TX_ATK_SET1_TX_ATK_DQ_PI_EN Fld(1, 0) //[0:0] + #define TX_ATK_SET1_TX_ATK_DQM_PI_EN Fld(1, 1) //[1:1] + #define TX_ATK_SET1_TX_ATK_PI_LEN Fld(2, 2) //[3:2] + #define TX_ATK_SET1_TX_ATK_EARLY_BREAK Fld(1, 4) //[4:4] + #define TX_ATK_SET1_TX_ATK_PASS_PI_THRD Fld(6, 8) //[13:8] + #define TX_ATK_SET1_TX_ATK_DBG_EN Fld(1, 15) //[15:15] + #define TX_ATK_SET1_TX_ATK_DBG_BIT_SEL Fld(4, 16) //[19:16] + #define TX_ATK_SET1_TX_ATK_CLR Fld(1, 30) //[30:30] + #define TX_ATK_SET1_TX_ATK_TRIG Fld(1, 31) //[31:31] + +#define DRAMC_REG_TX_ATK_RESULT0 (DRAMC_NAO_BASE_ADDRESS + 0x0210) + #define TX_ATK_RESULT0_TX_ATK_MAX_PW_PI_INIT_BIT0 Fld(8, 0) //[7:0] + #define TX_ATK_RESULT0_TX_ATK_MAX_PW_PI_INIT_BIT1 Fld(8, 8) //[15:8] + #define TX_ATK_RESULT0_TX_ATK_MAX_PW_PI_INIT_BIT2 Fld(8, 16) //[23:16] + #define TX_ATK_RESULT0_TX_ATK_MAX_PW_PI_INIT_BIT3 Fld(8, 24) //[31:24] + +#define DRAMC_REG_TX_ATK_RESULT1 (DRAMC_NAO_BASE_ADDRESS + 0x0214) + #define TX_ATK_RESULT1_TX_ATK_MAX_PW_PI_INIT_BIT4 Fld(8, 0) //[7:0] + #define TX_ATK_RESULT1_TX_ATK_MAX_PW_PI_INIT_BIT5 Fld(8, 8) //[15:8] + #define TX_ATK_RESULT1_TX_ATK_MAX_PW_PI_INIT_BIT6 Fld(8, 16) //[23:16] + #define TX_ATK_RESULT1_TX_ATK_MAX_PW_PI_INIT_BIT7 Fld(8, 24) //[31:24] + +#define DRAMC_REG_TX_ATK_RESULT2 (DRAMC_NAO_BASE_ADDRESS + 0x0218) + #define TX_ATK_RESULT2_TX_ATK_MAX_PW_PI_INIT_BIT8 Fld(8, 0) //[7:0] + #define TX_ATK_RESULT2_TX_ATK_MAX_PW_PI_INIT_BIT9 Fld(8, 8) //[15:8] + #define TX_ATK_RESULT2_TX_ATK_MAX_PW_PI_INIT_BIT10 Fld(8, 16) //[23:16] + #define TX_ATK_RESULT2_TX_ATK_MAX_PW_PI_INIT_BIT11 Fld(8, 24) //[31:24] + +#define DRAMC_REG_TX_ATK_RESULT3 (DRAMC_NAO_BASE_ADDRESS + 0x021C) + #define TX_ATK_RESULT3_TX_ATK_MAX_PW_PI_INIT_BIT12 Fld(8, 0) //[7:0] + #define TX_ATK_RESULT3_TX_ATK_MAX_PW_PI_INIT_BIT13 Fld(8, 8) //[15:8] + #define TX_ATK_RESULT3_TX_ATK_MAX_PW_PI_INIT_BIT14 Fld(8, 16) //[23:16] + #define TX_ATK_RESULT3_TX_ATK_MAX_PW_PI_INIT_BIT15 Fld(8, 24) //[31:24] + +#define DRAMC_REG_TX_ATK_RESULT4 (DRAMC_NAO_BASE_ADDRESS + 0x0220) + #define TX_ATK_RESULT4_TX_ATK_MAX_PW_PI_LEN_BIT0 Fld(8, 0) //[7:0] + #define TX_ATK_RESULT4_TX_ATK_MAX_PW_PI_LEN_BIT1 Fld(8, 8) //[15:8] + #define TX_ATK_RESULT4_TX_ATK_MAX_PW_PI_LEN_BIT2 Fld(8, 16) //[23:16] + #define TX_ATK_RESULT4_TX_ATK_MAX_PW_PI_LEN_BIT3 Fld(8, 24) //[31:24] + +#define DRAMC_REG_TX_ATK_RESULT5 (DRAMC_NAO_BASE_ADDRESS + 0x0224) + #define TX_ATK_RESULT5_TX_ATK_MAX_PW_PI_LEN_BIT4 Fld(8, 0) //[7:0] + #define TX_ATK_RESULT5_TX_ATK_MAX_PW_PI_LEN_BIT5 Fld(8, 8) //[15:8] + #define TX_ATK_RESULT5_TX_ATK_MAX_PW_PI_LEN_BIT6 Fld(8, 16) //[23:16] + #define TX_ATK_RESULT5_TX_ATK_MAX_PW_PI_LEN_BIT7 Fld(8, 24) //[31:24] + +#define DRAMC_REG_TX_ATK_RESULT6 (DRAMC_NAO_BASE_ADDRESS + 0x0228) + #define TX_ATK_RESULT6_TX_ATK_MAX_PW_PI_LEN_BIT8 Fld(8, 0) //[7:0] + #define TX_ATK_RESULT6_TX_ATK_MAX_PW_PI_LEN_BIT9 Fld(8, 8) //[15:8] + #define TX_ATK_RESULT6_TX_ATK_MAX_PW_PI_LEN_BIT10 Fld(8, 16) //[23:16] + #define TX_ATK_RESULT6_TX_ATK_MAX_PW_PI_LEN_BIT11 Fld(8, 24) //[31:24] + +#define DRAMC_REG_TX_ATK_RESULT7 (DRAMC_NAO_BASE_ADDRESS + 0x022C) + #define TX_ATK_RESULT7_TX_ATK_MAX_PW_PI_LEN_BIT12 Fld(8, 0) //[7:0] + #define TX_ATK_RESULT7_TX_ATK_MAX_PW_PI_LEN_BIT13 Fld(8, 8) //[15:8] + #define TX_ATK_RESULT7_TX_ATK_MAX_PW_PI_LEN_BIT14 Fld(8, 16) //[23:16] + #define TX_ATK_RESULT7_TX_ATK_MAX_PW_PI_LEN_BIT15 Fld(8, 24) //[31:24] + +#define DRAMC_REG_TX_ATK_RESULT8 (DRAMC_NAO_BASE_ADDRESS + 0x0230) + #define TX_ATK_RESULT8_TX_ATK_FIND_PW Fld(1, 24) //[24:24] + #define TX_ATK_RESULT8_TX_ATK_DONE Fld(1, 31) //[31:31] + +#define DRAMC_REG_TX_ATK_DBG_BIT_STATUS1 (DRAMC_NAO_BASE_ADDRESS + 0x0240) + #define TX_ATK_DBG_BIT_STATUS1_TX_ATK_DBG_BIT_STATUS1 Fld(32, 0) //[31:0] + +#define DRAMC_REG_TX_ATK_DBG_BIT_STATUS2 (DRAMC_NAO_BASE_ADDRESS + 0x0244) + #define TX_ATK_DBG_BIT_STATUS2_TX_ATK_DBG_BIT_STATUS2 Fld(32, 0) //[31:0] + +#define DRAMC_REG_TX_ATK_DBG_BIT_STATUS3 (DRAMC_NAO_BASE_ADDRESS + 0x0248) + #define TX_ATK_DBG_BIT_STATUS3_TX_ATK_DBG_BIT_STATUS3 Fld(32, 0) //[31:0] + +#define DRAMC_REG_TX_ATK_DBG_BIT_STATUS4 (DRAMC_NAO_BASE_ADDRESS + 0x024C) + #define TX_ATK_DBG_BIT_STATUS4_TX_ATK_DBG_BIT_STATUS4 Fld(32, 0) //[31:0] + +#define DRAMC_REG_LP5_PDX_PDE_MON (DRAMC_NAO_BASE_ADDRESS + 0x02D8) + #define LP5_PDX_PDE_MON_PDX_CMD_REQ_RK0_COUNTER Fld(8, 0) //[7:0] + #define LP5_PDX_PDE_MON_PDX_CMD_REQ_RK1_COUNTER Fld(8, 8) //[15:8] + #define LP5_PDX_PDE_MON_PDE_CMD_REQ_RK0_COUNTER Fld(8, 16) //[23:16] + #define LP5_PDX_PDE_MON_PDE_CMD_REQ_RK1_COUNTER Fld(8, 24) //[31:24] + +#define DRAMC_REG_LP5_PDX_PDE_MAX_MON (DRAMC_NAO_BASE_ADDRESS + 0x02DC) + #define LP5_PDX_PDE_MAX_MON_WAIT_PDX_CMD_RK0_MAX_COUNTER Fld(8, 0) //[7:0] + #define LP5_PDX_PDE_MAX_MON_WAIT_PDX_CMD_RK1_MAX_COUNTER Fld(8, 8) //[15:8] + #define LP5_PDX_PDE_MAX_MON_WAIT_PDE_CMD_RK0_MAX_COUNTER Fld(8, 16) //[23:16] + #define LP5_PDX_PDE_MAX_MON_WAIT_PDE_CMD_RK1_MAX_COUNTER Fld(8, 24) //[31:24] + +#define DRAMC_REG_DRAM_CLK_EN_0_OLD_COUNTER (DRAMC_NAO_BASE_ADDRESS + 0x02E0) + #define DRAM_CLK_EN_0_OLD_COUNTER_DRAM_CLK_EN_0_OLD_COUNTER Fld(32, 0) //[31:0] + +#define DRAMC_REG_APHYPI_CG_CK_OLD_COUNTER (DRAMC_NAO_BASE_ADDRESS + 0x02E4) + #define APHYPI_CG_CK_OLD_COUNTER_APHYPI_CG_CK_OLD_COUNTER Fld(32, 0) //[31:0] + +#define DRAMC_REG_CKEO_PRE_OLD_COUNTER (DRAMC_NAO_BASE_ADDRESS + 0x02E8) + #define CKEO_PRE_OLD_COUNTER_CKEO_PRE_OLD_COUNTER Fld(32, 0) //[31:0] + +#define DRAMC_REG_CKE1O_PRE_OLD_COUNTER (DRAMC_NAO_BASE_ADDRESS + 0x02EC) + #define CKE1O_PRE_OLD_COUNTER_CKE1O_PRE_OLD_COUNTER Fld(32, 0) //[31:0] + +#define DRAMC_REG_DRAM_CLK_EN_0_NEW_COUNTER (DRAMC_NAO_BASE_ADDRESS + 0x02F0) + #define DRAM_CLK_EN_0_NEW_COUNTER_DRAM_CLK_EN_0_NEW_COUNTER Fld(32, 0) //[31:0] + +#define DRAMC_REG_APHYPI_CG_CK_NEW_COUNTER (DRAMC_NAO_BASE_ADDRESS + 0x02F4) + #define APHYPI_CG_CK_NEW_COUNTER_APHYPI_CG_CK_NEW_COUNTER Fld(32, 0) //[31:0] + +#define DRAMC_REG_CKEO_PRE_NEW_COUNTER (DRAMC_NAO_BASE_ADDRESS + 0x02F8) + #define CKEO_PRE_NEW_COUNTER_CKEO_PRE_NEW_COUNTER Fld(32, 0) //[31:0] + +#define DRAMC_REG_CKE1O_PRE_NEW_COUNTER (DRAMC_NAO_BASE_ADDRESS + 0x02FC) + #define CKE1O_PRE_NEW_COUNTER_CKE1O_PRE_NEW_COUNTER Fld(32, 0) //[31:0] + +#define DRAMC_REG_REFRESH_POP_COUNTER (DRAMC_NAO_BASE_ADDRESS + 0x0300) + #define REFRESH_POP_COUNTER_REFRESH_POP_COUNTER Fld(32, 0) //[31:0] + +#define DRAMC_REG_FREERUN_26M_COUNTER (DRAMC_NAO_BASE_ADDRESS + 0x0304) + #define FREERUN_26M_COUNTER_FREERUN_26M_COUNTER Fld(32, 0) //[31:0] + +#define DRAMC_REG_DRAMC_IDLE_COUNTER (DRAMC_NAO_BASE_ADDRESS + 0x0308) + #define DRAMC_IDLE_COUNTER_DRAMC_IDLE_COUNTER Fld(32, 0) //[31:0] + +#define DRAMC_REG_R2R_PAGE_HIT_COUNTER (DRAMC_NAO_BASE_ADDRESS + 0x030C) + #define R2R_PAGE_HIT_COUNTER_R2R_PAGE_HIT_COUNTER Fld(32, 0) //[31:0] + +#define DRAMC_REG_R2R_PAGE_MISS_COUNTER (DRAMC_NAO_BASE_ADDRESS + 0x0310) + #define R2R_PAGE_MISS_COUNTER_R2R_PAGE_MISS_COUNTER Fld(32, 0) //[31:0] + +#define DRAMC_REG_R2R_INTERBANK_COUNTER (DRAMC_NAO_BASE_ADDRESS + 0x0314) + #define R2R_INTERBANK_COUNTER_R2R_INTERBANK_COUNTER Fld(32, 0) //[31:0] + +#define DRAMC_REG_R2W_PAGE_HIT_COUNTER (DRAMC_NAO_BASE_ADDRESS + 0x0318) + #define R2W_PAGE_HIT_COUNTER_R2W_PAGE_HIT_COUNTER Fld(32, 0) //[31:0] + +#define DRAMC_REG_R2W_PAGE_MISS_COUNTER (DRAMC_NAO_BASE_ADDRESS + 0x031C) + #define R2W_PAGE_MISS_COUNTER_R2W_PAGE_MISS_COUNTER Fld(32, 0) //[31:0] + +#define DRAMC_REG_R2W_INTERBANK_COUNTER (DRAMC_NAO_BASE_ADDRESS + 0x0320) + #define R2W_INTERBANK_COUNTER_R2W_INTERBANK_COUNTER Fld(32, 0) //[31:0] + +#define DRAMC_REG_W2R_PAGE_HIT_COUNTER (DRAMC_NAO_BASE_ADDRESS + 0x0324) + #define W2R_PAGE_HIT_COUNTER_W2R_PAGE_HIT_COUNTER Fld(32, 0) //[31:0] + +#define DRAMC_REG_W2R_PAGE_MISS_COUNTER (DRAMC_NAO_BASE_ADDRESS + 0x0328) + #define W2R_PAGE_MISS_COUNTER_W2R_PAGE_MISS_COUNTER Fld(32, 0) //[31:0] + +#define DRAMC_REG_W2R_INTERBANK_COUNTER (DRAMC_NAO_BASE_ADDRESS + 0x032C) + #define W2R_INTERBANK_COUNTER_W2R_INTERBANK_COUNTER Fld(32, 0) //[31:0] + +#define DRAMC_REG_W2W_PAGE_HIT_COUNTER (DRAMC_NAO_BASE_ADDRESS + 0x0330) + #define W2W_PAGE_HIT_COUNTER_W2W_PAGE_HIT_COUNTER Fld(32, 0) //[31:0] + +#define DRAMC_REG_W2W_PAGE_MISS_COUNTER (DRAMC_NAO_BASE_ADDRESS + 0x0334) + #define W2W_PAGE_MISS_COUNTER_W2W_PAGE_MISS_COUNTER Fld(32, 0) //[31:0] + +#define DRAMC_REG_W2W_INTERBANK_COUNTER (DRAMC_NAO_BASE_ADDRESS + 0x0338) + #define W2W_INTERBANK_COUNTER_W2W_INTERBANK_COUNTER Fld(32, 0) //[31:0] + +#define DRAMC_REG_RK0_PRE_STANDBY_COUNTER (DRAMC_NAO_BASE_ADDRESS + 0x033C) + #define RK0_PRE_STANDBY_COUNTER_RK0_PRE_STANDBY_COUNTER Fld(32, 0) //[31:0] + +#define DRAMC_REG_RK0_PRE_POWERDOWN_COUNTER (DRAMC_NAO_BASE_ADDRESS + 0x0340) + #define RK0_PRE_POWERDOWN_COUNTER_RK0_PRE_POWERDOWN_COUNTER Fld(32, 0) //[31:0] + +#define DRAMC_REG_RK0_ACT_STANDBY_COUNTER (DRAMC_NAO_BASE_ADDRESS + 0x0344) + #define RK0_ACT_STANDBY_COUNTER_RK0_ACT_STANDBY_COUNTER Fld(32, 0) //[31:0] + +#define DRAMC_REG_RK0_ACT_POWERDOWN_COUNTER (DRAMC_NAO_BASE_ADDRESS + 0x0348) + #define RK0_ACT_POWERDOWN_COUNTER_RK0_ACT_POWERDOWN_COUNTER Fld(32, 0) //[31:0] + +#define DRAMC_REG_RK1_PRE_STANDBY_COUNTER (DRAMC_NAO_BASE_ADDRESS + 0x034C) + #define RK1_PRE_STANDBY_COUNTER_RK1_PRE_STANDBY_COUNTER Fld(32, 0) //[31:0] + +#define DRAMC_REG_RK1_PRE_POWERDOWN_COUNTER (DRAMC_NAO_BASE_ADDRESS + 0x0350) + #define RK1_PRE_POWERDOWN_COUNTER_RK1_PRE_POWERDOWN_COUNTER Fld(32, 0) //[31:0] + +#define DRAMC_REG_RK1_ACT_STANDBY_COUNTER (DRAMC_NAO_BASE_ADDRESS + 0x0354) + #define RK1_ACT_STANDBY_COUNTER_RK1_ACT_STANDBY_COUNTER Fld(32, 0) //[31:0] + +#define DRAMC_REG_RK1_ACT_POWERDOWN_COUNTER (DRAMC_NAO_BASE_ADDRESS + 0x0358) + #define RK1_ACT_POWERDOWN_COUNTER_RK1_ACT_POWERDOWN_COUNTER Fld(32, 0) //[31:0] + +#define DRAMC_REG_RK2_PRE_STANDBY_COUNTER (DRAMC_NAO_BASE_ADDRESS + 0x035C) + #define RK2_PRE_STANDBY_COUNTER_RK2_PRE_STANDBY_COUNTER Fld(32, 0) //[31:0] + +#define DRAMC_REG_RK2_PRE_POWERDOWN_COUNTER (DRAMC_NAO_BASE_ADDRESS + 0x0360) + #define RK2_PRE_POWERDOWN_COUNTER_RK2_PRE_POWERDOWN_COUNTER Fld(32, 0) //[31:0] + +#define DRAMC_REG_RK2_ACT_STANDBY_COUNTER (DRAMC_NAO_BASE_ADDRESS + 0x0364) + #define RK2_ACT_STANDBY_COUNTER_RK2_ACT_STANDBY_COUNTER Fld(32, 0) //[31:0] + +#define DRAMC_REG_RK2_ACT_POWERDOWN_COUNTER (DRAMC_NAO_BASE_ADDRESS + 0x0368) + #define RK2_ACT_POWERDOWN_COUNTER_RK2_ACT_POWERDOWN_COUNTER Fld(32, 0) //[31:0] + +#define DRAMC_REG_DQ0_TOGGLE_COUNTER (DRAMC_NAO_BASE_ADDRESS + 0x036C) + #define DQ0_TOGGLE_COUNTER_DQ0_TOGGLE_COUNTER Fld(32, 0) //[31:0] + +#define DRAMC_REG_DQ1_TOGGLE_COUNTER (DRAMC_NAO_BASE_ADDRESS + 0x0370) + #define DQ1_TOGGLE_COUNTER_DQ1_TOGGLE_COUNTER Fld(32, 0) //[31:0] + +#define DRAMC_REG_DQ2_TOGGLE_COUNTER (DRAMC_NAO_BASE_ADDRESS + 0x0374) + #define DQ2_TOGGLE_COUNTER_DQ2_TOGGLE_COUNTER Fld(32, 0) //[31:0] + +#define DRAMC_REG_DQ3_TOGGLE_COUNTER (DRAMC_NAO_BASE_ADDRESS + 0x0378) + #define DQ3_TOGGLE_COUNTER_DQ3_TOGGLE_COUNTER Fld(32, 0) //[31:0] + +#define DRAMC_REG_DQ0_TOGGLE_COUNTER_R (DRAMC_NAO_BASE_ADDRESS + 0x037C) + #define DQ0_TOGGLE_COUNTER_R_DQ0_TOGGLE_COUNTER_R Fld(32, 0) //[31:0] + +#define DRAMC_REG_DQ1_TOGGLE_COUNTER_R (DRAMC_NAO_BASE_ADDRESS + 0x0380) + #define DQ1_TOGGLE_COUNTER_R_DQ1_TOGGLE_COUNTER_R Fld(32, 0) //[31:0] + +#define DRAMC_REG_DQ2_TOGGLE_COUNTER_R (DRAMC_NAO_BASE_ADDRESS + 0x0384) + #define DQ2_TOGGLE_COUNTER_R_DQ2_TOGGLE_COUNTER_R Fld(32, 0) //[31:0] + +#define DRAMC_REG_DQ3_TOGGLE_COUNTER_R (DRAMC_NAO_BASE_ADDRESS + 0x0388) + #define DQ3_TOGGLE_COUNTER_R_DQ3_TOGGLE_COUNTER_R Fld(32, 0) //[31:0] + +#define DRAMC_REG_READ_BYTES_COUNTER (DRAMC_NAO_BASE_ADDRESS + 0x038C) + #define READ_BYTES_COUNTER_READ_BYTES_COUNTER Fld(32, 0) //[31:0] + +#define DRAMC_REG_WRITE_BYTES_COUNTER (DRAMC_NAO_BASE_ADDRESS + 0x0390) + #define WRITE_BYTES_COUNTER_WRITE_BYTES_COUNTER Fld(32, 0) //[31:0] + +#define DRAMC_REG_MAX_SREF_REQ_TO_ACK_LATENCY_COUNTER (DRAMC_NAO_BASE_ADDRESS + 0x0394) + #define MAX_SREF_REQ_TO_ACK_LATENCY_COUNTER_SREF_REQTOACK_MAX_COUNTER Fld(32, 0) //[31:0] + +#define DRAMC_REG_DRAMC_IDLE_DCM_COUNTER (DRAMC_NAO_BASE_ADDRESS + 0x03A0) + #define DRAMC_IDLE_DCM_COUNTER_DRAMC_IDLE_DCM_COUNTER Fld(32, 0) //[31:0] + +#define DRAMC_REG_DDRPHY_CLK_EN_COUNTER (DRAMC_NAO_BASE_ADDRESS + 0x03A4) + #define DDRPHY_CLK_EN_COUNTER_DDRPHY_CLK_EN_COUNTER Fld(32, 0) //[31:0] + +#define DRAMC_REG_DDRPHY_CLK_EN_COMB_COUNTER (DRAMC_NAO_BASE_ADDRESS + 0x03A8) + #define DDRPHY_CLK_EN_COMB_COUNTER_DDRPHY_CLK_EN_COMB_COUNTER Fld(32, 0) //[31:0] + +#define DRAMC_REG_EBG_COUNTER_CNT0 (DRAMC_NAO_BASE_ADDRESS + 0x03B0) + #define EBG_COUNTER_CNT0_EBG_PGHIT_COUNTER Fld(16, 0) //[15:0] + +#define DRAMC_REG_EBG_COUNTER_CNT1 (DRAMC_NAO_BASE_ADDRESS + 0x03B4) + #define EBG_COUNTER_CNT1_EBG_PGMISS_COUNTER Fld(32, 0) //[31:0] + +#define DRAMC_REG_EBG_COUNTER_CNT2 (DRAMC_NAO_BASE_ADDRESS + 0x03B8) + #define EBG_COUNTER_CNT2_EBG_PGOPEN_COUNTER Fld(32, 0) //[31:0] + +#define DRAMC_REG_LAT_COUNTER_CMD0 (DRAMC_NAO_BASE_ADDRESS + 0x03C0) + #define LAT_COUNTER_CMD0_LAT_CMD0_CNT_MAX Fld(16, 0) //[15:0] + #define LAT_COUNTER_CMD0_LAT_CMD0_CNT_MAX_HPRI Fld(1, 16) //[16:16] + #define LAT_COUNTER_CMD0_LAT_CMD0_CNT_MAX_LLAT Fld(1, 17) //[17:17] + #define LAT_COUNTER_CMD0_LAT_CMD0_CNT_MAX_REORDER Fld(1, 18) //[18:18] + +#define DRAMC_REG_LAT_COUNTER_CMD1 (DRAMC_NAO_BASE_ADDRESS + 0x03C4) + #define LAT_COUNTER_CMD1_LAT_CMD1_CNT_MAX Fld(16, 0) //[15:0] + #define LAT_COUNTER_CMD1_LAT_CMD1_CNT_MAX_HPRI Fld(1, 16) //[16:16] + #define LAT_COUNTER_CMD1_LAT_CMD1_CNT_MAX_LLAT Fld(1, 17) //[17:17] + #define LAT_COUNTER_CMD1_LAT_CMD1_CNT_MAX_REORDER Fld(1, 18) //[18:18] + +#define DRAMC_REG_LAT_COUNTER_CMD2 (DRAMC_NAO_BASE_ADDRESS + 0x03C8) + #define LAT_COUNTER_CMD2_LAT_CMD2_CNT_MAX Fld(16, 0) //[15:0] + #define LAT_COUNTER_CMD2_LAT_CMD2_CNT_MAX_HPRI Fld(1, 16) //[16:16] + #define LAT_COUNTER_CMD2_LAT_CMD2_CNT_MAX_LLAT Fld(1, 17) //[17:17] + #define LAT_COUNTER_CMD2_LAT_CMD2_CNT_MAX_REORDER Fld(1, 18) //[18:18] + +#define DRAMC_REG_LAT_COUNTER_CMD3 (DRAMC_NAO_BASE_ADDRESS + 0x03CC) + #define LAT_COUNTER_CMD3_LAT_CMD3_CNT_MAX Fld(16, 0) //[15:0] + #define LAT_COUNTER_CMD3_LAT_CMD3_CNT_MAX_HPRI Fld(1, 16) //[16:16] + #define LAT_COUNTER_CMD3_LAT_CMD3_CNT_MAX_LLAT Fld(1, 17) //[17:17] + #define LAT_COUNTER_CMD3_LAT_CMD3_CNT_MAX_REORDER Fld(1, 18) //[18:18] + +#define DRAMC_REG_LAT_COUNTER_CMD4 (DRAMC_NAO_BASE_ADDRESS + 0x03D0) + #define LAT_COUNTER_CMD4_LAT_CMD4_CNT_MAX Fld(16, 0) //[15:0] + #define LAT_COUNTER_CMD4_LAT_CMD4_CNT_MAX_HPRI Fld(1, 16) //[16:16] + #define LAT_COUNTER_CMD4_LAT_CMD4_CNT_MAX_LLAT Fld(1, 17) //[17:17] + #define LAT_COUNTER_CMD4_LAT_CMD4_CNT_MAX_REORDER Fld(1, 18) //[18:18] + +#define DRAMC_REG_LAT_COUNTER_CMD5 (DRAMC_NAO_BASE_ADDRESS + 0x03D4) + #define LAT_COUNTER_CMD5_LAT_CMD5_CNT_MAX Fld(16, 0) //[15:0] + #define LAT_COUNTER_CMD5_LAT_CMD5_CNT_MAX_HPRI Fld(1, 16) //[16:16] + #define LAT_COUNTER_CMD5_LAT_CMD5_CNT_MAX_LLAT Fld(1, 17) //[17:17] + #define LAT_COUNTER_CMD5_LAT_CMD5_CNT_MAX_REORDER Fld(1, 18) //[18:18] + +#define DRAMC_REG_LAT_COUNTER_CMD6 (DRAMC_NAO_BASE_ADDRESS + 0x03D8) + #define LAT_COUNTER_CMD6_LAT_CMD6_CNT_MAX Fld(16, 0) //[15:0] + #define LAT_COUNTER_CMD6_LAT_CMD6_CNT_MAX_HPRI Fld(1, 16) //[16:16] + #define LAT_COUNTER_CMD6_LAT_CMD6_CNT_MAX_LLAT Fld(1, 17) //[17:17] + #define LAT_COUNTER_CMD6_LAT_CMD6_CNT_MAX_REORDER Fld(1, 18) //[18:18] + +#define DRAMC_REG_LAT_COUNTER_CMD7 (DRAMC_NAO_BASE_ADDRESS + 0x03DC) + #define LAT_COUNTER_CMD7_LAT_CMD7_CNT_MAX Fld(16, 0) //[15:0] + #define LAT_COUNTER_CMD7_LAT_CMD7_CNT_MAX_HPRI Fld(1, 16) //[16:16] + #define LAT_COUNTER_CMD7_LAT_CMD7_CNT_MAX_LLAT Fld(1, 17) //[17:17] + #define LAT_COUNTER_CMD7_LAT_CMD7_CNT_MAX_REORDER Fld(1, 18) //[18:18] + +#define DRAMC_REG_LAT_COUNTER_AVER (DRAMC_NAO_BASE_ADDRESS + 0x03E0) + #define LAT_COUNTER_AVER_LAT_CMD_AVER_CNT Fld(32, 0) //[31:0] + +#define DRAMC_REG_LAT_COUNTER_NUM (DRAMC_NAO_BASE_ADDRESS + 0x03E4) + #define LAT_COUNTER_NUM_LAT_CMD_NUM Fld(16, 0) //[15:0] + +#define DRAMC_REG_LAT_COUNTER_BLOCK_ALE (DRAMC_NAO_BASE_ADDRESS + 0x03E8) + #define LAT_COUNTER_BLOCK_ALE_CTO_BLOCK_CNT_MAX Fld(16, 0) //[15:0] + +#define DRAMC_REG_DRAMC_LOOP_BAK_ADR (DRAMC_NAO_BASE_ADDRESS + 0x0504) + #define DRAMC_LOOP_BAK_ADR_TEST_WR_BK_ADR Fld(3, 0) //[2:0] + #define DRAMC_LOOP_BAK_ADR_TEST_WR_COL_ADR Fld(11, 3) //[13:3] + #define DRAMC_LOOP_BAK_ADR_TEST_WR_ROW_ADR Fld(18, 14) //[31:14] + +#define DRAMC_REG_DRAMC_LOOP_BAK_RK (DRAMC_NAO_BASE_ADDRESS + 0x0508) + #define DRAMC_LOOP_BAK_RK_TEST_WR_RK Fld(2, 0) //[1:0] + #define DRAMC_LOOP_BAK_RK_LOOP_BAK_ADR_CMP_FAIL Fld(1, 4) //[4:4] + +#define DRAMC_REG_DRAMC_LOOP_BAK_WDAT0 (DRAMC_NAO_BASE_ADDRESS + 0x0510) + #define DRAMC_LOOP_BAK_WDAT0_LOOP_BACK_WDAT0 Fld(32, 0) //[31:0] + +#define DRAMC_REG_DRAMC_LOOP_BAK_WDAT1 (DRAMC_NAO_BASE_ADDRESS + 0x0514) + #define DRAMC_LOOP_BAK_WDAT1_LOOP_BACK_WDAT1 Fld(32, 0) //[31:0] + +#define DRAMC_REG_DRAMC_LOOP_BAK_WDAT2 (DRAMC_NAO_BASE_ADDRESS + 0x0518) + #define DRAMC_LOOP_BAK_WDAT2_LOOP_BACK_WDAT2 Fld(32, 0) //[31:0] + +#define DRAMC_REG_DRAMC_LOOP_BAK_WDAT3 (DRAMC_NAO_BASE_ADDRESS + 0x051C) + #define DRAMC_LOOP_BAK_WDAT3_LOOP_BACK_WDAT3 Fld(32, 0) //[31:0] + +#define DRAMC_REG_DRAMC_LOOP_BAK_WDAT4 (DRAMC_NAO_BASE_ADDRESS + 0x0520) + #define DRAMC_LOOP_BAK_WDAT4_LOOP_BACK_WDAT4 Fld(32, 0) //[31:0] + +#define DRAMC_REG_DRAMC_LOOP_BAK_WDAT5 (DRAMC_NAO_BASE_ADDRESS + 0x0524) + #define DRAMC_LOOP_BAK_WDAT5_LOOP_BACK_WDAT5 Fld(32, 0) //[31:0] + +#define DRAMC_REG_DRAMC_LOOP_BAK_WDAT6 (DRAMC_NAO_BASE_ADDRESS + 0x0528) + #define DRAMC_LOOP_BAK_WDAT6_LOOP_BACK_WDAT6 Fld(32, 0) //[31:0] + +#define DRAMC_REG_DRAMC_LOOP_BAK_WDAT7 (DRAMC_NAO_BASE_ADDRESS + 0x052C) + #define DRAMC_LOOP_BAK_WDAT7_LOOP_BACK_WDAT7 Fld(32, 0) //[31:0] + +#define DRAMC_REG_RK0_DQSOSC_STATUS (DRAMC_NAO_BASE_ADDRESS + 0x0600) + #define RK0_DQSOSC_STATUS_MR18_REG Fld(16, 0) //[15:0] + #define RK0_DQSOSC_STATUS_MR19_REG Fld(16, 16) //[31:16] + +#define DRAMC_REG_RK0_DQSOSC_DELTA (DRAMC_NAO_BASE_ADDRESS + 0x0604) + #define RK0_DQSOSC_DELTA_ABS_RK0_DQSOSC_DELTA Fld(16, 0) //[15:0] + #define RK0_DQSOSC_DELTA_SIGN_RK0_DQSOSC_DELTA Fld(1, 16) //[16:16] + #define RK0_DQSOSC_DELTA_DQSOSCR_RESPONSE Fld(1, 17) //[17:17] + #define RK0_DQSOSC_DELTA_H_DQSOSCLSBR_REQ Fld(1, 18) //[18:18] + #define RK0_DQSOSC_DELTA_DQSOSC_INT_RK0 Fld(1, 19) //[19:19] + +#define DRAMC_REG_RK0_DQSOSC_DELTA2 (DRAMC_NAO_BASE_ADDRESS + 0x0608) + #define RK0_DQSOSC_DELTA2_ABS_RK0_DQSOSC_B1_DELTA Fld(16, 0) //[15:0] + #define RK0_DQSOSC_DELTA2_SIGN_RK0_DQSOSC_B1_DELTA Fld(1, 16) //[16:16] + +#define DRAMC_REG_RK0_CURRENT_TX_SETTING1 (DRAMC_NAO_BASE_ADDRESS + 0x0610) + #define RK0_CURRENT_TX_SETTING1_REG_TX_DLY_DQ0_MOD Fld(3, 0) //[2:0] + #define RK0_CURRENT_TX_SETTING1_REG_TX_DLY_DQ1_MOD Fld(3, 4) //[6:4] + #define RK0_CURRENT_TX_SETTING1_REG_TX_DLY_DQ2_MOD Fld(3, 8) //[10:8] + #define RK0_CURRENT_TX_SETTING1_REG_TX_DLY_DQ3_MOD Fld(3, 12) //[14:12] + #define RK0_CURRENT_TX_SETTING1_REG_TX_DLY_DQM0_MOD Fld(3, 16) //[18:16] + #define RK0_CURRENT_TX_SETTING1_REG_TX_DLY_DQM1_MOD Fld(3, 20) //[22:20] + #define RK0_CURRENT_TX_SETTING1_REG_TX_DLY_DQM2_MOD Fld(3, 24) //[26:24] + #define RK0_CURRENT_TX_SETTING1_REG_TX_DLY_DQM3_MOD Fld(3, 28) //[30:28] + +#define DRAMC_REG_RK0_CURRENT_TX_SETTING2 (DRAMC_NAO_BASE_ADDRESS + 0x0614) + #define RK0_CURRENT_TX_SETTING2_REG_DLY_DQ0_MOD Fld(3, 0) //[2:0] + #define RK0_CURRENT_TX_SETTING2_REG_DLY_DQ1_MOD Fld(3, 4) //[6:4] + #define RK0_CURRENT_TX_SETTING2_REG_DLY_DQ2_MOD Fld(3, 8) //[10:8] + #define RK0_CURRENT_TX_SETTING2_REG_DLY_DQ3_MOD Fld(3, 12) //[14:12] + #define RK0_CURRENT_TX_SETTING2_REG_DLY_DQM0_MOD Fld(3, 16) //[18:16] + #define RK0_CURRENT_TX_SETTING2_REG_DLY_DQM1_MOD Fld(3, 20) //[22:20] + #define RK0_CURRENT_TX_SETTING2_REG_DLY_DQM2_MOD Fld(3, 24) //[26:24] + #define RK0_CURRENT_TX_SETTING2_REG_DLY_DQM3_MOD Fld(3, 28) //[30:28] + +#define DRAMC_REG_RK0_CURRENT_TX_SETTING3 (DRAMC_NAO_BASE_ADDRESS + 0x0618) + #define RK0_CURRENT_TX_SETTING3_REG_TX_DLY_OEN_DQ0_MOD Fld(3, 0) //[2:0] + #define RK0_CURRENT_TX_SETTING3_REG_TX_DLY_OEN_DQ1_MOD Fld(3, 4) //[6:4] + #define RK0_CURRENT_TX_SETTING3_REG_TX_DLY_OEN_DQ2_MOD Fld(3, 8) //[10:8] + #define RK0_CURRENT_TX_SETTING3_REG_TX_DLY_OEN_DQ3_MOD Fld(3, 12) //[14:12] + #define RK0_CURRENT_TX_SETTING3_REG_TX_DLY_OEN_DQM0_MOD Fld(3, 16) //[18:16] + #define RK0_CURRENT_TX_SETTING3_REG_TX_DLY_OEN_DQM1_MOD Fld(3, 20) //[22:20] + #define RK0_CURRENT_TX_SETTING3_REG_TX_DLY_OEN_DQM2_MOD Fld(3, 24) //[26:24] + #define RK0_CURRENT_TX_SETTING3_REG_TX_DLY_OEN_DQM3_MOD Fld(3, 28) //[30:28] + +#define DRAMC_REG_RK0_CURRENT_TX_SETTING4 (DRAMC_NAO_BASE_ADDRESS + 0x061C) + #define RK0_CURRENT_TX_SETTING4_REG_DLY_OEN_DQ0_MOD Fld(3, 0) //[2:0] + #define RK0_CURRENT_TX_SETTING4_REG_DLY_OEN_DQ1_MOD Fld(3, 4) //[6:4] + #define RK0_CURRENT_TX_SETTING4_REG_DLY_OEN_DQ2_MOD Fld(3, 8) //[10:8] + #define RK0_CURRENT_TX_SETTING4_REG_DLY_OEN_DQ3_MOD Fld(3, 12) //[14:12] + #define RK0_CURRENT_TX_SETTING4_REG_DLY_OEN_DQM0_MOD Fld(3, 16) //[18:16] + #define RK0_CURRENT_TX_SETTING4_REG_DLY_OEN_DQM1_MOD Fld(3, 20) //[22:20] + #define RK0_CURRENT_TX_SETTING4_REG_DLY_OEN_DQM2_MOD Fld(3, 24) //[26:24] + #define RK0_CURRENT_TX_SETTING4_REG_DLY_OEN_DQM3_MOD Fld(3, 28) //[30:28] + +#define DRAMC_REG_RK0_DUMMY_RD_DATA0 (DRAMC_NAO_BASE_ADDRESS + 0x0620) + #define RK0_DUMMY_RD_DATA0_DUMMY_RD_RK0_DATA0 Fld(32, 0) //[31:0] + +#define DRAMC_REG_RK0_DUMMY_RD_DATA1 (DRAMC_NAO_BASE_ADDRESS + 0x0624) + #define RK0_DUMMY_RD_DATA1_DUMMY_RD_RK0_DATA1 Fld(32, 0) //[31:0] + +#define DRAMC_REG_RK0_DUMMY_RD_DATA2 (DRAMC_NAO_BASE_ADDRESS + 0x0628) + #define RK0_DUMMY_RD_DATA2_DUMMY_RD_RK0_DATA2 Fld(32, 0) //[31:0] + +#define DRAMC_REG_RK0_DUMMY_RD_DATA3 (DRAMC_NAO_BASE_ADDRESS + 0x062C) + #define RK0_DUMMY_RD_DATA3_DUMMY_RD_RK0_DATA3 Fld(32, 0) //[31:0] + +#define DRAMC_REG_RK0_DUMMY_RD_DATA4 (DRAMC_NAO_BASE_ADDRESS + 0x0630) + #define RK0_DUMMY_RD_DATA4_DUMMY_RD_RK0_DATA4 Fld(32, 0) //[31:0] + +#define DRAMC_REG_RK0_DUMMY_RD_DATA5 (DRAMC_NAO_BASE_ADDRESS + 0x0634) + #define RK0_DUMMY_RD_DATA5_DUMMY_RD_RK0_DATA5 Fld(32, 0) //[31:0] + +#define DRAMC_REG_RK0_DUMMY_RD_DATA6 (DRAMC_NAO_BASE_ADDRESS + 0x0638) + #define RK0_DUMMY_RD_DATA6_DUMMY_RD_RK0_DATA6 Fld(32, 0) //[31:0] + +#define DRAMC_REG_RK0_DUMMY_RD_DATA7 (DRAMC_NAO_BASE_ADDRESS + 0x063C) + #define RK0_DUMMY_RD_DATA7_DUMMY_RD_RK0_DATA7 Fld(32, 0) //[31:0] + +#define DRAMC_REG_RK0_PI_DQ_CAL (DRAMC_NAO_BASE_ADDRESS + 0x0660) + #define RK0_PI_DQ_CAL_RK0_ARPI_DQ_B0_CAL Fld(6, 0) //[5:0] + #define RK0_PI_DQ_CAL_RK0_ARPI_DQ_B1_CAL Fld(6, 8) //[13:8] + #define RK0_PI_DQ_CAL_PI_DQ_ADJ_RK0 Fld(6, 16) //[21:16] + #define RK0_PI_DQ_CAL_PI_DQ_ADJ_RK0_OVERFLOW Fld(1, 22) //[22:22] + #define RK0_PI_DQ_CAL_RK0_B0_PI_CHANGE_DBG Fld(1, 23) //[23:23] + #define RK0_PI_DQ_CAL_PI_DQ_ADJ_RK0_B1 Fld(6, 24) //[29:24] + #define RK0_PI_DQ_CAL_PI_DQ_ADJ_RK0_B1_OVERFLOW Fld(1, 30) //[30:30] + #define RK0_PI_DQ_CAL_RK0_B1_PI_CHANGE_DBG Fld(1, 31) //[31:31] + +#define DRAMC_REG_RK0_PI_DQM_CAL (DRAMC_NAO_BASE_ADDRESS + 0x0668) + #define RK0_PI_DQM_CAL_RK0_ARPI_DQM_B0_CAL Fld(6, 0) //[5:0] + #define RK0_PI_DQM_CAL_RK0_ARPI_DQM_B1_CAL Fld(6, 8) //[13:8] + +#define DRAMC_REG_RK1_DQSOSC_STATUS (DRAMC_NAO_BASE_ADDRESS + 0x0700) + #define RK1_DQSOSC_STATUS_MR18_RK1_REG Fld(16, 0) //[15:0] + #define RK1_DQSOSC_STATUS_MR19_RK1_REG Fld(16, 16) //[31:16] + +#define DRAMC_REG_RK1_DQSOSC_DELTA (DRAMC_NAO_BASE_ADDRESS + 0x0704) + #define RK1_DQSOSC_DELTA_ABS_RK1_DQSOSC_DELTA Fld(16, 0) //[15:0] + #define RK1_DQSOSC_DELTA_SIGN_RK1_DQSOSC_DELTA Fld(1, 16) //[16:16] + #define RK1_DQSOSC_DELTA_DQSOSCR_RK1_RESPONSE Fld(1, 17) //[17:17] + #define RK1_DQSOSC_DELTA_H_DQSOSCLSBR_RK1_REQ Fld(1, 18) //[18:18] + #define RK1_DQSOSC_DELTA_DQSOSC_INT_RK1 Fld(1, 19) //[19:19] + +#define DRAMC_REG_RK1_DQSOSC_DELTA2 (DRAMC_NAO_BASE_ADDRESS + 0x0708) + #define RK1_DQSOSC_DELTA2_ABS_RK1_DQSOSC_B1_DELTA Fld(16, 0) //[15:0] + #define RK1_DQSOSC_DELTA2_SIGN_RK1_DQSOSC_B1_DELTA Fld(1, 16) //[16:16] + +#define DRAMC_REG_RK1_CURRENT_TX_SETTING1 (DRAMC_NAO_BASE_ADDRESS + 0x0710) + #define RK1_CURRENT_TX_SETTING1_REG_TX_DLY_R1DQ0_MOD Fld(3, 0) //[2:0] + #define RK1_CURRENT_TX_SETTING1_REG_TX_DLY_R1DQ1_MOD Fld(3, 4) //[6:4] + #define RK1_CURRENT_TX_SETTING1_REG_TX_DLY_R1DQ2_MOD Fld(3, 8) //[10:8] + #define RK1_CURRENT_TX_SETTING1_REG_TX_DLY_R1DQ3_MOD Fld(3, 12) //[14:12] + #define RK1_CURRENT_TX_SETTING1_REG_TX_DLY_R1DQM0_MOD Fld(3, 16) //[18:16] + #define RK1_CURRENT_TX_SETTING1_REG_TX_DLY_R1DQM1_MOD Fld(3, 20) //[22:20] + #define RK1_CURRENT_TX_SETTING1_REG_TX_DLY_R1DQM2_MOD Fld(3, 24) //[26:24] + #define RK1_CURRENT_TX_SETTING1_REG_TX_DLY_R1DQM3_MOD Fld(3, 28) //[30:28] + +#define DRAMC_REG_RK1_CURRENT_TX_SETTING2 (DRAMC_NAO_BASE_ADDRESS + 0x0714) + #define RK1_CURRENT_TX_SETTING2_REG_DLY_R1DQ0_MOD Fld(3, 0) //[2:0] + #define RK1_CURRENT_TX_SETTING2_REG_DLY_R1DQ1_MOD Fld(3, 4) //[6:4] + #define RK1_CURRENT_TX_SETTING2_REG_DLY_R1DQ2_MOD Fld(3, 8) //[10:8] + #define RK1_CURRENT_TX_SETTING2_REG_DLY_R1DQ3_MOD Fld(3, 12) //[14:12] + #define RK1_CURRENT_TX_SETTING2_REG_DLY_R1DQM0_MOD Fld(3, 16) //[18:16] + #define RK1_CURRENT_TX_SETTING2_REG_DLY_R1DQM1_MOD Fld(3, 20) //[22:20] + #define RK1_CURRENT_TX_SETTING2_REG_DLY_R1DQM2_MOD Fld(3, 24) //[26:24] + #define RK1_CURRENT_TX_SETTING2_REG_DLY_R1DQM3_MOD Fld(3, 28) //[30:28] + +#define DRAMC_REG_RK1_CURRENT_TX_SETTING3 (DRAMC_NAO_BASE_ADDRESS + 0x0718) + #define RK1_CURRENT_TX_SETTING3_REG_TX_DLY_OEN_R1DQ0_MOD Fld(3, 0) //[2:0] + #define RK1_CURRENT_TX_SETTING3_REG_TX_DLY_OEN_R1DQ1_MOD Fld(3, 4) //[6:4] + #define RK1_CURRENT_TX_SETTING3_REG_TX_DLY_OEN_R1DQ2_MOD Fld(3, 8) //[10:8] + #define RK1_CURRENT_TX_SETTING3_REG_TX_DLY_OEN_R1DQ3_MOD Fld(3, 12) //[14:12] + #define RK1_CURRENT_TX_SETTING3_REG_TX_DLY_OEN_R1DQM0_MOD Fld(3, 16) //[18:16] + #define RK1_CURRENT_TX_SETTING3_REG_TX_DLY_OEN_R1DQM1_MOD Fld(3, 20) //[22:20] + #define RK1_CURRENT_TX_SETTING3_REG_TX_DLY_OEN_R1DQM2_MOD Fld(3, 24) //[26:24] + #define RK1_CURRENT_TX_SETTING3_REG_TX_DLY_OEN_R1DQM3_MOD Fld(3, 28) //[30:28] + +#define DRAMC_REG_RK1_CURRENT_TX_SETTING4 (DRAMC_NAO_BASE_ADDRESS + 0x071C) + #define RK1_CURRENT_TX_SETTING4_REG_DLY_OEN_R1DQ0_MOD Fld(3, 0) //[2:0] + #define RK1_CURRENT_TX_SETTING4_REG_DLY_OEN_R1DQ1_MOD Fld(3, 4) //[6:4] + #define RK1_CURRENT_TX_SETTING4_REG_DLY_OEN_R1DQ2_MOD Fld(3, 8) //[10:8] + #define RK1_CURRENT_TX_SETTING4_REG_DLY_OEN_R1DQ3_MOD Fld(3, 12) //[14:12] + #define RK1_CURRENT_TX_SETTING4_REG_DLY_OEN_R1DQM0_MOD Fld(3, 16) //[18:16] + #define RK1_CURRENT_TX_SETTING4_REG_DLY_OEN_R1DQM1_MOD Fld(3, 20) //[22:20] + #define RK1_CURRENT_TX_SETTING4_REG_DLY_OEN_R1DQM2_MOD Fld(3, 24) //[26:24] + #define RK1_CURRENT_TX_SETTING4_REG_DLY_OEN_R1DQM3_MOD Fld(3, 28) //[30:28] + +#define DRAMC_REG_RK1_DUMMY_RD_DATA0 (DRAMC_NAO_BASE_ADDRESS + 0x0720) + #define RK1_DUMMY_RD_DATA0_DUMMY_RD_RK1_DATA0 Fld(32, 0) //[31:0] + +#define DRAMC_REG_RK1_DUMMY_RD_DATA1 (DRAMC_NAO_BASE_ADDRESS + 0x0724) + #define RK1_DUMMY_RD_DATA1_DUMMY_RD_RK1_DATA1 Fld(32, 0) //[31:0] + +#define DRAMC_REG_RK1_DUMMY_RD_DATA2 (DRAMC_NAO_BASE_ADDRESS + 0x0728) + #define RK1_DUMMY_RD_DATA2_DUMMY_RD_RK1_DATA2 Fld(32, 0) //[31:0] + +#define DRAMC_REG_RK1_DUMMY_RD_DATA3 (DRAMC_NAO_BASE_ADDRESS + 0x072C) + #define RK1_DUMMY_RD_DATA3_DUMMY_RD_RK1_DATA3 Fld(32, 0) //[31:0] + +#define DRAMC_REG_RK1_DUMMY_RD_DATA4 (DRAMC_NAO_BASE_ADDRESS + 0x0730) + #define RK1_DUMMY_RD_DATA4_DUMMY_RD_RK1_DATA4 Fld(32, 0) //[31:0] + +#define DRAMC_REG_RK1_DUMMY_RD_DATA5 (DRAMC_NAO_BASE_ADDRESS + 0x0734) + #define RK1_DUMMY_RD_DATA5_DUMMY_RD_RK1_DATA5 Fld(32, 0) //[31:0] + +#define DRAMC_REG_RK1_DUMMY_RD_DATA6 (DRAMC_NAO_BASE_ADDRESS + 0x0738) + #define RK1_DUMMY_RD_DATA6_DUMMY_RD_RK1_DATA6 Fld(32, 0) //[31:0] + +#define DRAMC_REG_RK1_DUMMY_RD_DATA7 (DRAMC_NAO_BASE_ADDRESS + 0x073C) + #define RK1_DUMMY_RD_DATA7_DUMMY_RD_RK1_DATA7 Fld(32, 0) //[31:0] + +#define DRAMC_REG_RK1_PI_DQ_CAL (DRAMC_NAO_BASE_ADDRESS + 0x0760) + #define RK1_PI_DQ_CAL_RK1_ARPI_DQ_B0_CAL Fld(6, 0) //[5:0] + #define RK1_PI_DQ_CAL_RK1_ARPI_DQ_B1_CAL Fld(6, 8) //[13:8] + #define RK1_PI_DQ_CAL_PI_DQ_ADJ_RK1 Fld(6, 16) //[21:16] + #define RK1_PI_DQ_CAL_PI_DQ_ADJ_RK1_OVERFLOW Fld(1, 22) //[22:22] + #define RK1_PI_DQ_CAL_RK1_B0_PI_CHANGE_DBG Fld(1, 23) //[23:23] + #define RK1_PI_DQ_CAL_PI_DQ_ADJ_RK1_B1 Fld(6, 24) //[29:24] + #define RK1_PI_DQ_CAL_PI_DQ_ADJ_RK1_B1_OVERFLOW Fld(1, 30) //[30:30] + #define RK1_PI_DQ_CAL_RK1_B1_PI_CHANGE_DBG Fld(1, 31) //[31:31] + +#define DRAMC_REG_RK1_PI_DQM_CAL (DRAMC_NAO_BASE_ADDRESS + 0x0768) + #define RK1_PI_DQM_CAL_RK1_ARPI_DQM_B0_CAL Fld(6, 0) //[5:0] + #define RK1_PI_DQM_CAL_RK1_ARPI_DQM_B1_CAL Fld(6, 8) //[13:8] + +#define DRAMC_REG_MR_BACKUP_00_RK0_FSP0 (DRAMC_NAO_BASE_ADDRESS + 0x0900) + #define MR_BACKUP_00_RK0_FSP0_MRWBK_RK0_FSP0_MR1 Fld(8, 0) //[7:0] + #define MR_BACKUP_00_RK0_FSP0_MRWBK_RK0_FSP0_MR2 Fld(8, 8) //[15:8] + #define MR_BACKUP_00_RK0_FSP0_MRWBK_RK0_FSP0_MR3 Fld(8, 16) //[23:16] + #define MR_BACKUP_00_RK0_FSP0_MRWBK_RK0_FSP0_MR4 Fld(8, 24) //[31:24] + +#define DRAMC_REG_MR_BACKUP_01_RK0_FSP0 (DRAMC_NAO_BASE_ADDRESS + 0x0904) + #define MR_BACKUP_01_RK0_FSP0_MRWBK_RK0_FSP0_MR9 Fld(8, 0) //[7:0] + #define MR_BACKUP_01_RK0_FSP0_MRWBK_RK0_FSP0_MR10 Fld(8, 8) //[15:8] + #define MR_BACKUP_01_RK0_FSP0_MRWBK_RK0_FSP0_MR11 Fld(8, 16) //[23:16] + #define MR_BACKUP_01_RK0_FSP0_MRWBK_RK0_FSP0_MR12 Fld(8, 24) //[31:24] + +#define DRAMC_REG_MR_BACKUP_02_RK0_FSP0 (DRAMC_NAO_BASE_ADDRESS + 0x0908) + #define MR_BACKUP_02_RK0_FSP0_MRWBK_RK0_FSP0_MR13 Fld(8, 0) //[7:0] + #define MR_BACKUP_02_RK0_FSP0_MRWBK_RK0_FSP0_MR14 Fld(8, 8) //[15:8] + #define MR_BACKUP_02_RK0_FSP0_MRWBK_RK0_FSP0_MR15 Fld(8, 16) //[23:16] + #define MR_BACKUP_02_RK0_FSP0_MRWBK_RK0_FSP0_MR16 Fld(8, 24) //[31:24] + +#define DRAMC_REG_MR_BACKUP_03_RK0_FSP0 (DRAMC_NAO_BASE_ADDRESS + 0x090C) + #define MR_BACKUP_03_RK0_FSP0_MRWBK_RK0_FSP0_MR17 Fld(8, 0) //[7:0] + #define MR_BACKUP_03_RK0_FSP0_MRWBK_RK0_FSP0_MR18 Fld(8, 8) //[15:8] + #define MR_BACKUP_03_RK0_FSP0_MRWBK_RK0_FSP0_MR19 Fld(8, 16) //[23:16] + #define MR_BACKUP_03_RK0_FSP0_MRWBK_RK0_FSP0_MR20 Fld(8, 24) //[31:24] + +#define DRAMC_REG_MR_BACKUP_04_RK0_FSP0 (DRAMC_NAO_BASE_ADDRESS + 0x0910) + #define MR_BACKUP_04_RK0_FSP0_MRWBK_RK0_FSP0_MR21 Fld(8, 0) //[7:0] + #define MR_BACKUP_04_RK0_FSP0_MRWBK_RK0_FSP0_MR22 Fld(8, 8) //[15:8] + #define MR_BACKUP_04_RK0_FSP0_MRWBK_RK0_FSP0_MR23 Fld(8, 16) //[23:16] + #define MR_BACKUP_04_RK0_FSP0_MRWBK_RK0_FSP0_MR24 Fld(8, 24) //[31:24] + +#define DRAMC_REG_MR_BACKUP_05_RK0_FSP0 (DRAMC_NAO_BASE_ADDRESS + 0x0914) + #define MR_BACKUP_05_RK0_FSP0_MRWBK_RK0_FSP0_MR25 Fld(8, 0) //[7:0] + #define MR_BACKUP_05_RK0_FSP0_MRWBK_RK0_FSP0_MR26 Fld(8, 8) //[15:8] + #define MR_BACKUP_05_RK0_FSP0_MRWBK_RK0_FSP0_MR27 Fld(8, 16) //[23:16] + #define MR_BACKUP_05_RK0_FSP0_MRWBK_RK0_FSP0_MR28 Fld(8, 24) //[31:24] + +#define DRAMC_REG_MR_BACKUP_06_RK0_FSP0 (DRAMC_NAO_BASE_ADDRESS + 0x0918) + #define MR_BACKUP_06_RK0_FSP0_MRWBK_RK0_FSP0_MR30 Fld(8, 0) //[7:0] + #define MR_BACKUP_06_RK0_FSP0_MRWBK_RK0_FSP0_MR31 Fld(8, 8) //[15:8] + #define MR_BACKUP_06_RK0_FSP0_MRWBK_RK0_FSP0_MR32 Fld(8, 16) //[23:16] + #define MR_BACKUP_06_RK0_FSP0_MRWBK_RK0_FSP0_MR33 Fld(8, 24) //[31:24] + +#define DRAMC_REG_MR_BACKUP_07_RK0_FSP0 (DRAMC_NAO_BASE_ADDRESS + 0x091C) + #define MR_BACKUP_07_RK0_FSP0_MRWBK_RK0_FSP0_MR34 Fld(8, 0) //[7:0] + #define MR_BACKUP_07_RK0_FSP0_MRWBK_RK0_FSP0_MR37 Fld(8, 8) //[15:8] + #define MR_BACKUP_07_RK0_FSP0_MRWBK_RK0_FSP0_MR39 Fld(8, 16) //[23:16] + #define MR_BACKUP_07_RK0_FSP0_MRWBK_RK0_FSP0_MR40 Fld(8, 24) //[31:24] + +#define DRAMC_REG_MR_BACKUP_08_RK0_FSP0 (DRAMC_NAO_BASE_ADDRESS + 0x0920) + #define MR_BACKUP_08_RK0_FSP0_MRWBK_RK0_FSP0_MR41 Fld(8, 0) //[7:0] + #define MR_BACKUP_08_RK0_FSP0_MRWBK_RK0_FSP0_MR42 Fld(8, 8) //[15:8] + #define MR_BACKUP_08_RK0_FSP0_MRWBK_RK0_FSP0_MR46 Fld(8, 16) //[23:16] + #define MR_BACKUP_08_RK0_FSP0_MRWBK_RK0_FSP0_MR48 Fld(8, 24) //[31:24] + +#define DRAMC_REG_MR_BACKUP_09_RK0_FSP0 (DRAMC_NAO_BASE_ADDRESS + 0x0924) + #define MR_BACKUP_09_RK0_FSP0_MRWBK_RK0_FSP0_MR63 Fld(8, 0) //[7:0] + #define MR_BACKUP_09_RK0_FSP0_MRWBK_RK0_FSP0_MR51 Fld(8, 8) //[15:8] + +#define DRAMC_REG_MR_BACKUP_00_RK0_FSP1 (DRAMC_NAO_BASE_ADDRESS + 0x0930) + #define MR_BACKUP_00_RK0_FSP1_MRWBK_RK0_FSP1_MR1 Fld(8, 0) //[7:0] + #define MR_BACKUP_00_RK0_FSP1_MRWBK_RK0_FSP1_MR2 Fld(8, 8) //[15:8] + #define MR_BACKUP_00_RK0_FSP1_MRWBK_RK0_FSP1_MR3 Fld(8, 16) //[23:16] + #define MR_BACKUP_00_RK0_FSP1_MRWBK_RK0_FSP1_MR10 Fld(8, 24) //[31:24] + +#define DRAMC_REG_MR_BACKUP_01_RK0_FSP1 (DRAMC_NAO_BASE_ADDRESS + 0x0934) + #define MR_BACKUP_01_RK0_FSP1_MRWBK_RK0_FSP1_MR11 Fld(8, 0) //[7:0] + #define MR_BACKUP_01_RK0_FSP1_MRWBK_RK0_FSP1_MR12 Fld(8, 8) //[15:8] + #define MR_BACKUP_01_RK0_FSP1_MRWBK_RK0_FSP1_MR14 Fld(8, 16) //[23:16] + #define MR_BACKUP_01_RK0_FSP1_MRWBK_RK0_FSP1_MR15 Fld(8, 24) //[31:24] + +#define DRAMC_REG_MR_BACKUP_02_RK0_FSP1 (DRAMC_NAO_BASE_ADDRESS + 0x0938) + #define MR_BACKUP_02_RK0_FSP1_MRWBK_RK0_FSP1_MR17 Fld(8, 0) //[7:0] + #define MR_BACKUP_02_RK0_FSP1_MRWBK_RK0_FSP1_MR18 Fld(8, 8) //[15:8] + #define MR_BACKUP_02_RK0_FSP1_MRWBK_RK0_FSP1_MR19 Fld(8, 16) //[23:16] + #define MR_BACKUP_02_RK0_FSP1_MRWBK_RK0_FSP1_MR20 Fld(8, 24) //[31:24] + +#define DRAMC_REG_MR_BACKUP_03_RK0_FSP1 (DRAMC_NAO_BASE_ADDRESS + 0x093C) + #define MR_BACKUP_03_RK0_FSP1_MRWBK_RK0_FSP1_MR22 Fld(8, 0) //[7:0] + #define MR_BACKUP_03_RK0_FSP1_MRWBK_RK0_FSP1_MR24 Fld(8, 8) //[15:8] + #define MR_BACKUP_03_RK0_FSP1_MRWBK_RK0_FSP1_MR30 Fld(8, 16) //[23:16] + #define MR_BACKUP_03_RK0_FSP1_MRWBK_RK0_FSP1_MR41 Fld(8, 24) //[31:24] + +#define DRAMC_REG_MR_BACKUP_04_RK0_FSP1 (DRAMC_NAO_BASE_ADDRESS + 0x0940) + #define MR_BACKUP_04_RK0_FSP1_MRWBK_RK0_FSP1_MR21 Fld(8, 0) //[7:0] + #define MR_BACKUP_04_RK0_FSP1_MRWBK_RK0_FSP1_MR51 Fld(8, 8) //[15:8] + +#define DRAMC_REG_MR_BACKUP_00_RK0_FSP2 (DRAMC_NAO_BASE_ADDRESS + 0x0960) + #define MR_BACKUP_00_RK0_FSP2_MRWBK_RK0_FSP2_MR1 Fld(8, 0) //[7:0] + #define MR_BACKUP_00_RK0_FSP2_MRWBK_RK0_FSP2_MR2 Fld(8, 8) //[15:8] + #define MR_BACKUP_00_RK0_FSP2_MRWBK_RK0_FSP2_MR3 Fld(8, 16) //[23:16] + #define MR_BACKUP_00_RK0_FSP2_MRWBK_RK0_FSP2_MR10 Fld(8, 24) //[31:24] + +#define DRAMC_REG_MR_BACKUP_01_RK0_FSP2 (DRAMC_NAO_BASE_ADDRESS + 0x0964) + #define MR_BACKUP_01_RK0_FSP2_MRWBK_RK0_FSP2_MR11 Fld(8, 0) //[7:0] + #define MR_BACKUP_01_RK0_FSP2_MRWBK_RK0_FSP2_MR12 Fld(8, 8) //[15:8] + #define MR_BACKUP_01_RK0_FSP2_MRWBK_RK0_FSP2_MR14 Fld(8, 16) //[23:16] + #define MR_BACKUP_01_RK0_FSP2_MRWBK_RK0_FSP2_MR15 Fld(8, 24) //[31:24] + +#define DRAMC_REG_MR_BACKUP_02_RK0_FSP2 (DRAMC_NAO_BASE_ADDRESS + 0x0968) + #define MR_BACKUP_02_RK0_FSP2_MRWBK_RK0_FSP2_MR17 Fld(8, 0) //[7:0] + #define MR_BACKUP_02_RK0_FSP2_MRWBK_RK0_FSP2_MR18 Fld(8, 8) //[15:8] + #define MR_BACKUP_02_RK0_FSP2_MRWBK_RK0_FSP2_MR19 Fld(8, 16) //[23:16] + #define MR_BACKUP_02_RK0_FSP2_MRWBK_RK0_FSP2_MR20 Fld(8, 24) //[31:24] + +#define DRAMC_REG_MR_BACKUP_03_RK0_FSP2 (DRAMC_NAO_BASE_ADDRESS + 0x096C) + #define MR_BACKUP_03_RK0_FSP2_MRWBK_RK0_FSP2_MR24 Fld(8, 0) //[7:0] + #define MR_BACKUP_03_RK0_FSP2_MRWBK_RK0_FSP2_MR30 Fld(8, 8) //[15:8] + #define MR_BACKUP_03_RK0_FSP2_MRWBK_RK0_FSP2_MR41 Fld(8, 16) //[23:16] + +#define DRAMC_REG_MR_BACKUP_00_RK1_FSP0 (DRAMC_NAO_BASE_ADDRESS + 0x0B00) + #define MR_BACKUP_00_RK1_FSP0_MRWBK_RK1_FSP0_MR1 Fld(8, 0) //[7:0] + #define MR_BACKUP_00_RK1_FSP0_MRWBK_RK1_FSP0_MR2 Fld(8, 8) //[15:8] + #define MR_BACKUP_00_RK1_FSP0_MRWBK_RK1_FSP0_MR3 Fld(8, 16) //[23:16] + #define MR_BACKUP_00_RK1_FSP0_MRWBK_RK1_FSP0_MR4 Fld(8, 24) //[31:24] + +#define DRAMC_REG_MR_BACKUP_01_RK1_FSP0 (DRAMC_NAO_BASE_ADDRESS + 0x0B04) + #define MR_BACKUP_01_RK1_FSP0_MRWBK_RK1_FSP0_MR9 Fld(8, 0) //[7:0] + #define MR_BACKUP_01_RK1_FSP0_MRWBK_RK1_FSP0_MR10 Fld(8, 8) //[15:8] + #define MR_BACKUP_01_RK1_FSP0_MRWBK_RK1_FSP0_MR11 Fld(8, 16) //[23:16] + #define MR_BACKUP_01_RK1_FSP0_MRWBK_RK1_FSP0_MR12 Fld(8, 24) //[31:24] + +#define DRAMC_REG_MR_BACKUP_02_RK1_FSP0 (DRAMC_NAO_BASE_ADDRESS + 0x0B08) + #define MR_BACKUP_02_RK1_FSP0_MRWBK_RK1_FSP0_MR13 Fld(8, 0) //[7:0] + #define MR_BACKUP_02_RK1_FSP0_MRWBK_RK1_FSP0_MR14 Fld(8, 8) //[15:8] + #define MR_BACKUP_02_RK1_FSP0_MRWBK_RK1_FSP0_MR15 Fld(8, 16) //[23:16] + #define MR_BACKUP_02_RK1_FSP0_MRWBK_RK1_FSP0_MR16 Fld(8, 24) //[31:24] + +#define DRAMC_REG_MR_BACKUP_03_RK1_FSP0 (DRAMC_NAO_BASE_ADDRESS + 0x0B0C) + #define MR_BACKUP_03_RK1_FSP0_MRWBK_RK1_FSP0_MR17 Fld(8, 0) //[7:0] + #define MR_BACKUP_03_RK1_FSP0_MRWBK_RK1_FSP0_MR18 Fld(8, 8) //[15:8] + #define MR_BACKUP_03_RK1_FSP0_MRWBK_RK1_FSP0_MR19 Fld(8, 16) //[23:16] + #define MR_BACKUP_03_RK1_FSP0_MRWBK_RK1_FSP0_MR20 Fld(8, 24) //[31:24] + +#define DRAMC_REG_MR_BACKUP_04_RK1_FSP0 (DRAMC_NAO_BASE_ADDRESS + 0x0B10) + #define MR_BACKUP_04_RK1_FSP0_MRWBK_RK1_FSP0_MR21 Fld(8, 0) //[7:0] + #define MR_BACKUP_04_RK1_FSP0_MRWBK_RK1_FSP0_MR22 Fld(8, 8) //[15:8] + #define MR_BACKUP_04_RK1_FSP0_MRWBK_RK1_FSP0_MR23 Fld(8, 16) //[23:16] + #define MR_BACKUP_04_RK1_FSP0_MRWBK_RK1_FSP0_MR24 Fld(8, 24) //[31:24] + +#define DRAMC_REG_MR_BACKUP_05_RK1_FSP0 (DRAMC_NAO_BASE_ADDRESS + 0x0B14) + #define MR_BACKUP_05_RK1_FSP0_MRWBK_RK1_FSP0_MR25 Fld(8, 0) //[7:0] + #define MR_BACKUP_05_RK1_FSP0_MRWBK_RK1_FSP0_MR26 Fld(8, 8) //[15:8] + #define MR_BACKUP_05_RK1_FSP0_MRWBK_RK1_FSP0_MR27 Fld(8, 16) //[23:16] + #define MR_BACKUP_05_RK1_FSP0_MRWBK_RK1_FSP0_MR28 Fld(8, 24) //[31:24] + +#define DRAMC_REG_MR_BACKUP_06_RK1_FSP0 (DRAMC_NAO_BASE_ADDRESS + 0x0B18) + #define MR_BACKUP_06_RK1_FSP0_MRWBK_RK1_FSP0_MR30 Fld(8, 0) //[7:0] + #define MR_BACKUP_06_RK1_FSP0_MRWBK_RK1_FSP0_MR31 Fld(8, 8) //[15:8] + #define MR_BACKUP_06_RK1_FSP0_MRWBK_RK1_FSP0_MR32 Fld(8, 16) //[23:16] + #define MR_BACKUP_06_RK1_FSP0_MRWBK_RK1_FSP0_MR33 Fld(8, 24) //[31:24] + +#define DRAMC_REG_MR_BACKUP_07_RK1_FSP0 (DRAMC_NAO_BASE_ADDRESS + 0x0B1C) + #define MR_BACKUP_07_RK1_FSP0_MRWBK_RK1_FSP0_MR34 Fld(8, 0) //[7:0] + #define MR_BACKUP_07_RK1_FSP0_MRWBK_RK1_FSP0_MR37 Fld(8, 8) //[15:8] + #define MR_BACKUP_07_RK1_FSP0_MRWBK_RK1_FSP0_MR39 Fld(8, 16) //[23:16] + #define MR_BACKUP_07_RK1_FSP0_MRWBK_RK1_FSP0_MR40 Fld(8, 24) //[31:24] + +#define DRAMC_REG_MR_BACKUP_08_RK1_FSP0 (DRAMC_NAO_BASE_ADDRESS + 0x0B20) + #define MR_BACKUP_08_RK1_FSP0_MRWBK_RK1_FSP0_MR41 Fld(8, 0) //[7:0] + #define MR_BACKUP_08_RK1_FSP0_MRWBK_RK1_FSP0_MR42 Fld(8, 8) //[15:8] + #define MR_BACKUP_08_RK1_FSP0_MRWBK_RK1_FSP0_MR46 Fld(8, 16) //[23:16] + #define MR_BACKUP_08_RK1_FSP0_MRWBK_RK1_FSP0_MR48 Fld(8, 24) //[31:24] + +#define DRAMC_REG_MR_BACKUP_09_RK1_FSP0 (DRAMC_NAO_BASE_ADDRESS + 0x0B24) + #define MR_BACKUP_09_RK1_FSP0_MRWBK_RK1_FSP0_MR63 Fld(8, 0) //[7:0] + #define MR_BACKUP_09_RK1_FSP0_MRWBK_RK1_FSP0_MR51 Fld(8, 8) //[15:8] + +#define DRAMC_REG_MR_BACKUP_00_RK1_FSP1 (DRAMC_NAO_BASE_ADDRESS + 0x0B30) + #define MR_BACKUP_00_RK1_FSP1_MRWBK_RK1_FSP1_MR1 Fld(8, 0) //[7:0] + #define MR_BACKUP_00_RK1_FSP1_MRWBK_RK1_FSP1_MR2 Fld(8, 8) //[15:8] + #define MR_BACKUP_00_RK1_FSP1_MRWBK_RK1_FSP1_MR3 Fld(8, 16) //[23:16] + #define MR_BACKUP_00_RK1_FSP1_MRWBK_RK1_FSP1_MR10 Fld(8, 24) //[31:24] + +#define DRAMC_REG_MR_BACKUP_01_RK1_FSP1 (DRAMC_NAO_BASE_ADDRESS + 0x0B34) + #define MR_BACKUP_01_RK1_FSP1_MRWBK_RK1_FSP1_MR11 Fld(8, 0) //[7:0] + #define MR_BACKUP_01_RK1_FSP1_MRWBK_RK1_FSP1_MR12 Fld(8, 8) //[15:8] + #define MR_BACKUP_01_RK1_FSP1_MRWBK_RK1_FSP1_MR14 Fld(8, 16) //[23:16] + #define MR_BACKUP_01_RK1_FSP1_MRWBK_RK1_FSP1_MR15 Fld(8, 24) //[31:24] + +#define DRAMC_REG_MR_BACKUP_02_RK1_FSP1 (DRAMC_NAO_BASE_ADDRESS + 0x0B38) + #define MR_BACKUP_02_RK1_FSP1_MRWBK_RK1_FSP1_MR17 Fld(8, 0) //[7:0] + #define MR_BACKUP_02_RK1_FSP1_MRWBK_RK1_FSP1_MR18 Fld(8, 8) //[15:8] + #define MR_BACKUP_02_RK1_FSP1_MRWBK_RK1_FSP1_MR19 Fld(8, 16) //[23:16] + #define MR_BACKUP_02_RK1_FSP1_MRWBK_RK1_FSP1_MR20 Fld(8, 24) //[31:24] + +#define DRAMC_REG_MR_BACKUP_03_RK1_FSP1 (DRAMC_NAO_BASE_ADDRESS + 0x0B3C) + #define MR_BACKUP_03_RK1_FSP1_MRWBK_RK1_FSP1_MR22 Fld(8, 0) //[7:0] + #define MR_BACKUP_03_RK1_FSP1_MRWBK_RK1_FSP1_MR24 Fld(8, 8) //[15:8] + #define MR_BACKUP_03_RK1_FSP1_MRWBK_RK1_FSP1_MR30 Fld(8, 16) //[23:16] + #define MR_BACKUP_03_RK1_FSP1_MRWBK_RK1_FSP1_MR41 Fld(8, 24) //[31:24] + +#define DRAMC_REG_MR_BACKUP_04_RK1_FSP1 (DRAMC_NAO_BASE_ADDRESS + 0x0B40) + #define MR_BACKUP_04_RK1_FSP1_MRWBK_RK1_FSP1_MR21 Fld(8, 0) //[7:0] + #define MR_BACKUP_04_RK1_FSP1_MRWBK_RK1_FSP1_MR51 Fld(8, 8) //[15:8] + +#define DRAMC_REG_MR_BACKUP_00_RK1_FSP2 (DRAMC_NAO_BASE_ADDRESS + 0x0B60) + #define MR_BACKUP_00_RK1_FSP2_MRWBK_RK1_FSP2_MR1 Fld(8, 0) //[7:0] + #define MR_BACKUP_00_RK1_FSP2_MRWBK_RK1_FSP2_MR2 Fld(8, 8) //[15:8] + #define MR_BACKUP_00_RK1_FSP2_MRWBK_RK1_FSP2_MR3 Fld(8, 16) //[23:16] + #define MR_BACKUP_00_RK1_FSP2_MRWBK_RK1_FSP2_MR10 Fld(8, 24) //[31:24] + +#define DRAMC_REG_MR_BACKUP_01_RK1_FSP2 (DRAMC_NAO_BASE_ADDRESS + 0x0B64) + #define MR_BACKUP_01_RK1_FSP2_MRWBK_RK1_FSP2_MR11 Fld(8, 0) //[7:0] + #define MR_BACKUP_01_RK1_FSP2_MRWBK_RK1_FSP2_MR12 Fld(8, 8) //[15:8] + #define MR_BACKUP_01_RK1_FSP2_MRWBK_RK1_FSP2_MR14 Fld(8, 16) //[23:16] + #define MR_BACKUP_01_RK1_FSP2_MRWBK_RK1_FSP2_MR15 Fld(8, 24) //[31:24] + +#define DRAMC_REG_MR_BACKUP_02_RK1_FSP2 (DRAMC_NAO_BASE_ADDRESS + 0x0B68) + #define MR_BACKUP_02_RK1_FSP2_MRWBK_RK1_FSP2_MR17 Fld(8, 0) //[7:0] + #define MR_BACKUP_02_RK1_FSP2_MRWBK_RK1_FSP2_MR18 Fld(8, 8) //[15:8] + #define MR_BACKUP_02_RK1_FSP2_MRWBK_RK1_FSP2_MR19 Fld(8, 16) //[23:16] + #define MR_BACKUP_02_RK1_FSP2_MRWBK_RK1_FSP2_MR20 Fld(8, 24) //[31:24] + +#define DRAMC_REG_MR_BACKUP_03_RK1_FSP2 (DRAMC_NAO_BASE_ADDRESS + 0x0B6C) + #define MR_BACKUP_03_RK1_FSP2_MRWBK_RK1_FSP2_MR24 Fld(8, 0) //[7:0] + #define MR_BACKUP_03_RK1_FSP2_MRWBK_RK1_FSP2_MR30 Fld(8, 8) //[15:8] + #define MR_BACKUP_03_RK1_FSP2_MRWBK_RK1_FSP2_MR41 Fld(8, 16) //[23:16] + +#endif // __DRAMC_NAO_REGS_H__ diff --git a/src/vendorcode/mediatek/mt8192/include/addressmap.h b/src/vendorcode/mediatek/mt8192/include/addressmap.h new file mode 100644 index 000000000000..85402d0010e3 --- /dev/null +++ b/src/vendorcode/mediatek/mt8192/include/addressmap.h @@ -0,0 +1,12 @@ +/* SPDX-License-Identifier: BSD-3-Clause */ + +#ifndef ADDRESSMAP_H +#define ADDRESSMAP_H + +#include <soc/addressmap.h> + +enum { + PWRAP_BASE = IO_PHYS + 0x00026000, +}; + +#endif diff --git a/src/vendorcode/mediatek/mt8192/include/custom_emi.h b/src/vendorcode/mediatek/mt8192/include/custom_emi.h new file mode 100644 index 000000000000..c8cf32598c7e --- /dev/null +++ b/src/vendorcode/mediatek/mt8192/include/custom_emi.h @@ -0,0 +1,227 @@ +/* SPDX-License-Identifier: BSD-3-Clause */ + +#ifndef __CUSTOM_EMI__ +#define __CUSTOM_EMI__ + +#define __ETT__ 0 + +#include "dramc_pi_api.h" +#include "emi.h" + +#define MT29VZZZBD9DQKPR + +#ifdef MT29VZZZBD9DQKPR +EMI_SETTINGS default_emi_setting = +//MT29VZZZBD9DQKPR +{ + 0x1, /* sub_version */ + 0x0206, /* TYPE */ + 9, /* EMMC ID/FW ID checking length */ + 0, /* FW length */ + {0x13,0x01,0x4E,0x53,0x30,0x4A,0x39,0x4D,0x39,0x0,0x0,0x0,0x0,0x0,0x0,0x0}, /* NAND_EMMC_ID */ + {0x0,0x0,0x0,0x0,0x0,0x0,0x0,0x0}, /* FW_ID */ + 0x3530154, /* EMI_CONA_VAL */ + 0x66660033, /* EMI_CONH_VAL */ + .DRAMC_ACTIME_UNION = { + 0x00000000, /* U 00 */ + 0x00000000, /* U 01 */ + 0x00000000, /* U 02 */ + 0x00000000, /* U 03 */ + 0x00000000, /* U 04 */ + 0x00000000, /* U 05 */ + 0x00000000, /* U 06 */ + 0x00000000, /* U 07 */ + }, + {0xC0000000,0xC0000000,0,0}, /* DRAM RANK SIZE */ + 0x421000, /* EMI_CONF_VAL */ + 0x466005D, /* CHN0_EMI_CONA_VAL */ + 0x466005D, /* CHN1_EMI_CONA_VAL */ + CBT_R0_R1_NORMAL, /* dram_cbt_mode_extern */ + {0,0,0,0,0,0}, /* reserved 6 */ + 0x000000FF, /* LPDDR4X_MODE_REG5 */ + 0, /* PIN_MUX_TYPE for tablet */ +}; +#endif + +EMI_SETTINGS emi_settings[] = +{ + //H9HKNNNFBMMVAR - 4GB (2+2) + { + 0x1, /* sub_version */ + 0x0006, /* TYPE */ + 0, /* EMMC ID/FW ID checking length */ + 0, /* FW length */ + {0x0,0x0,0x0,0x0,0x0,0x0,0x0,0x0,0x0,0x0,0x0,0x0,0x0,0x0,0x0,0x0}, /* NAND_EMMC_ID */ + {0x0,0x0,0x0,0x0,0x0,0x0,0x0,0x0}, /* FW_ID */ + 0xF053F154, /* EMI_CONA_VAL */ + 0x44440003, /* EMI_CONH_VAL */ + .DRAMC_ACTIME_UNION = { + 0x00000000, /* U 00 */ + 0x00000000, /* U 01 */ + 0x00000000, /* U 02 */ + 0x00000000, /* U 03 */ + 0x00000000, /* U 04 */ + 0x00000000, /* U 05 */ + 0x00000000, /* U 06 */ + 0x00000000, /* U 07 */ + }, + {0x80000000,0x80000000,0,0}, /* DRAM RANK SIZE */ + 0x421000, /* EMI_CONF_VAL */ + 0x444F051, /* CHN0_EMI_CONA_VAL */ + 0x444F051, /* CHN1_EMI_CONA_VAL */ + CBT_R0_R1_NORMAL, /* dram_cbt_mode_extern */ + {0,0,0,0,0,0}, /* reserved 6 */ + 0x00000006, /* LPDDR4X_MODE_REG5 */ + 0, /* PIN_MUX_TYPE for tablet */ + } , + //MT29VZZZBD9DQKPR - 6GB (3+3) + { + 0x1, /* sub_version */ + 0x0206, /* TYPE */ + 9, /* EMMC ID/FW ID checking length */ + 0, /* FW length */ + {0x13,0x01,0x4E,0x53,0x30,0x4A,0x39,0x4D,0x39,0x0,0x0,0x0,0x0,0x0,0x0,0x0}, /* NAND_EMMC_ID */ + {0x0,0x0,0x0,0x0,0x0,0x0,0x0,0x0}, /* FW_ID */ + 0x3530154, /* EMI_CONA_VAL */ + 0x66660033, /* EMI_CONH_VAL */ + .DRAMC_ACTIME_UNION = { + 0x00000000, /* U 00 */ + 0x00000000, /* U 01 */ + 0x00000000, /* U 02 */ + 0x00000000, /* U 03 */ + 0x00000000, /* U 04 */ + 0x00000000, /* U 05 */ + 0x00000000, /* U 06 */ + 0x00000000, /* U 07 */ + }, + {0xC0000000,0xC0000000,0,0}, /* DRAM RANK SIZE */ + 0x421000, /* EMI_CONF_VAL */ + 0x466005D, /* CHN0_EMI_CONA_VAL */ + 0x466005D, /* CHN1_EMI_CONA_VAL */ + CBT_R0_R1_NORMAL, /* dram_cbt_mode_extern */ + {0,0,0,0,0,0}, /* reserved 6 */ + 0x000000FF, /* LPDDR4X_MODE_REG5 */ + 0, /* PIN_MUX_TYPE for tablet */ + } , + //H9HQ16AFAMMDAR / H9HCNNNFAMMLXR-NEE / K4UCE3Q4AA-MGCR - 8GB (4+4) Byte Mode + { + 0x1, /* sub_version */ + 0x0306, /* TYPE */ + 14, /* EMMC ID/FW ID checking length */ + 0, /* FW length */ + {0x48,0x39,0x48,0x51,0x31,0x36,0x41,0x46,0x41,0x4D,0x4D,0x44,0x41,0x52,0x0,0x0}, /* NAND_EMMC_ID */ + {0x0,0x0,0x0,0x0,0x0,0x0,0x0,0x0}, /* FW_ID */ + 0x3530154, /* EMI_CONA_VAL */ + 0x88880033, /* EMI_CONH_VAL */ + .DRAMC_ACTIME_UNION = { + 0x00000000, /* U 00 */ + 0x00000000, /* U 01 */ + 0x00000000, /* U 02 */ + 0x00000000, /* U 03 */ + 0x00000000, /* U 04 */ + 0x00000000, /* U 05 */ + 0x00000000, /* U 06 */ + 0x00000000, /* U 07 */ + }, + {0x100000000,0x100000000,0,0}, /* DRAM RANK SIZE */ + 0x421000, /* EMI_CONF_VAL */ + 0x488005D, /* CHN0_EMI_CONA_VAL */ + 0x488005D, /* CHN1_EMI_CONA_VAL */ + CBT_R0_R1_BYTE, /* dram_cbt_mode_extern */ + {0,0,0,0,0,0}, /* reserved 6 */ + 0x00000006, /* LPDDR4X_MODE_REG5 */ + 0, /* PIN_MUX_TYPE for tablet */ + }, + //MT29VZZZAD8GQFSL-046 - 4GB -Normal mode (4+0) + { + 0x1, /* sub_version */ + 0x0006, /* TYPE */ + 0, /* EMMC ID/FW ID checking length */ + 0, /* FW length */ + {0x0,0x0,0x0,0x0,0x0,0x0,0x0,0x0,0x0,0x0,0x0,0x0,0x0,0x0,0x0,0x0}, /* NAND_EMMC_ID */ + {0x0,0x0,0x0,0x0,0x0,0x0,0x0,0x0}, /* FW_ID */ + 0x3500154, /* EMI_CONA_VAL */ + 0x88880033, /* EMI_CONH_VAL */ + .DRAMC_ACTIME_UNION = { + 0x00000000, /* U 00 */ + 0x00000000, /* U 01 */ + 0x00000000, /* U 02 */ + 0x00000000, /* U 03 */ + 0x00000000, /* U 04 */ + 0x00000000, /* U 05 */ + 0x00000000, /* U 06 */ + 0x00000000, /* U 07 */ + }, + {0x100000000,0,0,0}, /* DRAM RANK SIZE */ + 0x421000, /* EMI_CONF_VAL */ + 0x488005C, /* CHN0_EMI_CONA_VAL */ + 0x488005C, /* CHN1_EMI_CONA_VAL */ + CBT_R0_R1_NORMAL, /* dram_cbt_mode_extern */ + {0,0,0,0,0,0}, /* reserved 6 */ + 0x00000006, /* LPDDR4X_MODE_REG5 */ + 0, /* PIN_MUX_TYPE for tablet */ + }, + //KM2V8001CM_B707 - 6GB -byte mode (2+4) + { + 0x1, /* sub_version */ + 0x0306, /* TYPE */ + 14, /* EMMC ID/FW ID checking length */ + 0, /* FW length */ + {0x4b,0x4d,0x32,0x56,0x38,0x30,0x30,0x31,0x43,0x4d,0x2d,0x42,0x37,0x30,0x0,0x0}, /* NAND_EMMC_ID */ + {0x0,0x0,0x0,0x0,0x0,0x0,0x0,0x0}, /* FW_ID */ + 0x32533154, /* EMI_CONA_VAL */ + 0x84840023, /* EMI_CONH_VAL */ + .DRAMC_ACTIME_UNION = { + 0x00000000, /* U 00 */ + 0x00000000, /* U 01 */ + 0x00000000, /* U 02 */ + 0x00000000, /* U 03 */ + 0x00000000, /* U 04 */ + 0x00000000, /* U 05 */ + 0x00000000, /* U 06 */ + 0x00000000, /* U 07 */ + }, + {0x80000000,0x100000000,0,0}, /* DRAM RANK SIZE */ + 0x421000, /* EMI_CONF_VAL */ + 0x4843059, /* CHN0_EMI_CONA_VAL */ + 0x4843059, /* CHN1_EMI_CONA_VAL */ + CBT_R0_NORMAL_R1_BYTE, /* dram_cbt_mode_extern */ + {0,0,0,0,0,0}, /* reserved 6 */ + 0x00000001, /* LPDDR4X_MODE_REG5 */ + 0, /* PIN_MUX_TYPE for tablet */ + } , + //MT53E2G32D4 - 8GB (4+4) Normal Mode + { + 0x1, /* sub_version */ + 0x0306, /* TYPE */ + 14, /* EMMC ID/FW ID checking length */ + 0, /* FW length */ + {0x48,0x39,0x48,0x51,0x31,0x36,0x41,0x46,0x41,0x4D,0x4D,0x44,0x41,0x52,0x0,0x0}, /* NAND_EMMC_ID */ + {0x0,0x0,0x0,0x0,0x0,0x0,0x0,0x0}, /* FW_ID */ + 0x3530154, /* EMI_CONA_VAL */ + 0x88880033, /* EMI_CONH_VAL */ + .DRAMC_ACTIME_UNION = { + 0x00000000, /* U 00 */ + 0x00000000, /* U 01 */ + 0x00000000, /* U 02 */ + 0x00000000, /* U 03 */ + 0x00000000, /* U 04 */ + 0x00000000, /* U 05 */ + 0x00000000, /* U 06 */ + 0x00000000, /* U 07 */ + }, + {0x100000000,0x100000000,0,0}, /* DRAM RANK SIZE */ + 0x421000, /* EMI_CONF_VAL */ + 0x488005D, /* CHN0_EMI_CONA_VAL */ + 0x488005D, /* CHN1_EMI_CONA_VAL */ + CBT_R0_R1_NORMAL, /* dram_cbt_mode_extern */ + {0,0,0,0,0,0}, /* reserved 6 */ + 0x00000006, /* LPDDR4X_MODE_REG5 */ + 0, /* PIN_MUX_TYPE for tablet */ + }, +}; + +#define num_of_emi_records (sizeof(emi_settings) / sizeof(emi_settings[0])) + +#endif /* __CUSTOM_EMI__ */ + diff --git a/src/vendorcode/mediatek/mt8192/include/ddrphy_nao_reg.h b/src/vendorcode/mediatek/mt8192/include/ddrphy_nao_reg.h new file mode 100644 index 000000000000..a48629f914e9 --- /dev/null +++ b/src/vendorcode/mediatek/mt8192/include/ddrphy_nao_reg.h @@ -0,0 +1,391 @@ +/* SPDX-License-Identifier: BSD-3-Clause */ + +#ifndef __DDRPHY_NAO_REG_H__ +#define __DDRPHY_NAO_REG_H__ + +/* ----------------- Register Definitions ------------------- */ +#define MISC_STA_EXTLB0 0x00000000 + #define MISC_STA_EXTLB0_STA_EXTLB_DONE GENMASK(31, 0) +#define MISC_STA_EXTLB1 0x00000004 + #define MISC_STA_EXTLB1_STA_EXTLB_FAIL GENMASK(31, 0) +#define MISC_STA_EXTLB2 0x00000008 + #define MISC_STA_EXTLB2_STA_EXTLB_DBG_INFO GENMASK(31, 0) +#define MISC_DQ_RXDLY_TRRO0 0x00000080 + #define MISC_DQ_RXDLY_TRRO0_DVS_RKX_BX_SW_LAG_CNT_OUT_B0 GENMASK(7, 0) + #define MISC_DQ_RXDLY_TRRO0_DVS_RKX_BX_SW_LEAD_CNT_OUT_B0 GENMASK(15, 8) + #define MISC_DQ_RXDLY_TRRO0_DVS_RKX_BX_SW_LAG_CNT_OUT_B1 GENMASK(23, 16) + #define MISC_DQ_RXDLY_TRRO0_DVS_RKX_BX_SW_LEAD_CNT_OUT_B1 GENMASK(31, 24) +#define MISC_DQ_RXDLY_TRRO1 0x00000084 + #define MISC_DQ_RXDLY_TRRO1_DVS_RKX_BX_SW_LAG_CNT_OUT_B2 GENMASK(7, 0) + #define MISC_DQ_RXDLY_TRRO1_DVS_RKX_BX_SW_LEAD_CNT_OUT_B2 GENMASK(15, 8) + #define MISC_DQ_RXDLY_TRRO1_DVS_RKX_BX_SW_LAG_CNT_OUT_B3 GENMASK(23, 16) + #define MISC_DQ_RXDLY_TRRO1_DVS_RKX_BX_SW_LEAD_CNT_OUT_B3 GENMASK(31, 24) +#define MISC_DQ_RXDLY_TRRO2 0x00000088 + #define MISC_DQ_RXDLY_TRRO2_DVS_RKX_BX_SW_LAG_CNT_OUT_B4 GENMASK(7, 0) + #define MISC_DQ_RXDLY_TRRO2_DVS_RKX_BX_SW_LEAD_CNT_OUT_B4 GENMASK(15, 8) + #define MISC_DQ_RXDLY_TRRO2_DVS_RKX_BX_SW_LAG_CNT_OUT_B5 GENMASK(23, 16) + #define MISC_DQ_RXDLY_TRRO2_DVS_RKX_BX_SW_LEAD_CNT_OUT_B5 GENMASK(31, 24) +#define MISC_DQ_RXDLY_TRRO3 0x0000008c + #define MISC_DQ_RXDLY_TRRO3_DVS_RKX_BX_SW_LAG_CNT_OUT_B6 GENMASK(7, 0) + #define MISC_DQ_RXDLY_TRRO3_DVS_RKX_BX_SW_LEAD_CNT_OUT_B6 GENMASK(15, 8) + #define MISC_DQ_RXDLY_TRRO3_DVS_RKX_BX_SW_LAG_CNT_OUT_B7 GENMASK(23, 16) + #define MISC_DQ_RXDLY_TRRO3_DVS_RKX_BX_SW_LEAD_CNT_OUT_B7 GENMASK(31, 24) +#define MISC_DQ_RXDLY_TRRO4 0x00000090 + #define MISC_DQ_RXDLY_TRRO4_DVS_RKX_BX_LEAD_LAG_CNT_OUT_B0 GENMASK(7, 0) + #define MISC_DQ_RXDLY_TRRO4_DVS_RKX_BX_LEAD_LAG_CNT_OUT_B1 GENMASK(15, 8) + #define MISC_DQ_RXDLY_TRRO4_DVS_RKX_BX_LEAD_LAG_CNT_OUT_B2 GENMASK(23, 16) + #define MISC_DQ_RXDLY_TRRO4_DVS_RKX_BX_LEAD_LAG_CNT_OUT_B3 GENMASK(31, 24) +#define MISC_DQ_RXDLY_TRRO5 0x00000094 + #define MISC_DQ_RXDLY_TRRO5_DVS_RKX_BX_LEAD_LAG_CNT_OUT_B4 GENMASK(7, 0) + #define MISC_DQ_RXDLY_TRRO5_DVS_RKX_BX_LEAD_LAG_CNT_OUT_B5 GENMASK(15, 8) + #define MISC_DQ_RXDLY_TRRO5_DVS_RKX_BX_LEAD_LAG_CNT_OUT_B6 GENMASK(23, 16) + #define MISC_DQ_RXDLY_TRRO5_DVS_RKX_BX_LEAD_LAG_CNT_OUT_B7 GENMASK(31, 24) +#define MISC_DQ_RXDLY_TRRO6 0x00000098 + #define MISC_DQ_RXDLY_TRRO6_DVS_RKX_BX_SW_LAG_CNT_OUT_DQM0 GENMASK(7, 0) + #define MISC_DQ_RXDLY_TRRO6_DVS_RKX_BX_SW_LEAD_CNT_OUT_DQM0 GENMASK(15, 8) + #define MISC_DQ_RXDLY_TRRO6_DVS_RKX_BX_LEAD_LAG_CNT_OUT_DQM0 GENMASK(31, 24) +#define MISC_DQ_RXDLY_TRRO7 0x0000009c + #define MISC_DQ_RXDLY_TRRO7_DVS_RK0_B0_SW_UP_DONE BIT(0) + #define MISC_DQ_RXDLY_TRRO7_DVS_RK0_B1_SW_UP_DONE BIT(4) + #define MISC_DQ_RXDLY_TRRO7_DVS_RK1_B0_SW_UP_DONE BIT(8) + #define MISC_DQ_RXDLY_TRRO7_DVS_RK1_B1_SW_UP_DONE BIT(12) + #define MISC_DQ_RXDLY_TRRO7_DVS_RK2_B0_SW_UP_DONE BIT(16) + #define MISC_DQ_RXDLY_TRRO7_DVS_RK2_B1_SW_UP_DONE BIT(20) +#define MISC_DQ_RXDLY_TRRO8 0x000000a0 + #define MISC_DQ_RXDLY_TRRO8_DVS_RKX_BX_TH_CNT_OUT_B0 GENMASK(8, 0) + #define MISC_DQ_RXDLY_TRRO8_DVS_RKX_BX_TH_CNT_OUT_B1 GENMASK(24, 16) +#define MISC_DQ_RXDLY_TRRO9 0x000000a4 + #define MISC_DQ_RXDLY_TRRO9_DVS_RKX_BX_TH_CNT_OUT_B2 GENMASK(8, 0) + #define MISC_DQ_RXDLY_TRRO9_DVS_RKX_BX_TH_CNT_OUT_B3 GENMASK(24, 16) +#define MISC_DQ_RXDLY_TRRO10 0x000000a8 + #define MISC_DQ_RXDLY_TRRO10_DVS_RKX_BX_TH_CNT_OUT_B4 GENMASK(8, 0) + #define MISC_DQ_RXDLY_TRRO10_DVS_RKX_BX_TH_CNT_OUT_B5 GENMASK(24, 16) +#define MISC_DQ_RXDLY_TRRO11 0x000000ac + #define MISC_DQ_RXDLY_TRRO11_DVS_RKX_BX_TH_CNT_OUT_B6 GENMASK(8, 0) + #define MISC_DQ_RXDLY_TRRO11_DVS_RKX_BX_TH_CNT_OUT_B7 GENMASK(24, 16) +#define MISC_DQ_RXDLY_TRRO12 0x000000b0 + #define MISC_DQ_RXDLY_TRRO12_DVS_RKX_BX_TH_CNT_OUT_DQM0 GENMASK(8, 0) +#define MISC_DQ_RXDLY_TRRO13 0x000000b4 + #define MISC_DQ_RXDLY_TRRO13_DA_RK0_DQX_B0_R_DLY GENMASK(5, 0) + #define MISC_DQ_RXDLY_TRRO13_DA_RK0_DQS0_R_DLY GENMASK(14, 8) + #define MISC_DQ_RXDLY_TRRO13_DA_RK0_DQX_B1_R_DLY GENMASK(21, 16) + #define MISC_DQ_RXDLY_TRRO13_DA_RK0_DQS1_R_DLY GENMASK(30, 24) +#define MISC_DQ_RXDLY_TRRO14 0x000000b8 + #define MISC_DQ_RXDLY_TRRO14_DA_RK1_DQX_B0_R_DLY GENMASK(5, 0) + #define MISC_DQ_RXDLY_TRRO14_DA_RK1_DQS0_R_DLY GENMASK(14, 8) + #define MISC_DQ_RXDLY_TRRO14_DA_RK1_DQX_B1_R_DLY GENMASK(21, 16) + #define MISC_DQ_RXDLY_TRRO14_DA_RK1_DQS1_R_DLY GENMASK(30, 24) +#define MISC_DQ_RXDLY_TRRO15 0x000000bc + #define MISC_DQ_RXDLY_TRRO15_DA_RK2_DQX_B0_R_DLY GENMASK(5, 0) + #define MISC_DQ_RXDLY_TRRO15_DA_RK2_DQS0_R_DLY GENMASK(14, 8) + #define MISC_DQ_RXDLY_TRRO15_DA_RK2_DQX_B1_R_DLY GENMASK(21, 16) + #define MISC_DQ_RXDLY_TRRO15_DA_RK2_DQS1_R_DLY GENMASK(30, 24) +#define MISC_DQ_RXDLY_TRRO16 0x000000c0 + #define MISC_DQ_RXDLY_TRRO16_DVS_RXDLY_STS_ERR_CNT_ALL GENMASK(31, 0) +#define MISC_DQ_RXDLY_TRRO17 0x000000c4 + #define MISC_DQ_RXDLY_TRRO17_DVS_RXDLY_STS_ERR_CNT_ALL_47_32 GENMASK(15, 0) + #define MISC_DQ_RXDLY_TRRO17_PBYTE_LEADLAG_STUCK_B0 BIT(16) + #define MISC_DQ_RXDLY_TRRO17_PBYTE_LEADLAG_STUCK_B1 BIT(24) +#define MISC_DQ_RXDLY_TRRO18 0x000000c8 + #define MISC_DQ_RXDLY_TRRO18_RXDLY_DBG_MON_VALID BIT(0) + #define MISC_DQ_RXDLY_TRRO18_RXDLY_RK0_FAIL_LAT BIT(1) + #define MISC_DQ_RXDLY_TRRO18_RXDLY_RK1_FAIL_LAT BIT(2) + #define MISC_DQ_RXDLY_TRRO18_RXDLY_RK2_FAIL_LAT BIT(3) + #define MISC_DQ_RXDLY_TRRO18_DFS_SHU_GP_FAIL_LAT GENMASK(5, 4) +#define MISC_DQ_RXDLY_TRRO19 0x000000cc + #define MISC_DQ_RXDLY_TRRO19_RESERVED_0X00C GENMASK(31, 0) +#define MISC_DQ_RXDLY_TRRO20 0x000000d0 + #define MISC_DQ_RXDLY_TRRO20_RESERVED_0X0D0 GENMASK(31, 0) +#define MISC_DQ_RXDLY_TRRO21 0x000000d4 + #define MISC_DQ_RXDLY_TRRO21_RESERVED_0X0D4 GENMASK(31, 0) +#define MISC_DQ_RXDLY_TRRO22 0x000000d8 + #define MISC_DQ_RXDLY_TRRO22_RESERVED_0X0D8 GENMASK(31, 0) +#define MISC_DQ_RXDLY_TRRO23 0x000000dc + #define MISC_DQ_RXDLY_TRRO23_RESERVED_0X0DC GENMASK(31, 0) +#define MISC_DQ_RXDLY_TRRO24 0x000000e0 + #define MISC_DQ_RXDLY_TRRO24_RESERVED_0X0E0 GENMASK(31, 0) +#define MISC_DQ_RXDLY_TRRO25 0x000000e4 + #define MISC_DQ_RXDLY_TRRO25_RESERVED_0X0E4 GENMASK(31, 0) +#define MISC_DQ_RXDLY_TRRO26 0x000000e8 + #define MISC_DQ_RXDLY_TRRO26_RESERVED_0X0E8 GENMASK(31, 0) +#define MISC_DQ_RXDLY_TRRO27 0x000000ec + #define MISC_DQ_RXDLY_TRRO27_RESERVED_0X0EC GENMASK(31, 0) +#define MISC_DQ_RXDLY_TRRO28 0x000000f0 + #define MISC_DQ_RXDLY_TRRO28_RESERVED_0X0F0 GENMASK(31, 0) +#define MISC_DQ_RXDLY_TRRO29 0x000000f4 + #define MISC_DQ_RXDLY_TRRO29_RESERVED_0X0F4 GENMASK(31, 0) +#define MISC_DQ_RXDLY_TRRO30 0x000000f8 + #define MISC_DQ_RXDLY_TRRO30_RESERVED_0X0F8 GENMASK(31, 0) +#define MISC_DQ_RXDLY_TRRO31 0x000000fc + #define MISC_DQ_RXDLY_TRRO31_RESERVED_0X0FC GENMASK(31, 0) +#define MISC_CA_RXDLY_TRRO0 0x00000100 + #define MISC_CA_RXDLY_TRRO0_DVS_RKX_CA_SW_LAG_CNT_OUT_CA0 GENMASK(7, 0) + #define MISC_CA_RXDLY_TRRO0_DVS_RKX_CA_SW_LEAD_CNT_OUT_CA0 GENMASK(15, 8) + #define MISC_CA_RXDLY_TRRO0_DVS_RKX_CA_SW_LAG_CNT_OUT_CA1 GENMASK(23, 16) + #define MISC_CA_RXDLY_TRRO0_DVS_RKX_CA_SW_LEAD_CNT_OUT_CA1 GENMASK(31, 24) +#define MISC_CA_RXDLY_TRRO1 0x00000104 + #define MISC_CA_RXDLY_TRRO1_DVS_RKX_CA_SW_LAG_CNT_OUT_CA2 GENMASK(7, 0) + #define MISC_CA_RXDLY_TRRO1_DVS_RKX_CA_SW_LEAD_CNT_OUT_CA2 GENMASK(15, 8) + #define MISC_CA_RXDLY_TRRO1_DVS_RKX_CA_SW_LAG_CNT_OUT_CA3 GENMASK(23, 16) + #define MISC_CA_RXDLY_TRRO1_DVS_RKX_CA_SW_LEAD_CNT_OUT_CA3 GENMASK(31, 24) +#define MISC_CA_RXDLY_TRRO2 0x00000108 + #define MISC_CA_RXDLY_TRRO2_DVS_RKX_CA_SW_LAG_CNT_OUT_CA4 GENMASK(7, 0) + #define MISC_CA_RXDLY_TRRO2_DVS_RKX_CA_SW_LEAD_CNT_OUT_CA4 GENMASK(15, 8) + #define MISC_CA_RXDLY_TRRO2_DVS_RKX_CA_SW_LAG_CNT_OUT_CA5 GENMASK(23, 16) + #define MISC_CA_RXDLY_TRRO2_DVS_RKX_CA_SW_LEAD_CNT_OUT_CA5 GENMASK(31, 24) +#define MISC_CA_RXDLY_TRRO3 0x0000010c + #define MISC_CA_RXDLY_TRRO3_DVS_RKX_CA_SW_LAG_CNT_OUT_CKE0 GENMASK(7, 0) + #define MISC_CA_RXDLY_TRRO3_DVS_RKX_CA_SW_LEAD_CNT_OUT_CKE0 GENMASK(15, 8) + #define MISC_CA_RXDLY_TRRO3_DVS_RKX_CA_SW_LAG_CNT_OUT_CKE1 GENMASK(23, 16) + #define MISC_CA_RXDLY_TRRO3_DVS_RKX_CA_SW_LEAD_CNT_OUT_CKE1 GENMASK(31, 24) +#define MISC_CA_RXDLY_TRRO4 0x00000110 + #define MISC_CA_RXDLY_TRRO4_DVS_RKX_CA_SW_LAG_CNT_OUT_CKE2 GENMASK(7, 0) + #define MISC_CA_RXDLY_TRRO4_DVS_RKX_CA_SW_LEAD_CNT_OUT_CKE2 GENMASK(15, 8) + #define MISC_CA_RXDLY_TRRO4_DVS_RKX_CA_SW_LAG_CNT_OUT_CS0 GENMASK(23, 16) + #define MISC_CA_RXDLY_TRRO4_DVS_RKX_CA_SW_LEAD_CNT_OUT_CS0 GENMASK(31, 24) +#define MISC_CA_RXDLY_TRRO5 0x00000114 + #define MISC_CA_RXDLY_TRRO5_DVS_RKX_CA_SW_LAG_CNT_OUT_CS1 GENMASK(7, 0) + #define MISC_CA_RXDLY_TRRO5_DVS_RKX_CA_SW_LEAD_CNT_OUT_CS1 GENMASK(15, 8) + #define MISC_CA_RXDLY_TRRO5_DVS_RKX_CA_SW_LAG_CNT_OUT_CS2 GENMASK(23, 16) + #define MISC_CA_RXDLY_TRRO5_DVS_RKX_CA_SW_LEAD_CNT_OUT_CS2 GENMASK(31, 24) +#define MISC_CA_RXDLY_TRRO6 0x00000118 + #define MISC_CA_RXDLY_TRRO6_DVS_RKX_CA_LEAD_LAG_CNT_OUT_CA0 GENMASK(7, 0) + #define MISC_CA_RXDLY_TRRO6_DVS_RKX_CA_LEAD_LAG_CNT_OUT_CA1 GENMASK(15, 8) + #define MISC_CA_RXDLY_TRRO6_DVS_RKX_CA_LEAD_LAG_CNT_OUT_CA2 GENMASK(23, 16) + #define MISC_CA_RXDLY_TRRO6_DVS_RKX_CA_LEAD_LAG_CNT_OUT_CA3 GENMASK(31, 24) +#define MISC_CA_RXDLY_TRRO7 0x0000011c + #define MISC_CA_RXDLY_TRRO7_DVS_RKX_CA_LEAD_LAG_CNT_OUT_CA4 GENMASK(7, 0) + #define MISC_CA_RXDLY_TRRO7_DVS_RKX_CA_LEAD_LAG_CNT_OUT_CA5 GENMASK(15, 8) + #define MISC_CA_RXDLY_TRRO7_DVS_RKX_CA_LEAD_LAG_CNT_OUT_CKE0 GENMASK(23, 16) + #define MISC_CA_RXDLY_TRRO7_DVS_RKX_CA_LEAD_LAG_CNT_OUT_CKE1 GENMASK(31, 24) +#define MISC_CA_RXDLY_TRRO8 0x00000120 + #define MISC_CA_RXDLY_TRRO8_DVS_RKX_CA_LEAD_LAG_CNT_OUT_CKE2 GENMASK(7, 0) + #define MISC_CA_RXDLY_TRRO8_DVS_RKX_CA_LEAD_LAG_CNT_OUT_CS0 GENMASK(15, 8) + #define MISC_CA_RXDLY_TRRO8_DVS_RKX_CA_LEAD_LAG_CNT_OUT_CS1 GENMASK(23, 16) + #define MISC_CA_RXDLY_TRRO8_DVS_RKX_CA_LEAD_LAG_CNT_OUT_CS2 GENMASK(31, 24) +#define MISC_CA_RXDLY_TRRO9 0x00000124 + #define MISC_CA_RXDLY_TRRO9_DVS_RK0_CA_SW_UP_DONE BIT(0) + #define MISC_CA_RXDLY_TRRO9_DVS_RK1_CA_SW_UP_DONE BIT(8) + #define MISC_CA_RXDLY_TRRO9_DVS_RK2_CA_SW_UP_DONE BIT(16) +#define MISC_CA_RXDLY_TRRO10 0x00000128 + #define MISC_CA_RXDLY_TRRO10_DVS_RKX_CA_TH_CNT_OUT_CA0 GENMASK(8, 0) + #define MISC_CA_RXDLY_TRRO10_DVS_RKX_CA_TH_CNT_OUT_CA1 GENMASK(24, 16) +#define MISC_CA_RXDLY_TRRO11 0x0000012c + #define MISC_CA_RXDLY_TRRO11_DVS_RKX_CA_TH_CNT_OUT_CA2 GENMASK(8, 0) + #define MISC_CA_RXDLY_TRRO11_DVS_RKX_CA_TH_CNT_OUT_CA3 GENMASK(24, 16) +#define MISC_CA_RXDLY_TRRO12 0x00000130 + #define MISC_CA_RXDLY_TRRO12_DVS_RKX_CA_TH_CNT_OUT_CA4 GENMASK(8, 0) + #define MISC_CA_RXDLY_TRRO12_DVS_RKX_CA_TH_CNT_OUT_CA5 GENMASK(24, 16) +#define MISC_CA_RXDLY_TRRO13 0x00000134 + #define MISC_CA_RXDLY_TRRO13_DVS_RKX_CA_TH_CNT_OUT_CKE0 GENMASK(8, 0) + #define MISC_CA_RXDLY_TRRO13_DVS_RKX_CA_TH_CNT_OUT_CKE1 GENMASK(24, 16) +#define MISC_CA_RXDLY_TRRO14 0x00000138 + #define MISC_CA_RXDLY_TRRO14_DVS_RKX_CA_TH_CNT_OUT_CKE2 GENMASK(8, 0) + #define MISC_CA_RXDLY_TRRO14_DVS_RKX_CA_TH_CNT_OUT_CS0 GENMASK(24, 16) +#define MISC_CA_RXDLY_TRRO15 0x0000013c + #define MISC_CA_RXDLY_TRRO15_DVS_RKX_CA_TH_CNT_OUT_CS1 GENMASK(8, 0) + #define MISC_CA_RXDLY_TRRO15_DVS_RKX_CA_TH_CNT_OUT_CS2 GENMASK(24, 16) +#define MISC_CA_RXDLY_TRRO16 0x00000140 + #define MISC_CA_RXDLY_TRRO16_DA_RK0_CAX_CA_R_DLY GENMASK(5, 0) + #define MISC_CA_RXDLY_TRRO16_DA_RK0_CLK_R_DLY GENMASK(15, 8) +#define MISC_CA_RXDLY_TRRO17 0x00000144 + #define MISC_CA_RXDLY_TRRO17_DA_RK1_CAX_CA_R_DLY GENMASK(5, 0) + #define MISC_CA_RXDLY_TRRO17_DA_RK1_CLK_R_DLY GENMASK(15, 8) +#define MISC_CA_RXDLY_TRRO18 0x00000148 + #define MISC_CA_RXDLY_TRRO18_DA_RK2_CAX_CA_R_DLY GENMASK(5, 0) + #define MISC_CA_RXDLY_TRRO18_DA_RK2_CLK_R_DLY GENMASK(15, 8) +#define MISC_CA_RXDLY_TRRO19 0x0000014c + #define MISC_CA_RXDLY_TRRO19_DVS_RXDLY_STS_ERR_CNT_ALL_CA GENMASK(23, 0) + #define MISC_CA_RXDLY_TRRO19_PBYTE_LEADLAG_STUCK_CA BIT(24) +#define MISC_CA_RXDLY_TRRO20 0x00000150 + #define MISC_CA_RXDLY_TRRO20_RESERVED_0X150 GENMASK(31, 0) +#define MISC_CA_RXDLY_TRRO21 0x00000154 + #define MISC_CA_RXDLY_TRRO21_RESERVED_0X154 GENMASK(31, 0) +#define MISC_CA_RXDLY_TRRO22 0x00000158 + #define MISC_CA_RXDLY_TRRO22_RESERVED_0X158 GENMASK(31, 0) +#define MISC_CA_RXDLY_TRRO23 0x0000015c + #define MISC_CA_RXDLY_TRRO23_RESERVED_0X15C GENMASK(31, 0) +#define MISC_CA_RXDLY_TRRO24 0x00000160 + #define MISC_CA_RXDLY_TRRO24_RESERVED_0X160 GENMASK(31, 0) +#define MISC_CA_RXDLY_TRRO25 0x00000164 + #define MISC_CA_RXDLY_TRRO25_RESERVED_0X164 GENMASK(31, 0) +#define MISC_CA_RXDLY_TRRO26 0x00000168 + #define MISC_CA_RXDLY_TRRO26_RESERVED_0X168 GENMASK(31, 0) +#define MISC_CA_RXDLY_TRRO27 0x0000016c + #define MISC_CA_RXDLY_TRRO27_RESERVED_0X16C GENMASK(31, 0) +#define MISC_CA_RXDLY_TRRO28 0x00000170 + #define MISC_CA_RXDLY_TRRO28_RESERVED_0X170 GENMASK(31, 0) +#define MISC_CA_RXDLY_TRRO29 0x00000174 + #define MISC_CA_RXDLY_TRRO29_RESERVED_0X174 GENMASK(31, 0) +#define MISC_CA_RXDLY_TRRO30 0x00000178 + #define MISC_CA_RXDLY_TRRO30_RESERVED_0X178 GENMASK(31, 0) +#define MISC_CA_RXDLY_TRRO31 0x0000017c + #define MISC_CA_RXDLY_TRRO31_RESERVED_0X17C GENMASK(31, 0) +#define MISC_DQO1 0x00000180 + #define MISC_DQO1_DQO1_RO GENMASK(31, 0) +#define MISC_CAO1 0x00000184 + #define MISC_CAO1_RA0_O1 BIT(0) + #define MISC_CAO1_RA1_O1 BIT(1) + #define MISC_CAO1_RA2_O1 BIT(2) + #define MISC_CAO1_RA3_O1 BIT(3) + #define MISC_CAO1_RA4_O1 BIT(4) + #define MISC_CAO1_RA5_O1 BIT(5) + #define MISC_CAO1_RA6_O1 BIT(6) + #define MISC_CAO1_RA7_O1 BIT(7) + #define MISC_CAO1_RA8_O1 BIT(8) + #define MISC_CAO1_RA9_O1 BIT(9) + #define MISC_CAO1_CKEO1_RO BIT(10) + #define MISC_CAO1_CKE1O1_RO BIT(11) + #define MISC_CAO1_CKE2O1_RO BIT(12) + #define MISC_CAO1_CSO1_RO BIT(13) + #define MISC_CAO1_CS1O1_RO BIT(14) + #define MISC_CAO1_CS2O1_RO BIT(15) + #define MISC_CAO1_RESETO1_RO BIT(16) + #define MISC_CAO1_DQM0O1_RO BIT(24) + #define MISC_CAO1_DQM1O1_RO BIT(25) + #define MISC_CAO1_DQM2O1_RO BIT(26) + #define MISC_CAO1_DQM3O1_RO BIT(27) +#define MISC_AD_RX_DQ_O1 0x00000188 + #define MISC_AD_RX_DQ_O1_AD_RX_ARDQ_O1_B0 GENMASK(7, 0) + #define MISC_AD_RX_DQ_O1_AD_RX_ARDQ_O1_B0_BIT2 BIT(2)//[2:2] //francis added + #define MISC_AD_RX_DQ_O1_AD_RX_ARDQM0_O1_B0 BIT(8) + #define MISC_AD_RX_DQ_O1_AD_RX_ARDQ_O1_B1 GENMASK(23, 16) + #define MISC_AD_RX_DQ_O1_AD_RX_ARDQM0_O1_B1 BIT(24) + #define MISC_AD_RX_DQ_O1_AD_RX_ARDQ_O1_B1_BIT2 BIT(18)//[18:18] //francis added +#define MISC_AD_RX_CMD_O1 0x0000018c + #define MISC_AD_RX_CMD_O1_AD_RX_ARCA0_O1 BIT(0) + #define MISC_AD_RX_CMD_O1_AD_RX_ARCA1_O1 BIT(1) + #define MISC_AD_RX_CMD_O1_AD_RX_ARCA2_O1 BIT(2) + #define MISC_AD_RX_CMD_O1_AD_RX_ARCA3_O1 BIT(3) + #define MISC_AD_RX_CMD_O1_AD_RX_ARCA4_O1 BIT(4) + #define MISC_AD_RX_CMD_O1_AD_RX_ARCA5_O1 BIT(5) + #define MISC_AD_RX_CMD_O1_AD_RX_ARCA6_O1 BIT(6) + #define MISC_AD_RX_CMD_O1_AD_RX_ARCA7_O1 BIT(7) + #define MISC_AD_RX_CMD_O1_AD_RX_ARCA8_O1 BIT(8) + #define MISC_AD_RX_CMD_O1_AD_RX_ARCA9_O1 BIT(9) + #define MISC_AD_RX_CMD_O1_AD_RX_ARCKE0_O1 BIT(10) + #define MISC_AD_RX_CMD_O1_AD_RX_ARCKE1_O1 BIT(11) + #define MISC_AD_RX_CMD_O1_AD_RX_ARCKE2_O1 BIT(12) + #define MISC_AD_RX_CMD_O1_AD_RX_ARCS0_O1 BIT(13) + #define MISC_AD_RX_CMD_O1_AD_RX_ARCS1_O1 BIT(14) + #define MISC_AD_RX_CMD_O1_AD_RX_ARCS2_O1 BIT(15) +#define MISC_PHY_RGS_DQ 0x00000190 + #define MISC_PHY_RGS_DQ_RGS_ARDQ_OFFSET_FLAG_B0 GENMASK(7, 0) + #define MISC_PHY_RGS_DQ_RGS_ARDQM0_OFFSET_FLAG_B0 BIT(8) + #define MISC_PHY_RGS_DQ_RGS_RX_ARDQS0_RDY_EYE_B0 BIT(9) + #define MISC_PHY_RGS_DQ_RGS_ARDQ_OFFSET_FLAG_B1 GENMASK(23, 16) + #define MISC_PHY_RGS_DQ_RGS_ARDQM0_OFFSET_FLAG_B1 BIT(24) + #define MISC_PHY_RGS_DQ_RGS_RX_ARDQS0_RDY_EYE_B1 BIT(25) + #define MISC_PHY_RGS_DQ_DA_RPHYPLLGP_CK_SEL BIT(31) +#define MISC_PHY_RGS_CMD 0x00000194 + #define MISC_PHY_RGS_CMD_RGS_ARCA0_OFFSET_FLAG BIT(0) + #define MISC_PHY_RGS_CMD_RGS_ARCA1_OFFSET_FLAG BIT(1) + #define MISC_PHY_RGS_CMD_RGS_ARCA2_OFFSET_FLAG BIT(2) + #define MISC_PHY_RGS_CMD_RGS_ARCA3_OFFSET_FLAG BIT(3) + #define MISC_PHY_RGS_CMD_RGS_ARCA4_OFFSET_FLAG BIT(4) + #define MISC_PHY_RGS_CMD_RGS_ARCA5_OFFSET_FLAG BIT(5) + #define MISC_PHY_RGS_CMD_RGS_ARCA6_OFFSET_FLAG BIT(6) + #define MISC_PHY_RGS_CMD_RGS_ARCA7_OFFSET_FLAG BIT(7) + #define MISC_PHY_RGS_CMD_RGS_ARCA8_OFFSET_FLAG BIT(8) + #define MISC_PHY_RGS_CMD_RGS_ARCA9_OFFSET_FLAG BIT(9) + #define MISC_PHY_RGS_CMD_RGS_ARCKE0_OFFSET_FLAG BIT(10) + #define MISC_PHY_RGS_CMD_RGS_ARCKE1_OFFSET_FLAG BIT(11) + #define MISC_PHY_RGS_CMD_RGS_ARCKE2_OFFSET_FLAG BIT(12) + #define MISC_PHY_RGS_CMD_RGS_ARCS0_OFFSET_FLAG BIT(13) + #define MISC_PHY_RGS_CMD_RGS_ARCS1_OFFSET_FLAG BIT(14) + #define MISC_PHY_RGS_CMD_RGS_ARCS2_OFFSET_FLAG BIT(15) + #define MISC_PHY_RGS_CMD_RGS_RX_ARCLK_RDY_EYE BIT(16) + #define MISC_PHY_RGS_CMD_RGS_RIMPCALOUT BIT(24) +#define MISC_PHY_RGS_STBEN_B0 0x00000198 + #define MISC_PHY_RGS_STBEN_B0_AD_RX_ARDQ0_STBEN_B0 GENMASK(7, 0) + #define MISC_PHY_RGS_STBEN_B0_AD_RX_ARDQ4_STBEN_B0 GENMASK(15, 8) + #define MISC_PHY_RGS_STBEN_B0_AD_RX_ARDQS0_STBEN_LEAD_B0 BIT(16) + #define MISC_PHY_RGS_STBEN_B0_AD_RX_ARDQS0_STBEN_LAG_B0 BIT(17) + #define MISC_PHY_RGS_STBEN_B0_AD_ARDLL_PD_EN_B0 BIT(18) + #define MISC_PHY_RGS_STBEN_B0_AD_ARDLL_MON_B0 GENMASK(31, 24) +#define MISC_PHY_RGS_STBEN_B1 0x0000019c + #define MISC_PHY_RGS_STBEN_B1_AD_RX_ARDQ0_STBEN_B1 GENMASK(7, 0) + #define MISC_PHY_RGS_STBEN_B1_AD_RX_ARDQ4_STBEN_B1 GENMASK(15, 8) + #define MISC_PHY_RGS_STBEN_B1_AD_RX_ARDQS0_STBEN_LEAD_B1 BIT(16) + #define MISC_PHY_RGS_STBEN_B1_AD_RX_ARDQS0_STBEN_LAG_B1 BIT(17) + #define MISC_PHY_RGS_STBEN_B1_AD_ARDLL_PD_EN_B1 BIT(18) + #define MISC_PHY_RGS_STBEN_B1_AD_ARDLL_MON_B1 GENMASK(31, 24) +#define MISC_PHY_RGS_STBEN_CMD 0x000001a0 + #define MISC_PHY_RGS_STBEN_CMD_AD_RX_ARCA0_STBEN GENMASK(7, 0) + #define MISC_PHY_RGS_STBEN_CMD_AD_RX_ARCA4_STBEN GENMASK(15, 8) + #define MISC_PHY_RGS_STBEN_CMD_AD_RX_ARCLK_STBEN_LEAD BIT(16) + #define MISC_PHY_RGS_STBEN_CMD_AD_RX_ARCLK_STBEN_LAG BIT(17) + #define MISC_PHY_RGS_STBEN_CMD_AD_ARDLL_PD_EN_CA BIT(18) + #define MISC_PHY_RGS_STBEN_CMD_AD_ARDLL_MON_CA GENMASK(31, 24) +#define MISC_STA_TOGLB0 0x000001a4 + #define MISC_STA_TOGLB0_STA_TOGLB_DONE GENMASK(31, 0) +#define MISC_STA_TOGLB1 0x000001a8 + #define MISC_STA_TOGLB1_STA_TOGLB_FAIL GENMASK(31, 0) +#define MISC_STA_TOGLB2 0x000001ac + #define MISC_STA_TOGLB2_STA_TOGLB_PUHI_TIMEOUT GENMASK(31, 0) +#define MISC_STA_TOGLB3 0x000001b0 + #define MISC_STA_TOGLB3_STA_TOGLB_PULO_TIMEOUT GENMASK(31, 0) +#define MISC_FT_STATUS_0 0x000001b4 + #define MISC_FT_STATUS_0_AD_RX_ARDQ_DVS_R_LAG_B1 GENMASK(7, 0) + #define MISC_FT_STATUS_0_AD_RX_ARDQ_DVS_R_LEAD_B1 GENMASK(15, 8) + #define MISC_FT_STATUS_0_AD_RX_ARDQ_DVS_R_LAG_B0 GENMASK(23, 16) + #define MISC_FT_STATUS_0_AD_RX_ARDQ_DVS_R_LEAD_B0 GENMASK(31, 24) +#define MISC_FT_STATUS_1 0x000001b8 + #define MISC_FT_STATUS_1_AD_RX_ARDQ_DVS_F_LAG_B1 GENMASK(7, 0) + #define MISC_FT_STATUS_1_AD_RX_ARDQ_DVS_F_LEAD_B1 GENMASK(15, 8) + #define MISC_FT_STATUS_1_AD_RX_ARDQ_DVS_F_LAG_B0 GENMASK(23, 16) + #define MISC_FT_STATUS_1_AD_RX_ARDQ_DVS_F_LEAD_B0 GENMASK(31, 24) +#define MISC_FT_STATUS_2 0x000001bc + #define MISC_FT_STATUS_2_AD_RRESETB_O BIT(0) +#define MISC_FT_STATUS_3 0x000001c0 + #define MISC_FT_STATUS_3_AD_RX_ARCA0_DVS_R_LAG BIT(0) + #define MISC_FT_STATUS_3_AD_RX_ARCA1_DVS_R_LAG BIT(1) + #define MISC_FT_STATUS_3_AD_RX_ARCA2_DVS_R_LAG BIT(2) + #define MISC_FT_STATUS_3_AD_RX_ARCA3_DVS_R_LAG BIT(3) + #define MISC_FT_STATUS_3_AD_RX_ARCA4_DVS_R_LAG BIT(4) + #define MISC_FT_STATUS_3_AD_RX_ARCA5_DVS_R_LAG BIT(5) + #define MISC_FT_STATUS_3_AD_RX_ARCKE0_DVS_R_LAG BIT(6) + #define MISC_FT_STATUS_3_AD_RX_ARCKE1_DVS_R_LAG BIT(7) + #define MISC_FT_STATUS_3_AD_RX_ARCS0_DVS_R_LAG BIT(8) + #define MISC_FT_STATUS_3_AD_RX_ARCS1_DVS_R_LAG BIT(9) + #define MISC_FT_STATUS_3_AD_RX_ARCA0_DVS_R_LEAD BIT(16) + #define MISC_FT_STATUS_3_AD_RX_ARCA1_DVS_R_LEAD BIT(17) + #define MISC_FT_STATUS_3_AD_RX_ARCA2_DVS_R_LEAD BIT(18) + #define MISC_FT_STATUS_3_AD_RX_ARCA3_DVS_R_LEAD BIT(19) + #define MISC_FT_STATUS_3_AD_RX_ARCA4_DVS_R_LEAD BIT(20) + #define MISC_FT_STATUS_3_AD_RX_ARCA5_DVS_R_LEAD BIT(21) + #define MISC_FT_STATUS_3_AD_RX_ARCKE0_DVS_R_LEAD BIT(22) + #define MISC_FT_STATUS_3_AD_RX_ARCKE1_DVS_R_LEAD BIT(23) + #define MISC_FT_STATUS_3_AD_RX_ARCS0_DVS_R_LEAD BIT(24) + #define MISC_FT_STATUS_3_AD_RX_ARCS1_DVS_R_LEAD BIT(25) +#define MISC_FT_STATUS_4 0x000001c4 + #define MISC_FT_STATUS_4_AD_RX_ARCA0_DVS_F_LAG BIT(0) + #define MISC_FT_STATUS_4_AD_RX_ARCA1_DVS_F_LAG BIT(1) + #define MISC_FT_STATUS_4_AD_RX_ARCA2_DVS_F_LAG BIT(2) + #define MISC_FT_STATUS_4_AD_RX_ARCA3_DVS_F_LAG BIT(3) + #define MISC_FT_STATUS_4_AD_RX_ARCA4_DVS_F_LAG BIT(4) + #define MISC_FT_STATUS_4_AD_RX_ARCA5_DVS_F_LAG BIT(5) + #define MISC_FT_STATUS_4_AD_RX_ARCKE0_DVS_F_LAG BIT(6) + #define MISC_FT_STATUS_4_AD_RX_ARCKE1_DVS_F_LAG BIT(7) + #define MISC_FT_STATUS_4_AD_RX_ARCS0_DVS_F_LAG BIT(8) + #define MISC_FT_STATUS_4_AD_RX_ARCS1_DVS_F_LAG BIT(9) + #define MISC_FT_STATUS_4_AD_RX_ARCA0_DVS_F_LEAD BIT(16) + #define MISC_FT_STATUS_4_AD_RX_ARCA1_DVS_F_LEAD BIT(17) + #define MISC_FT_STATUS_4_AD_RX_ARCA2_DVS_F_LEAD BIT(18) + #define MISC_FT_STATUS_4_AD_RX_ARCA3_DVS_F_LEAD BIT(19) + #define MISC_FT_STATUS_4_AD_RX_ARCA4_DVS_F_LEAD BIT(20) + #define MISC_FT_STATUS_4_AD_RX_ARCA5_DVS_F_LEAD BIT(21) + #define MISC_FT_STATUS_4_AD_RX_ARCKE0_DVS_F_LEAD BIT(22) + #define MISC_FT_STATUS_4_AD_RX_ARCKE1_DVS_F_LEAD BIT(23) + #define MISC_FT_STATUS_4_AD_RX_ARCS0_DVS_F_LEAD BIT(24) + #define MISC_FT_STATUS_4_AD_RX_ARCS1_DVS_F_LEAD BIT(25) +#define MISC_STA_EXTLB_DBG0 0x000001c8 + #define MISC_STA_EXTLB_DBG0_STA_EXTLB_DVS_LEAD_0TO1 GENMASK(31, 0) +#define MISC_STA_EXTLB_DBG1 0x000001cc + #define MISC_STA_EXTLB_DBG1_STA_EXTLB_DVS_LEAD_1TO0 GENMASK(31, 0) +#define MISC_STA_EXTLB_DBG2 0x000001d0 + #define MISC_STA_EXTLB_DBG2_STA_EXTLB_DVS_LAG_0TO1 GENMASK(31, 0) +#define MISC_STA_EXTLB_DBG3 0x000001d4 + #define MISC_STA_EXTLB_DBG3_STA_EXTLB_DVS_LAG_1TO0 GENMASK(31, 0) + +#endif /*__DDRPHY_NAO_REG_H__*/ diff --git a/src/vendorcode/mediatek/mt8192/include/ddrphy_pll_reg.h b/src/vendorcode/mediatek/mt8192/include/ddrphy_pll_reg.h new file mode 100644 index 000000000000..4546910893ed --- /dev/null +++ b/src/vendorcode/mediatek/mt8192/include/ddrphy_pll_reg.h @@ -0,0 +1,387 @@ +/* SPDX-License-Identifier: BSD-3-Clause */ + +#ifndef __DDRPHY_PLL_REG_H__ +#define __DDRPHY_PLL_REG_H__ + +/* ----------------- Register Definitions ------------------- */ +#define PLL1 0x00000000 + #define PLL1_RG_RPHYPLL_SDM_SSC_EN BIT(2) + #define PLL1_RG_RPHYPLL_EN BIT(31) +#define PLL2 0x00000004 + #define PLL2_RG_RCLRPLL_SDM_SSC_EN BIT(2) + #define PLL2_RG_RCLRPLL_EN BIT(31) +#define PLL3 0x00000008 + #define PLL3_RG_RPHYPLL_TSTOP_EN BIT(0) + #define PLL3_RG_RPHYPLL_TSTOD_EN BIT(1) + #define PLL3_RG_RPHYPLL_TSTFM_EN BIT(2) + #define PLL3_RG_RPHYPLL_TSTCK_EN BIT(3) + #define PLL3_RG_RPHYPLL_TST_EN BIT(4) + #define PLL3_RG_RPHYPLL_TSTLVROD_EN BIT(5) + #define PLL3_RG_RPHYPLL_TST_SEL GENMASK(11, 8) +#define PLL4 0x0000000c + #define PLL4_RG_RPHYPLL_RESETB BIT(16) + #define PLL4_RG_RPHYPLL_ATPG_EN BIT(17) + #define PLL4_RG_RPHYPLL_MCK8X_SEL BIT(18) + #define PLL4_PLL4_RFU BIT(19) + #define PLL4_RG_RPHYPLL_SER_MODE BIT(20) + #define PLL4_RG_RPHYPLL_AD_MCK8X_EN BIT(21) + #define PLL4_RG_RPHYPLL_ADA_MCK8X_EN BIT(22) + #define PLL4_RESERVED_0X0C BIT(24) +#define PLL5 0x00000010 + #define PLL5_RESERVED_0X010 GENMASK(31, 0) +#define PLL6 0x00000014 + #define PLL6_RESERVED_0X014 GENMASK(31, 0) +#define PLL7 0x00000018 + #define PLL7_RESERVED_0X018 GENMASK(31, 0) +#define PLL8 0x0000001c + #define PLL8_RESERVED_0X01C GENMASK(31, 0) +#define PLL9 0x00000020 + #define PLL9_RESERVED_0X020 GENMASK(31, 0) +#define PLL10 0x00000024 + #define PLL10_RESERVED_0X024 GENMASK(31, 0) +#define PLL11 0x00000028 + #define PLL11_RESERVED_0X028 GENMASK(31, 0) +#define PLL12 0x0000002c + #define PLL12_RESERVED_0X02C GENMASK(31, 0) +#define PLL13 0x00000030 + #define PLL13_RESERVED_0X030 GENMASK(31, 0) +#define PLL14 0x00000034 + #define PLL14_RESERVED_0X034 GENMASK(31, 0) +#define PLL15 0x00000038 + #define PLL15_RESERVED_0X038 GENMASK(31, 0) +#define PLL16 0x0000003c + #define PLL16_RESERVED_0X03C GENMASK(31, 0) +#define SHU1_PLL0 0x00000d80 + #define SHU1_PLL0_RG_RPHYPLL_TOP_REV GENMASK(15, 0) + #define SHU1_PLL0_RG_RPHYPLL_LOAD_EN BIT(19) +#define SHU1_PLL1 0x00000d84 + #define SHU1_PLL1_RG_RPHYPLLGP_CK_SEL BIT(0) + #define SHU1_PLL1_SHU1_PLL1_RFU GENMASK(3, 1) + #define SHU1_PLL1_R_SHU_AUTO_PLL_MUX BIT(4) + #define SHU1_PLL1_RESERVED_0XD84 GENMASK(31, 5) +#define SHU1_PLL2 0x00000d88 + #define SHU1_PLL2_RG_RCLRPLL_LOAD_EN BIT(19) +#define SHU1_PLL3 0x00000d8c + #define SHU1_PLL3_RESERVED_0XD8C GENMASK(31, 0) +#define SHU1_PLL4 0x00000d90 + #define SHU1_PLL4_RG_RPHYPLL_RESERVED GENMASK(15, 0) + #define SHU1_PLL4_RG_RPHYPLL_FS GENMASK(19, 18) + #define SHU1_PLL4_RG_RPHYPLL_BW GENMASK(22, 20) + #define SHU1_PLL4_RG_RPHYPLL_ICHP GENMASK(25, 24) + #define SHU1_PLL4_RG_RPHYPLL_IBIAS GENMASK(27, 26) + #define SHU1_PLL4_RG_RPHYPLL_BLP BIT(29) + #define SHU1_PLL4_RG_RPHYPLL_BR BIT(30) + #define SHU1_PLL4_RG_RPHYPLL_BP BIT(31) +#define SHU1_PLL5 0x00000d94 + #define SHU1_PLL5_RG_RPHYPLL_SDM_FRA_EN BIT(0) + #define SHU1_PLL5_RG_RPHYPLL_SDM_PCW_CHG BIT(1) + #define SHU1_PLL5_RG_RPHYPLL_SDM_PCW GENMASK(31, 16) +#define SHU1_PLL6 0x00000d98 + #define SHU1_PLL6_RG_RCLRPLL_RESERVED GENMASK(15, 0) + #define SHU1_PLL6_RG_RCLRPLL_FS GENMASK(19, 18) + #define SHU1_PLL6_RG_RCLRPLL_BW GENMASK(22, 20) + #define SHU1_PLL6_RG_RCLRPLL_ICHP GENMASK(25, 24) + #define SHU1_PLL6_RG_RCLRPLL_IBIAS GENMASK(27, 26) + #define SHU1_PLL6_RG_RCLRPLL_BLP BIT(29) + #define SHU1_PLL6_RG_RCLRPLL_BR BIT(30) + #define SHU1_PLL6_RG_RCLRPLL_BP BIT(31) +#define SHU1_PLL7 0x00000d9c + #define SHU1_PLL7_RG_RCLRPLL_SDM_FRA_EN BIT(0) + #define SHU1_PLL7_RG_RCLRPLL_SDM_PCW_CHG BIT(1) + #define SHU1_PLL7_RG_RCLRPLL_SDM_PCW GENMASK(31, 16) +#define SHU1_PLL8 0x00000da0 + #define SHU1_PLL8_RG_RPHYPLL_POSDIV GENMASK(2, 0) + #define SHU1_PLL8_RG_RPHYPLL_PREDIV GENMASK(19, 18) +#define SHU1_PLL9 0x00000da4 + #define SHU1_PLL9_RG_RPHYPLL_RST_DLY GENMASK(9, 8) + #define SHU1_PLL9_RG_RPHYPLL_LVROD_EN BIT(12) + #define SHU1_PLL9_RG_RPHYPLL_MONREF_EN BIT(13) + #define SHU1_PLL9_RG_RPHYPLL_MONVC_EN GENMASK(15, 14) + #define SHU1_PLL9_RG_RPHYPLL_MONCK_EN BIT(16) +#define SHU1_PLL10 0x00000da8 + #define SHU1_PLL10_RG_RCLRPLL_POSDIV GENMASK(2, 0) + #define SHU1_PLL10_RG_RCLRPLL_PREDIV GENMASK(19, 18) +#define SHU1_PLL11 0x00000dac + #define SHU1_PLL11_RG_RCLRPLL_RST_DLY GENMASK(9, 8) + #define SHU1_PLL11_RG_RCLRPLL_LVROD_EN BIT(12) + #define SHU1_PLL11_RG_RCLRPLL_MONREF_EN BIT(13) + #define SHU1_PLL11_RG_RCLRPLL_MONVC_EN GENMASK(15, 14) + #define SHU1_PLL11_RG_RCLRPLL_MONCK_EN BIT(16) +#define SHU1_PLL12 0x00000db0 + #define SHU1_PLL12_RG_RCLRPLL_EXT_PODIV GENMASK(5, 0) + #define SHU1_PLL12_RG_RCLRPLL_BYPASS BIT(6) + #define SHU1_PLL12_RG_RCLRPLL_EXTPODIV_EN BIT(7) + #define SHU1_PLL12_RG_RCLRPLL_EXT_FBDIV GENMASK(13, 8) + #define SHU1_PLL12_RG_RCLRPLL_EXTFBDIV_EN BIT(15) + #define SHU1_PLL12_RG_RPHYPLL_EXT_FBDIV GENMASK(21, 16) + #define SHU1_PLL12_RG_RPHYPLL_EXTFBDIV_EN BIT(22) +#define SHU1_PLL13 0x00000db4 + #define SHU1_PLL13_RG_RCLRPLL_FB_DL GENMASK(5, 0) + #define SHU1_PLL13_RG_RCLRPLL_REF_DL GENMASK(13, 8) + #define SHU1_PLL13_RG_RPHYPLL_FB_DL GENMASK(21, 16) + #define SHU1_PLL13_RG_RPHYPLL_REF_DL GENMASK(29, 24) +#define SHU1_PLL14 0x00000db8 + #define SHU1_PLL14_RG_RPHYPLL_SDM_HREN BIT(0) + #define SHU1_PLL14_RG_RPHYPLL_SDM_SSC_PH_INIT BIT(1) + #define SHU1_PLL14_RG_RPHYPLL_SDM_SSC_PRD GENMASK(31, 16) +#define SHU1_PLL15 0x00000dbc + #define SHU1_PLL15_RG_RPHYPLL_SDM_SSC_DELTA GENMASK(15, 0) + #define SHU1_PLL15_RG_RPHYPLL_SDM_SSC_DELTA1 GENMASK(31, 16) +#define SHU1_PLL20 0x00000dd0 + #define SHU1_PLL20_RG_RCLRPLL_SDM_HREN BIT(0) + #define SHU1_PLL20_RG_RCLRPLL_SDM_SSC_PH_INIT BIT(1) + #define SHU1_PLL20_RG_RCLRPLL_SDM_SSC_PRD GENMASK(31, 16) +#define SHU1_PLL21 0x00000dd4 + #define SHU1_PLL21_RG_RCLRPLL_SDM_SSC_DELTA GENMASK(15, 0) + #define SHU1_PLL21_RG_RCLRPLL_SDM_SSC_DELTA1 GENMASK(31, 16) +#define SHU2_PLL0 0x00001280 + #define SHU2_PLL0_RG_RPHYPLL_TOP_REV GENMASK(15, 0) + #define SHU2_PLL0_RG_RPHYPLL_LOAD_EN BIT(19) +#define SHU2_PLL1 0x00001284 + #define SHU2_PLL1_RG_RPHYPLLGP_CK_SEL BIT(0) + #define SHU2_PLL1_SHU2_PLL1_RFU GENMASK(3, 1) + #define SHU2_PLL1_R_SHU_AUTO_PLL_MUX BIT(4) + #define SHU2_PLL1_RESERVED_0X1284 GENMASK(31, 5) +#define SHU2_PLL2 0x00001288 + #define SHU2_PLL2_RG_RCLRPLL_LOAD_EN BIT(19) +#define SHU2_PLL3 0x0000128c + #define SHU2_PLL3_RESERVED_0X128C GENMASK(31, 0) +#define SHU2_PLL4 0x00001290 + #define SHU2_PLL4_RG_RPHYPLL_RESERVED GENMASK(15, 0) + #define SHU2_PLL4_RG_RPHYPLL_FS GENMASK(19, 18) + #define SHU2_PLL4_RG_RPHYPLL_BW GENMASK(22, 20) + #define SHU2_PLL4_RG_RPHYPLL_ICHP GENMASK(25, 24) + #define SHU2_PLL4_RG_RPHYPLL_IBIAS GENMASK(27, 26) + #define SHU2_PLL4_RG_RPHYPLL_BLP BIT(29) + #define SHU2_PLL4_RG_RPHYPLL_BR BIT(30) + #define SHU2_PLL4_RG_RPHYPLL_BP BIT(31) +#define SHU2_PLL5 0x00001294 + #define SHU2_PLL5_RG_RPHYPLL_SDM_FRA_EN BIT(0) + #define SHU2_PLL5_RG_RPHYPLL_SDM_PCW_CHG BIT(1) + #define SHU2_PLL5_RG_RPHYPLL_SDM_PCW GENMASK(31, 16) +#define SHU2_PLL6 0x00001298 + #define SHU2_PLL6_RG_RCLRPLL_RESERVED GENMASK(15, 0) + #define SHU2_PLL6_RG_RCLRPLL_FS GENMASK(19, 18) + #define SHU2_PLL6_RG_RCLRPLL_BW GENMASK(22, 20) + #define SHU2_PLL6_RG_RCLRPLL_ICHP GENMASK(25, 24) + #define SHU2_PLL6_RG_RCLRPLL_IBIAS GENMASK(27, 26) + #define SHU2_PLL6_RG_RCLRPLL_BLP BIT(29) + #define SHU2_PLL6_RG_RCLRPLL_BR BIT(30) + #define SHU2_PLL6_RG_RCLRPLL_BP BIT(31) +#define SHU2_PLL7 0x0000129c + #define SHU2_PLL7_RG_RCLRPLL_SDM_FRA_EN BIT(0) + #define SHU2_PLL7_RG_RCLRPLL_SDM_PCW_CHG BIT(1) + #define SHU2_PLL7_RG_RCLRPLL_SDM_PCW GENMASK(31, 16) +#define SHU2_PLL8 0x000012a0 + #define SHU2_PLL8_RG_RPHYPLL_POSDIV GENMASK(2, 0) + #define SHU2_PLL8_RG_RPHYPLL_PREDIV GENMASK(19, 18) +#define SHU2_PLL9 0x000012a4 + #define SHU2_PLL9_RG_RPHYPLL_RST_DLY GENMASK(9, 8) + #define SHU2_PLL9_RG_RPHYPLL_LVROD_EN BIT(12) + #define SHU2_PLL9_RG_RPHYPLL_MONREF_EN BIT(13) + #define SHU2_PLL9_RG_RPHYPLL_MONVC_EN GENMASK(15, 14) + #define SHU2_PLL9_RG_RPHYPLL_MONCK_EN BIT(16) +#define SHU2_PLL10 0x000012a8 + #define SHU2_PLL10_RG_RCLRPLL_POSDIV GENMASK(2, 0) + #define SHU2_PLL10_RG_RCLRPLL_PREDIV GENMASK(19, 18) +#define SHU2_PLL11 0x000012ac + #define SHU2_PLL11_RG_RCLRPLL_RST_DLY GENMASK(9, 8) + #define SHU2_PLL11_RG_RCLRPLL_LVROD_EN BIT(12) + #define SHU2_PLL11_RG_RCLRPLL_MONREF_EN BIT(13) + #define SHU2_PLL11_RG_RCLRPLL_MONVC_EN GENMASK(15, 14) + #define SHU2_PLL11_RG_RCLRPLL_MONCK_EN BIT(16) +#define SHU2_PLL12 0x000012b0 + #define SHU2_PLL12_RG_RCLRPLL_EXT_PODIV GENMASK(5, 0) + #define SHU2_PLL12_RG_RCLRPLL_BYPASS BIT(6) + #define SHU2_PLL12_RG_RCLRPLL_EXTPODIV_EN BIT(7) + #define SHU2_PLL12_RG_RCLRPLL_EXT_FBDIV GENMASK(13, 8) + #define SHU2_PLL12_RG_RCLRPLL_EXTFBDIV_EN BIT(15) + #define SHU2_PLL12_RG_RPHYPLL_EXT_FBDIV GENMASK(21, 16) + #define SHU2_PLL12_RG_RPHYPLL_EXTFBDIV_EN BIT(22) +#define SHU2_PLL13 0x000012b4 + #define SHU2_PLL13_RG_RCLRPLL_FB_DL GENMASK(5, 0) + #define SHU2_PLL13_RG_RCLRPLL_REF_DL GENMASK(13, 8) + #define SHU2_PLL13_RG_RPHYPLL_FB_DL GENMASK(21, 16) + #define SHU2_PLL13_RG_RPHYPLL_REF_DL GENMASK(29, 24) +#define SHU2_PLL14 0x000012b8 + #define SHU2_PLL14_RG_RPHYPLL_SDM_HREN BIT(0) + #define SHU2_PLL14_RG_RPHYPLL_SDM_SSC_PH_INIT BIT(1) + #define SHU2_PLL14_RG_RPHYPLL_SDM_SSC_PRD GENMASK(31, 16) +#define SHU2_PLL15 0x000012bc + #define SHU2_PLL15_RG_RPHYPLL_SDM_SSC_DELTA GENMASK(15, 0) + #define SHU2_PLL15_RG_RPHYPLL_SDM_SSC_DELTA1 GENMASK(31, 16) +#define SHU2_PLL20 0x000012d0 + #define SHU2_PLL20_RG_RCLRPLL_SDM_HREN BIT(0) + #define SHU2_PLL20_RG_RCLRPLL_SDM_SSC_PH_INIT BIT(1) + #define SHU2_PLL20_RG_RCLRPLL_SDM_SSC_PRD GENMASK(31, 16) +#define SHU2_PLL21 0x000012d4 + #define SHU2_PLL21_RG_RCLRPLL_SDM_SSC_DELTA GENMASK(15, 0) + #define SHU2_PLL21_RG_RCLRPLL_SDM_SSC_DELTA1 GENMASK(31, 16) +#define SHU3_PLL0 0x00001780 + #define SHU3_PLL0_RG_RPHYPLL_TOP_REV GENMASK(15, 0) + #define SHU3_PLL0_RG_RPHYPLL_LOAD_EN BIT(19) +#define SHU3_PLL1 0x00001784 + #define SHU3_PLL1_RG_RPHYPLLGP_CK_SEL BIT(0) + #define SHU3_PLL1_SHU3_PLL1_RFU GENMASK(3, 1) + #define SHU3_PLL1_R_SHU_AUTO_PLL_MUX BIT(4) + #define SHU3_PLL1_RESERVED_0X1784 GENMASK(31, 5) +#define SHU3_PLL2 0x00001788 + #define SHU3_PLL2_RG_RCLRPLL_LOAD_EN BIT(19) +#define SHU3_PLL3 0x0000178c + #define SHU3_PLL3_RESERVED_0X178C GENMASK(31, 0) +#define SHU3_PLL4 0x00001790 + #define SHU3_PLL4_RG_RPHYPLL_RESERVED GENMASK(15, 0) + #define SHU3_PLL4_RG_RPHYPLL_FS GENMASK(19, 18) + #define SHU3_PLL4_RG_RPHYPLL_BW GENMASK(22, 20) + #define SHU3_PLL4_RG_RPHYPLL_ICHP GENMASK(25, 24) + #define SHU3_PLL4_RG_RPHYPLL_IBIAS GENMASK(27, 26) + #define SHU3_PLL4_RG_RPHYPLL_BLP BIT(29) + #define SHU3_PLL4_RG_RPHYPLL_BR BIT(30) + #define SHU3_PLL4_RG_RPHYPLL_BP BIT(31) +#define SHU3_PLL5 0x00001794 + #define SHU3_PLL5_RG_RPHYPLL_SDM_FRA_EN BIT(0) + #define SHU3_PLL5_RG_RPHYPLL_SDM_PCW_CHG BIT(1) + #define SHU3_PLL5_RG_RPHYPLL_SDM_PCW GENMASK(31, 16) +#define SHU3_PLL6 0x00001798 + #define SHU3_PLL6_RG_RCLRPLL_RESERVED GENMASK(15, 0) + #define SHU3_PLL6_RG_RCLRPLL_FS GENMASK(19, 18) + #define SHU3_PLL6_RG_RCLRPLL_BW GENMASK(22, 20) + #define SHU3_PLL6_RG_RCLRPLL_ICHP GENMASK(25, 24) + #define SHU3_PLL6_RG_RCLRPLL_IBIAS GENMASK(27, 26) + #define SHU3_PLL6_RG_RCLRPLL_BLP BIT(29) + #define SHU3_PLL6_RG_RCLRPLL_BR BIT(30) + #define SHU3_PLL6_RG_RCLRPLL_BP BIT(31) +#define SHU3_PLL7 0x0000179c + #define SHU3_PLL7_RG_RCLRPLL_SDM_FRA_EN BIT(0) + #define SHU3_PLL7_RG_RCLRPLL_SDM_PCW_CHG BIT(1) + #define SHU3_PLL7_RG_RCLRPLL_SDM_PCW GENMASK(31, 16) +#define SHU3_PLL8 0x000017a0 + #define SHU3_PLL8_RG_RPHYPLL_POSDIV GENMASK(2, 0) + #define SHU3_PLL8_RG_RPHYPLL_PREDIV GENMASK(19, 18) +#define SHU3_PLL9 0x000017a4 + #define SHU3_PLL9_RG_RPHYPLL_RST_DLY GENMASK(9, 8) + #define SHU3_PLL9_RG_RPHYPLL_LVROD_EN BIT(12) + #define SHU3_PLL9_RG_RPHYPLL_MONREF_EN BIT(13) + #define SHU3_PLL9_RG_RPHYPLL_MONVC_EN GENMASK(15, 14) + #define SHU3_PLL9_RG_RPHYPLL_MONCK_EN BIT(16) +#define SHU3_PLL10 0x000017a8 + #define SHU3_PLL10_RG_RCLRPLL_POSDIV GENMASK(2, 0) + #define SHU3_PLL10_RG_RCLRPLL_PREDIV GENMASK(19, 18) +#define SHU3_PLL11 0x000017ac + #define SHU3_PLL11_RG_RCLRPLL_RST_DLY GENMASK(9, 8) + #define SHU3_PLL11_RG_RCLRPLL_LVROD_EN BIT(12) + #define SHU3_PLL11_RG_RCLRPLL_MONREF_EN BIT(13) + #define SHU3_PLL11_RG_RCLRPLL_MONVC_EN GENMASK(15, 14) + #define SHU3_PLL11_RG_RCLRPLL_MONCK_EN BIT(16) +#define SHU3_PLL12 0x000017b0 + #define SHU3_PLL12_RG_RCLRPLL_EXT_PODIV GENMASK(5, 0) + #define SHU3_PLL12_RG_RCLRPLL_BYPASS BIT(6) + #define SHU3_PLL12_RG_RCLRPLL_EXTPODIV_EN BIT(7) + #define SHU3_PLL12_RG_RCLRPLL_EXT_FBDIV GENMASK(13, 8) + #define SHU3_PLL12_RG_RCLRPLL_EXTFBDIV_EN BIT(15) + #define SHU3_PLL12_RG_RPHYPLL_EXT_FBDIV GENMASK(21, 16) + #define SHU3_PLL12_RG_RPHYPLL_EXTFBDIV_EN BIT(22) +#define SHU3_PLL13 0x000017b4 + #define SHU3_PLL13_RG_RCLRPLL_FB_DL GENMASK(5, 0) + #define SHU3_PLL13_RG_RCLRPLL_REF_DL GENMASK(13, 8) + #define SHU3_PLL13_RG_RPHYPLL_FB_DL GENMASK(21, 16) + #define SHU3_PLL13_RG_RPHYPLL_REF_DL GENMASK(29, 24) +#define SHU3_PLL14 0x000017b8 + #define SHU3_PLL14_RG_RPHYPLL_SDM_HREN BIT(0) + #define SHU3_PLL14_RG_RPHYPLL_SDM_SSC_PH_INIT BIT(1) + #define SHU3_PLL14_RG_RPHYPLL_SDM_SSC_PRD GENMASK(31, 16) +#define SHU3_PLL15 0x000017bc + #define SHU3_PLL15_RG_RPHYPLL_SDM_SSC_DELTA GENMASK(15, 0) + #define SHU3_PLL15_RG_RPHYPLL_SDM_SSC_DELTA1 GENMASK(31, 16) +#define SHU3_PLL20 0x000017d0 + #define SHU3_PLL20_RG_RCLRPLL_SDM_HREN BIT(0) + #define SHU3_PLL20_RG_RCLRPLL_SDM_SSC_PH_INIT BIT(1) + #define SHU3_PLL20_RG_RCLRPLL_SDM_SSC_PRD GENMASK(31, 16) +#define SHU3_PLL21 0x000017d4 + #define SHU3_PLL21_RG_RCLRPLL_SDM_SSC_DELTA GENMASK(15, 0) + #define SHU3_PLL21_RG_RCLRPLL_SDM_SSC_DELTA1 GENMASK(31, 16) +#define SHU4_PLL0 0x00001c80 + #define SHU4_PLL0_RG_RPHYPLL_TOP_REV GENMASK(15, 0) + #define SHU4_PLL0_RG_RPHYPLL_LOAD_EN BIT(19) +#define SHU4_PLL1 0x00001c84 + #define SHU4_PLL1_RG_RPHYPLLGP_CK_SEL BIT(0) + #define SHU4_PLL1_SHU4_PLL1_RFU GENMASK(3, 1) + #define SHU4_PLL1_R_SHU_AUTO_PLL_MUX BIT(4) + #define SHU4_PLL1_RESERVED_0X1C84 GENMASK(31, 5) +#define SHU4_PLL2 0x00001c88 + #define SHU4_PLL2_RG_RCLRPLL_LOAD_EN BIT(19) +#define SHU4_PLL3 0x00001c8c + #define SHU4_PLL3_RESERVED_0X1C8C GENMASK(31, 0) +#define SHU4_PLL4 0x00001c90 + #define SHU4_PLL4_RG_RPHYPLL_RESERVED GENMASK(15, 0) + #define SHU4_PLL4_RG_RPHYPLL_FS GENMASK(19, 18) + #define SHU4_PLL4_RG_RPHYPLL_BW GENMASK(22, 20) + #define SHU4_PLL4_RG_RPHYPLL_ICHP GENMASK(25, 24) + #define SHU4_PLL4_RG_RPHYPLL_IBIAS GENMASK(27, 26) + #define SHU4_PLL4_RG_RPHYPLL_BLP BIT(29) + #define SHU4_PLL4_RG_RPHYPLL_BR BIT(30) + #define SHU4_PLL4_RG_RPHYPLL_BP BIT(31) +#define SHU4_PLL5 0x00001c94 + #define SHU4_PLL5_RG_RPHYPLL_SDM_FRA_EN BIT(0) + #define SHU4_PLL5_RG_RPHYPLL_SDM_PCW_CHG BIT(1) + #define SHU4_PLL5_RG_RPHYPLL_SDM_PCW GENMASK(31, 16) +#define SHU4_PLL6 0x00001c98 + #define SHU4_PLL6_RG_RCLRPLL_RESERVED GENMASK(15, 0) + #define SHU4_PLL6_RG_RCLRPLL_FS GENMASK(19, 18) + #define SHU4_PLL6_RG_RCLRPLL_BW GENMASK(22, 20) + #define SHU4_PLL6_RG_RCLRPLL_ICHP GENMASK(25, 24) + #define SHU4_PLL6_RG_RCLRPLL_IBIAS GENMASK(27, 26) + #define SHU4_PLL6_RG_RCLRPLL_BLP BIT(29) + #define SHU4_PLL6_RG_RCLRPLL_BR BIT(30) + #define SHU4_PLL6_RG_RCLRPLL_BP BIT(31) +#define SHU4_PLL7 0x00001c9c + #define SHU4_PLL7_RG_RCLRPLL_SDM_FRA_EN BIT(0) + #define SHU4_PLL7_RG_RCLRPLL_SDM_PCW_CHG BIT(1) + #define SHU4_PLL7_RG_RCLRPLL_SDM_PCW GENMASK(31, 16) +#define SHU4_PLL8 0x00001ca0 + #define SHU4_PLL8_RG_RPHYPLL_POSDIV GENMASK(2, 0) + #define SHU4_PLL8_RG_RPHYPLL_PREDIV GENMASK(19, 18) +#define SHU4_PLL9 0x00001ca4 + #define SHU4_PLL9_RG_RPHYPLL_RST_DLY GENMASK(9, 8) + #define SHU4_PLL9_RG_RPHYPLL_LVROD_EN BIT(12) + #define SHU4_PLL9_RG_RPHYPLL_MONREF_EN BIT(13) + #define SHU4_PLL9_RG_RPHYPLL_MONVC_EN GENMASK(15, 14) + #define SHU4_PLL9_RG_RPHYPLL_MONCK_EN BIT(16) +#define SHU4_PLL10 0x00001ca8 + #define SHU4_PLL10_RG_RCLRPLL_POSDIV GENMASK(2, 0) + #define SHU4_PLL10_RG_RCLRPLL_PREDIV GENMASK(19, 18) +#define SHU4_PLL11 0x00001cac + #define SHU4_PLL11_RG_RCLRPLL_RST_DLY GENMASK(9, 8) + #define SHU4_PLL11_RG_RCLRPLL_LVROD_EN BIT(12) + #define SHU4_PLL11_RG_RCLRPLL_MONREF_EN BIT(13) + #define SHU4_PLL11_RG_RCLRPLL_MONVC_EN GENMASK(15, 14) + #define SHU4_PLL11_RG_RCLRPLL_MONCK_EN BIT(16) +#define SHU4_PLL12 0x00001cb0 + #define SHU4_PLL12_RG_RCLRPLL_EXT_PODIV GENMASK(5, 0) + #define SHU4_PLL12_RG_RCLRPLL_BYPASS BIT(6) + #define SHU4_PLL12_RG_RCLRPLL_EXTPODIV_EN BIT(7) + #define SHU4_PLL12_RG_RCLRPLL_EXT_FBDIV GENMASK(13, 8) + #define SHU4_PLL12_RG_RCLRPLL_EXTFBDIV_EN BIT(15) + #define SHU4_PLL12_RG_RPHYPLL_EXT_FBDIV GENMASK(21, 16) + #define SHU4_PLL12_RG_RPHYPLL_EXTFBDIV_EN BIT(22) +#define SHU4_PLL13 0x00001cb4 + #define SHU4_PLL13_RG_RCLRPLL_FB_DL GENMASK(5, 0) + #define SHU4_PLL13_RG_RCLRPLL_REF_DL GENMASK(13, 8) + #define SHU4_PLL13_RG_RPHYPLL_FB_DL GENMASK(21, 16) + #define SHU4_PLL13_RG_RPHYPLL_REF_DL GENMASK(29, 24) +#define SHU4_PLL14 0x00001cb8 + #define SHU4_PLL14_RG_RPHYPLL_SDM_HREN BIT(0) + #define SHU4_PLL14_RG_RPHYPLL_SDM_SSC_PH_INIT BIT(1) + #define SHU4_PLL14_RG_RPHYPLL_SDM_SSC_PRD GENMASK(31, 16) +#define SHU4_PLL15 0x00001cbc + #define SHU4_PLL15_RG_RPHYPLL_SDM_SSC_DELTA GENMASK(15, 0) + #define SHU4_PLL15_RG_RPHYPLL_SDM_SSC_DELTA1 GENMASK(31, 16) +#define SHU4_PLL20 0x00001cd0 + #define SHU4_PLL20_RG_RCLRPLL_SDM_HREN BIT(0) + #define SHU4_PLL20_RG_RCLRPLL_SDM_SSC_PH_INIT BIT(1) + #define SHU4_PLL20_RG_RCLRPLL_SDM_SSC_PRD GENMASK(31, 16) +#define SHU4_PLL21 0x00001cd4 + #define SHU4_PLL21_RG_RCLRPLL_SDM_SSC_DELTA GENMASK(15, 0) + #define SHU4_PLL21_RG_RCLRPLL_SDM_SSC_DELTA1 GENMASK(31, 16) + +#endif /*__DDRPHY_PLL_REG_H__*/ diff --git a/src/vendorcode/mediatek/mt8192/include/ddrphy_wo_pll_reg.h b/src/vendorcode/mediatek/mt8192/include/ddrphy_wo_pll_reg.h new file mode 100644 index 000000000000..10cda8c9e419 --- /dev/null +++ b/src/vendorcode/mediatek/mt8192/include/ddrphy_wo_pll_reg.h @@ -0,0 +1,4604 @@ +/* SPDX-License-Identifier: BSD-3-Clause */ + +#ifndef __DDRPHY_WO_PLL_REG_H__ +#define __DDRPHY_WO_PLL_REG_H__ + +/* ----------------- Register Definitions ------------------- */ +#define B0_DLL_ARPI0 0x00000080 + #define B0_DLL_ARPI0_RG_ARMCTLPLL_CK_SEL_B0 BIT(1) + #define B0_DLL_ARPI0_RG_ARPI_RESETB_B0 BIT(3) + #define B0_DLL_ARPI0_RG_ARPI_LS_EN_B0 BIT(4) + #define B0_DLL_ARPI0_RG_ARPI_LS_SEL_B0 BIT(5) + #define B0_DLL_ARPI0_RG_ARPI_MCK8X_SEL_B0 BIT(6) +#define B0_DLL_ARPI1 0x00000084 + #define B0_DLL_ARPI1_RG_ARPI_DQSIEN_JUMP_EN_B0 BIT(11) + #define B0_DLL_ARPI1_RG_ARPI_DQ_JUMP_EN_B0 BIT(13) + #define B0_DLL_ARPI1_RG_ARPI_DQM_JUMP_EN_B0 BIT(14) + #define B0_DLL_ARPI1_RG_ARPI_DQS_JUMP_EN_B0 BIT(15) + #define B0_DLL_ARPI1_RG_ARPI_FB_JUMP_EN_B0 BIT(17) + #define B0_DLL_ARPI1_RG_ARPI_MCTL_JUMP_EN_B0 BIT(19) + #define B0_DLL_ARPI1_RG_ARPISM_MCK_SEL_B0_REG_OPT BIT(20) + #define B0_DLL_ARPI1_RG_ARPISM_MCK_SEL_B0 BIT(21) + #define B0_DLL_ARPI1_RG_ARPI_SET_UPDN_B0 GENMASK(30, 28) +#define B0_DLL_ARPI2 0x00000088 + #define B0_DLL_ARPI2_RG_ARDLL_PHDET_EN_B0 BIT(0) + #define B0_DLL_ARPI2_RG_ARPI_MPDIV_CG_B0 BIT(10) + #define B0_DLL_ARPI2_RG_ARPI_CG_DQSIEN_B0 BIT(11) + #define B0_DLL_ARPI2_RG_ARPI_CG_DQ_B0 BIT(13) + #define B0_DLL_ARPI2_RG_ARPI_CG_DQM_B0 BIT(14) + #define B0_DLL_ARPI2_RG_ARPI_CG_DQS_B0 BIT(15) + #define B0_DLL_ARPI2_RG_ARPI_CG_FB_B0 BIT(17) + #define B0_DLL_ARPI2_RG_ARPI_CG_MCTL_B0 BIT(19) + #define B0_DLL_ARPI2_RG_ARPI_CG_MCK_FB2DLL_B0 BIT(27) + #define B0_DLL_ARPI2_RG_ARPI_CG_MCK_B0 BIT(31) +#define B0_DLL_ARPI3 0x0000008c + #define B0_DLL_ARPI3_RG_ARPI_DQSIEN_EN_B0 BIT(11) + #define B0_DLL_ARPI3_RG_ARPI_DQ_EN_B0 BIT(13) + #define B0_DLL_ARPI3_RG_ARPI_DQM_EN_B0 BIT(14) + #define B0_DLL_ARPI3_RG_ARPI_DQS_EN_B0 BIT(15) + #define B0_DLL_ARPI3_RG_ARPI_FB_EN_B0 BIT(17) + #define B0_DLL_ARPI3_RG_ARPI_MCTL_EN_B0 BIT(19) +#define B0_DLL_ARPI4 0x00000090 + #define B0_DLL_ARPI4_RG_ARPI_BYPASS_DQSIEN_B0 BIT(11) + #define B0_DLL_ARPI4_RG_ARPI_BYPASS_DQ_B0 BIT(13) + #define B0_DLL_ARPI4_RG_ARPI_BYPASS_DQM_B0 BIT(14) + #define B0_DLL_ARPI4_RG_ARPI_BYPASS_DQS_B0 BIT(15) + #define B0_DLL_ARPI4_RG_ARPI_BYPASS_FB_B0 BIT(17) + #define B0_DLL_ARPI4_RG_ARPI_BYPASS_MCTL_B0 BIT(19) +#define B0_DLL_ARPI5 0x00000094 + #define B0_DLL_ARPI5_RG_ARDLL_DIV_MCTL_B0 GENMASK(3, 2) + #define B0_DLL_ARPI5_RG_ARDLL_MON_SEL_B0 GENMASK(7, 4) + #define B0_DLL_ARPI5_RG_ARDLL_DIV_DEC_B0 BIT(8) + #define B0_DLL_ARPI5_B0_DLL_ARPI5_RFU GENMASK(23, 12) + #define B0_DLL_ARPI5_RG_ARDLL_FJ_OUT_MODE_SEL_B0 BIT(25) + #define B0_DLL_ARPI5_RG_ARDLL_FJ_OUT_MODE_B0 BIT(26) + #define B0_DLL_ARPI5_B0_DLL_ARPI5_RFU1 BIT(31) +#define B0_DQ0 0x00000098 + #define B0_DQ0_RG_RX_ARDQ0_OFFC_B0 GENMASK(3, 0) + #define B0_DQ0_RG_RX_ARDQ1_OFFC_B0 GENMASK(7, 4) + #define B0_DQ0_RG_RX_ARDQ2_OFFC_B0 GENMASK(11, 8) + #define B0_DQ0_RG_RX_ARDQ3_OFFC_B0 GENMASK(15, 12) + #define B0_DQ0_RG_RX_ARDQ4_OFFC_B0 GENMASK(19, 16) + #define B0_DQ0_RG_RX_ARDQ5_OFFC_B0 GENMASK(23, 20) + #define B0_DQ0_RG_RX_ARDQ6_OFFC_B0 GENMASK(27, 24) + #define B0_DQ0_RG_RX_ARDQ7_OFFC_B0 GENMASK(31, 28) +#define B0_DQ1 0x0000009c + #define B0_DQ1_RG_RX_ARDQM0_OFFC_B0 GENMASK(3, 0) +#define B0_DQ2 0x000000a0 + #define B0_DQ2_RG_TX_ARDQS0_ODTEN_DIS_B0 BIT(16) + #define B0_DQ2_RG_TX_ARDQS0_OE_DIS_B0 BIT(17) + #define B0_DQ2_RG_TX_ARDQM0_ODTEN_DIS_B0 BIT(18) + #define B0_DQ2_RG_TX_ARDQM0_OE_DIS_B0 BIT(19) + #define B0_DQ2_RG_TX_ARDQ_ODTEN_DIS_B0 BIT(20) + #define B0_DQ2_RG_TX_ARDQ_OE_DIS_B0 BIT(21) +#define B0_DQ3 0x000000a4 + #define B0_DQ3_RG_ARDQ_ATPG_EN_B0 BIT(0) + #define B0_DQ3_RG_RX_ARDQ_SMT_EN_B0 BIT(1) + #define B0_DQ3_RG_TX_ARDQ_EN_B0 BIT(2) + #define B0_DQ3_RG_ARDQ_RESETB_B0 BIT(3) + #define B0_DQ3_RG_RX_ARDQS0_IN_BUFF_EN_B0 BIT(5) + #define B0_DQ3_RG_RX_ARDQM0_IN_BUFF_EN_B0 BIT(6) + #define B0_DQ3_RG_RX_ARDQ_IN_BUFF_EN_B0 BIT(7) + #define B0_DQ3_RG_RX_ARDQ_STBENCMP_EN_B0 BIT(10) + #define B0_DQ3_RG_RX_ARDQ_OFFC_EN_B0 BIT(11) + #define B0_DQ3_RG_RX_ARDQS0_SWAP_EN_B0 BIT(15) +#define B0_DQ4 0x000000a8 + #define B0_DQ4_RG_RX_ARDQS_EYE_R_DLY_B0 GENMASK(6, 0) + #define B0_DQ4_RG_RX_ARDQS_EYE_F_DLY_B0 GENMASK(14, 8) + #define B0_DQ4_RG_RX_ARDQ_EYE_R_DLY_B0 GENMASK(21, 16) + #define B0_DQ4_RG_RX_ARDQ_EYE_F_DLY_B0 GENMASK(29, 24) +#define B0_DQ5 0x000000ac + #define B0_DQ5_B0_DQ5_RFU GENMASK(7, 0) + #define B0_DQ5_RG_RX_ARDQ_EYE_VREF_SEL_B0 GENMASK(13, 8) + #define B0_DQ5_RG_RX_ARDQ_VREF_EN_B0 BIT(16) + #define B0_DQ5_RG_RX_ARDQ_EYE_VREF_EN_B0 BIT(17) + #define B0_DQ5_RG_RX_ARDQ_EYE_SEL_B0 GENMASK(23, 20) + #define B0_DQ5_RG_RX_ARDQ_EYE_EN_B0 BIT(24) + #define B0_DQ5_RG_RX_ARDQ_EYE_STBEN_RESETB_B0 BIT(25) + #define B0_DQ5_RG_RX_ARDQS0_DVS_EN_B0 BIT(31) +#define B0_DQ6 0x000000b0 + #define B0_DQ6_RG_RX_ARDQ_BIAS_PS_B0 GENMASK(1, 0) + #define B0_DQ6_RG_TX_ARDQ_OE_EXT_DIS_B0 BIT(2) + #define B0_DQ6_RG_TX_ARDQ_ODTEN_EXT_DIS_B0 BIT(3) + #define B0_DQ6_RG_TX_ARDQ_SER_MODE_B0 BIT(4) + #define B0_DQ6_RG_RX_ARDQ_RPRE_TOG_EN_B0 BIT(5) + #define B0_DQ6_RG_RX_ARDQ_RES_BIAS_EN_B0 BIT(6) + #define B0_DQ6_RG_RX_ARDQ_OP_BIAS_SW_EN_B0 BIT(7) + #define B0_DQ6_RG_RX_ARDQ_LPBK_EN_B0 BIT(8) + #define B0_DQ6_RG_RX_ARDQ_O1_SEL_B0 BIT(9) + #define B0_DQ6_RG_RX_ARDQ_JM_SEL_B0 BIT(11) + #define B0_DQ6_RG_RX_ARDQ_BIAS_EN_B0 BIT(12) + #define B0_DQ6_RG_RX_ARDQ_BIAS_VREF_SEL_B0 GENMASK(15, 14) + #define B0_DQ6_RG_RX_ARDQ_DDR4_SEL_B0 BIT(16) + #define B0_DQ6_RG_TX_ARDQ_DDR4_SEL_B0 BIT(17) + #define B0_DQ6_RG_RX_ARDQ_DDR3_SEL_B0 BIT(18) + #define B0_DQ6_RG_TX_ARDQ_DDR3_SEL_B0 BIT(19) + #define B0_DQ6_RG_RX_ARDQ_EYE_DLY_DQS_BYPASS_B0 BIT(24) + #define B0_DQ6_RG_RX_ARDQ_EYE_OE_GATE_EN_B0 BIT(28) + #define B0_DQ6_RG_RX_ARDQ_DMRANK_OUTSEL_B0 BIT(31) +#define B0_DQ7 0x000000b4 + #define B0_DQ7_RG_TX_ARDQS0B_PULL_DN_B0 BIT(0) + #define B0_DQ7_RG_TX_ARDQS0B_PULL_UP_B0 BIT(1) + #define B0_DQ7_RG_TX_ARDQS0_PULL_DN_B0 BIT(2) + #define B0_DQ7_RG_TX_ARDQS0_PULL_UP_B0 BIT(3) + #define B0_DQ7_RG_TX_ARDQM0_PULL_DN_B0 BIT(4) + #define B0_DQ7_RG_TX_ARDQM0_PULL_UP_B0 BIT(5) + #define B0_DQ7_RG_TX_ARDQ_PULL_DN_B0 BIT(6) + #define B0_DQ7_RG_TX_ARDQ_PULL_UP_B0 BIT(7) + #define B0_DQ7_RG_TX_ARDQS0B_PULL_DN_B0_LP4Y BIT(16) +#define B0_DQ8 0x000000b8 + #define B0_DQ8_RG_TX_ARDQ_EN_LP4P_B0 BIT(0) + #define B0_DQ8_RG_TX_ARDQ_EN_CAP_LP4P_B0 BIT(1) + #define B0_DQ8_RG_TX_ARDQ_CAP_DET_B0 BIT(2) + #define B0_DQ8_RG_TX_ARDQ_CKE_MCK4X_SEL_B0 GENMASK(4, 3) + #define B0_DQ8_RG_ARPI_TX_CG_DQ_EN_B0 BIT(5) + #define B0_DQ8_RG_ARPI_TX_CG_DQM_EN_B0 BIT(6) + #define B0_DQ8_RG_ARPI_TX_CG_DQS_EN_B0 BIT(7) + #define B0_DQ8_RG_RX_ARDQS_BURST_E1_EN_B0 BIT(8) + #define B0_DQ8_RG_RX_ARDQS_BURST_E2_EN_B0 BIT(9) + #define B0_DQ8_RG_RX_ARDQS_DQSSTB_CG_EN_B0 BIT(10) + #define B0_DQ8_RG_RX_ARDQS_GATE_EN_MODE_B0 BIT(12) + #define B0_DQ8_RG_RX_ARDQS_SER_RST_MODE_B0 BIT(13) + #define B0_DQ8_RG_ARDLL_RESETB_B0 BIT(15) +#define B0_DQ9 0x000000bc + #define B0_DQ9_RG_RX_ARDQ_STBEN_RESETB_B0 BIT(0) + #define B0_DQ9_RG_RX_ARDQS0_STBEN_RESETB_B0 BIT(4) + #define B0_DQ9_RG_RX_ARDQS0_DQSIENMODE_B0 BIT(5) + #define B0_DQ9_R_DMRXFIFO_STBENCMP_EN_B0 BIT(7) + #define B0_DQ9_R_IN_GATE_EN_LOW_OPT_B0 GENMASK(15, 8) + #define B0_DQ9_R_DMDQSIEN_VALID_LAT_B0 GENMASK(18, 16) + #define B0_DQ9_R_DMDQSIEN_RDSEL_LAT_B0 GENMASK(22, 20) + #define B0_DQ9_R_DMRXDVS_VALID_LAT_B0 GENMASK(26, 24) + #define B0_DQ9_R_DMRXDVS_RDSEL_LAT_B0 GENMASK(30, 28) +#define RFU_0X0C0 0x000000c0 + #define RFU_0X0C0_RESERVED_0X0C0 GENMASK(31, 0) +#define RFU_0X0C4 0x000000c4 + #define RFU_0X0C4_RESERVED_0X0C4 GENMASK(31, 0) +#define RFU_0X0C8 0x000000c8 + #define RFU_0X0C8_RESERVED_0X0C8 GENMASK(31, 0) +#define RFU_0X0CC 0x000000cc + #define RFU_0X0CC_RESERVED_0X0CC GENMASK(31, 0) +#define B0_TX_MCK 0x000000d0 + #define B0_TX_MCK_R_DM_TX_MCK_FRUN_B0 GENMASK(9, 0) +#define RFU_0X0D4 0x000000d4 + #define RFU_0X0D4_RESERVED_0X0D4 GENMASK(31, 0) +#define RFU_0X0D8 0x000000d8 + #define RFU_0X0D8_RESERVED_0X0D8 GENMASK(31, 0) +#define RFU_0X0DC 0x000000dc + #define RFU_0X0DC_RESERVED_0X0DC GENMASK(31, 0) +#define B1_DLL_ARPI0 0x00000100 + #define B1_DLL_ARPI0_RG_ARMCTLPLL_CK_SEL_B1 BIT(1) + #define B1_DLL_ARPI0_RG_ARPI_RESETB_B1 BIT(3) + #define B1_DLL_ARPI0_RG_ARPI_LS_EN_B1 BIT(4) + #define B1_DLL_ARPI0_RG_ARPI_LS_SEL_B1 BIT(5) + #define B1_DLL_ARPI0_RG_ARPI_MCK8X_SEL_B1 BIT(6) +#define B1_DLL_ARPI1 0x00000104 + #define B1_DLL_ARPI1_RG_ARPI_DQSIEN_JUMP_EN_B1 BIT(11) + #define B1_DLL_ARPI1_RG_ARPI_DQ_JUMP_EN_B1 BIT(13) + #define B1_DLL_ARPI1_RG_ARPI_DQM_JUMP_EN_B1 BIT(14) + #define B1_DLL_ARPI1_RG_ARPI_DQS_JUMP_EN_B1 BIT(15) + #define B1_DLL_ARPI1_RG_ARPI_FB_JUMP_EN_B1 BIT(17) + #define B1_DLL_ARPI1_RG_ARPI_MCTL_JUMP_EN_B1 BIT(19) + #define B1_DLL_ARPI1_RG_ARPISM_MCK_SEL_B1_REG_OPT BIT(20) + #define B1_DLL_ARPI1_RG_ARPISM_MCK_SEL_B1 BIT(21) + #define B1_DLL_ARPI1_RG_ARPI_SET_UPDN_B1 GENMASK(30, 28) +#define B1_DLL_ARPI2 0x00000108 + #define B1_DLL_ARPI2_RG_ARDLL_PHDET_EN_B1 BIT(0) + #define B1_DLL_ARPI2_RG_ARPI_MPDIV_CG_B1 BIT(10) + #define B1_DLL_ARPI2_RG_ARPI_CG_DQSIEN_B1 BIT(11) + #define B1_DLL_ARPI2_RG_ARPI_CG_DQ_B1 BIT(13) + #define B1_DLL_ARPI2_RG_ARPI_CG_DQM_B1 BIT(14) + #define B1_DLL_ARPI2_RG_ARPI_CG_DQS_B1 BIT(15) + #define B1_DLL_ARPI2_RG_ARPI_CG_FB_B1 BIT(17) + #define B1_DLL_ARPI2_RG_ARPI_CG_MCTL_B1 BIT(19) + #define B1_DLL_ARPI2_RG_ARPI_CG_MCK_FB2DLL_B1 BIT(27) + #define B1_DLL_ARPI2_RG_ARPI_CG_MCK_B1 BIT(31) +#define B1_DLL_ARPI3 0x0000010c + #define B1_DLL_ARPI3_RG_ARPI_DQSIEN_EN_B1 BIT(11) + #define B1_DLL_ARPI3_RG_ARPI_DQ_EN_B1 BIT(13) + #define B1_DLL_ARPI3_RG_ARPI_DQM_EN_B1 BIT(14) + #define B1_DLL_ARPI3_RG_ARPI_DQS_EN_B1 BIT(15) + #define B1_DLL_ARPI3_RG_ARPI_FB_EN_B1 BIT(17) + #define B1_DLL_ARPI3_RG_ARPI_MCTL_EN_B1 BIT(19) +#define B1_DLL_ARPI4 0x00000110 + #define B1_DLL_ARPI4_RG_ARPI_BYPASS_DQSIEN_B1 BIT(11) + #define B1_DLL_ARPI4_RG_ARPI_BYPASS_DQ_B1 BIT(13) + #define B1_DLL_ARPI4_RG_ARPI_BYPASS_DQM_B1 BIT(14) + #define B1_DLL_ARPI4_RG_ARPI_BYPASS_DQS_B1 BIT(15) + #define B1_DLL_ARPI4_RG_ARPI_BYPASS_FB_B1 BIT(17) + #define B1_DLL_ARPI4_RG_ARPI_BYPASS_MCTL_B1 BIT(19) +#define B1_DLL_ARPI5 0x00000114 + #define B1_DLL_ARPI5_RG_ARDLL_DIV_MCTL_B1 GENMASK(3, 2) + #define B1_DLL_ARPI5_RG_ARDLL_MON_SEL_B1 GENMASK(7, 4) + #define B1_DLL_ARPI5_RG_ARDLL_DIV_DEC_B1 BIT(8) + #define B1_DLL_ARPI5_B1_DLL_ARPI5_RFU GENMASK(23, 12) + #define B1_DLL_ARPI5_RG_ARDLL_FJ_OUT_MODE_SEL_B1 BIT(25) + #define B1_DLL_ARPI5_RG_ARDLL_FJ_OUT_MODE_B1 BIT(26) + #define B1_DLL_ARPI5_B1_DLL_ARPI5_RFU1 BIT(31) +#define B1_DQ0 0x00000118 + #define B1_DQ0_RG_RX_ARDQ0_OFFC_B1 GENMASK(3, 0) + #define B1_DQ0_RG_RX_ARDQ1_OFFC_B1 GENMASK(7, 4) + #define B1_DQ0_RG_RX_ARDQ2_OFFC_B1 GENMASK(11, 8) + #define B1_DQ0_RG_RX_ARDQ3_OFFC_B1 GENMASK(15, 12) + #define B1_DQ0_RG_RX_ARDQ4_OFFC_B1 GENMASK(19, 16) + #define B1_DQ0_RG_RX_ARDQ5_OFFC_B1 GENMASK(23, 20) + #define B1_DQ0_RG_RX_ARDQ6_OFFC_B1 GENMASK(27, 24) + #define B1_DQ0_RG_RX_ARDQ7_OFFC_B1 GENMASK(31, 28) +#define B1_DQ1 0x0000011c + #define B1_DQ1_RG_RX_ARDQM0_OFFC_B1 GENMASK(3, 0) +#define B1_DQ2 0x00000120 + #define B1_DQ2_RG_TX_ARDQS0_ODTEN_DIS_B1 BIT(16) + #define B1_DQ2_RG_TX_ARDQS0_OE_DIS_B1 BIT(17) + #define B1_DQ2_RG_TX_ARDQM0_ODTEN_DIS_B1 BIT(18) + #define B1_DQ2_RG_TX_ARDQM0_OE_DIS_B1 BIT(19) + #define B1_DQ2_RG_TX_ARDQ_ODTEN_DIS_B1 BIT(20) + #define B1_DQ2_RG_TX_ARDQ_OE_DIS_B1 BIT(21) +#define B1_DQ3 0x00000124 + #define B1_DQ3_RG_ARDQ_ATPG_EN_B1 BIT(0) + #define B1_DQ3_RG_RX_ARDQ_SMT_EN_B1 BIT(1) + #define B1_DQ3_RG_TX_ARDQ_EN_B1 BIT(2) + #define B1_DQ3_RG_ARDQ_RESETB_B1 BIT(3) + #define B1_DQ3_RG_RX_ARDQS0_IN_BUFF_EN_B1 BIT(5) + #define B1_DQ3_RG_RX_ARDQM0_IN_BUFF_EN_B1 BIT(6) + #define B1_DQ3_RG_RX_ARDQ_IN_BUFF_EN_B1 BIT(7) + #define B1_DQ3_RG_RX_ARDQ_STBENCMP_EN_B1 BIT(10) + #define B1_DQ3_RG_RX_ARDQ_OFFC_EN_B1 BIT(11) + #define B1_DQ3_RG_RX_ARDQS0_SWAP_EN_B1 BIT(15) +#define B1_DQ4 0x00000128 + #define B1_DQ4_RG_RX_ARDQS_EYE_R_DLY_B1 GENMASK(6, 0) + #define B1_DQ4_RG_RX_ARDQS_EYE_F_DLY_B1 GENMASK(14, 8) + #define B1_DQ4_RG_RX_ARDQ_EYE_R_DLY_B1 GENMASK(21, 16) + #define B1_DQ4_RG_RX_ARDQ_EYE_F_DLY_B1 GENMASK(29, 24) +#define B1_DQ5 0x0000012c + #define B1_DQ5_B1_DQ5_RFU GENMASK(7, 0) + #define B1_DQ5_RG_RX_ARDQ_EYE_VREF_SEL_B1 GENMASK(13, 8) + #define B1_DQ5_RG_RX_ARDQ_VREF_EN_B1 BIT(16) + #define B1_DQ5_RG_RX_ARDQ_EYE_VREF_EN_B1 BIT(17) + #define B1_DQ5_RG_RX_ARDQ_EYE_SEL_B1 GENMASK(23, 20) + #define B1_DQ5_RG_RX_ARDQ_EYE_EN_B1 BIT(24) + #define B1_DQ5_RG_RX_ARDQ_EYE_STBEN_RESETB_B1 BIT(25) + #define B1_DQ5_RG_RX_ARDQS0_DVS_EN_B1 BIT(31) +#define B1_DQ6 0x00000130 + #define B1_DQ6_RG_RX_ARDQ_BIAS_PS_B1 GENMASK(1, 0) + #define B1_DQ6_RG_TX_ARDQ_OE_EXT_DIS_B1 BIT(2) + #define B1_DQ6_RG_TX_ARDQ_ODTEN_EXT_DIS_B1 BIT(3) + #define B1_DQ6_RG_TX_ARDQ_SER_MODE_B1 BIT(4) + #define B1_DQ6_RG_RX_ARDQ_RPRE_TOG_EN_B1 BIT(5) + #define B1_DQ6_RG_RX_ARDQ_RES_BIAS_EN_B1 BIT(6) + #define B1_DQ6_RG_RX_ARDQ_OP_BIAS_SW_EN_B1 BIT(7) + #define B1_DQ6_RG_RX_ARDQ_LPBK_EN_B1 BIT(8) + #define B1_DQ6_RG_RX_ARDQ_O1_SEL_B1 BIT(9) + #define B1_DQ6_RG_RX_ARDQ_JM_SEL_B1 BIT(11) + #define B1_DQ6_RG_RX_ARDQ_BIAS_EN_B1 BIT(12) + #define B1_DQ6_RG_RX_ARDQ_BIAS_VREF_SEL_B1 GENMASK(15, 14) + #define B1_DQ6_RG_RX_ARDQ_DDR4_SEL_B1 BIT(16) + #define B1_DQ6_RG_TX_ARDQ_DDR4_SEL_B1 BIT(17) + #define B1_DQ6_RG_RX_ARDQ_DDR3_SEL_B1 BIT(18) + #define B1_DQ6_RG_TX_ARDQ_DDR3_SEL_B1 BIT(19) + #define B1_DQ6_RG_RX_ARDQ_EYE_DLY_DQS_BYPASS_B1 BIT(24) + #define B1_DQ6_RG_RX_ARDQ_EYE_OE_GATE_EN_B1 BIT(28) + #define B1_DQ6_RG_RX_ARDQ_DMRANK_OUTSEL_B1 BIT(31) +#define B1_DQ7 0x00000134 + #define B1_DQ7_RG_TX_ARDQS0B_PULL_DN_B1 BIT(0) + #define B1_DQ7_RG_TX_ARDQS0B_PULL_UP_B1 BIT(1) + #define B1_DQ7_RG_TX_ARDQS0_PULL_DN_B1 BIT(2) + #define B1_DQ7_RG_TX_ARDQS0_PULL_UP_B1 BIT(3) + #define B1_DQ7_RG_TX_ARDQM0_PULL_DN_B1 BIT(4) + #define B1_DQ7_RG_TX_ARDQM0_PULL_UP_B1 BIT(5) + #define B1_DQ7_RG_TX_ARDQ_PULL_DN_B1 BIT(6) + #define B1_DQ7_RG_TX_ARDQ_PULL_UP_B1 BIT(7) + #define B1_DQ7_RG_TX_ARDQS0B_PULL_DN_B1_LP4Y BIT(16) +#define B1_DQ8 0x00000138 + #define B1_DQ8_RG_TX_ARDQ_EN_LP4P_B1 BIT(0) + #define B1_DQ8_RG_TX_ARDQ_EN_CAP_LP4P_B1 BIT(1) + #define B1_DQ8_RG_TX_ARDQ_CAP_DET_B1 BIT(2) + #define B1_DQ8_RG_TX_ARDQ_CKE_MCK4X_SEL_B1 GENMASK(4, 3) + #define B1_DQ8_RG_ARPI_TX_CG_DQ_EN_B1 BIT(5) + #define B1_DQ8_RG_ARPI_TX_CG_DQM_EN_B1 BIT(6) + #define B1_DQ8_RG_ARPI_TX_CG_DQS_EN_B1 BIT(7) + #define B1_DQ8_RG_RX_ARDQS_BURST_E1_EN_B1 BIT(8) + #define B1_DQ8_RG_RX_ARDQS_BURST_E2_EN_B1 BIT(9) + #define B1_DQ8_RG_RX_ARDQS_DQSSTB_CG_EN_B1 BIT(10) + #define B1_DQ8_RG_RX_ARDQS_GATE_EN_MODE_B1 BIT(12) + #define B1_DQ8_RG_RX_ARDQS_SER_RST_MODE_B1 BIT(13) + #define B1_DQ8_RG_ARDLL_RESETB_B1 BIT(15) +#define B1_DQ9 0x0000013c + #define B1_DQ9_RG_RX_ARDQ_STBEN_RESETB_B1 BIT(0) + #define B1_DQ9_RG_RX_ARDQS0_STBEN_RESETB_B1 BIT(4) + #define B1_DQ9_RG_RX_ARDQS0_DQSIENMODE_B1 BIT(5) + #define B1_DQ9_R_DMRXFIFO_STBENCMP_EN_B1 BIT(7) + #define B1_DQ9_R_IN_GATE_EN_LOW_OPT_B1 GENMASK(15, 8) + #define B1_DQ9_R_DMDQSIEN_VALID_LAT_B1 GENMASK(18, 16) + #define B1_DQ9_R_DMDQSIEN_RDSEL_LAT_B1 GENMASK(22, 20) + #define B1_DQ9_R_DMRXDVS_VALID_LAT_B1 GENMASK(26, 24) + #define B1_DQ9_R_DMRXDVS_RDSEL_LAT_B1 GENMASK(30, 28) +#define RFU_0X140 0x00000140 + #define RFU_0X140_RESERVED_0X140 GENMASK(31, 0) +#define RFU_0X144 0x00000144 + #define RFU_0X144_RESERVED_0X144 GENMASK(31, 0) +#define RFU_0X148 0x00000148 + #define RFU_0X148_RESERVED_0X148 GENMASK(31, 0) +#define RFU_0X14C 0x0000014c + #define RFU_0X14C_RESERVED_0X14C GENMASK(31, 0) +#define B1_TX_MCK 0x00000150 + #define B1_TX_MCK_R_DM_TX_MCK_FRUN_B1 GENMASK(9, 0) +#define RFU_0X154 0x00000154 + #define RFU_0X154_RESERVED_0X154 GENMASK(31, 0) +#define RFU_0X158 0x00000158 + #define RFU_0X158_RESERVED_0X158 GENMASK(31, 0) +#define RFU_0X15C 0x0000015c + #define RFU_0X15C_RESERVED_0X15C GENMASK(31, 0) +#define CA_DLL_ARPI0 0x00000180 + #define CA_DLL_ARPI0_RG_ARMCTLPLL_CK_SEL_CA BIT(1) + #define CA_DLL_ARPI0_RG_ARPI_RESETB_CA BIT(3) + #define CA_DLL_ARPI0_RG_ARPI_LS_EN_CA BIT(4) + #define CA_DLL_ARPI0_RG_ARPI_LS_SEL_CA BIT(5) + #define CA_DLL_ARPI0_RG_ARPI_MCK8X_SEL_CA BIT(6) +#define CA_DLL_ARPI1 0x00000184 + #define CA_DLL_ARPI1_RG_ARPI_CLKIEN_JUMP_EN BIT(11) + #define CA_DLL_ARPI1_RG_ARPI_CMD_JUMP_EN BIT(13) + #define CA_DLL_ARPI1_RG_ARPI_CLK_JUMP_EN BIT(15) + #define CA_DLL_ARPI1_RG_ARPI_CS_JUMP_EN BIT(16) + #define CA_DLL_ARPI1_RG_ARPI_FB_JUMP_EN_CA BIT(17) + #define CA_DLL_ARPI1_RG_ARPI_MCTL_JUMP_EN_CA BIT(19) + #define CA_DLL_ARPI1_RG_ARPISM_MCK_SEL_CA_REG_OPT BIT(20) + #define CA_DLL_ARPI1_RG_ARPISM_MCK_SEL_CA BIT(21) + #define CA_DLL_ARPI1_RG_ARPI_SET_UPDN_CA GENMASK(30, 28) +#define CA_DLL_ARPI2 0x00000188 + #define CA_DLL_ARPI2_RG_ARDLL_PHDET_EN_CA BIT(0) + #define CA_DLL_ARPI2_RG_ARPI_MPDIV_CG_CA BIT(10) + #define CA_DLL_ARPI2_RG_ARPI_CG_CLKIEN BIT(11) + #define CA_DLL_ARPI2_RG_ARPI_CG_CMD BIT(13) + #define CA_DLL_ARPI2_RG_ARPI_CG_CLK BIT(15) + #define CA_DLL_ARPI2_RG_ARPI_CG_CS BIT(16) + #define CA_DLL_ARPI2_RG_ARPI_CG_FB_CA BIT(17) + #define CA_DLL_ARPI2_RG_ARPI_CG_MCTL_CA BIT(19) + #define CA_DLL_ARPI2_RG_ARPI_CG_MCK_FB2DLL_CA BIT(27) + #define CA_DLL_ARPI2_RG_ARPI_CG_MCK_CA BIT(31) +#define CA_DLL_ARPI3 0x0000018c + #define CA_DLL_ARPI3_RG_ARPI_CLKIEN_EN BIT(11) + #define CA_DLL_ARPI3_RG_ARPI_CMD_EN BIT(13) + #define CA_DLL_ARPI3_RG_ARPI_CLK_EN BIT(15) + #define CA_DLL_ARPI3_RG_ARPI_CS_EN BIT(16) + #define CA_DLL_ARPI3_RG_ARPI_FB_EN_CA BIT(17) + #define CA_DLL_ARPI3_RG_ARPI_MCTL_EN_CA BIT(19) +#define CA_DLL_ARPI4 0x00000190 + #define CA_DLL_ARPI4_RG_ARPI_BYPASS_CLKIEN BIT(11) + #define CA_DLL_ARPI4_RG_ARPI_BYPASS_CMD BIT(13) + #define CA_DLL_ARPI4_RG_ARPI_BYPASS_CLK BIT(15) + #define CA_DLL_ARPI4_RG_ARPI_BYPASS_CS BIT(16) + #define CA_DLL_ARPI4_RG_ARPI_BYPASS_FB_CA BIT(17) + #define CA_DLL_ARPI4_RG_ARPI_BYPASS_MCTL_CA BIT(19) +#define CA_DLL_ARPI5 0x00000194 + #define CA_DLL_ARPI5_RG_ARDLL_DIV_MCTL_CA GENMASK(3, 2) + #define CA_DLL_ARPI5_RG_ARDLL_MON_SEL_CA GENMASK(7, 4) + #define CA_DLL_ARPI5_RG_ARDLL_DIV_DEC_CA BIT(8) + #define CA_DLL_ARPI5_CA_DLL_ARPI5_RFU GENMASK(23, 12) + #define CA_DLL_ARPI5_RG_ARDLL_FJ_OUT_MODE_SEL_CA BIT(25) + #define CA_DLL_ARPI5_RG_ARDLL_FJ_OUT_MODE_CA BIT(26) +#define CA_CMD0 0x00000198 + #define CA_CMD0_RG_RX_ARCA0_OFFC GENMASK(3, 0) + #define CA_CMD0_RG_RX_ARCA1_OFFC GENMASK(7, 4) + #define CA_CMD0_RG_RX_ARCA2_OFFC GENMASK(11, 8) + #define CA_CMD0_RG_RX_ARCA3_OFFC GENMASK(15, 12) + #define CA_CMD0_RG_RX_ARCA4_OFFC GENMASK(19, 16) + #define CA_CMD0_RG_RX_ARCA5_OFFC GENMASK(23, 20) +#define CA_CMD1 0x0000019c + #define CA_CMD1_RG_RX_ARCS0_OFFC GENMASK(3, 0) + #define CA_CMD1_RG_RX_ARCS1_OFFC GENMASK(7, 4) + #define CA_CMD1_RG_RX_ARCS2_OFFC GENMASK(11, 8) + #define CA_CMD1_RG_RX_ARCKE0_OFFC GENMASK(15, 12) + #define CA_CMD1_RG_RX_ARCKE1_OFFC GENMASK(19, 16) + #define CA_CMD1_RG_RX_ARCKE2_OFFC GENMASK(23, 20) +#define CA_CMD2 0x000001a0 + #define CA_CMD2_RG_TX_ARCLK_ODTEN_DIS BIT(16) + #define CA_CMD2_RG_TX_ARCLK_OE_DIS BIT(17) + #define CA_CMD2_RG_TX_ARCMD_ODTEN_DIS BIT(20) + #define CA_CMD2_RG_TX_ARCMD_OE_DIS BIT(21) +#define CA_CMD3 0x000001a4 + #define CA_CMD3_RG_ARCMD_ATPG_EN BIT(0) + #define CA_CMD3_RG_RX_ARCMD_SMT_EN BIT(1) + #define CA_CMD3_RG_TX_ARCMD_EN BIT(2) + #define CA_CMD3_RG_ARCMD_RESETB BIT(3) + #define CA_CMD3_RG_RX_ARCLK_IN_BUFF_EN BIT(5) + #define CA_CMD3_RG_RX_ARCMD_IN_BUFF_EN BIT(7) + #define CA_CMD3_RG_RX_ARCMD_STBENCMP_EN BIT(10) + #define CA_CMD3_RG_RX_ARCMD_OFFC_EN BIT(11) + #define CA_CMD3_RG_RX_ARCLK_SWAP_EN BIT(15) +#define CA_CMD4 0x000001a8 + #define CA_CMD4_RG_RX_ARCLK_EYE_R_DLY GENMASK(6, 0) + #define CA_CMD4_RG_RX_ARCLK_EYE_F_DLY GENMASK(14, 8) + #define CA_CMD4_RG_RX_ARCMD_EYE_R_DLY GENMASK(21, 16) + #define CA_CMD4_RG_RX_ARCMD_EYE_F_DLY GENMASK(29, 24) +#define CA_CMD5 0x000001ac + #define CA_CMD5_CA_CMD5_RFU GENMASK(7, 0) + #define CA_CMD5_RG_RX_ARCMD_EYE_VREF_SEL GENMASK(13, 8) + #define CA_CMD5_RG_RX_ARCMD_VREF_EN BIT(16) + #define CA_CMD5_RG_RX_ARCMD_EYE_VREF_EN BIT(17) + #define CA_CMD5_RG_RX_ARCMD_EYE_SEL GENMASK(23, 20) + #define CA_CMD5_RG_RX_ARCMD_EYE_EN BIT(24) + #define CA_CMD5_RG_RX_ARCMD_EYE_STBEN_RESETB BIT(25) + #define CA_CMD5_RG_RX_ARCLK_DVS_EN BIT(31) +#define CA_CMD6 0x000001b0 + #define CA_CMD6_RG_RX_ARCMD_BIAS_PS GENMASK(1, 0) + #define CA_CMD6_RG_TX_ARCMD_OE_EXT_DIS BIT(2) + #define CA_CMD6_RG_TX_ARCMD_ODTEN_EXT_DIS BIT(3) + #define CA_CMD6_RG_TX_ARCMD_SER_MODE BIT(4) + #define CA_CMD6_RG_RX_ARCMD_RPRE_TOG_EN BIT(5) + #define CA_CMD6_RG_RX_ARCMD_RES_BIAS_EN BIT(6) + #define CA_CMD6_RG_RX_ARCMD_OP_BIAS_SW_EN BIT(7) + #define CA_CMD6_RG_RX_ARCMD_LPBK_EN BIT(8) + #define CA_CMD6_RG_RX_ARCMD_O1_SEL BIT(9) + #define CA_CMD6_RG_RX_ARCMD_JM_SEL BIT(11) + #define CA_CMD6_RG_RX_ARCMD_BIAS_EN BIT(12) + #define CA_CMD6_RG_RX_ARCMD_BIAS_VREF_SEL GENMASK(15, 14) + #define CA_CMD6_RG_RX_ARCMD_DDR4_SEL BIT(16) + #define CA_CMD6_RG_TX_ARCMD_DDR4_SEL BIT(17) + #define CA_CMD6_RG_RX_ARCMD_DDR3_SEL BIT(18) + #define CA_CMD6_RG_TX_ARCMD_DDR3_SEL BIT(19) + #define CA_CMD6_RG_RX_ARCMD_EYE_DLY_DQS_BYPASS BIT(24) + #define CA_CMD6_RG_RX_ARCMD_EYE_OE_GATE_EN BIT(28) + #define CA_CMD6_RG_RX_ARCMD_DMRANK_OUTSEL BIT(31) +#define CA_CMD7 0x000001b4 + #define CA_CMD7_RG_TX_ARCLKB_PULL_DN BIT(0) + #define CA_CMD7_RG_TX_ARCLKB_PULL_UP BIT(1) + #define CA_CMD7_RG_TX_ARCLK_PULL_DN BIT(2) + #define CA_CMD7_RG_TX_ARCLK_PULL_UP BIT(3) + #define CA_CMD7_RG_TX_ARCS_PULL_DN BIT(4) + #define CA_CMD7_RG_TX_ARCS_PULL_UP BIT(5) + #define CA_CMD7_RG_TX_ARCMD_PULL_DN BIT(6) + #define CA_CMD7_RG_TX_ARCMD_PULL_UP BIT(7) + #define CA_CMD7_RG_TX_ARCLKB_PULL_DN_LP4Y BIT(16) +#define CA_CMD8 0x000001b8 + #define CA_CMD8_RG_RRESETB_DRVP GENMASK(4, 0) + #define CA_CMD8_RG_RRESETB_DRVN GENMASK(12, 8) + #define CA_CMD8_RG_RX_RRESETB_SMT_EN BIT(16) + #define CA_CMD8_RG_TX_RRESETB_SCAN_IN_EN BIT(17) + #define CA_CMD8_RG_TX_RRESETB_DDR4_SEL BIT(18) + #define CA_CMD8_RG_TX_RRESETB_DDR3_SEL BIT(19) + #define CA_CMD8_RG_TX_RRESETB_PULL_DN BIT(20) + #define CA_CMD8_RG_TX_RRESETB_PULL_UP BIT(21) +#define CA_CMD9 0x000001bc + #define CA_CMD9_RG_TX_ARCMD_EN_LP4P BIT(0) + #define CA_CMD9_RG_TX_ARCMD_EN_CAP_LP4P BIT(1) + #define CA_CMD9_RG_TX_ARCMD_CAP_DET BIT(2) + #define CA_CMD9_RG_TX_ARCMD_CKE_MCK4X_SEL GENMASK(4, 3) + #define CA_CMD9_RG_ARPI_TX_CG_CS_EN BIT(5) + #define CA_CMD9_RG_ARPI_TX_CG_CA_EN BIT(6) + #define CA_CMD9_RG_ARPI_TX_CG_CLK_EN BIT(7) + #define CA_CMD9_RG_RX_ARCLK_DQSIEN_BURST_E1_EN BIT(8) + #define CA_CMD9_RG_RX_ARCLK_DQSIEN_BURST_E2_EN BIT(9) + #define CA_CMD9_RG_RX_ARCLK_DQSSTB_CG_EN BIT(10) + #define CA_CMD9_RG_RX_ARCLK_GATE_EN_MODE BIT(12) + #define CA_CMD9_RG_RX_ARCLK_SER_RST_MODE BIT(13) + #define CA_CMD9_RG_ARDLL_RESETB_CA BIT(15) + #define CA_CMD9_RG_TX_ARCMD_LP3_CKE_SEL BIT(16) + #define CA_CMD9_RG_TX_ARCMD_LP4_CKE_SEL BIT(17) + #define CA_CMD9_RG_TX_ARCMD_LP4X_CKE_SEL BIT(18) + #define CA_CMD9_RG_TX_ARCMD_LSH_DQM_CG_EN BIT(20) + #define CA_CMD9_RG_TX_ARCMD_LSH_DQS_CG_EN BIT(21) + #define CA_CMD9_RG_TX_ARCMD_LSH_DQ_CG_EN BIT(22) + #define CA_CMD9_RG_TX_ARCMD_OE_SUS_EN BIT(24) + #define CA_CMD9_RG_TX_ARCMD_ODTEN_OE_SUS_EN BIT(25) +#define CA_CMD10 0x000001c0 + #define CA_CMD10_RG_RX_ARCMD_STBEN_RESETB BIT(0) + #define CA_CMD10_RG_RX_ARCLK_STBEN_RESETB BIT(4) + #define CA_CMD10_RG_RX_ARCLK_DQSIENMODE BIT(5) + #define CA_CMD10_R_DMRXFIFO_STBENCMP_EN_CA BIT(7) + #define CA_CMD10_R_IN_GATE_EN_LOW_OPT_CA GENMASK(15, 8) + #define CA_CMD10_R_DMDQSIEN_VALID_LAT_CA GENMASK(18, 16) + #define CA_CMD10_R_DMDQSIEN_RDSEL_LAT_CA GENMASK(22, 20) + #define CA_CMD10_R_DMRXDVS_VALID_LAT_CA GENMASK(26, 24) + #define CA_CMD10_R_DMRXDVS_RDSEL_LAT_CA GENMASK(30, 28) +#define RFU_0X1C4 0x000001c4 + #define RFU_0X1C4_RESERVED_0X1C4 GENMASK(31, 0) +#define RFU_0X1C8 0x000001c8 + #define RFU_0X1C8_RESERVED_0X1C8 GENMASK(31, 0) +#define RFU_0X1CC 0x000001cc + #define RFU_0X1CC_RESERVED_0X1CC GENMASK(31, 0) +#define CA_TX_MCK 0x000001d0 + #define CA_TX_MCK_R_DM_TX_MCK_FRUN_CA GENMASK(12, 0) + #define CA_TX_MCK_R_DMRESETB_DRVP_FRPHY GENMASK(25, 21) + #define CA_TX_MCK_R_DMRESETB_DRVN_FRPHY GENMASK(30, 26) + #define CA_TX_MCK_R_DMRESET_FRPHY_OPT BIT(31) +#define RFU_0X1D4 0x000001d4 + #define RFU_0X1D4_RESERVED_0X1D4 GENMASK(31, 0) +#define RFU_0X1D8 0x000001d8 + #define RFU_0X1D8_RESERVED_0X1D8 GENMASK(31, 0) +#define RFU_0X1DC 0x000001dc + #define RFU_0X1DC_RESERVED_0X1DC GENMASK(31, 0) +#define MISC_EXTLB0 0x00000200 + #define MISC_EXTLB0_R_EXTLB_LFSR_INI_0 GENMASK(15, 0) + #define MISC_EXTLB0_R_EXTLB_LFSR_INI_1 GENMASK(31, 16) +#define MISC_EXTLB1 0x00000204 + #define MISC_EXTLB1_R_EXTLB_LFSR_INI_2 GENMASK(15, 0) + #define MISC_EXTLB1_R_EXTLB_LFSR_INI_3 GENMASK(31, 16) +#define MISC_EXTLB2 0x00000208 + #define MISC_EXTLB2_R_EXTLB_LFSR_INI_4 GENMASK(15, 0) + #define MISC_EXTLB2_R_EXTLB_LFSR_INI_5 GENMASK(31, 16) +#define MISC_EXTLB3 0x0000020c + #define MISC_EXTLB3_R_EXTLB_LFSR_INI_6 GENMASK(15, 0) + #define MISC_EXTLB3_R_EXTLB_LFSR_INI_7 GENMASK(31, 16) +#define MISC_EXTLB4 0x00000210 + #define MISC_EXTLB4_R_EXTLB_LFSR_INI_8 GENMASK(15, 0) + #define MISC_EXTLB4_R_EXTLB_LFSR_INI_9 GENMASK(31, 16) +#define MISC_EXTLB5 0x00000214 + #define MISC_EXTLB5_R_EXTLB_LFSR_INI_10 GENMASK(15, 0) + #define MISC_EXTLB5_R_EXTLB_LFSR_INI_11 GENMASK(31, 16) +#define MISC_EXTLB6 0x00000218 + #define MISC_EXTLB6_R_EXTLB_LFSR_INI_12 GENMASK(15, 0) + #define MISC_EXTLB6_R_EXTLB_LFSR_INI_13 GENMASK(31, 16) +#define MISC_EXTLB7 0x0000021c + #define MISC_EXTLB7_R_EXTLB_LFSR_INI_14 GENMASK(15, 0) + #define MISC_EXTLB7_R_EXTLB_LFSR_INI_15 GENMASK(31, 16) +#define MISC_EXTLB8 0x00000220 + #define MISC_EXTLB8_R_EXTLB_LFSR_INI_16 GENMASK(15, 0) + #define MISC_EXTLB8_R_EXTLB_LFSR_INI_17 GENMASK(31, 16) +#define MISC_EXTLB9 0x00000224 + #define MISC_EXTLB9_R_EXTLB_LFSR_INI_18 GENMASK(15, 0) + #define MISC_EXTLB9_R_EXTLB_LFSR_INI_19 GENMASK(31, 16) +#define MISC_EXTLB10 0x00000228 + #define MISC_EXTLB10_R_EXTLB_LFSR_INI_20 GENMASK(15, 0) + #define MISC_EXTLB10_R_EXTLB_LFSR_INI_21 GENMASK(31, 16) +#define MISC_EXTLB11 0x0000022c + #define MISC_EXTLB11_R_EXTLB_LFSR_INI_22 GENMASK(15, 0) + #define MISC_EXTLB11_R_EXTLB_LFSR_INI_23 GENMASK(31, 16) +#define MISC_EXTLB12 0x00000230 + #define MISC_EXTLB12_R_EXTLB_LFSR_INI_24 GENMASK(15, 0) + #define MISC_EXTLB12_R_EXTLB_LFSR_INI_25 GENMASK(31, 16) +#define MISC_EXTLB13 0x00000234 + #define MISC_EXTLB13_R_EXTLB_LFSR_INI_26 GENMASK(15, 0) + #define MISC_EXTLB13_R_EXTLB_LFSR_INI_27 GENMASK(31, 16) +#define MISC_EXTLB14 0x00000238 + #define MISC_EXTLB14_R_EXTLB_LFSR_INI_28 GENMASK(15, 0) + #define MISC_EXTLB14_R_EXTLB_LFSR_INI_29 GENMASK(31, 16) +#define MISC_EXTLB15 0x0000023c + #define MISC_EXTLB15_R_EXTLB_LFSR_INI_30 GENMASK(15, 0) + #define MISC_EXTLB15_MISC_EXTLB15_RFU GENMASK(31, 16) +#define MISC_EXTLB16 0x00000240 + #define MISC_EXTLB16_R_EXTLB_LFSR_TAP GENMASK(15, 0) + #define MISC_EXTLB16_R_EXTLB_OE_DQB0_ON BIT(16) + #define MISC_EXTLB16_R_EXTLB_OE_DQM0_ON BIT(17) + #define MISC_EXTLB16_R_EXTLB_OE_DQS0_ON BIT(18) + #define MISC_EXTLB16_R_EXTLB_OE_DQB1_ON BIT(19) + #define MISC_EXTLB16_R_EXTLB_OE_DQM1_ON BIT(20) + #define MISC_EXTLB16_R_EXTLB_OE_DQS1_ON BIT(21) + #define MISC_EXTLB16_R_EXTLB_ODTEN_DQB0_ON BIT(22) + #define MISC_EXTLB16_R_EXTLB_ODTEN_DQM0_ON BIT(23) + #define MISC_EXTLB16_R_EXTLB_ODTEN_DQS0_ON BIT(24) + #define MISC_EXTLB16_R_EXTLB_ODTEN_DQB1_ON BIT(25) + #define MISC_EXTLB16_R_EXTLB_ODTEN_DQM1_ON BIT(26) + #define MISC_EXTLB16_R_EXTLB_ODTEN_DQS1_ON BIT(27) +#define MISC_EXTLB17 0x00000244 + #define MISC_EXTLB17_R_EXTLB BIT(0) + #define MISC_EXTLB17_R_EXTLB_RX_SWRST BIT(1) + #define MISC_EXTLB17_R_EXTLB_TX_EN BIT(2) + #define MISC_EXTLB17_R_EXTLB_TX_EN_OTHERCH_SEL BIT(3) + #define MISC_EXTLB17_R_INTLB_ARCLK_MUXSEL BIT(4) + #define MISC_EXTLB17_R_INTLB_DRDF_CA_MUXSEL BIT(5) + #define MISC_EXTLB17_R_EXTLB_TX_PRE_ON BIT(7) + #define MISC_EXTLB17_R_EXTLB_RX_LENGTH_M1 GENMASK(31, 8) +#define MISC_EXTLB18 0x00000248 + #define MISC_EXTLB18_R_TX_EN_SRC_SEL BIT(0) + #define MISC_EXTLB18_R_OTH_TX_EN_SRC_SEL BIT(1) + #define MISC_EXTLB18_R_LPBK_DQ_MODE_FOR_CA BIT(3) + #define MISC_EXTLB18_R_LPBK_DQ_TX_MODE BIT(4) + #define MISC_EXTLB18_R_LPBK_CA_TX_MODE BIT(5) + #define MISC_EXTLB18_R_LPBK_DQ_RX_MODE BIT(8) + #define MISC_EXTLB18_R_LPBK_CA_RX_MODE BIT(9) + #define MISC_EXTLB18_R_TX_TRIG_SRC_SEL GENMASK(19, 16) + #define MISC_EXTLB18_R_OTH_TX_TRIG_SRC_SEL GENMASK(23, 20) +#define MISC_EXTLB19 0x0000024c + #define MISC_EXTLB19_R_EXTLB_LFSR_ENABLE BIT(0) + #define MISC_EXTLB19_R_EXTLB_SSO_ENABLE BIT(1) + #define MISC_EXTLB19_R_EXTLB_XTALK_ENABLE BIT(2) + #define MISC_EXTLB19_R_EXTLB_LEADLAG_DBG_ENABLE BIT(3) + #define MISC_EXTLB19_R_EXTLB_DBG_SEL GENMASK(20, 16) + #define MISC_EXTLB19_R_LPBK_DC_TOG_MODE BIT(23) + #define MISC_EXTLB19_R_LPBK_DC_TOG_TIMER GENMASK(31, 24) +#define MISC_EXTLB20 0x00000250 + #define MISC_EXTLB20_R_XTALK_TX_00_TOG_CYCLE GENMASK(3, 0) + #define MISC_EXTLB20_R_XTALK_TX_01_TOG_CYCLE GENMASK(7, 4) + #define MISC_EXTLB20_R_XTALK_TX_02_TOG_CYCLE GENMASK(11, 8) + #define MISC_EXTLB20_R_XTALK_TX_03_TOG_CYCLE GENMASK(15, 12) + #define MISC_EXTLB20_R_XTALK_TX_04_TOG_CYCLE GENMASK(19, 16) + #define MISC_EXTLB20_R_XTALK_TX_05_TOG_CYCLE GENMASK(23, 20) + #define MISC_EXTLB20_R_XTALK_TX_06_TOG_CYCLE GENMASK(27, 24) + #define MISC_EXTLB20_R_XTALK_TX_07_TOG_CYCLE GENMASK(31, 28) +#define MISC_EXTLB21 0x00000254 + #define MISC_EXTLB21_R_XTALK_TX_08_TOG_CYCLE GENMASK(3, 0) + #define MISC_EXTLB21_R_XTALK_TX_09_TOG_CYCLE GENMASK(7, 4) + #define MISC_EXTLB21_R_XTALK_TX_10_TOG_CYCLE GENMASK(11, 8) + #define MISC_EXTLB21_R_XTALK_TX_11_TOG_CYCLE GENMASK(15, 12) + #define MISC_EXTLB21_R_XTALK_TX_12_TOG_CYCLE GENMASK(19, 16) + #define MISC_EXTLB21_R_XTALK_TX_13_TOG_CYCLE GENMASK(23, 20) + #define MISC_EXTLB21_R_XTALK_TX_14_TOG_CYCLE GENMASK(27, 24) + #define MISC_EXTLB21_R_XTALK_TX_15_TOG_CYCLE GENMASK(31, 28) +#define MISC_EXTLB22 0x00000258 + #define MISC_EXTLB22_R_XTALK_TX_16_TOG_CYCLE GENMASK(3, 0) + #define MISC_EXTLB22_R_XTALK_TX_17_TOG_CYCLE GENMASK(7, 4) + #define MISC_EXTLB22_R_XTALK_TX_18_TOG_CYCLE GENMASK(11, 8) + #define MISC_EXTLB22_R_XTALK_TX_19_TOG_CYCLE GENMASK(15, 12) + #define MISC_EXTLB22_R_XTALK_TX_20_TOG_CYCLE GENMASK(19, 16) + #define MISC_EXTLB22_R_XTALK_TX_21_TOG_CYCLE GENMASK(23, 20) + #define MISC_EXTLB22_R_XTALK_TX_22_TOG_CYCLE GENMASK(27, 24) + #define MISC_EXTLB22_R_XTALK_TX_23_TOG_CYCLE GENMASK(31, 28) +#define MISC_EXTLB23 0x0000025c + #define MISC_EXTLB23_R_XTALK_TX_24_TOG_CYCLE GENMASK(3, 0) + #define MISC_EXTLB23_R_XTALK_TX_25_TOG_CYCLE GENMASK(7, 4) + #define MISC_EXTLB23_R_XTALK_TX_26_TOG_CYCLE GENMASK(11, 8) + #define MISC_EXTLB23_R_XTALK_TX_27_TOG_CYCLE GENMASK(15, 12) + #define MISC_EXTLB23_R_XTALK_TX_28_TOG_CYCLE GENMASK(19, 16) + #define MISC_EXTLB23_R_XTALK_TX_29_TOG_CYCLE GENMASK(23, 20) + #define MISC_EXTLB23_R_XTALK_TX_30_TOG_CYCLE GENMASK(27, 24) + #define MISC_EXTLB23_R_XTALK_TX_31_TOG_CYCLE GENMASK(31, 28) +#define DVFS_EMI_CLK 0x00000260 + #define DVFS_EMI_CLK_RG_DLL_SHUFFLE BIT(24) + #define DVFS_EMI_CLK_RG_52M_104M_SEL BIT(29) + #define DVFS_EMI_CLK_RG_GATING_EMI_NEW GENMASK(31, 30) +#define MISC_VREF_CTRL 0x00000264 + #define MISC_VREF_CTRL_VREF_CTRL_RFU GENMASK(30, 16) + #define MISC_VREF_CTRL_RG_RVREF_VREF_EN BIT(31) +#define MISC_IMP_CTRL0 0x00000268 + #define MISC_IMP_CTRL0_RG_IMP_OCD_PUCMP_EN BIT(3) + #define MISC_IMP_CTRL0_RG_IMP_EN BIT(4) + #define MISC_IMP_CTRL0_RG_RIMP_DDR4_SEL BIT(5) + #define MISC_IMP_CTRL0_RG_RIMP_DDR3_SEL BIT(6) +#define MISC_IMP_CTRL1 0x0000026c + #define MISC_IMP_CTRL1_RG_RIMP_BIAS_EN BIT(4) + #define MISC_IMP_CTRL1_RG_RIMP_ODT_EN BIT(5) + #define MISC_IMP_CTRL1_RG_RIMP_PRE_EN BIT(6) + #define MISC_IMP_CTRL1_RG_RIMP_VREF_EN BIT(7) + #define MISC_IMP_CTRL1_RG_RIMP_DRV05 BIT(16) + #define MISC_IMP_CTRL1_RG_RIMP_SUS_ECO_OPT BIT(31) +#define MISC_SHU_OPT 0x00000270 + #define MISC_SHU_OPT_R_DQB0_SHU_PHY_GATING_RESETB_SPM_EN BIT(0) + #define MISC_SHU_OPT_R_DQB0_SHU_PHDET_SPM_EN GENMASK(3, 2) + #define MISC_SHU_OPT_R_DQB1_SHU_PHY_GATING_RESETB_SPM_EN BIT(8) + #define MISC_SHU_OPT_R_DQB1_SHU_PHDET_SPM_EN GENMASK(11, 10) + #define MISC_SHU_OPT_R_CA_SHU_PHY_GATING_RESETB_SPM_EN BIT(16) + #define MISC_SHU_OPT_R_CA_SHU_PHDET_SPM_EN GENMASK(19, 18) +#define MISC_SPM_CTRL0 0x00000274 + #define MISC_SPM_CTRL0_PHY_SPM_CTL0 GENMASK(31, 0) +#define MISC_SPM_CTRL1 0x00000278 + #define MISC_SPM_CTRL1_RG_ARDMSUS_10 BIT(0) + #define MISC_SPM_CTRL1_RG_ARDMSUS_10_B0 BIT(1) + #define MISC_SPM_CTRL1_RG_ARDMSUS_10_B1 BIT(2) + #define MISC_SPM_CTRL1_RG_ARDMSUS_10_CA BIT(3) + #define MISC_SPM_CTRL1_SPM_DVFS_CONTROL_SEL BIT(16) + #define MISC_SPM_CTRL1_RG_DR_SHU_LEVEL GENMASK(18, 17) + #define MISC_SPM_CTRL1_RG_PHYPLL_SHU_EN BIT(19) + #define MISC_SPM_CTRL1_RG_PHYPLL2_SHU_EN BIT(20) + #define MISC_SPM_CTRL1_RG_PHYPLL_MODE_SW BIT(21) + #define MISC_SPM_CTRL1_RG_PHYPLL2_MODE_SW BIT(22) + #define MISC_SPM_CTRL1_RG_DR_SHORT_QUEUE BIT(23) + #define MISC_SPM_CTRL1_RG_DR_SHU_EN BIT(24) + #define MISC_SPM_CTRL1_RG_DDRPHY_DB_CK_CH0_EN BIT(25) + #define MISC_SPM_CTRL1_RG_DDRPHY_DB_CK_CH1_EN BIT(26) +#define MISC_SPM_CTRL2 0x0000027c + #define MISC_SPM_CTRL2_PHY_SPM_CTL2 GENMASK(31, 0) +#define MISC_SPM_CTRL3 0x00000280 + #define MISC_SPM_CTRL3_PHY_SPM_CTL3 GENMASK(31, 0) +#define MISC_CG_CTRL0 0x00000284 + #define MISC_CG_CTRL0_W_CHG_MEM BIT(0) + #define MISC_CG_CTRL0_CLK_MEM_SEL GENMASK(5, 4) + #define MISC_CG_CTRL0_CLK_MEM_INV BIT(6) + #define MISC_CG_CTRL0_RG_CG_EMI_OFF_DISABLE BIT(8) + #define MISC_CG_CTRL0_RG_CG_DRAMC_OFF_DISABLE BIT(9) + #define MISC_CG_CTRL0_RG_CG_PHY_OFF_DIABLE BIT(10) + #define MISC_CG_CTRL0_RG_CG_COMB_OFF_DISABLE BIT(11) + #define MISC_CG_CTRL0_RG_CG_CMD_OFF_DISABLE BIT(12) + #define MISC_CG_CTRL0_RG_CG_COMB0_OFF_DISABLE BIT(13) + #define MISC_CG_CTRL0_RG_CG_COMB1_OFF_DISABLE BIT(14) + #define MISC_CG_CTRL0_RG_CG_RX_CMD_OFF_DISABLE BIT(15) + #define MISC_CG_CTRL0_RG_CG_RX_COMB0_OFF_DISABLE BIT(16) + #define MISC_CG_CTRL0_RG_CG_RX_COMB1_OFF_DISABLE BIT(17) + #define MISC_CG_CTRL0_RG_CG_IDLE_SYNC_EN BIT(18) + #define MISC_CG_CTRL0_RG_CG_INFRA_OFF_DISABLE BIT(19) + #define MISC_CG_CTRL0_RG_CG_DRAMC_CHB_CK_OFF BIT(20) + #define MISC_CG_CTRL0_RG_DBG_OUT_SEL BIT(21) + #define MISC_CG_CTRL0_RG_CG_NAO_FORCE_OFF BIT(22) + #define MISC_CG_CTRL0_RG_DA_RREF_CK_SEL BIT(28) + #define MISC_CG_CTRL0_RG_FREERUN_MCK_CG BIT(29) + #define MISC_CG_CTRL0_RG_FREERUN_MCK_CHB_SEL BIT(30) + #define MISC_CG_CTRL0_CLK_MEM_DFS_CFG GENMASK(31, 0) //cc add +#define MISC_CG_CTRL1 0x00000288 + #define MISC_CG_CTRL1_R_DVS_DIV4_CG_CTRL GENMASK(31, 0) +#define MISC_CG_CTRL2 0x0000028c + #define MISC_CG_CTRL2_RG_MEM_DCM_APB_TOG BIT(0) + #define MISC_CG_CTRL2_RG_MEM_DCM_APB_SEL GENMASK(5, 1) + #define MISC_CG_CTRL2_RG_MEM_DCM_FORCE_ON BIT(6) + #define MISC_CG_CTRL2_RG_MEM_DCM_DCM_EN BIT(7) + #define MISC_CG_CTRL2_RG_MEM_DCM_DBC_EN BIT(8) + #define MISC_CG_CTRL2_RG_MEM_DCM_DBC_CNT GENMASK(15, 9) + #define MISC_CG_CTRL2_RG_MEM_DCM_FSEL GENMASK(20, 16) + #define MISC_CG_CTRL2_RG_MEM_DCM_IDLE_FSEL GENMASK(25, 21) + #define MISC_CG_CTRL2_RG_MEM_DCM_FORCE_OFF BIT(26) + #define MISC_CG_CTRL2_RG_PHY_CG_OFF_DISABLE BIT(28) + #define MISC_CG_CTRL2_RG_PIPE0_CG_OFF_DISABLE BIT(29) + #define MISC_CG_CTRL2_RG_MEM_DCM_CG_OFF_DISABLE BIT(31) + #define MISC_CG_CTRL2_RG_MEM_DCM_CTL GENMASK(31, 0) +#define MISC_CG_CTRL3 0x00000290 + #define MISC_CG_CTRL3_R_LBK_CG_CTRL GENMASK(31, 0) +#define MISC_CG_CTRL4 0x00000294 + #define MISC_CG_CTRL4_R_PHY_MCK_CG_CTRL GENMASK(31, 0) +#define MISC_CG_CTRL5 0x00000298 + #define MISC_CG_CTRL5_RESERVE GENMASK(15, 0) + #define MISC_CG_CTRL5_R_DQ1_DLY_DCM_EN BIT(16) + #define MISC_CG_CTRL5_R_DQ0_DLY_DCM_EN BIT(17) + #define MISC_CG_CTRL5_R_CA_DLY_DCM_EN BIT(18) + #define MISC_CG_CTRL5_R_DQ1_PI_DCM_EN BIT(20) + #define MISC_CG_CTRL5_R_DQ0_PI_DCM_EN BIT(21) + #define MISC_CG_CTRL5_R_CA_PI_DCM_EN BIT(22) +#define MISC_CTRL0 0x0000029c + #define MISC_CTRL0_R_DMDQSIEN_SYNCOPT GENMASK(3, 0) + #define MISC_CTRL0_R_DMDQSIEN_OUTSEL GENMASK(7, 4) + #define MISC_CTRL0_R_DMSTBEN_SYNCOPT BIT(8) + #define MISC_CTRL0_R_DMSTBEN_OUTSEL BIT(9) + #define MISC_CTRL0_IMPCAL_CHAB_EN BIT(10) + #define MISC_CTRL0_R_DMVALID_DLY_OPT BIT(11) + #define MISC_CTRL0_R_DMVALID_NARROW_IG BIT(12) + #define MISC_CTRL0_R_DMVALID_DLY GENMASK(15, 13) + #define MISC_CTRL0_R_DMDQSIEN_DEPTH_HALF BIT(16) + #define MISC_CTRL0_R_DMRDSEL_DIV2_OPT BIT(17) + #define MISC_CTRL0_IMPCAL_LP_ECO_OPT BIT(18) + #define MISC_CTRL0_IMPCAL_CDC_ECO_OPT BIT(19) + #define MISC_CTRL0_IDLE_DCM_CHB_CDC_ECO_OPT BIT(20) + #define MISC_CTRL0_IMPCAL_CTL_CK_SEL BIT(21) + #define MISC_CTRL0_R_DMDQSIEN_FIFO_EN BIT(24) + #define MISC_CTRL0_R_DMSTBENCMP_FIFO_EN BIT(25) + #define MISC_CTRL0_R_DMSTBENCMP_RK_FIFO_EN BIT(26) + #define MISC_CTRL0_R_DMSHU_PHYDCM_FORCEOFF BIT(27) + #define MISC_CTRL0_R_DQS0IEN_DIV4_CK_CG_CTRL BIT(28) + #define MISC_CTRL0_R_DQS1IEN_DIV4_CK_CG_CTRL BIT(29) + #define MISC_CTRL0_R_CLKIEN_DIV4_CK_CG_CTRL BIT(30) + #define MISC_CTRL0_R_STBENCMP_DIV4CK_EN BIT(31) +#define MISC_CTRL1 0x000002a0 + #define MISC_CTRL1_R_DMPHYRST BIT(1) + #define MISC_CTRL1_R_DM_TX_ARCLK_OE BIT(2) + #define MISC_CTRL1_R_DM_TX_ARCMD_OE BIT(3) + #define MISC_CTRL1_R_DMMCTLPLL_CKSEL GENMASK(5, 4) + #define MISC_CTRL1_R_DMMUXCA BIT(6) + #define MISC_CTRL1_R_DMARPIDQ_SW BIT(7) + #define MISC_CTRL1_R_DMPINMUX GENMASK(9, 8) + #define MISC_CTRL1_R_DMARPICA_SW_UPDX BIT(10) + #define MISC_CTRL1_CK_BFE_DCM_EN BIT(11) + #define MISC_CTRL1_R_DMRRESETB_I_OPT BIT(12) + #define MISC_CTRL1_R_DMDA_RRESETB_I BIT(13) + #define MISC_CTRL1_R_DMMUXCA_SEC BIT(14) + #define MISC_CTRL1_R_DQ2DM_SWAP BIT(15) + #define MISC_CTRL1_R_DMDRAMCLKEN0 GENMASK(19, 16) + #define MISC_CTRL1_R_DMDRAMCLKEN1 GENMASK(23, 20) + #define MISC_CTRL1_R_DMDQSIENCG_EN BIT(24) + #define MISC_CTRL1_R_DMSTBENCMP_RK_OPT BIT(25) + #define MISC_CTRL1_R_WL_DOWNSP BIT(26) + #define MISC_CTRL1_R_DMODTDISOE_A BIT(27) + #define MISC_CTRL1_R_DMODTDISOE_B BIT(28) + #define MISC_CTRL1_R_DMODTDISOE_C BIT(29) + #define MISC_CTRL1_R_DMDA_RRESETB_E BIT(31) +#define MISC_CTRL2 0x000002a4 + #define MISC_CTRL2_PLL_SHU_GP GENMASK(1, 0) +#define MISC_CTRL3 0x000002a8 + #define MISC_CTRL3_ARPI_CG_CMD_OPT GENMASK(1, 0) + #define MISC_CTRL3_ARPI_CG_CLK_OPT GENMASK(3, 2) + #define MISC_CTRL3_ARPI_MPDIV_CG_CA_OPT BIT(4) + #define MISC_CTRL3_ARPI_CG_MCK_CA_OPT BIT(5) + #define MISC_CTRL3_ARPI_CG_MCTL_CA_OPT BIT(6) + #define MISC_CTRL3_DDRPHY_MCK_MPDIV_CG_CA_SEL GENMASK(9, 8) + #define MISC_CTRL3_DRAM_CLK_NEW_CA_EN_SEL GENMASK(15, 12) + #define MISC_CTRL3_ARPI_CG_DQ_OPT GENMASK(17, 16) + #define MISC_CTRL3_ARPI_CG_DQS_OPT GENMASK(19, 18) + #define MISC_CTRL3_ARPI_MPDIV_CG_DQ_OPT BIT(20) + #define MISC_CTRL3_ARPI_CG_MCK_DQ_OPT BIT(21) + #define MISC_CTRL3_ARPI_CG_MCTL_DQ_OPT BIT(22) + #define MISC_CTRL3_DDRPHY_MCK_MPDIV_CG_DQ_SEL GENMASK(25, 24) + #define MISC_CTRL3_R_DDRPHY_COMB_CG_IG BIT(26) + #define MISC_CTRL3_R_DDRPHY_RX_PIPE_CG_IG BIT(27) + #define MISC_CTRL3_DRAM_CLK_NEW_DQ_EN_SEL GENMASK(31, 28) +#define MISC_CTRL4 0x000002ac + #define MISC_CTRL4_RG_PW_CON_CHA_0 GENMASK(31, 0) +#define MISC_CTRL5 0x000002b0 + #define MISC_CTRL5_RG_PW_CON_CHA_1 GENMASK(31, 0) +#define MISC_EXTLB_RX0 0x000002b4 + #define MISC_EXTLB_RX0_R_EXTLB_LFSR_RX_INI_0 GENMASK(15, 0) + #define MISC_EXTLB_RX0_R_EXTLB_LFSR_RX_INI_1 GENMASK(31, 16) +#define MISC_EXTLB_RX1 0x000002b8 + #define MISC_EXTLB_RX1_R_EXTLB_LFSR_RX_INI_2 GENMASK(15, 0) + #define MISC_EXTLB_RX1_R_EXTLB_LFSR_RX_INI_3 GENMASK(31, 16) +#define MISC_EXTLB_RX2 0x000002bc + #define MISC_EXTLB_RX2_R_EXTLB_LFSR_RX_INI_4 GENMASK(15, 0) + #define MISC_EXTLB_RX2_R_EXTLB_LFSR_RX_INI_5 GENMASK(31, 16) +#define MISC_EXTLB_RX3 0x000002c0 + #define MISC_EXTLB_RX3_R_EXTLB_LFSR_RX_INI_6 GENMASK(15, 0) + #define MISC_EXTLB_RX3_R_EXTLB_LFSR_RX_INI_7 GENMASK(31, 16) +#define MISC_EXTLB_RX4 0x000002c4 + #define MISC_EXTLB_RX4_R_EXTLB_LFSR_RX_INI_8 GENMASK(15, 0) + #define MISC_EXTLB_RX4_R_EXTLB_LFSR_RX_INI_9 GENMASK(31, 16) +#define MISC_EXTLB_RX5 0x000002c8 + #define MISC_EXTLB_RX5_R_EXTLB_LFSR_RX_INI_10 GENMASK(15, 0) + #define MISC_EXTLB_RX5_R_EXTLB_LFSR_RX_INI_11 GENMASK(31, 16) +#define MISC_EXTLB_RX6 0x000002cc + #define MISC_EXTLB_RX6_R_EXTLB_LFSR_RX_INI_12 GENMASK(15, 0) + #define MISC_EXTLB_RX6_R_EXTLB_LFSR_RX_INI_13 GENMASK(31, 16) +#define MISC_EXTLB_RX7 0x000002d0 + #define MISC_EXTLB_RX7_R_EXTLB_LFSR_RX_INI_14 GENMASK(15, 0) + #define MISC_EXTLB_RX7_R_EXTLB_LFSR_RX_INI_15 GENMASK(31, 16) +#define MISC_EXTLB_RX8 0x000002d4 + #define MISC_EXTLB_RX8_R_EXTLB_LFSR_RX_INI_16 GENMASK(15, 0) + #define MISC_EXTLB_RX8_R_EXTLB_LFSR_RX_INI_17 GENMASK(31, 16) +#define MISC_EXTLB_RX9 0x000002d8 + #define MISC_EXTLB_RX9_R_EXTLB_LFSR_RX_INI_18 GENMASK(15, 0) + #define MISC_EXTLB_RX9_R_EXTLB_LFSR_RX_INI_19 GENMASK(31, 16) +#define MISC_EXTLB_RX10 0x000002dc + #define MISC_EXTLB_RX10_R_EXTLB_LFSR_RX_INI_20 GENMASK(15, 0) + #define MISC_EXTLB_RX10_R_EXTLB_LFSR_RX_INI_21 GENMASK(31, 16) +#define MISC_EXTLB_RX11 0x000002e0 + #define MISC_EXTLB_RX11_R_EXTLB_LFSR_RX_INI_22 GENMASK(15, 0) + #define MISC_EXTLB_RX11_R_EXTLB_LFSR_RX_INI_23 GENMASK(31, 16) +#define MISC_EXTLB_RX12 0x000002e4 + #define MISC_EXTLB_RX12_R_EXTLB_LFSR_RX_INI_24 GENMASK(15, 0) + #define MISC_EXTLB_RX12_R_EXTLB_LFSR_RX_INI_25 GENMASK(31, 16) +#define MISC_EXTLB_RX13 0x000002e8 + #define MISC_EXTLB_RX13_R_EXTLB_LFSR_RX_INI_26 GENMASK(15, 0) + #define MISC_EXTLB_RX13_R_EXTLB_LFSR_RX_INI_27 GENMASK(31, 16) +#define MISC_EXTLB_RX14 0x000002ec + #define MISC_EXTLB_RX14_R_EXTLB_LFSR_RX_INI_28 GENMASK(15, 0) + #define MISC_EXTLB_RX14_R_EXTLB_LFSR_RX_INI_29 GENMASK(31, 16) +#define MISC_EXTLB_RX15 0x000002f0 + #define MISC_EXTLB_RX15_R_EXTLB_LFSR_RX_INI_30 GENMASK(15, 0) + #define MISC_EXTLB_RX15_MISC_EXTLB_RX15_RFU GENMASK(31, 16) +#define MISC_EXTLB_RX16 0x000002f4 + #define MISC_EXTLB_RX16_R_EXTLB_RX_GATE_DELSEL_DQB0 GENMASK(6, 0) + #define MISC_EXTLB_RX16_R_EXTLB_RX_GATE_DELSEL_DQB1 GENMASK(14, 8) + #define MISC_EXTLB_RX16_R_EXTLB_RX_GATE_DELSEL_CA GENMASK(22, 16) +#define MISC_EXTLB_RX17 0x000002f8 + #define MISC_EXTLB_RX17_R_XTALK_RX_00_TOG_CYCLE GENMASK(3, 0) + #define MISC_EXTLB_RX17_R_XTALK_RX_01_TOG_CYCLE GENMASK(7, 4) + #define MISC_EXTLB_RX17_R_XTALK_RX_02_TOG_CYCLE GENMASK(11, 8) + #define MISC_EXTLB_RX17_R_XTALK_RX_03_TOG_CYCLE GENMASK(15, 12) + #define MISC_EXTLB_RX17_R_XTALK_RX_04_TOG_CYCLE GENMASK(19, 16) + #define MISC_EXTLB_RX17_R_XTALK_RX_05_TOG_CYCLE GENMASK(23, 20) + #define MISC_EXTLB_RX17_R_XTALK_RX_06_TOG_CYCLE GENMASK(27, 24) + #define MISC_EXTLB_RX17_R_XTALK_RX_07_TOG_CYCLE GENMASK(31, 28) +#define MISC_EXTLB_RX18 0x000002fc + #define MISC_EXTLB_RX18_R_XTALK_RX_08_TOG_CYCLE GENMASK(3, 0) + #define MISC_EXTLB_RX18_R_XTALK_RX_09_TOG_CYCLE GENMASK(7, 4) + #define MISC_EXTLB_RX18_R_XTALK_RX_10_TOG_CYCLE GENMASK(11, 8) + #define MISC_EXTLB_RX18_R_XTALK_RX_11_TOG_CYCLE GENMASK(15, 12) + #define MISC_EXTLB_RX18_R_XTALK_RX_12_TOG_CYCLE GENMASK(19, 16) + #define MISC_EXTLB_RX18_R_XTALK_RX_13_TOG_CYCLE GENMASK(23, 20) + #define MISC_EXTLB_RX18_R_XTALK_RX_14_TOG_CYCLE GENMASK(27, 24) + #define MISC_EXTLB_RX18_R_XTALK_RX_15_TOG_CYCLE GENMASK(31, 28) +#define MISC_EXTLB_RX19 0x00000300 + #define MISC_EXTLB_RX19_R_XTALK_RX_16_TOG_CYCLE GENMASK(3, 0) + #define MISC_EXTLB_RX19_R_XTALK_RX_17_TOG_CYCLE GENMASK(7, 4) + #define MISC_EXTLB_RX19_R_XTALK_RX_18_TOG_CYCLE GENMASK(11, 8) + #define MISC_EXTLB_RX19_R_XTALK_RX_19_TOG_CYCLE GENMASK(15, 12) + #define MISC_EXTLB_RX19_R_XTALK_RX_20_TOG_CYCLE GENMASK(19, 16) + #define MISC_EXTLB_RX19_R_XTALK_RX_21_TOG_CYCLE GENMASK(23, 20) + #define MISC_EXTLB_RX19_R_XTALK_RX_22_TOG_CYCLE GENMASK(27, 24) + #define MISC_EXTLB_RX19_R_XTALK_RX_23_TOG_CYCLE GENMASK(31, 28) +#define MISC_EXTLB_RX20 0x00000304 + #define MISC_EXTLB_RX20_R_XTALK_RX_24_TOG_CYCLE GENMASK(3, 0) + #define MISC_EXTLB_RX20_R_XTALK_RX_25_TOG_CYCLE GENMASK(7, 4) + #define MISC_EXTLB_RX20_R_XTALK_RX_26_TOG_CYCLE GENMASK(11, 8) + #define MISC_EXTLB_RX20_R_XTALK_RX_27_TOG_CYCLE GENMASK(15, 12) + #define MISC_EXTLB_RX20_R_XTALK_RX_28_TOG_CYCLE GENMASK(19, 16) + #define MISC_EXTLB_RX20_R_XTALK_RX_29_TOG_CYCLE GENMASK(23, 20) + #define MISC_EXTLB_RX20_R_XTALK_RX_30_TOG_CYCLE GENMASK(27, 24) + #define MISC_EXTLB_RX20_R_XTALK_RX_31_TOG_CYCLE GENMASK(31, 28) +#define CKMUX_SEL 0x00000308 + #define CKMUX_SEL_R_PHYCTRLMUX BIT(0) + #define CKMUX_SEL_R_PHYCTRLDCM BIT(1) + #define CKMUX_SEL_FB_CK_MUX GENMASK(17, 16) + #define CKMUX_SEL_FMEM_CK_MUX GENMASK(19, 18) +#define RFU_0X30C 0x0000030c + #define RFU_0X30C_RESERVED_0X30C GENMASK(31, 0) +#define RFU_0X310 0x00000310 + #define RFU_0X310_RESERVED_0X310 GENMASK(31, 0) +#define RFU_0X314 0x00000314 + #define RFU_0X314_RESERVED_0X314 GENMASK(31, 0) +#define RFU_0X318 0x00000318 + #define RFU_0X318_RESERVED_0X318 GENMASK(31, 0) +#define RFU_0X31C 0x0000031c + #define RFU_0X31C_RESERVED_0X31C GENMASK(31, 0) +#define RFU_0X320 0x00000320 + #define RFU_0X320_RESERVED_0X320 GENMASK(31, 0) +#define RFU_0X324 0x00000324 + #define RFU_0X324_RESERVED_0X324 GENMASK(31, 0) +#define RFU_0X328 0x00000328 + #define RFU_0X328_RESERVED_0X328 GENMASK(31, 0) +#define RFU_0X32C 0x0000032c + #define RFU_0X32C_RESERVED_0X32C GENMASK(31, 0) +#define RFU_0X330 0x00000330 + #define RFU_0X330_RESERVED_0X330 GENMASK(31, 0) +#define RFU_0X334 0x00000334 + #define RFU_0X334_RESERVED_0X334 GENMASK(31, 0) +#define RFU_0X338 0x00000338 + #define RFU_0X338_RESERVED_0X338 GENMASK(31, 0) +#define RFU_0X33C 0x0000033c + #define RFU_0X33C_RESERVED_0X33C GENMASK(31, 0) +#define MISC_STBERR_RK0_R 0x00000510 + #define MISC_STBERR_RK0_R_STBERR_RK0_R GENMASK(15, 0) + #define MISC_STBERR_RK0_R_STBENERR_ALL BIT(16) + #define MISC_STBERR_RK0_R_RX_ARDQ0_FIFO_STBEN_ERR_B0 BIT(24) + #define MISC_STBERR_RK0_R_RX_ARDQ4_FIFO_STBEN_ERR_B0 BIT(25) + #define MISC_STBERR_RK0_R_RX_ARDQ0_FIFO_STBEN_ERR_B1 BIT(26) + #define MISC_STBERR_RK0_R_RX_ARDQ4_FIFO_STBEN_ERR_B1 BIT(27) + #define MISC_STBERR_RK0_R_RX_ARCA0_FIFO_STBEN_ERR BIT(28) + #define MISC_STBERR_RK0_R_RX_ARCA4_FIFO_STBEN_ERR BIT(29) + #define MISC_STBERR_RK0_R_DA_RPHYPLLGP_CK_SEL BIT(31) +#define MISC_STBERR_RK0_F 0x00000514 + #define MISC_STBERR_RK0_F_STBERR_RK0_F GENMASK(15, 0) +#define MISC_STBERR_RK1_R 0x00000518 + #define MISC_STBERR_RK1_R_STBERR_RK1_R GENMASK(15, 0) +#define MISC_STBERR_RK1_F 0x0000051c + #define MISC_STBERR_RK1_F_STBERR_RK1_F GENMASK(15, 0) +#define MISC_STBERR_RK2_R 0x00000520 + #define MISC_STBERR_RK2_R_STBERR_RK2_R GENMASK(15, 0) +#define MISC_STBERR_RK2_F 0x00000524 + #define MISC_STBERR_RK2_F_STBERR_RK2_F GENMASK(15, 0) +#define MISC_RXDVS0 0x000005e0 + #define MISC_RXDVS0_R_RX_DLY_TRACK_RO_SEL GENMASK(2, 0) + #define MISC_RXDVS0_R_DA_DQX_R_DLY_RO_SEL GENMASK(11, 8) + #define MISC_RXDVS0_R_DA_CAX_R_DLY_RO_SEL GENMASK(15, 12) +#define MISC_RXDVS2 0x000005e8 + #define MISC_RXDVS2_R_DMRXDVS_DEPTH_HALF BIT(0) + #define MISC_RXDVS2_R_DMRXDVS_SHUFFLE_CTRL_CG_IG BIT(8) + #define MISC_RXDVS2_R_DMRXDVS_DBG_MON_EN BIT(16) + #define MISC_RXDVS2_R_DMRXDVS_DBG_MON_CLR BIT(17) + #define MISC_RXDVS2_R_DMRXDVS_DBG_PAUSE_EN BIT(18) +#define RFU_0X5EC 0x000005ec + #define RFU_0X5EC_RESERVED_0X5EC GENMASK(31, 0) +#define B0_RXDVS0 0x000005f0 + #define B0_RXDVS0_R_RX_RANKINSEL_B0 BIT(0) + #define B0_RXDVS0_B0_RXDVS0_RFU GENMASK(3, 1) + #define B0_RXDVS0_R_RX_RANKINCTL_B0 GENMASK(7, 4) + #define B0_RXDVS0_R_DVS_SW_UP_B0 BIT(8) + #define B0_RXDVS0_R_DMRXDVS_DQIENPRE_OPT_B0 BIT(9) + #define B0_RXDVS0_R_DMRXDVS_PBYTESTUCK_RST_B0 BIT(10) + #define B0_RXDVS0_R_DMRXDVS_PBYTESTUCK_IG_B0 BIT(11) + #define B0_RXDVS0_R_DMRXDVS_DQIENPOST_OPT_B0 GENMASK(13, 12) + #define B0_RXDVS0_R_RX_DLY_RANK_ERR_ST_CLR_B0 GENMASK(18, 16) + #define B0_RXDVS0_R_DMRXDVS_CNTCMP_OPT_B0 BIT(19) + #define B0_RXDVS0_R_RX_DLY_RK_OPT_B0 GENMASK(21, 20) + #define B0_RXDVS0_R_HWRESTORE_ENA_B0 BIT(22) + #define B0_RXDVS0_R_HWSAVE_MODE_ENA_B0 BIT(24) + #define B0_RXDVS0_R_RX_DLY_DVS_MODE_SYNC_DIS_B0 BIT(26) + #define B0_RXDVS0_R_RX_DLY_TRACK_BYPASS_MODESYNC_B0 BIT(27) + #define B0_RXDVS0_R_RX_DLY_TRACK_CG_EN_B0 BIT(28) + #define B0_RXDVS0_R_RX_DLY_TRACK_SPM_CTRL_B0 BIT(29) + #define B0_RXDVS0_R_RX_DLY_TRACK_CLR_B0 BIT(30) + #define B0_RXDVS0_R_RX_DLY_TRACK_ENA_B0 BIT(31) +#define B0_RXDVS1 0x000005f4 + #define B0_RXDVS1_B0_RXDVS1_RFU GENMASK(15, 0) + #define B0_RXDVS1_R_DMRXDVS_UPD_CLR_ACK_B0 BIT(16) + #define B0_RXDVS1_R_DMRXDVS_UPD_CLR_NORD_B0 BIT(17) +#define RFU_0X5F8 0x000005f8 + #define RFU_0X5F8_RESERVED_0X5F8 GENMASK(31, 0) +#define RFU_0X5FC 0x000005fc + #define RFU_0X5FC_RESERVED_0X5FC GENMASK(31, 0) +#define R0_B0_RXDVS0 0x00000600 + #define R0_B0_RXDVS0_R_RK0_B0_DVS_LEAD_LAG_CNT_CLR BIT(26) + #define R0_B0_RXDVS0_R_RK0_B0_DVS_SW_CNT_CLR BIT(27) + #define R0_B0_RXDVS0_R_RK0_B0_DVS_SW_CNT_ENA BIT(31) +#define R0_B0_RXDVS1 0x00000604 + #define R0_B0_RXDVS1_R_RK0_B0_DVS_TH_LAG GENMASK(15, 0) + #define R0_B0_RXDVS1_R_RK0_B0_DVS_TH_LEAD GENMASK(31, 16) +#define R0_B0_RXDVS2 0x00000608 + #define R0_B0_RXDVS2_R_RK0_RX_DLY_FAL_DQS_SCALE_B0 GENMASK(17, 16) + #define R0_B0_RXDVS2_R_RK0_RX_DLY_FAL_DQ_SCALE_B0 GENMASK(19, 18) + #define R0_B0_RXDVS2_R_RK0_RX_DLY_FAL_TRACK_GATE_ENA_B0 BIT(23) + #define R0_B0_RXDVS2_R_RK0_RX_DLY_RIS_DQS_SCALE_B0 GENMASK(25, 24) + #define R0_B0_RXDVS2_R_RK0_RX_DLY_RIS_DQ_SCALE_B0 GENMASK(27, 26) + #define R0_B0_RXDVS2_R_RK0_RX_DLY_RIS_TRACK_GATE_ENA_B0 BIT(28) + #define R0_B0_RXDVS2_R_RK0_DVS_FDLY_MODE_B0 BIT(29) + #define R0_B0_RXDVS2_R_RK0_DVS_MODE_B0 GENMASK(31, 30) +#define R0_B0_RXDVS7 0x0000061c + #define R0_B0_RXDVS7_RG_RK0_ARDQ_MIN_DLY_B0 GENMASK(5, 0) + #define R0_B0_RXDVS7_RG_RK0_ARDQ_MIN_DLY_B0_RFU GENMASK(7, 6) + #define R0_B0_RXDVS7_RG_RK0_ARDQ_MAX_DLY_B0 GENMASK(13, 8) + #define R0_B0_RXDVS7_RG_RK0_ARDQ_MAX_DLY_B0_RFU GENMASK(15, 14) + #define R0_B0_RXDVS7_RG_RK0_ARDQS0_MIN_DLY_B0 GENMASK(22, 16) + #define R0_B0_RXDVS7_RG_RK0_ARDQS0_MIN_DLY_B0_RFU BIT(23) + #define R0_B0_RXDVS7_RG_RK0_ARDQS0_MAX_DLY_B0 GENMASK(30, 24) + #define R0_B0_RXDVS7_RG_RK0_ARDQS0_MAX_DLY_B0_RFU BIT(31) +#define RFU_0X620 0x00000620 + #define RFU_0X620_RESERVED_0X620 GENMASK(31, 0) +#define RFU_0X624 0x00000624 + #define RFU_0X624_RESERVED_0X624 GENMASK(31, 0) +#define RFU_0X628 0x00000628 + #define RFU_0X628_RESERVED_0X628 GENMASK(31, 0) +#define RFU_0X62C 0x0000062c + #define RFU_0X62C_RESERVED_0X62C GENMASK(31, 0) +#define B1_RXDVS0 0x00000670 + #define B1_RXDVS0_R_RX_RANKINSEL_B1 BIT(0) + #define B1_RXDVS0_B1_RXDVS0_RFU GENMASK(3, 1) + #define B1_RXDVS0_R_RX_RANKINCTL_B1 GENMASK(7, 4) + #define B1_RXDVS0_R_DVS_SW_UP_B1 BIT(8) + #define B1_RXDVS0_R_DMRXDVS_DQIENPRE_OPT_B1 BIT(9) + #define B1_RXDVS0_R_DMRXDVS_PBYTESTUCK_RST_B1 BIT(10) + #define B1_RXDVS0_R_DMRXDVS_PBYTESTUCK_IG_B1 BIT(11) + #define B1_RXDVS0_R_DMRXDVS_DQIENPOST_OPT_B1 GENMASK(13, 12) + #define B1_RXDVS0_R_RX_DLY_RANK_ERR_ST_CLR_B1 GENMASK(18, 16) + #define B1_RXDVS0_R_DMRXDVS_CNTCMP_OPT_B1 BIT(19) + #define B1_RXDVS0_R_RX_DLY_RK_OPT_B1 GENMASK(21, 20) + #define B1_RXDVS0_R_HWRESTORE_ENA_B1 BIT(22) + #define B1_RXDVS0_R_HWSAVE_MODE_ENA_B1 BIT(24) + #define B1_RXDVS0_R_RX_DLY_DVS_MODE_SYNC_DIS_B1 BIT(26) + #define B1_RXDVS0_R_RX_DLY_TRACK_BYPASS_MODESYNC_B1 BIT(27) + #define B1_RXDVS0_R_RX_DLY_TRACK_CG_EN_B1 BIT(28) + #define B1_RXDVS0_R_RX_DLY_TRACK_SPM_CTRL_B1 BIT(29) + #define B1_RXDVS0_R_RX_DLY_TRACK_CLR_B1 BIT(30) + #define B1_RXDVS0_R_RX_DLY_TRACK_ENA_B1 BIT(31) +#define B1_RXDVS1 0x00000674 + #define B1_RXDVS1_B1_RXDVS1_RFU GENMASK(15, 0) + #define B1_RXDVS1_R_DMRXDVS_UPD_CLR_ACK_B1 BIT(16) + #define B1_RXDVS1_R_DMRXDVS_UPD_CLR_NORD_B1 BIT(17) +#define RFU_0X678 0x00000678 + #define RFU_0X678_RESERVED_0X678 GENMASK(31, 0) +#define RFU_0X67C 0x0000067c + #define RFU_0X67C_RESERVED_0X67C GENMASK(31, 0) +#define R0_B1_RXDVS0 0x00000680 + #define R0_B1_RXDVS0_R_RK0_B1_DVS_LEAD_LAG_CNT_CLR BIT(26) + #define R0_B1_RXDVS0_R_RK0_B1_DVS_SW_CNT_CLR BIT(27) + #define R0_B1_RXDVS0_R_RK0_B1_DVS_SW_CNT_ENA BIT(31) +#define R0_B1_RXDVS1 0x00000684 + #define R0_B1_RXDVS1_R_RK0_B1_DVS_TH_LAG GENMASK(15, 0) + #define R0_B1_RXDVS1_R_RK0_B1_DVS_TH_LEAD GENMASK(31, 16) +#define R0_B1_RXDVS2 0x00000688 + #define R0_B1_RXDVS2_R_RK0_RX_DLY_FAL_DQS_SCALE_B1 GENMASK(17, 16) + #define R0_B1_RXDVS2_R_RK0_RX_DLY_FAL_DQ_SCALE_B1 GENMASK(19, 18) + #define R0_B1_RXDVS2_R_RK0_RX_DLY_FAL_TRACK_GATE_ENA_B1 BIT(23) + #define R0_B1_RXDVS2_R_RK0_RX_DLY_RIS_DQS_SCALE_B1 GENMASK(25, 24) + #define R0_B1_RXDVS2_R_RK0_RX_DLY_RIS_DQ_SCALE_B1 GENMASK(27, 26) + #define R0_B1_RXDVS2_R_RK0_RX_DLY_RIS_TRACK_GATE_ENA_B1 BIT(28) + #define R0_B1_RXDVS2_R_RK0_DVS_FDLY_MODE_B1 BIT(29) + #define R0_B1_RXDVS2_R_RK0_DVS_MODE_B1 GENMASK(31, 30) +#define R0_B1_RXDVS7 0x0000069c + #define R0_B1_RXDVS7_RG_RK0_ARDQ_MIN_DLY_B1 GENMASK(5, 0) + #define R0_B1_RXDVS7_RG_RK0_ARDQ_MIN_DLY_B1_RFU GENMASK(7, 6) + #define R0_B1_RXDVS7_RG_RK0_ARDQ_MAX_DLY_B1 GENMASK(13, 8) + #define R0_B1_RXDVS7_RG_RK0_ARDQ_MAX_DLY_B1_RFU GENMASK(15, 14) + #define R0_B1_RXDVS7_RG_RK0_ARDQS0_MIN_DLY_B1 GENMASK(22, 16) + #define R0_B1_RXDVS7_RG_RK0_ARDQS0_MIN_DLY_B1_RFU BIT(23) + #define R0_B1_RXDVS7_RG_RK0_ARDQS0_MAX_DLY_B1 GENMASK(30, 24) + #define R0_B1_RXDVS7_RG_RK0_ARDQS0_MAX_DLY_B1_RFU BIT(31) +#define RFU_0X6A0 0x000006a0 + #define RFU_0X6A0_RESERVED_0X6A0 GENMASK(31, 0) +#define RFU_0X6A4 0x000006a4 + #define RFU_0X6A4_RESERVED_0X6A4 GENMASK(31, 0) +#define RFU_0X6A8 0x000006a8 + #define RFU_0X6A8_RESERVED_0X6A8 GENMASK(31, 0) +#define RFU_0X6AC 0x000006ac + #define RFU_0X6AC_RESERVED_0X6AC GENMASK(31, 0) +#define CA_RXDVS0 0x000006f0 + #define CA_RXDVS0_R_RX_RANKINSEL_CA BIT(0) + #define CA_RXDVS0_CA_RXDVS0_RFU GENMASK(3, 1) + #define CA_RXDVS0_R_RX_RANKINCTL_CA GENMASK(7, 4) + #define CA_RXDVS0_R_DVS_SW_UP_CA BIT(8) + #define CA_RXDVS0_R_DMRXDVS_DQIENPRE_OPT_CA BIT(9) + #define CA_RXDVS0_R_DMRXDVS_PBYTESTUCK_RST_CA BIT(10) + #define CA_RXDVS0_R_DMRXDVS_PBYTESTUCK_IG_CA BIT(11) + #define CA_RXDVS0_R_DMRXDVS_DQIENPOST_OPT_CA GENMASK(13, 12) + #define CA_RXDVS0_R_RX_DLY_RANK_ERR_ST_CLR_CA GENMASK(18, 16) + #define CA_RXDVS0_R_DMRXDVS_CNTCMP_OPT_CA BIT(19) + #define CA_RXDVS0_R_RX_DLY_RK_OPT_CA GENMASK(21, 20) + #define CA_RXDVS0_R_HWRESTORE_ENA_CA BIT(22) + #define CA_RXDVS0_R_HWSAVE_MODE_ENA_CA BIT(24) + #define CA_RXDVS0_R_RX_DLY_DVS_MODE_SYNC_DIS_CA BIT(26) + #define CA_RXDVS0_R_RX_DLY_TRACK_BYPASS_MODESYNC_CA BIT(27) + #define CA_RXDVS0_R_RX_DLY_TRACK_CG_EN_CA BIT(28) + #define CA_RXDVS0_R_RX_DLY_TRACK_SPM_CTRL_CA BIT(29) + #define CA_RXDVS0_R_RX_DLY_TRACK_CLR_CA BIT(30) + #define CA_RXDVS0_R_RX_DLY_TRACK_ENA_CA BIT(31) +#define CA_RXDVS1 0x000006f4 + #define CA_RXDVS1_CA_RXDVS1_RFU GENMASK(15, 0) + #define CA_RXDVS1_R_DMRXDVS_UPD_CLR_ACK_CA BIT(16) + #define CA_RXDVS1_R_DMRXDVS_UPD_CLR_NORD_CA BIT(17) +#define RFU_0X6F8 0x000006f8 + #define RFU_0X6F8_RESERVED_0X6F8 GENMASK(31, 0) +#define RFU_0X6FC 0x000006fc + #define RFU_0X6FC_RESERVED_0X6FC GENMASK(31, 0) +#define R0_CA_RXDVS0 0x00000700 + #define R0_CA_RXDVS0_R_RK0_CA_DVS_LEAD_LAG_CNT_CLR BIT(26) + #define R0_CA_RXDVS0_R_RK0_CA_DVS_SW_CNT_CLR BIT(27) + #define R0_CA_RXDVS0_R_RK0_CA_DVS_SW_CNT_ENA BIT(31) +#define R0_CA_RXDVS1 0x00000704 + #define R0_CA_RXDVS1_R_RK0_CA_DVS_TH_LAG GENMASK(15, 0) + #define R0_CA_RXDVS1_R_RK0_CA_DVS_TH_LEAD GENMASK(31, 16) +#define R0_CA_RXDVS2 0x00000708 + #define R0_CA_RXDVS2_R_RK0_RX_DLY_FAL_DQS_SCALE_CA GENMASK(17, 16) + #define R0_CA_RXDVS2_R_RK0_RX_DLY_FAL_DQ_SCALE_CA GENMASK(19, 18) + #define R0_CA_RXDVS2_R_RK0_RX_DLY_FAL_TRACK_GATE_ENA_CA BIT(23) + #define R0_CA_RXDVS2_R_RK0_RX_DLY_RIS_DQS_SCALE_CA GENMASK(25, 24) + #define R0_CA_RXDVS2_R_RK0_RX_DLY_RIS_DQ_SCALE_CA GENMASK(27, 26) + #define R0_CA_RXDVS2_R_RK0_RX_DLY_RIS_TRACK_GATE_ENA_CA BIT(28) + #define R0_CA_RXDVS2_R_RK0_DVS_FDLY_MODE_CA BIT(29) + #define R0_CA_RXDVS2_R_RK0_DVS_MODE_CA GENMASK(31, 30) +#define R0_CA_RXDVS9 0x00000724 + #define R0_CA_RXDVS9_RG_RK0_ARCMD_MIN_DLY GENMASK(5, 0) + #define R0_CA_RXDVS9_RG_RK0_ARCMD_MIN_DLY_RFU GENMASK(7, 6) + #define R0_CA_RXDVS9_RG_RK0_ARCMD_MAX_DLY GENMASK(13, 8) + #define R0_CA_RXDVS9_RG_RK0_ARCMD_MAX_DLY_RFU GENMASK(15, 14) + #define R0_CA_RXDVS9_RG_RK0_ARCLK_MIN_DLY GENMASK(22, 16) + #define R0_CA_RXDVS9_RG_RK0_ARCLK_MIN_DLY_RFU BIT(23) + #define R0_CA_RXDVS9_RG_RK0_ARCLK_MAX_DLY GENMASK(30, 24) + #define R0_CA_RXDVS9_RG_RK0_ARCLK_MAX_DLY_RFU BIT(31) +#define RFU_0X728 0x00000728 + #define RFU_0X728_RESERVED_0X728 GENMASK(31, 0) +#define RFU_0X72C 0x0000072c + #define RFU_0X72C_RESERVED_0X72C GENMASK(31, 0) +#define R1_B0_RXDVS0 0x00000800 + #define R1_B0_RXDVS0_R_RK1_B0_DVS_LEAD_LAG_CNT_CLR BIT(26) + #define R1_B0_RXDVS0_R_RK1_B0_DVS_SW_CNT_CLR BIT(27) + #define R1_B0_RXDVS0_R_RK1_B0_DVS_SW_CNT_ENA BIT(31) +#define R1_B0_RXDVS1 0x00000804 + #define R1_B0_RXDVS1_R_RK1_B0_DVS_TH_LAG GENMASK(15, 0) + #define R1_B0_RXDVS1_R_RK1_B0_DVS_TH_LEAD GENMASK(31, 16) +#define R1_B0_RXDVS2 0x00000808 + #define R1_B0_RXDVS2_R_RK1_RX_DLY_FAL_DQS_SCALE_B0 GENMASK(17, 16) + #define R1_B0_RXDVS2_R_RK1_RX_DLY_FAL_DQ_SCALE_B0 GENMASK(19, 18) + #define R1_B0_RXDVS2_R_RK1_RX_DLY_FAL_TRACK_GATE_ENA_B0 BIT(23) + #define R1_B0_RXDVS2_R_RK1_RX_DLY_RIS_DQS_SCALE_B0 GENMASK(25, 24) + #define R1_B0_RXDVS2_R_RK1_RX_DLY_RIS_DQ_SCALE_B0 GENMASK(27, 26) + #define R1_B0_RXDVS2_R_RK1_RX_DLY_RIS_TRACK_GATE_ENA_B0 BIT(28) + #define R1_B0_RXDVS2_R_RK1_DVS_FDLY_MODE_B0 BIT(29) + #define R1_B0_RXDVS2_R_RK1_DVS_MODE_B0 GENMASK(31, 30) +#define R1_B0_RXDVS7 0x0000081c + #define R1_B0_RXDVS7_RG_RK1_ARDQ_MIN_DLY_B0 GENMASK(5, 0) + #define R1_B0_RXDVS7_RG_RK1_ARDQ_MIN_DLY_B0_RFU GENMASK(7, 6) + #define R1_B0_RXDVS7_RG_RK1_ARDQ_MAX_DLY_B0 GENMASK(13, 8) + #define R1_B0_RXDVS7_RG_RK1_ARDQ_MAX_DLY_B0_RFU GENMASK(15, 14) + #define R1_B0_RXDVS7_RG_RK1_ARDQS0_MIN_DLY_B0 GENMASK(22, 16) + #define R1_B0_RXDVS7_RG_RK1_ARDQS0_MIN_DLY_B0_RFU BIT(23) + #define R1_B0_RXDVS7_RG_RK1_ARDQS0_MAX_DLY_B0 GENMASK(30, 24) + #define R1_B0_RXDVS7_RG_RK1_ARDQS0_MAX_DLY_B0_RFU BIT(31) +#define RFU_0X820 0x00000820 + #define RFU_0X820_RESERVED_0X820 GENMASK(31, 0) +#define RFU_0X824 0x00000824 + #define RFU_0X824_RESERVED_0X824 GENMASK(31, 0) +#define RFU_0X828 0x00000828 + #define RFU_0X828_RESERVED_0X828 GENMASK(31, 0) +#define RFU_0X82C 0x0000082c + #define RFU_0X82C_RESERVED_0X82C GENMASK(31, 0) +#define R1_B1_RXDVS0 0x00000880 + #define R1_B1_RXDVS0_R_RK1_B1_DVS_LEAD_LAG_CNT_CLR BIT(26) + #define R1_B1_RXDVS0_R_RK1_B1_DVS_SW_CNT_CLR BIT(27) + #define R1_B1_RXDVS0_R_RK1_B1_DVS_SW_CNT_ENA BIT(31) +#define R1_B1_RXDVS1 0x00000884 + #define R1_B1_RXDVS1_R_RK1_B1_DVS_TH_LAG GENMASK(15, 0) + #define R1_B1_RXDVS1_R_RK1_B1_DVS_TH_LEAD GENMASK(31, 16) +#define R1_B1_RXDVS2 0x00000888 + #define R1_B1_RXDVS2_R_RK1_RX_DLY_FAL_DQS_SCALE_B1 GENMASK(17, 16) + #define R1_B1_RXDVS2_R_RK1_RX_DLY_FAL_DQ_SCALE_B1 GENMASK(19, 18) + #define R1_B1_RXDVS2_R_RK1_RX_DLY_FAL_TRACK_GATE_ENA_B1 BIT(23) + #define R1_B1_RXDVS2_R_RK1_RX_DLY_RIS_DQS_SCALE_B1 GENMASK(25, 24) + #define R1_B1_RXDVS2_R_RK1_RX_DLY_RIS_DQ_SCALE_B1 GENMASK(27, 26) + #define R1_B1_RXDVS2_R_RK1_RX_DLY_RIS_TRACK_GATE_ENA_B1 BIT(28) + #define R1_B1_RXDVS2_R_RK1_DVS_FDLY_MODE_B1 BIT(29) + #define R1_B1_RXDVS2_R_RK1_DVS_MODE_B1 GENMASK(31, 30) +#define R1_B1_RXDVS7 0x0000089c + #define R1_B1_RXDVS7_RG_RK1_ARDQ_MIN_DLY_B1 GENMASK(5, 0) + #define R1_B1_RXDVS7_RG_RK1_ARDQ_MIN_DLY_B1_RFU GENMASK(7, 6) + #define R1_B1_RXDVS7_RG_RK1_ARDQ_MAX_DLY_B1 GENMASK(13, 8) + #define R1_B1_RXDVS7_RG_RK1_ARDQ_MAX_DLY_B1_RFU GENMASK(15, 14) + #define R1_B1_RXDVS7_RG_RK1_ARDQS0_MIN_DLY_B1 GENMASK(22, 16) + #define R1_B1_RXDVS7_RG_RK1_ARDQS0_MIN_DLY_B1_RFU BIT(23) + #define R1_B1_RXDVS7_RG_RK1_ARDQS0_MAX_DLY_B1 GENMASK(30, 24) + #define R1_B1_RXDVS7_RG_RK1_ARDQS0_MAX_DLY_B1_RFU BIT(31) +#define RFU_0X8A0 0x000008a0 + #define RFU_0X8A0_RESERVED_0X8A0 GENMASK(31, 0) +#define RFU_0X8A4 0x000008a4 + #define RFU_0X8A4_RESERVED_0X8A4 GENMASK(31, 0) +#define RFU_0X8A8 0x000008a8 + #define RFU_0X8A8_RESERVED_0X8A8 GENMASK(31, 0) +#define RFU_0X8AC 0x000008ac + #define RFU_0X8AC_RESERVED_0X8AC GENMASK(31, 0) +#define R1_CA_RXDVS0 0x00000900 + #define R1_CA_RXDVS0_R_RK1_CA_DVS_LEAD_LAG_CNT_CLR BIT(26) + #define R1_CA_RXDVS0_R_RK1_CA_DVS_SW_CNT_CLR BIT(27) + #define R1_CA_RXDVS0_R_RK1_CA_DVS_SW_CNT_ENA BIT(31) +#define R1_CA_RXDVS1 0x00000904 + #define R1_CA_RXDVS1_R_RK1_CA_DVS_TH_LAG GENMASK(15, 0) + #define R1_CA_RXDVS1_R_RK1_CA_DVS_TH_LEAD GENMASK(31, 16) +#define R1_CA_RXDVS2 0x00000908 + #define R1_CA_RXDVS2_R_RK1_RX_DLY_FAL_DQS_SCALE_CA GENMASK(17, 16) + #define R1_CA_RXDVS2_R_RK1_RX_DLY_FAL_DQ_SCALE_CA GENMASK(19, 18) + #define R1_CA_RXDVS2_R_RK1_RX_DLY_FAL_TRACK_GATE_ENA_CA BIT(23) + #define R1_CA_RXDVS2_R_RK1_RX_DLY_RIS_DQS_SCALE_CA GENMASK(25, 24) + #define R1_CA_RXDVS2_R_RK1_RX_DLY_RIS_DQ_SCALE_CA GENMASK(27, 26) + #define R1_CA_RXDVS2_R_RK1_RX_DLY_RIS_TRACK_GATE_ENA_CA BIT(28) + #define R1_CA_RXDVS2_R_RK1_DVS_FDLY_MODE_CA BIT(29) + #define R1_CA_RXDVS2_R_RK1_DVS_MODE_CA GENMASK(31, 30) +#define R1_CA_RXDVS9 0x00000924 + #define R1_CA_RXDVS9_RG_RK1_ARCMD_MIN_DLY GENMASK(5, 0) + #define R1_CA_RXDVS9_RG_RK1_ARCMD_MIN_DLY_RFU GENMASK(7, 6) + #define R1_CA_RXDVS9_RG_RK1_ARCMD_MAX_DLY GENMASK(13, 8) + #define R1_CA_RXDVS9_RG_RK1_ARCMD_MAX_DLY_RFU GENMASK(15, 14) + #define R1_CA_RXDVS9_RG_RK1_ARCLK_MIN_DLY GENMASK(22, 16) + #define R1_CA_RXDVS9_RG_RK1_ARCLK_MIN_DLY_RFU BIT(23) + #define R1_CA_RXDVS9_RG_RK1_ARCLK_MAX_DLY GENMASK(30, 24) + #define R1_CA_RXDVS9_RG_RK1_ARCLK_MAX_DLY_RFU BIT(31) +#define RFU_0X928 0x00000928 + #define RFU_0X928_RESERVED_0X928 GENMASK(31, 0) +#define RFU_0X92C 0x0000092c + #define RFU_0X92C_RESERVED_0X92C GENMASK(31, 0) +#define R2_B0_RXDVS0 0x00000a00 + #define R2_B0_RXDVS0_R_RK2_B0_DVS_LEAD_LAG_CNT_CLR BIT(26) + #define R2_B0_RXDVS0_R_RK2_B0_DVS_SW_CNT_CLR BIT(27) + #define R2_B0_RXDVS0_R_RK2_B0_DVS_SW_CNT_ENA BIT(31) +#define R2_B0_RXDVS1 0x00000a04 + #define R2_B0_RXDVS1_R_RK2_B0_DVS_TH_LAG GENMASK(15, 0) + #define R2_B0_RXDVS1_R_RK2_B0_DVS_TH_LEAD GENMASK(31, 16) +#define R2_B0_RXDVS2 0x00000a08 + #define R2_B0_RXDVS2_R_RK2_RX_DLY_FAL_DQS_SCALE_B0 GENMASK(17, 16) + #define R2_B0_RXDVS2_R_RK2_RX_DLY_FAL_DQ_SCALE_B0 GENMASK(19, 18) + #define R2_B0_RXDVS2_R_RK2_RX_DLY_FAL_TRACK_GATE_ENA_B0 BIT(23) + #define R2_B0_RXDVS2_R_RK2_RX_DLY_RIS_DQS_SCALE_B0 GENMASK(25, 24) + #define R2_B0_RXDVS2_R_RK2_RX_DLY_RIS_DQ_SCALE_B0 GENMASK(27, 26) + #define R2_B0_RXDVS2_R_RK2_RX_DLY_RIS_TRACK_GATE_ENA_B0 BIT(28) + #define R2_B0_RXDVS2_R_RK2_DVS_FDLY_MODE_B0 BIT(29) + #define R2_B0_RXDVS2_R_RK2_DVS_MODE_B0 GENMASK(31, 30) +#define R2_B0_RXDVS7 0x00000a1c + #define R2_B0_RXDVS7_RG_RK2_ARDQ_MIN_DLY_B0 GENMASK(5, 0) + #define R2_B0_RXDVS7_RG_RK2_ARDQ_MIN_DLY_B0_RFU GENMASK(7, 6) + #define R2_B0_RXDVS7_RG_RK2_ARDQ_MAX_DLY_B0 GENMASK(13, 8) + #define R2_B0_RXDVS7_RG_RK2_ARDQ_MAX_DLY_B0_RFU GENMASK(15, 14) + #define R2_B0_RXDVS7_RG_RK2_ARDQS0_MIN_DLY_B0 GENMASK(22, 16) + #define R2_B0_RXDVS7_RG_RK2_ARDQS0_MIN_DLY_B0_RFU BIT(23) + #define R2_B0_RXDVS7_RG_RK2_ARDQS0_MAX_DLY_B0 GENMASK(30, 24) + #define R2_B0_RXDVS7_RG_RK2_ARDQS0_MAX_DLY_B0_RFU BIT(31) +#define RFU_0XA20 0x00000a20 + #define RFU_0XA20_RESERVED_0XA20 GENMASK(31, 0) +#define RFU_0XA24 0x00000a24 + #define RFU_0XA24_RESERVED_0XA24 GENMASK(31, 0) +#define RFU_0XA28 0x00000a28 + #define RFU_0XA28_RESERVED_0XA28 GENMASK(31, 0) +#define RFU_0XA2C 0x00000a2c + #define RFU_0XA2C_RESERVED_0XA2C GENMASK(31, 0) +#define R2_B1_RXDVS0 0x00000a80 + #define R2_B1_RXDVS0_R_RK2_B1_DVS_LEAD_LAG_CNT_CLR BIT(26) + #define R2_B1_RXDVS0_R_RK2_B1_DVS_SW_CNT_CLR BIT(27) + #define R2_B1_RXDVS0_R_RK2_B1_DVS_SW_CNT_ENA BIT(31) +#define R2_B1_RXDVS1 0x00000a84 + #define R2_B1_RXDVS1_R_RK2_B1_DVS_TH_LAG GENMASK(15, 0) + #define R2_B1_RXDVS1_R_RK2_B1_DVS_TH_LEAD GENMASK(31, 16) +#define R2_B1_RXDVS2 0x00000a88 + #define R2_B1_RXDVS2_R_RK2_RX_DLY_FAL_DQS_SCALE_B1 GENMASK(17, 16) + #define R2_B1_RXDVS2_R_RK2_RX_DLY_FAL_DQ_SCALE_B1 GENMASK(19, 18) + #define R2_B1_RXDVS2_R_RK2_RX_DLY_FAL_TRACK_GATE_ENA_B1 BIT(23) + #define R2_B1_RXDVS2_R_RK2_RX_DLY_RIS_DQS_SCALE_B1 GENMASK(25, 24) + #define R2_B1_RXDVS2_R_RK2_RX_DLY_RIS_DQ_SCALE_B1 GENMASK(27, 26) + #define R2_B1_RXDVS2_R_RK2_RX_DLY_RIS_TRACK_GATE_ENA_B1 BIT(28) + #define R2_B1_RXDVS2_R_RK2_DVS_FDLY_MODE_B1 BIT(29) + #define R2_B1_RXDVS2_R_RK2_DVS_MODE_B1 GENMASK(31, 30) +#define R2_B1_RXDVS7 0x00000a9c + #define R2_B1_RXDVS7_RG_RK2_ARDQ_MIN_DLY_B1 GENMASK(5, 0) + #define R2_B1_RXDVS7_RG_RK2_ARDQ_MIN_DLY_B1_RFU GENMASK(7, 6) + #define R2_B1_RXDVS7_RG_RK2_ARDQ_MAX_DLY_B1 GENMASK(13, 8) + #define R2_B1_RXDVS7_RG_RK2_ARDQ_MAX_DLY_B1_RFU GENMASK(15, 14) + #define R2_B1_RXDVS7_RG_RK2_ARDQS0_MIN_DLY_B1 GENMASK(22, 16) + #define R2_B1_RXDVS7_RG_RK2_ARDQS0_MIN_DLY_B1_RFU BIT(23) + #define R2_B1_RXDVS7_RG_RK2_ARDQS0_MAX_DLY_B1 GENMASK(30, 24) + #define R2_B1_RXDVS7_RG_RK2_ARDQS0_MAX_DLY_B1_RFU BIT(31) +#define RFU_0XAA0 0x00000aa0 + #define RFU_0XAA0_RESERVED_0XAA0 GENMASK(31, 0) +#define RFU_0XAA4 0x00000aa4 + #define RFU_0XAA4_RESERVED_0XAA4 GENMASK(31, 0) +#define RFU_0XAA8 0x00000aa8 + #define RFU_0XAA8_RESERVED_0XAA8 GENMASK(31, 0) +#define RFU_0XAAC 0x00000aac + #define RFU_0XAAC_RESERVED_0XAAC GENMASK(31, 0) +#define R2_CA_RXDVS0 0x00000b00 + #define R2_CA_RXDVS0_R_RK2_CA_DVS_LEAD_LAG_CNT_CLR BIT(26) + #define R2_CA_RXDVS0_R_RK2_CA_DVS_SW_CNT_CLR BIT(27) + #define R2_CA_RXDVS0_R_RK2_CA_DVS_SW_CNT_ENA BIT(31) +#define R2_CA_RXDVS1 0x00000b04 + #define R2_CA_RXDVS1_R_RK2_CA_DVS_TH_LAG GENMASK(15, 0) + #define R2_CA_RXDVS1_R_RK2_CA_DVS_TH_LEAD GENMASK(31, 16) +#define R2_CA_RXDVS2 0x00000b08 + #define R2_CA_RXDVS2_R_RK2_RX_DLY_FAL_DQS_SCALE_CA GENMASK(17, 16) + #define R2_CA_RXDVS2_R_RK2_RX_DLY_FAL_DQ_SCALE_CA GENMASK(19, 18) + #define R2_CA_RXDVS2_R_RK2_RX_DLY_FAL_TRACK_GATE_ENA_CA BIT(23) + #define R2_CA_RXDVS2_R_RK2_RX_DLY_RIS_DQS_SCALE_CA GENMASK(25, 24) + #define R2_CA_RXDVS2_R_RK2_RX_DLY_RIS_DQ_SCALE_CA GENMASK(27, 26) + #define R2_CA_RXDVS2_R_RK2_RX_DLY_RIS_TRACK_GATE_ENA_CA BIT(28) + #define R2_CA_RXDVS2_R_RK2_DVS_FDLY_MODE_CA BIT(29) + #define R2_CA_RXDVS2_R_RK2_DVS_MODE_CA GENMASK(31, 30) +#define R2_CA_RXDVS9 0x00000b24 + #define R2_CA_RXDVS9_RG_RK2_ARCMD_MIN_DLY GENMASK(5, 0) + #define R2_CA_RXDVS9_RG_RK2_ARCMD_MIN_DLY_RFU GENMASK(7, 6) + #define R2_CA_RXDVS9_RG_RK2_ARCMD_MAX_DLY GENMASK(13, 8) + #define R2_CA_RXDVS9_RG_RK2_ARCMD_MAX_DLY_RFU GENMASK(15, 14) + #define R2_CA_RXDVS9_RG_RK2_ARCLK_MIN_DLY GENMASK(22, 16) + #define R2_CA_RXDVS9_RG_RK2_ARCLK_MIN_DLY_RFU BIT(23) + #define R2_CA_RXDVS9_RG_RK2_ARCLK_MAX_DLY GENMASK(30, 24) + #define R2_CA_RXDVS9_RG_RK2_ARCLK_MAX_DLY_RFU BIT(31) +#define RFU_0XB28 0x00000b28 + #define RFU_0XB28_RESERVED_0XB28 GENMASK(31, 0) +#define RFU_0XB2C 0x00000b2c + #define RFU_0XB2C_RESERVED_0XB2C GENMASK(31, 0) +#define SHU1_B0_DQ0 0x00000c00 + #define SHU1_B0_DQ0_RG_TX_ARDQS0_PRE_EN_B0 BIT(4) + #define SHU1_B0_DQ0_RG_TX_ARDQS0_DRVP_PRE_B0 GENMASK(10, 8) + #define SHU1_B0_DQ0_RG_TX_ARDQS0_DRVP_PRE_B0_BIT2 BIT(10)//[10:10] //Francis added + #define SHU1_B0_DQ0_RG_TX_ARDQS0_DRVP_PRE_B0_BIT1 BIT(9)//[9:9] //Francis added + #define SHU1_B0_DQ0_RG_TX_ARDQS0_DRVP_PRE_B0_BIT0 BIT(8)//[8:8] //Francis added + #define SHU1_B0_DQ0_RG_TX_ARDQS0_DRVN_PRE_B0 GENMASK(14, 12) + #define SHU1_B0_DQ0_RG_TX_ARDQ_PRE_EN_B0 BIT(20) + #define SHU1_B0_DQ0_RG_TX_ARDQ_DRVP_PRE_B0 GENMASK(26, 24) + #define SHU1_B0_DQ0_RG_TX_ARDQ_DRVN_PRE_B0 GENMASK(30, 28) + #define SHU1_B0_DQ0_R_LP4Y_WDN_MODE_DQS0 BIT(31) +#define SHU1_B0_DQ1 0x00000c04 + #define SHU1_B0_DQ1_RG_TX_ARDQ_DRVP_B0 GENMASK(4, 0) + #define SHU1_B0_DQ1_RG_TX_ARDQ_DRVN_B0 GENMASK(12, 8) + #define SHU1_B0_DQ1_RG_TX_ARDQ_ODTP_B0 GENMASK(20, 16) + #define SHU1_B0_DQ1_RG_TX_ARDQ_ODTN_B0 GENMASK(28, 24) +#define SHU1_B0_DQ2 0x00000c08 + #define SHU1_B0_DQ2_RG_TX_ARDQS0_DRVP_B0 GENMASK(4, 0) + #define SHU1_B0_DQ2_RG_TX_ARDQS0_DRVN_B0 GENMASK(12, 8) + #define SHU1_B0_DQ2_RG_TX_ARDQS0_ODTP_B0 GENMASK(20, 16) + #define SHU1_B0_DQ2_RG_TX_ARDQS0_ODTN_B0 GENMASK(28, 24) +#define SHU1_B0_DQ3 0x00000c0c + #define SHU1_B0_DQ3_RG_TX_ARDQS0_PU_B0 GENMASK(1, 0) + #define SHU1_B0_DQ3_RG_TX_ARDQS0_PU_PRE_B0 GENMASK(3, 2) + #define SHU1_B0_DQ3_RG_TX_ARDQS0_PDB_B0 GENMASK(5, 4) + #define SHU1_B0_DQ3_RG_TX_ARDQS0_PDB_PRE_B0 GENMASK(7, 6) + #define SHU1_B0_DQ3_RG_TX_ARDQ_PU_B0 GENMASK(9, 8) + #define SHU1_B0_DQ3_RG_TX_ARDQ_PU_PRE_B0 GENMASK(11, 10) + #define SHU1_B0_DQ3_RG_TX_ARDQ_PDB_B0 GENMASK(13, 12) + #define SHU1_B0_DQ3_RG_TX_ARDQ_PDB_PRE_B0 GENMASK(15, 14) +#define SHU1_B0_DQ4 0x00000c10 + #define SHU1_B0_DQ4_RG_ARPI_AA_MCK_DL_B0 GENMASK(5, 0) + #define SHU1_B0_DQ4_RG_ARPI_AA_MCK_FB_DL_B0 GENMASK(13, 8) + #define SHU1_B0_DQ4_RG_ARPI_DA_MCK_FB_DL_B0 GENMASK(21, 16) +#define SHU1_B0_DQ5 0x00000c14 + #define SHU1_B0_DQ5_RG_RX_ARDQ_VREF_SEL_B0 GENMASK(5, 0) + #define SHU1_B0_DQ5_RG_RX_ARDQ_VREF_BYPASS_B0 BIT(6) + #define SHU1_B0_DQ5_RG_ARPI_FB_B0 GENMASK(13, 8) + #define SHU1_B0_DQ5_RG_RX_ARDQS0_DQSIEN_DLY_B0 GENMASK(18, 16) + #define SHU1_B0_DQ5_DA_RX_ARDQS_DQSIEN_RB_DLY_B0 BIT(19) + #define SHU1_B0_DQ5_RG_RX_ARDQS0_DVS_DLY_B0 GENMASK(22, 20) + #define SHU1_B0_DQ5_RG_ARPI_MCTL_B0 GENMASK(29, 24) +#define SHU1_B0_DQ6 0x00000c18 + #define SHU1_B0_DQ6_RG_ARPI_OFFSET_DQSIEN_B0 GENMASK(5, 0) + #define SHU1_B0_DQ6_RG_ARPI_RESERVE_B0 GENMASK(21, 6) + #define SHU1_B0_DQ6_RG_ARPI_MIDPI_CAP_SEL_B0 GENMASK(23, 22) + #define SHU1_B0_DQ6_RG_ARPI_MIDPI_VTH_SEL_B0 GENMASK(25, 24) + #define SHU1_B0_DQ6_RG_ARPI_MIDPI_EN_B0 BIT(26) + #define SHU1_B0_DQ6_RG_ARPI_MIDPI_CKDIV4_EN_B0 BIT(27) + #define SHU1_B0_DQ6_RG_ARPI_CAP_SEL_B0 GENMASK(29, 28) + #define SHU1_B0_DQ6_RG_ARPI_MIDPI_BYPASS_EN_B0 BIT(31) +#define SHU1_B0_DQ7 0x00000c1c + #define SHU1_B0_DQ7_R_DMRANKRXDVS_B0 GENMASK(3, 0) + #define SHU1_B0_DQ7_MIDPI_ENABLE BIT(4) + #define SHU1_B0_DQ7_MIDPI_DIV4_ENABLE BIT(5) + #define SHU1_B0_DQ7_R_DMDQMDBI_EYE_SHU_B0 BIT(6) + #define SHU1_B0_DQ7_R_DMDQMDBI_SHU_B0 BIT(7) + #define SHU1_B0_DQ7_R_DMRXDVS_DQM_FLAGSEL_B0 GENMASK(11, 8) + #define SHU1_B0_DQ7_R_DMRXDVS_PBYTE_FLAG_OPT_B0 BIT(12) + #define SHU1_B0_DQ7_R_DMRXDVS_PBYTE_DQM_EN_B0 BIT(13) + #define SHU1_B0_DQ7_R_DMRXTRACK_DQM_EN_B0 BIT(14) + #define SHU1_B0_DQ7_R_DMRODTEN_B0 BIT(15) + #define SHU1_B0_DQ7_R_DMARPI_CG_FB2DLL_DCM_EN_B0 BIT(16) + #define SHU1_B0_DQ7_R_DMTX_ARPI_CG_DQ_NEW_B0 BIT(17) + #define SHU1_B0_DQ7_R_DMTX_ARPI_CG_DQS_NEW_B0 BIT(18) + #define SHU1_B0_DQ7_R_DMTX_ARPI_CG_DQM_NEW_B0 BIT(19) + #define SHU1_B0_DQ7_R_LP4Y_SDN_MODE_DQS0 BIT(20) + #define SHU1_B0_DQ7_R_DMRXRANK_DQ_EN_B0 BIT(24) + #define SHU1_B0_DQ7_R_DMRXRANK_DQ_LAT_B0 GENMASK(27, 25) + #define SHU1_B0_DQ7_R_DMRXRANK_DQS_EN_B0 BIT(28) + #define SHU1_B0_DQ7_R_DMRXRANK_DQS_LAT_B0 GENMASK(31, 29) +#define SHU1_B0_DQ8 0x00000c20 + #define SHU1_B0_DQ8_R_DMRXDVS_UPD_FORCE_CYC_B0 GENMASK(14, 0) + #define SHU1_B0_DQ8_R_DMRXDVS_UPD_FORCE_EN_B0 BIT(15) + #define SHU1_B0_DQ8_R_DMRANK_RXDLY_PIPE_CG_IG_B0 BIT(19) + #define SHU1_B0_DQ8_R_RMRODTEN_CG_IG_B0 BIT(20) + #define SHU1_B0_DQ8_R_RMRX_TOPHY_CG_IG_B0 BIT(21) + #define SHU1_B0_DQ8_R_DMRXDVS_RDSEL_PIPE_CG_IG_B0 BIT(22) + #define SHU1_B0_DQ8_R_DMRXDVS_RDSEL_TOG_PIPE_CG_IG_B0 BIT(23) + #define SHU1_B0_DQ8_R_DMRXDLY_CG_IG_B0 BIT(24) + #define SHU1_B0_DQ8_R_DMSTBEN_SYNC_CG_IG_B0 BIT(25) + #define SHU1_B0_DQ8_R_DMDQSIEN_FLAG_SYNC_CG_IG_B0 BIT(26) + #define SHU1_B0_DQ8_R_DMDQSIEN_FLAG_PIPE_CG_IG_B0 BIT(27) + #define SHU1_B0_DQ8_R_DMDQSIEN_RDSEL_PIPE_CG_IG_B0 BIT(28) + #define SHU1_B0_DQ8_R_DMDQSIEN_RDSEL_TOG_PIPE_CG_IG_B0 BIT(29) + #define SHU1_B0_DQ8_R_DMRANK_PIPE_CG_IG_B0 BIT(30) + #define SHU1_B0_DQ8_R_DMRANK_CHG_PIPE_CG_IG_B0 BIT(31) +#define SHU1_B0_DQ9 0x00000c24 + #define SHU1_B0_DQ9_RESERVED_0XC24 GENMASK(31, 0) +#define SHU1_B0_DQ10 0x00000c28 + #define SHU1_B0_DQ10_RESERVED_0XC28 GENMASK(31, 0) +#define SHU1_B0_DQ11 0x00000c2c + #define SHU1_B0_DQ11_RESERVED_0XC2C GENMASK(31, 0) +#define SHU1_B0_DQ12 0x00000c30 + #define SHU1_B0_DQ12_RESERVED_0XC30 GENMASK(31, 0) +#define SHU1_B0_DLL0 0x00000c34 + #define SHU1_B0_DLL0_RG_ARPISM_MCK_SEL_B0_SHU BIT(0) + #define SHU1_B0_DLL0_B0_DLL0_RFU BIT(3) + #define SHU1_B0_DLL0_RG_ARDLL_FAST_PSJP_B0 BIT(4) + #define SHU1_B0_DLL0_RG_ARDLL_PHDIV_B0 BIT(9) + #define SHU1_B0_DLL0_RG_ARDLL_PHJUMP_EN_B0 BIT(10) + #define SHU1_B0_DLL0_RG_ARDLL_P_GAIN_B0 GENMASK(15, 12) + #define SHU1_B0_DLL0_RG_ARDLL_IDLECNT_B0 GENMASK(19, 16) + #define SHU1_B0_DLL0_RG_ARDLL_GAIN_B0 GENMASK(23, 20) + #define SHU1_B0_DLL0_RG_ARDLL_PHDET_IN_SWAP_B0 BIT(30) + #define SHU1_B0_DLL0_RG_ARDLL_PHDET_OUT_SEL_B0 BIT(31) +#define SHU1_B0_DLL1 0x00000c38 + #define SHU1_B0_DLL1_RG_ARDLL_FASTPJ_CK_SEL_B0 BIT(0) + #define SHU1_B0_DLL1_RG_ARDLL_PS_EN_B0 BIT(1) + #define SHU1_B0_DLL1_RG_ARDLL_PD_CK_SEL_B0 BIT(2) + #define SHU1_B0_DLL1_RG_ARDQ_REV_B0 GENMASK(31, 8) +#define SHU1_B1_DQ0 0x00000c80 + #define SHU1_B1_DQ0_RG_TX_ARDQS0_PRE_EN_B1 BIT(4) + #define SHU1_B1_DQ0_RG_TX_ARDQS0_DRVP_PRE_B1 GENMASK(10, 8) + #define SHU1_B1_DQ0_RG_TX_ARDQS0_DRVP_PRE_B1_BIT2 BIT(10)//[10:10] //Francis added + #define SHU1_B1_DQ0_RG_TX_ARDQS0_DRVP_PRE_B1_BIT1 BIT(9)//[9:9] //Francis added + #define SHU1_B1_DQ0_RG_TX_ARDQS0_DRVP_PRE_B1_BIT0 BIT(8)//[8:8] //Francis added + #define SHU1_B1_DQ0_RG_TX_ARDQS0_DRVN_PRE_B1 GENMASK(14, 12) + #define SHU1_B1_DQ0_RG_TX_ARDQ_PRE_EN_B1 BIT(20) + #define SHU1_B1_DQ0_RG_TX_ARDQ_DRVP_PRE_B1 GENMASK(26, 24) + #define SHU1_B1_DQ0_RG_TX_ARDQ_DRVN_PRE_B1 GENMASK(30, 28) + #define SHU1_B1_DQ0_R_LP4Y_WDN_MODE_DQS1 BIT(31) +#define SHU1_B1_DQ1 0x00000c84 + #define SHU1_B1_DQ1_RG_TX_ARDQ_DRVP_B1 GENMASK(4, 0) + #define SHU1_B1_DQ1_RG_TX_ARDQ_DRVN_B1 GENMASK(12, 8) + #define SHU1_B1_DQ1_RG_TX_ARDQ_ODTP_B1 GENMASK(20, 16) + #define SHU1_B1_DQ1_RG_TX_ARDQ_ODTN_B1 GENMASK(28, 24) +#define SHU1_B1_DQ2 0x00000c88 + #define SHU1_B1_DQ2_RG_TX_ARDQS0_DRVP_B1 GENMASK(4, 0) + #define SHU1_B1_DQ2_RG_TX_ARDQS0_DRVN_B1 GENMASK(12, 8) + #define SHU1_B1_DQ2_RG_TX_ARDQS0_ODTP_B1 GENMASK(20, 16) + #define SHU1_B1_DQ2_RG_TX_ARDQS0_ODTN_B1 GENMASK(28, 24) +#define SHU1_B1_DQ3 0x00000c8c + #define SHU1_B1_DQ3_RG_TX_ARDQS0_PU_B1 GENMASK(1, 0) + #define SHU1_B1_DQ3_RG_TX_ARDQS0_PU_PRE_B1 GENMASK(3, 2) + #define SHU1_B1_DQ3_RG_TX_ARDQS0_PDB_B1 GENMASK(5, 4) + #define SHU1_B1_DQ3_RG_TX_ARDQS0_PDB_PRE_B1 GENMASK(7, 6) + #define SHU1_B1_DQ3_RG_TX_ARDQ_PU_B1 GENMASK(9, 8) + #define SHU1_B1_DQ3_RG_TX_ARDQ_PU_PRE_B1 GENMASK(11, 10) + #define SHU1_B1_DQ3_RG_TX_ARDQ_PDB_B1 GENMASK(13, 12) + #define SHU1_B1_DQ3_RG_TX_ARDQ_PDB_PRE_B1 GENMASK(15, 14) +#define SHU1_B1_DQ4 0x00000c90 + #define SHU1_B1_DQ4_RG_ARPI_AA_MCK_DL_B1 GENMASK(5, 0) + #define SHU1_B1_DQ4_RG_ARPI_AA_MCK_FB_DL_B1 GENMASK(13, 8) + #define SHU1_B1_DQ4_RG_ARPI_DA_MCK_FB_DL_B1 GENMASK(21, 16) +#define SHU1_B1_DQ5 0x00000c94 + #define SHU1_B1_DQ5_RG_RX_ARDQ_VREF_SEL_B1 GENMASK(5, 0) + #define SHU1_B1_DQ5_RG_RX_ARDQ_VREF_BYPASS_B1 BIT(6) + #define SHU1_B1_DQ5_RG_ARPI_FB_B1 GENMASK(13, 8) + #define SHU1_B1_DQ5_RG_RX_ARDQS0_DQSIEN_DLY_B1 GENMASK(18, 16) + #define SHU1_B1_DQ5_DA_RX_ARDQS_DQSIEN_RB_DLY_B1 BIT(19) + #define SHU1_B1_DQ5_RG_RX_ARDQS0_DVS_DLY_B1 GENMASK(22, 20) + #define SHU1_B1_DQ5_RG_ARPI_MCTL_B1 GENMASK(29, 24) +#define SHU1_B1_DQ6 0x00000c98 + #define SHU1_B1_DQ6_RG_ARPI_OFFSET_DQSIEN_B1 GENMASK(5, 0) + #define SHU1_B1_DQ6_RG_ARPI_RESERVE_B1 GENMASK(21, 6) + #define SHU1_B1_DQ6_RG_ARPI_MIDPI_CAP_SEL_B1 GENMASK(23, 22) + #define SHU1_B1_DQ6_RG_ARPI_MIDPI_VTH_SEL_B1 GENMASK(25, 24) + #define SHU1_B1_DQ6_RG_ARPI_MIDPI_EN_B1 BIT(26) + #define SHU1_B1_DQ6_RG_ARPI_MIDPI_CKDIV4_EN_B1 BIT(27) + #define SHU1_B1_DQ6_RG_ARPI_CAP_SEL_B1 GENMASK(29, 28) + #define SHU1_B1_DQ6_RG_ARPI_MIDPI_BYPASS_EN_B1 BIT(31) +#define SHU1_B1_DQ7 0x00000c9c + #define SHU1_B1_DQ7_R_DMRANKRXDVS_B1 GENMASK(3, 0) + #define SHU1_B1_DQ7_R_DMDQMDBI_EYE_SHU_B1 BIT(6) + #define SHU1_B1_DQ7_R_DMDQMDBI_SHU_B1 BIT(7) + #define SHU1_B1_DQ7_R_DMRXDVS_DQM_FLAGSEL_B1 GENMASK(11, 8) + #define SHU1_B1_DQ7_R_DMRXDVS_PBYTE_FLAG_OPT_B1 BIT(12) + #define SHU1_B1_DQ7_R_DMRXDVS_PBYTE_DQM_EN_B1 BIT(13) + #define SHU1_B1_DQ7_R_DMRXTRACK_DQM_EN_B1 BIT(14) + #define SHU1_B1_DQ7_R_DMRODTEN_B1 BIT(15) + #define SHU1_B1_DQ7_R_DMARPI_CG_FB2DLL_DCM_EN_B1 BIT(16) + #define SHU1_B1_DQ7_R_DMTX_ARPI_CG_DQ_NEW_B1 BIT(17) + #define SHU1_B1_DQ7_R_DMTX_ARPI_CG_DQS_NEW_B1 BIT(18) + #define SHU1_B1_DQ7_R_DMTX_ARPI_CG_DQM_NEW_B1 BIT(19) + #define SHU1_B1_DQ7_R_LP4Y_SDN_MODE_DQS1 BIT(20) + #define SHU1_B1_DQ7_R_DMRXRANK_DQ_EN_B1 BIT(24) + #define SHU1_B1_DQ7_R_DMRXRANK_DQ_LAT_B1 GENMASK(27, 25) + #define SHU1_B1_DQ7_R_DMRXRANK_DQS_EN_B1 BIT(28) + #define SHU1_B1_DQ7_R_DMRXRANK_DQS_LAT_B1 GENMASK(31, 29) +#define SHU1_B1_DQ8 0x00000ca0 + #define SHU1_B1_DQ8_R_DMRXDVS_UPD_FORCE_CYC_B1 GENMASK(14, 0) + #define SHU1_B1_DQ8_R_DMRXDVS_UPD_FORCE_EN_B1 BIT(15) + #define SHU1_B1_DQ8_R_DMRANK_RXDLY_PIPE_CG_IG_B1 BIT(19) + #define SHU1_B1_DQ8_R_RMRODTEN_CG_IG_B1 BIT(20) + #define SHU1_B1_DQ8_R_RMRX_TOPHY_CG_IG_B1 BIT(21) + #define SHU1_B1_DQ8_R_DMRXDVS_RDSEL_PIPE_CG_IG_B1 BIT(22) + #define SHU1_B1_DQ8_R_DMRXDVS_RDSEL_TOG_PIPE_CG_IG_B1 BIT(23) + #define SHU1_B1_DQ8_R_DMRXDLY_CG_IG_B1 BIT(24) + #define SHU1_B1_DQ8_R_DMSTBEN_SYNC_CG_IG_B1 BIT(25) + #define SHU1_B1_DQ8_R_DMDQSIEN_FLAG_SYNC_CG_IG_B1 BIT(26) + #define SHU1_B1_DQ8_R_DMDQSIEN_FLAG_PIPE_CG_IG_B1 BIT(27) + #define SHU1_B1_DQ8_R_DMDQSIEN_RDSEL_PIPE_CG_IG_B1 BIT(28) + #define SHU1_B1_DQ8_R_DMDQSIEN_RDSEL_TOG_PIPE_CG_IG_B1 BIT(29) + #define SHU1_B1_DQ8_R_DMRANK_PIPE_CG_IG_B1 BIT(30) + #define SHU1_B1_DQ8_R_DMRANK_CHG_PIPE_CG_IG_B1 BIT(31) +#define SHU1_B1_DQ9 0x00000ca4 + #define SHU1_B1_DQ9_RESERVED_0XCA4 GENMASK(31, 0) +#define SHU1_B1_DQ10 0x00000ca8 + #define SHU1_B1_DQ10_RESERVED_0XCA8 GENMASK(31, 0) +#define SHU1_B1_DQ11 0x00000cac + #define SHU1_B1_DQ11_RESERVED_0XCAC GENMASK(31, 0) +#define SHU1_B1_DQ12 0x00000cb0 + #define SHU1_B1_DQ12_RESERVED_0XCB0 GENMASK(31, 0) +#define SHU1_B1_DLL0 0x00000cb4 + #define SHU1_B1_DLL0_RG_ARPISM_MCK_SEL_B1_SHU BIT(0) + #define SHU1_B1_DLL0_B1_DLL0_RFU BIT(3) + #define SHU1_B1_DLL0_RG_ARDLL_FAST_PSJP_B1 BIT(4) + #define SHU1_B1_DLL0_RG_ARDLL_PHDIV_B1 BIT(9) + #define SHU1_B1_DLL0_RG_ARDLL_PHJUMP_EN_B1 BIT(10) + #define SHU1_B1_DLL0_RG_ARDLL_P_GAIN_B1 GENMASK(15, 12) + #define SHU1_B1_DLL0_RG_ARDLL_IDLECNT_B1 GENMASK(19, 16) + #define SHU1_B1_DLL0_RG_ARDLL_GAIN_B1 GENMASK(23, 20) + #define SHU1_B1_DLL0_RG_ARDLL_PHDET_IN_SWAP_B1 BIT(30) + #define SHU1_B1_DLL0_RG_ARDLL_PHDET_OUT_SEL_B1 BIT(31) +#define SHU1_B1_DLL1 0x00000cb8 + #define SHU1_B1_DLL1_RG_ARDLL_FASTPJ_CK_SEL_B1 BIT(0) + #define SHU1_B1_DLL1_RG_ARDLL_PS_EN_B1 BIT(1) + #define SHU1_B1_DLL1_RG_ARDLL_PD_CK_SEL_B1 BIT(2) + #define SHU1_B1_DLL1_RG_ARDQ_REV_B1 GENMASK(31, 8) +#define SHU1_CA_CMD0 0x00000d00 + #define SHU1_CA_CMD0_RG_TX_ARCLK_PRE_EN BIT(4) + #define SHU1_CA_CMD0_RG_TX_ARCLK_DRVP_PRE GENMASK(10, 8) + #define SHU1_CA_CMD0_RG_TX_ARCLK_DRVP_PRE_BIT2 BIT(10)//[10:10] //Francis added + #define SHU1_CA_CMD0_RG_TX_ARCLK_DRVP_PRE_BIT1 BIT(9)//[9:9] //Francis added + #define SHU1_CA_CMD0_RG_TX_ARCLK_DRVP_PRE_BIT0 BIT(8)//[8:8] //Francis added + #define SHU1_CA_CMD0_RG_TX_ARCLK_DRVN_PRE GENMASK(14, 12) + #define SHU1_CA_CMD0_RG_CGEN_FMEM_CK_CG_DLL BIT(17) + #define SHU1_CA_CMD0_RG_FB_CK_MUX GENMASK(19, 18) + #define SHU1_CA_CMD0_RG_TX_ARCMD_PRE_EN BIT(20) + #define SHU1_CA_CMD0_RG_TX_ARCMD_DRVP_PRE GENMASK(26, 24) + #define SHU1_CA_CMD0_RG_TX_ARCMD_DRVN_PRE GENMASK(30, 28) + #define SHU1_CA_CMD0_R_LP4Y_WDN_MODE_CLK BIT(31) +#define SHU1_CA_CMD1 0x00000d04 + #define SHU1_CA_CMD1_RG_TX_ARCMD_DRVP GENMASK(4, 0) + #define SHU1_CA_CMD1_RG_TX_ARCMD_DRVN GENMASK(12, 8) + #define SHU1_CA_CMD1_RG_TX_ARCMD_ODTP GENMASK(20, 16) + #define SHU1_CA_CMD1_RG_TX_ARCMD_ODTN GENMASK(28, 24) +#define SHU1_CA_CMD2 0x00000d08 + #define SHU1_CA_CMD2_RG_TX_ARCLK_DRVP GENMASK(4, 0) + #define SHU1_CA_CMD2_RG_TX_ARCLK_DRVN GENMASK(12, 8) + #define SHU1_CA_CMD2_RG_TX_ARCLK_ODTP GENMASK(20, 16) + #define SHU1_CA_CMD2_RG_TX_ARCLK_ODTN GENMASK(28, 24) +#define SHU1_CA_CMD3 0x00000d0c + #define SHU1_CA_CMD3_RG_TX_ARCLK_PU GENMASK(1, 0) + #define SHU1_CA_CMD3_RG_TX_ARCLK_PU_PRE GENMASK(3, 2) + #define SHU1_CA_CMD3_RG_TX_ARCLK_PDB GENMASK(5, 4) + #define SHU1_CA_CMD3_RG_TX_ARCLK_PDB_PRE GENMASK(7, 6) + #define SHU1_CA_CMD3_RG_TX_ARCMD_PU GENMASK(9, 8) + #define SHU1_CA_CMD3_RG_TX_ARCMD_PU_BIT1 BIT(9)//[9:9] //Francis added + #define SHU1_CA_CMD3_RG_TX_ARCMD_PU_BIT0 BIT(8)//[8:8] //Francis added + #define SHU1_CA_CMD3_RG_TX_ARCMD_PU_PRE GENMASK(11, 10) + #define SHU1_CA_CMD3_RG_TX_ARCMD_PDB GENMASK(13, 12) + #define SHU1_CA_CMD3_RG_TX_ARCMD_PDB_PRE GENMASK(15, 14) + #define SHU1_CA_CMD3_ARCMD_REV_BIT_06 BIT(22)//[22:22] //Francis added + #define SHU1_CA_CMD3_ARCMD_REV_BIT_05 BIT(21)//[21:21] //Francis added + #define SHU1_CA_CMD3_ARCMD_REV_BIT_04 BIT(20)//[20:20] //Francis added + #define SHU1_CA_CMD3_ARCMD_REV_BIT_03 BIT(19)//[19:19] //Francis added +#define SHU1_CA_CMD4 0x00000d10 + #define SHU1_CA_CMD4_RG_ARPI_AA_MCK_DL_CA GENMASK(5, 0) + #define SHU1_CA_CMD4_RG_ARPI_AA_MCK_FB_DL_CA GENMASK(13, 8) + #define SHU1_CA_CMD4_RG_ARPI_DA_MCK_FB_DL_CA GENMASK(21, 16) +#define SHU1_CA_CMD5 0x00000d14 + #define SHU1_CA_CMD5_RG_RX_ARCMD_VREF_SEL GENMASK(5, 0) + #define SHU1_CA_CMD5_RG_RX_ARCMD_VREF_BYPASS BIT(6) + #define SHU1_CA_CMD5_RG_ARPI_FB_CA GENMASK(13, 8) + #define SHU1_CA_CMD5_RG_RX_ARCLK_DQSIEN_DLY GENMASK(18, 16) + #define SHU1_CA_CMD5_DA_RX_ARCLK_DQSIEN_RB_DLY BIT(19) + #define SHU1_CA_CMD5_RG_RX_ARCLK_DVS_DLY GENMASK(22, 20) + #define SHU1_CA_CMD5_RG_ARPI_MCTL_CA GENMASK(29, 24) +#define SHU1_CA_CMD6 0x00000d18 + #define SHU1_CA_CMD6_RG_ARPI_OFFSET_CLKIEN GENMASK(5, 0) + #define SHU1_CA_CMD6_RG_ARPI_RESERVE_CA GENMASK(21, 6) + #define SHU1_CA_CMD6_RG_ARPI_MIDPI_CAP_SEL_CA GENMASK(23, 22) + #define SHU1_CA_CMD6_RG_ARPI_MIDPI_VTH_SEL_CA GENMASK(25, 24) + #define SHU1_CA_CMD6_RG_ARPI_MIDPI_EN_CA BIT(26) + #define SHU1_CA_CMD6_RG_ARPI_MIDPI_CKDIV4_EN_CA BIT(27) + #define SHU1_CA_CMD6_RG_ARPI_CAP_SEL_CA GENMASK(29, 28) + #define SHU1_CA_CMD6_RG_ARPI_MIDPI_BYPASS_EN_CA BIT(31) +#define SHU1_CA_CMD7 0x00000d1c + #define SHU1_CA_CMD7_R_DMRANKRXDVS_CA GENMASK(3, 0) + #define SHU1_CA_CMD7_R_DMRXDVS_PBYTE_FLAG_OPT_CA BIT(12) + #define SHU1_CA_CMD7_R_DMRODTEN_CA BIT(15) + #define SHU1_CA_CMD7_R_DMARPI_CG_FB2DLL_DCM_EN_CA BIT(16) + #define SHU1_CA_CMD7_R_DMTX_ARPI_CG_CMD_NEW BIT(17) + #define SHU1_CA_CMD7_R_DMTX_ARPI_CG_CLK_NEW BIT(18) + #define SHU1_CA_CMD7_R_DMTX_ARPI_CG_CS_NEW BIT(19) + #define SHU1_CA_CMD7_R_LP4Y_SDN_MODE_CLK BIT(20) + #define SHU1_CA_CMD7_R_DMRXRANK_CMD_EN BIT(24) + #define SHU1_CA_CMD7_R_DMRXRANK_CMD_LAT GENMASK(27, 25) + #define SHU1_CA_CMD7_R_DMRXRANK_CLK_EN BIT(28) + #define SHU1_CA_CMD7_R_DMRXRANK_CLK_LAT GENMASK(31, 29) +#define SHU1_CA_CMD8 0x00000d20 + #define SHU1_CA_CMD8_R_DMRXDVS_UPD_FORCE_CYC_CA GENMASK(14, 0) + #define SHU1_CA_CMD8_R_DMRXDVS_UPD_FORCE_EN_CA BIT(15) + #define SHU1_CA_CMD8_R_DMRANK_RXDLY_PIPE_CG_IG_CA BIT(19) + #define SHU1_CA_CMD8_R_RMRODTEN_CG_IG_CA BIT(20) + #define SHU1_CA_CMD8_R_RMRX_TOPHY_CG_IG_CA BIT(21) + #define SHU1_CA_CMD8_R_DMRXDVS_RDSEL_PIPE_CG_IG_CA BIT(22) + #define SHU1_CA_CMD8_R_DMRXDVS_RDSEL_TOG_PIPE_CG_IG_CA BIT(23) + #define SHU1_CA_CMD8_R_DMRXDLY_CG_IG_CA BIT(24) + #define SHU1_CA_CMD8_R_DMSTBEN_SYNC_CG_IG_CA BIT(25) + #define SHU1_CA_CMD8_R_DMDQSIEN_FLAG_SYNC_CG_IG_CA BIT(26) + #define SHU1_CA_CMD8_R_DMDQSIEN_FLAG_PIPE_CG_IG_CA BIT(27) + #define SHU1_CA_CMD8_R_DMDQSIEN_RDSEL_PIPE_CG_IG_CA BIT(28) + #define SHU1_CA_CMD8_R_DMDQSIEN_RDSEL_TOG_PIPE_CG_IG_CA BIT(29) + #define SHU1_CA_CMD8_R_DMRANK_PIPE_CG_IG_CA BIT(30) + #define SHU1_CA_CMD8_R_DMRANK_CHG_PIPE_CG_IG_CA BIT(31) +#define SHU1_CA_CMD9 0x00000d24 + #define SHU1_CA_CMD9_RESERVED_0XD24 GENMASK(31, 0) +#define SHU1_CA_CMD10 0x00000d28 + #define SHU1_CA_CMD10_RESERVED_0XD28 GENMASK(31, 0) +#define SHU1_CA_CMD11 0x00000d2c + #define SHU1_CA_CMD11_RG_RIMP_REV GENMASK(7, 0) + #define SHU1_CA_CMD11_RG_RIMP_VREF_SEL GENMASK(13, 8) + #define SHU1_CA_CMD11_RG_TX_ARCKE_DRVP GENMASK(21, 17) + #define SHU1_CA_CMD11_RG_TX_ARCKE_DRVN GENMASK(26, 22) +#define SHU1_CA_CMD12 0x00000d30 + #define SHU1_CA_CMD12_RESERVED_0XD30 GENMASK(31, 0) +#define SHU1_CA_DLL0 0x00000d34 + #define SHU1_CA_DLL0_RG_ARPISM_MCK_SEL_CA_SHU BIT(0) + #define SHU1_CA_DLL0_CA_DLL0_RFU BIT(3) + #define SHU1_CA_DLL0_RG_ARDLL_FAST_PSJP_CA BIT(4) + #define SHU1_CA_DLL0_RG_ARDLL_PHDIV_CA BIT(9) + #define SHU1_CA_DLL0_RG_ARDLL_PHJUMP_EN_CA BIT(10) + #define SHU1_CA_DLL0_RG_ARDLL_P_GAIN_CA GENMASK(15, 12) + #define SHU1_CA_DLL0_RG_ARDLL_IDLECNT_CA GENMASK(19, 16) + #define SHU1_CA_DLL0_RG_ARDLL_GAIN_CA GENMASK(23, 20) + #define SHU1_CA_DLL0_RG_ARDLL_PHDET_IN_SWAP_CA BIT(30) + #define SHU1_CA_DLL0_RG_ARDLL_PHDET_OUT_SEL_CA BIT(31) +#define SHU1_CA_DLL1 0x00000d38 + #define SHU1_CA_DLL1_RG_ARDLL_FASTPJ_CK_SEL_CA BIT(0) + #define SHU1_CA_DLL1_RG_ARDLL_PS_EN_CA BIT(1) + #define SHU1_CA_DLL1_RG_ARDLL_PD_CK_SEL_CA BIT(2) + #define SHU1_CA_DLL1_RG_ARCMD_REV GENMASK(31, 8) +#define SHU1_MISC0 0x00000df0 + #define SHU1_MISC0_R_RX_PIPE_BYPASS_EN BIT(1) + #define SHU1_MISC0_RG_CMD_TXPIPE_BYPASS_EN BIT(2) + #define SHU1_MISC0_RG_CK_TXPIPE_BYPASS_EN BIT(3) + #define SHU1_MISC0_RG_RVREF_SEL_DQ GENMASK(21, 16) + #define SHU1_MISC0_RG_RVREF_DDR4_SEL BIT(22) + #define SHU1_MISC0_RG_RVREF_DDR3_SEL BIT(23) + #define SHU1_MISC0_RG_RVREF_SEL_CMD GENMASK(29, 24) +#define SHU1_R0_B0_DQ0 0x00000e00 + #define SHU1_R0_B0_DQ0_RK0_TX_ARDQ0_DLY_B0 GENMASK(3, 0) + #define SHU1_R0_B0_DQ0_RK0_TX_ARDQ1_DLY_B0 GENMASK(7, 4) + #define SHU1_R0_B0_DQ0_RK0_TX_ARDQ2_DLY_B0 GENMASK(11, 8) + #define SHU1_R0_B0_DQ0_RK0_TX_ARDQ3_DLY_B0 GENMASK(15, 12) + #define SHU1_R0_B0_DQ0_RK0_TX_ARDQ4_DLY_B0 GENMASK(19, 16) + #define SHU1_R0_B0_DQ0_RK0_TX_ARDQ5_DLY_B0 GENMASK(23, 20) + #define SHU1_R0_B0_DQ0_RK0_TX_ARDQ6_DLY_B0 GENMASK(27, 24) + #define SHU1_R0_B0_DQ0_RK0_TX_ARDQ7_DLY_B0 GENMASK(31, 28) +#define SHU1_R0_B0_DQ1 0x00000e04 + #define SHU1_R0_B0_DQ1_RK0_TX_ARDQM0_DLY_B0 GENMASK(3, 0) + #define SHU1_R0_B0_DQ1_RK0_TX_ARDQS0_DLYB_B0 GENMASK(19, 16) + #define SHU1_R0_B0_DQ1_RK0_TX_ARDQS0B_DLYB_B0 GENMASK(23, 20) + #define SHU1_R0_B0_DQ1_RK0_TX_ARDQS0_DLY_B0 GENMASK(27, 24) + #define SHU1_R0_B0_DQ1_RK0_TX_ARDQS0B_DLY_B0 GENMASK(31, 28) +#define SHU1_R0_B0_DQ2 0x00000e08 + #define SHU1_R0_B0_DQ2_RK0_RX_ARDQ0_R_DLY_B0 GENMASK(5, 0) + #define SHU1_R0_B0_DQ2_RK0_RX_ARDQ0_F_DLY_B0 GENMASK(13, 8) + #define SHU1_R0_B0_DQ2_RK0_RX_ARDQ1_R_DLY_B0 GENMASK(21, 16) + #define SHU1_R0_B0_DQ2_RK0_RX_ARDQ1_F_DLY_B0 GENMASK(29, 24) +#define SHU1_R0_B0_DQ3 0x00000e0c + #define SHU1_R0_B0_DQ3_RK0_RX_ARDQ2_R_DLY_B0 GENMASK(5, 0) + #define SHU1_R0_B0_DQ3_RK0_RX_ARDQ2_F_DLY_B0 GENMASK(13, 8) + #define SHU1_R0_B0_DQ3_RK0_RX_ARDQ3_R_DLY_B0 GENMASK(21, 16) + #define SHU1_R0_B0_DQ3_RK0_RX_ARDQ3_F_DLY_B0 GENMASK(29, 24) +#define SHU1_R0_B0_DQ4 0x00000e10 + #define SHU1_R0_B0_DQ4_RK0_RX_ARDQ4_R_DLY_B0 GENMASK(5, 0) + #define SHU1_R0_B0_DQ4_RK0_RX_ARDQ4_F_DLY_B0 GENMASK(13, 8) + #define SHU1_R0_B0_DQ4_RK0_RX_ARDQ5_R_DLY_B0 GENMASK(21, 16) + #define SHU1_R0_B0_DQ4_RK0_RX_ARDQ5_F_DLY_B0 GENMASK(29, 24) +#define SHU1_R0_B0_DQ5 0x00000e14 + #define SHU1_R0_B0_DQ5_RK0_RX_ARDQ6_R_DLY_B0 GENMASK(5, 0) + #define SHU1_R0_B0_DQ5_RK0_RX_ARDQ6_F_DLY_B0 GENMASK(13, 8) + #define SHU1_R0_B0_DQ5_RK0_RX_ARDQ7_R_DLY_B0 GENMASK(21, 16) + #define SHU1_R0_B0_DQ5_RK0_RX_ARDQ7_F_DLY_B0 GENMASK(29, 24) +#define SHU1_R0_B0_DQ6 0x00000e18 + #define SHU1_R0_B0_DQ6_RK0_RX_ARDQM0_R_DLY_B0 GENMASK(5, 0) + #define SHU1_R0_B0_DQ6_RK0_RX_ARDQM0_F_DLY_B0 GENMASK(13, 8) + #define SHU1_R0_B0_DQ6_RK0_RX_ARDQS0_R_DLY_B0 GENMASK(22, 16) + #define SHU1_R0_B0_DQ6_RK0_RX_ARDQS0_F_DLY_B0 GENMASK(30, 24) +#define SHU1_R0_B0_DQ7 0x00000e1c + #define SHU1_R0_B0_DQ7_RK0_ARPI_DQ_B0 GENMASK(13, 8) + #define SHU1_R0_B0_DQ7_RK0_ARPI_DQM_B0 GENMASK(21, 16) + #define SHU1_R0_B0_DQ7_RK0_ARPI_PBYTE_B0 GENMASK(29, 24) +#define RFU_0XE20 0x00000e20 + #define RFU_0XE20_RESERVED_0XE20 GENMASK(31, 0) +#define RFU_0XE24 0x00000e24 + #define RFU_0XE24_RESERVED_0XE24 GENMASK(31, 0) +#define RFU_0XE28 0x00000e28 + #define RFU_0XE28_RESERVED_0XE28 GENMASK(31, 0) +#define RFU_0XE2C 0x00000e2c + #define RFU_0XE2C_RESERVED_0XE2C GENMASK(31, 0) +#define SHU1_R0_B1_DQ0 0x00000e50 + #define SHU1_R0_B1_DQ0_RK0_TX_ARDQ0_DLY_B1 GENMASK(3, 0) + #define SHU1_R0_B1_DQ0_RK0_TX_ARDQ1_DLY_B1 GENMASK(7, 4) + #define SHU1_R0_B1_DQ0_RK0_TX_ARDQ2_DLY_B1 GENMASK(11, 8) + #define SHU1_R0_B1_DQ0_RK0_TX_ARDQ3_DLY_B1 GENMASK(15, 12) + #define SHU1_R0_B1_DQ0_RK0_TX_ARDQ4_DLY_B1 GENMASK(19, 16) + #define SHU1_R0_B1_DQ0_RK0_TX_ARDQ5_DLY_B1 GENMASK(23, 20) + #define SHU1_R0_B1_DQ0_RK0_TX_ARDQ6_DLY_B1 GENMASK(27, 24) + #define SHU1_R0_B1_DQ0_RK0_TX_ARDQ7_DLY_B1 GENMASK(31, 28) +#define SHU1_R0_B1_DQ1 0x00000e54 + #define SHU1_R0_B1_DQ1_RK0_TX_ARDQM0_DLY_B1 GENMASK(3, 0) + #define SHU1_R0_B1_DQ1_RK0_TX_ARDQS0_DLYB_B1 GENMASK(19, 16) + #define SHU1_R0_B1_DQ1_RK0_TX_ARDQS0B_DLYB_B1 GENMASK(23, 20) + #define SHU1_R0_B1_DQ1_RK0_TX_ARDQS0_DLY_B1 GENMASK(27, 24) + #define SHU1_R0_B1_DQ1_RK0_TX_ARDQS0B_DLY_B1 GENMASK(31, 28) +#define SHU1_R0_B1_DQ2 0x00000e58 + #define SHU1_R0_B1_DQ2_RK0_RX_ARDQ0_R_DLY_B1 GENMASK(5, 0) + #define SHU1_R0_B1_DQ2_RK0_RX_ARDQ0_F_DLY_B1 GENMASK(13, 8) + #define SHU1_R0_B1_DQ2_RK0_RX_ARDQ1_R_DLY_B1 GENMASK(21, 16) + #define SHU1_R0_B1_DQ2_RK0_RX_ARDQ1_F_DLY_B1 GENMASK(29, 24) +#define SHU1_R0_B1_DQ3 0x00000e5c + #define SHU1_R0_B1_DQ3_RK0_RX_ARDQ2_R_DLY_B1 GENMASK(5, 0) + #define SHU1_R0_B1_DQ3_RK0_RX_ARDQ2_F_DLY_B1 GENMASK(13, 8) + #define SHU1_R0_B1_DQ3_RK0_RX_ARDQ3_R_DLY_B1 GENMASK(21, 16) + #define SHU1_R0_B1_DQ3_RK0_RX_ARDQ3_F_DLY_B1 GENMASK(29, 24) +#define SHU1_R0_B1_DQ4 0x00000e60 + #define SHU1_R0_B1_DQ4_RK0_RX_ARDQ4_R_DLY_B1 GENMASK(5, 0) + #define SHU1_R0_B1_DQ4_RK0_RX_ARDQ4_F_DLY_B1 GENMASK(13, 8) + #define SHU1_R0_B1_DQ4_RK0_RX_ARDQ5_R_DLY_B1 GENMASK(21, 16) + #define SHU1_R0_B1_DQ4_RK0_RX_ARDQ5_F_DLY_B1 GENMASK(29, 24) +#define SHU1_R0_B1_DQ5 0x00000e64 + #define SHU1_R0_B1_DQ5_RK0_RX_ARDQ6_R_DLY_B1 GENMASK(5, 0) + #define SHU1_R0_B1_DQ5_RK0_RX_ARDQ6_F_DLY_B1 GENMASK(13, 8) + #define SHU1_R0_B1_DQ5_RK0_RX_ARDQ7_R_DLY_B1 GENMASK(21, 16) + #define SHU1_R0_B1_DQ5_RK0_RX_ARDQ7_F_DLY_B1 GENMASK(29, 24) +#define SHU1_R0_B1_DQ6 0x00000e68 + #define SHU1_R0_B1_DQ6_RK0_RX_ARDQM0_R_DLY_B1 GENMASK(5, 0) + #define SHU1_R0_B1_DQ6_RK0_RX_ARDQM0_F_DLY_B1 GENMASK(13, 8) + #define SHU1_R0_B1_DQ6_RK0_RX_ARDQS0_R_DLY_B1 GENMASK(22, 16) + #define SHU1_R0_B1_DQ6_RK0_RX_ARDQS0_F_DLY_B1 GENMASK(30, 24) +#define SHU1_R0_B1_DQ7 0x00000e6c + #define SHU1_R0_B1_DQ7_RK0_ARPI_DQ_B1 GENMASK(13, 8) + #define SHU1_R0_B1_DQ7_RK0_ARPI_DQM_B1 GENMASK(21, 16) + #define SHU1_R0_B1_DQ7_RK0_ARPI_PBYTE_B1 GENMASK(29, 24) +#define RFU_0XE70 0x00000e70 + #define RFU_0XE70_RESERVED_0XE70 GENMASK(31, 0) +#define RFU_0XE74 0x00000e74 + #define RFU_0XE74_RESERVED_0XE74 GENMASK(31, 0) +#define RFU_0XE78 0x00000e78 + #define RFU_0XE78_RESERVED_0XE78 GENMASK(31, 0) +#define RFU_0XE7C 0x00000e7c + #define RFU_0XE7C_RESERVED_0XE7C GENMASK(31, 0) +#define SHU1_R0_CA_CMD0 0x00000ea0 + #define SHU1_R0_CA_CMD0_RK0_TX_ARCA0_DLY GENMASK(3, 0) + #define SHU1_R0_CA_CMD0_RK0_TX_ARCA1_DLY GENMASK(7, 4) + #define SHU1_R0_CA_CMD0_RK0_TX_ARCA2_DLY GENMASK(11, 8) + #define SHU1_R0_CA_CMD0_RK0_TX_ARCA3_DLY GENMASK(15, 12) + #define SHU1_R0_CA_CMD0_RK0_TX_ARCA4_DLY GENMASK(19, 16) + #define SHU1_R0_CA_CMD0_RK0_TX_ARCA5_DLY GENMASK(23, 20) + #define SHU1_R0_CA_CMD0_RK0_TX_ARCLK_DLYB GENMASK(27, 24) + #define SHU1_R0_CA_CMD0_RK0_TX_ARCLKB_DLYB GENMASK(31, 28) +#define SHU1_R0_CA_CMD1 0x00000ea4 + #define SHU1_R0_CA_CMD1_RK0_TX_ARCKE0_DLY GENMASK(3, 0) + #define SHU1_R0_CA_CMD1_RK0_TX_ARCKE1_DLY GENMASK(7, 4) + #define SHU1_R0_CA_CMD1_RK0_TX_ARCKE2_DLY GENMASK(11, 8) + #define SHU1_R0_CA_CMD1_RK0_TX_ARCS0_DLY GENMASK(15, 12) + #define SHU1_R0_CA_CMD1_RK0_TX_ARCS1_DLY GENMASK(19, 16) + #define SHU1_R0_CA_CMD1_RK0_TX_ARCS2_DLY GENMASK(23, 20) + #define SHU1_R0_CA_CMD1_RK0_TX_ARCLK_DLY GENMASK(27, 24) + #define SHU1_R0_CA_CMD1_RK0_TX_ARCLKB_DLY GENMASK(31, 28) +#define SHU1_R0_CA_CMD2 0x00000ea8 + #define SHU1_R0_CA_CMD2_RG_RK0_RX_ARCA0_R_DLY GENMASK(5, 0) + #define SHU1_R0_CA_CMD2_RG_RK0_RX_ARCA0_F_DLY GENMASK(13, 8) + #define SHU1_R0_CA_CMD2_RG_RK0_RX_ARCA1_R_DLY GENMASK(21, 16) + #define SHU1_R0_CA_CMD2_RG_RK0_RX_ARCA1_F_DLY GENMASK(29, 24) +#define SHU1_R0_CA_CMD3 0x00000eac + #define SHU1_R0_CA_CMD3_RG_RK0_RX_ARCA2_R_DLY GENMASK(5, 0) + #define SHU1_R0_CA_CMD3_RG_RK0_RX_ARCA2_F_DLY GENMASK(13, 8) + #define SHU1_R0_CA_CMD3_RG_RK0_RX_ARCA3_R_DLY GENMASK(21, 16) + #define SHU1_R0_CA_CMD3_RG_RK0_RX_ARCA3_F_DLY GENMASK(29, 24) +#define SHU1_R0_CA_CMD4 0x00000eb0 + #define SHU1_R0_CA_CMD4_RG_RK0_RX_ARCA4_R_DLY GENMASK(5, 0) + #define SHU1_R0_CA_CMD4_RG_RK0_RX_ARCA4_F_DLY GENMASK(13, 8) + #define SHU1_R0_CA_CMD4_RG_RK0_RX_ARCA5_R_DLY GENMASK(21, 16) + #define SHU1_R0_CA_CMD4_RG_RK0_RX_ARCA5_F_DLY GENMASK(29, 24) +#define SHU1_R0_CA_CMD5 0x00000eb4 + #define SHU1_R0_CA_CMD5_RG_RK0_RX_ARCKE0_R_DLY GENMASK(5, 0) + #define SHU1_R0_CA_CMD5_RG_RK0_RX_ARCKE0_F_DLY GENMASK(13, 8) + #define SHU1_R0_CA_CMD5_RG_RK0_RX_ARCKE1_R_DLY GENMASK(21, 16) + #define SHU1_R0_CA_CMD5_RG_RK0_RX_ARCKE1_F_DLY GENMASK(29, 24) +#define SHU1_R0_CA_CMD6 0x00000eb8 + #define SHU1_R0_CA_CMD6_RG_RK0_RX_ARCKE2_R_DLY GENMASK(5, 0) + #define SHU1_R0_CA_CMD6_RG_RK0_RX_ARCKE2_F_DLY GENMASK(13, 8) + #define SHU1_R0_CA_CMD6_RG_RK0_RX_ARCS0_R_DLY GENMASK(21, 16) + #define SHU1_R0_CA_CMD6_RG_RK0_RX_ARCS0_F_DLY GENMASK(29, 24) +#define SHU1_R0_CA_CMD7 0x00000ebc + #define SHU1_R0_CA_CMD7_RG_RK0_RX_ARCS1_R_DLY GENMASK(5, 0) + #define SHU1_R0_CA_CMD7_RG_RK0_RX_ARCS1_F_DLY GENMASK(13, 8) + #define SHU1_R0_CA_CMD7_RG_RK0_RX_ARCS2_R_DLY GENMASK(21, 16) + #define SHU1_R0_CA_CMD7_RG_RK0_RX_ARCS2_F_DLY GENMASK(29, 24) +#define SHU1_R0_CA_CMD8 0x00000ec0 + #define SHU1_R0_CA_CMD8_RG_RK0_RX_ARCLK_R_DLY GENMASK(22, 16) + #define SHU1_R0_CA_CMD8_RG_RK0_RX_ARCLK_F_DLY GENMASK(30, 24) +#define SHU1_R0_CA_CMD9 0x00000ec4 + #define SHU1_R0_CA_CMD9_RG_RK0_ARPI_CS GENMASK(5, 0) + #define SHU1_R0_CA_CMD9_RG_RK0_ARPI_CMD GENMASK(13, 8) + #define SHU1_R0_CA_CMD9_RG_RK0_ARPI_CLK GENMASK(29, 24) +#define RFU_0XEC8 0x00000ec8 + #define RFU_0XEC8_RESERVED_0XEC8 GENMASK(31, 0) +#define RFU_0XECC 0x00000ecc + #define RFU_0XECC_RESERVED_0XECC GENMASK(31, 0) +#define SHU1_R1_B0_DQ0 0x00000f00 + #define SHU1_R1_B0_DQ0_RK1_TX_ARDQ0_DLY_B0 GENMASK(3, 0) + #define SHU1_R1_B0_DQ0_RK1_TX_ARDQ1_DLY_B0 GENMASK(7, 4) + #define SHU1_R1_B0_DQ0_RK1_TX_ARDQ2_DLY_B0 GENMASK(11, 8) + #define SHU1_R1_B0_DQ0_RK1_TX_ARDQ3_DLY_B0 GENMASK(15, 12) + #define SHU1_R1_B0_DQ0_RK1_TX_ARDQ4_DLY_B0 GENMASK(19, 16) + #define SHU1_R1_B0_DQ0_RK1_TX_ARDQ5_DLY_B0 GENMASK(23, 20) + #define SHU1_R1_B0_DQ0_RK1_TX_ARDQ6_DLY_B0 GENMASK(27, 24) + #define SHU1_R1_B0_DQ0_RK1_TX_ARDQ7_DLY_B0 GENMASK(31, 28) +#define SHU1_R1_B0_DQ1 0x00000f04 + #define SHU1_R1_B0_DQ1_RK1_TX_ARDQM0_DLY_B0 GENMASK(3, 0) + #define SHU1_R1_B0_DQ1_RK1_TX_ARDQS0_DLYB_B0 GENMASK(19, 16) + #define SHU1_R1_B0_DQ1_RK1_TX_ARDQS0B_DLYB_B0 GENMASK(23, 20) + #define SHU1_R1_B0_DQ1_RK1_TX_ARDQS0_DLY_B0 GENMASK(27, 24) + #define SHU1_R1_B0_DQ1_RK1_TX_ARDQS0B_DLY_B0 GENMASK(31, 28) +#define SHU1_R1_B0_DQ2 0x00000f08 + #define SHU1_R1_B0_DQ2_RK1_RX_ARDQ0_R_DLY_B0 GENMASK(5, 0) + #define SHU1_R1_B0_DQ2_RK1_RX_ARDQ0_F_DLY_B0 GENMASK(13, 8) + #define SHU1_R1_B0_DQ2_RK1_RX_ARDQ1_R_DLY_B0 GENMASK(21, 16) + #define SHU1_R1_B0_DQ2_RK1_RX_ARDQ1_F_DLY_B0 GENMASK(29, 24) +#define SHU1_R1_B0_DQ3 0x00000f0c + #define SHU1_R1_B0_DQ3_RK1_RX_ARDQ2_R_DLY_B0 GENMASK(5, 0) + #define SHU1_R1_B0_DQ3_RK1_RX_ARDQ2_F_DLY_B0 GENMASK(13, 8) + #define SHU1_R1_B0_DQ3_RK1_RX_ARDQ3_R_DLY_B0 GENMASK(21, 16) + #define SHU1_R1_B0_DQ3_RK1_RX_ARDQ3_F_DLY_B0 GENMASK(29, 24) +#define SHU1_R1_B0_DQ4 0x00000f10 + #define SHU1_R1_B0_DQ4_RK1_RX_ARDQ4_R_DLY_B0 GENMASK(5, 0) + #define SHU1_R1_B0_DQ4_RK1_RX_ARDQ4_F_DLY_B0 GENMASK(13, 8) + #define SHU1_R1_B0_DQ4_RK1_RX_ARDQ5_R_DLY_B0 GENMASK(21, 16) + #define SHU1_R1_B0_DQ4_RK1_RX_ARDQ5_F_DLY_B0 GENMASK(29, 24) +#define SHU1_R1_B0_DQ5 0x00000f14 + #define SHU1_R1_B0_DQ5_RK1_RX_ARDQ6_R_DLY_B0 GENMASK(5, 0) + #define SHU1_R1_B0_DQ5_RK1_RX_ARDQ6_F_DLY_B0 GENMASK(13, 8) + #define SHU1_R1_B0_DQ5_RK1_RX_ARDQ7_R_DLY_B0 GENMASK(21, 16) + #define SHU1_R1_B0_DQ5_RK1_RX_ARDQ7_F_DLY_B0 GENMASK(29, 24) +#define SHU1_R1_B0_DQ6 0x00000f18 + #define SHU1_R1_B0_DQ6_RK1_RX_ARDQM0_R_DLY_B0 GENMASK(5, 0) + #define SHU1_R1_B0_DQ6_RK1_RX_ARDQM0_F_DLY_B0 GENMASK(13, 8) + #define SHU1_R1_B0_DQ6_RK1_RX_ARDQS0_R_DLY_B0 GENMASK(22, 16) + #define SHU1_R1_B0_DQ6_RK1_RX_ARDQS0_F_DLY_B0 GENMASK(30, 24) +#define SHU1_R1_B0_DQ7 0x00000f1c + #define SHU1_R1_B0_DQ7_RK1_ARPI_DQ_B0 GENMASK(13, 8) + #define SHU1_R1_B0_DQ7_RK1_ARPI_DQM_B0 GENMASK(21, 16) + #define SHU1_R1_B0_DQ7_RK1_ARPI_PBYTE_B0 GENMASK(29, 24) +#define RFU_0XF20 0x00000f20 + #define RFU_0XF20_RESERVED_0XF20 GENMASK(31, 0) +#define RFU_0XF24 0x00000f24 + #define RFU_0XF24_RESERVED_0XF24 GENMASK(31, 0) +#define RFU_0XF28 0x00000f28 + #define RFU_0XF28_RESERVED_0XF28 GENMASK(31, 0) +#define RFU_0XF2C 0x00000f2c + #define RFU_0XF2C_RESERVED_0XF2C GENMASK(31, 0) +#define SHU1_R1_B1_DQ0 0x00000f50 + #define SHU1_R1_B1_DQ0_RK1_TX_ARDQ0_DLY_B1 GENMASK(3, 0) + #define SHU1_R1_B1_DQ0_RK1_TX_ARDQ1_DLY_B1 GENMASK(7, 4) + #define SHU1_R1_B1_DQ0_RK1_TX_ARDQ2_DLY_B1 GENMASK(11, 8) + #define SHU1_R1_B1_DQ0_RK1_TX_ARDQ3_DLY_B1 GENMASK(15, 12) + #define SHU1_R1_B1_DQ0_RK1_TX_ARDQ4_DLY_B1 GENMASK(19, 16) + #define SHU1_R1_B1_DQ0_RK1_TX_ARDQ5_DLY_B1 GENMASK(23, 20) + #define SHU1_R1_B1_DQ0_RK1_TX_ARDQ6_DLY_B1 GENMASK(27, 24) + #define SHU1_R1_B1_DQ0_RK1_TX_ARDQ7_DLY_B1 GENMASK(31, 28) +#define SHU1_R1_B1_DQ1 0x00000f54 + #define SHU1_R1_B1_DQ1_RK1_TX_ARDQM0_DLY_B1 GENMASK(3, 0) + #define SHU1_R1_B1_DQ1_RK1_TX_ARDQS0_DLYB_B1 GENMASK(19, 16) + #define SHU1_R1_B1_DQ1_RK1_TX_ARDQS0B_DLYB_B1 GENMASK(23, 20) + #define SHU1_R1_B1_DQ1_RK1_TX_ARDQS0_DLY_B1 GENMASK(27, 24) + #define SHU1_R1_B1_DQ1_RK1_TX_ARDQS0B_DLY_B1 GENMASK(31, 28) +#define SHU1_R1_B1_DQ2 0x00000f58 + #define SHU1_R1_B1_DQ2_RK1_RX_ARDQ0_R_DLY_B1 GENMASK(5, 0) + #define SHU1_R1_B1_DQ2_RK1_RX_ARDQ0_F_DLY_B1 GENMASK(13, 8) + #define SHU1_R1_B1_DQ2_RK1_RX_ARDQ1_R_DLY_B1 GENMASK(21, 16) + #define SHU1_R1_B1_DQ2_RK1_RX_ARDQ1_F_DLY_B1 GENMASK(29, 24) +#define SHU1_R1_B1_DQ3 0x00000f5c + #define SHU1_R1_B1_DQ3_RK1_RX_ARDQ2_R_DLY_B1 GENMASK(5, 0) + #define SHU1_R1_B1_DQ3_RK1_RX_ARDQ2_F_DLY_B1 GENMASK(13, 8) + #define SHU1_R1_B1_DQ3_RK1_RX_ARDQ3_R_DLY_B1 GENMASK(21, 16) + #define SHU1_R1_B1_DQ3_RK1_RX_ARDQ3_F_DLY_B1 GENMASK(29, 24) +#define SHU1_R1_B1_DQ4 0x00000f60 + #define SHU1_R1_B1_DQ4_RK1_RX_ARDQ4_R_DLY_B1 GENMASK(5, 0) + #define SHU1_R1_B1_DQ4_RK1_RX_ARDQ4_F_DLY_B1 GENMASK(13, 8) + #define SHU1_R1_B1_DQ4_RK1_RX_ARDQ5_R_DLY_B1 GENMASK(21, 16) + #define SHU1_R1_B1_DQ4_RK1_RX_ARDQ5_F_DLY_B1 GENMASK(29, 24) +#define SHU1_R1_B1_DQ5 0x00000f64 + #define SHU1_R1_B1_DQ5_RK1_RX_ARDQ6_R_DLY_B1 GENMASK(5, 0) + #define SHU1_R1_B1_DQ5_RK1_RX_ARDQ6_F_DLY_B1 GENMASK(13, 8) + #define SHU1_R1_B1_DQ5_RK1_RX_ARDQ7_R_DLY_B1 GENMASK(21, 16) + #define SHU1_R1_B1_DQ5_RK1_RX_ARDQ7_F_DLY_B1 GENMASK(29, 24) +#define SHU1_R1_B1_DQ6 0x00000f68 + #define SHU1_R1_B1_DQ6_RK1_RX_ARDQM0_R_DLY_B1 GENMASK(5, 0) + #define SHU1_R1_B1_DQ6_RK1_RX_ARDQM0_F_DLY_B1 GENMASK(13, 8) + #define SHU1_R1_B1_DQ6_RK1_RX_ARDQS0_R_DLY_B1 GENMASK(22, 16) + #define SHU1_R1_B1_DQ6_RK1_RX_ARDQS0_F_DLY_B1 GENMASK(30, 24) +#define SHU1_R1_B1_DQ7 0x00000f6c + #define SHU1_R1_B1_DQ7_RK1_ARPI_DQ_B1 GENMASK(13, 8) + #define SHU1_R1_B1_DQ7_RK1_ARPI_DQM_B1 GENMASK(21, 16) + #define SHU1_R1_B1_DQ7_RK1_ARPI_PBYTE_B1 GENMASK(29, 24) +#define RFU_0XF70 0x00000f70 + #define RFU_0XF70_RESERVED_0XF70 GENMASK(31, 0) +#define RFU_0XF74 0x00000f74 + #define RFU_0XF74_RESERVED_0XF74 GENMASK(31, 0) +#define RFU_0XF78 0x00000f78 + #define RFU_0XF78_RESERVED_0XF78 GENMASK(31, 0) +#define RFU_0XF7C 0x00000f7c + #define RFU_0XF7C_RESERVED_0XF7C GENMASK(31, 0) +#define SHU1_R1_CA_CMD0 0x00000fa0 + #define SHU1_R1_CA_CMD0_RK1_TX_ARCA0_DLY GENMASK(3, 0) + #define SHU1_R1_CA_CMD0_RK1_TX_ARCA1_DLY GENMASK(7, 4) + #define SHU1_R1_CA_CMD0_RK1_TX_ARCA2_DLY GENMASK(11, 8) + #define SHU1_R1_CA_CMD0_RK1_TX_ARCA3_DLY GENMASK(15, 12) + #define SHU1_R1_CA_CMD0_RK1_TX_ARCA4_DLY GENMASK(19, 16) + #define SHU1_R1_CA_CMD0_RK1_TX_ARCA5_DLY GENMASK(23, 20) + #define SHU1_R1_CA_CMD0_RK1_TX_ARCLK_DLYB GENMASK(27, 24) + #define SHU1_R1_CA_CMD0_RK1_TX_ARCLKB_DLYB GENMASK(31, 28) +#define SHU1_R1_CA_CMD1 0x00000fa4 + #define SHU1_R1_CA_CMD1_RK1_TX_ARCKE0_DLY GENMASK(3, 0) + #define SHU1_R1_CA_CMD1_RK1_TX_ARCKE1_DLY GENMASK(7, 4) + #define SHU1_R1_CA_CMD1_RK1_TX_ARCKE2_DLY GENMASK(11, 8) + #define SHU1_R1_CA_CMD1_RK1_TX_ARCS0_DLY GENMASK(15, 12) + #define SHU1_R1_CA_CMD1_RK1_TX_ARCS1_DLY GENMASK(19, 16) + #define SHU1_R1_CA_CMD1_RK1_TX_ARCS2_DLY GENMASK(23, 20) + #define SHU1_R1_CA_CMD1_RK1_TX_ARCLK_DLY GENMASK(27, 24) + #define SHU1_R1_CA_CMD1_RK1_TX_ARCLKB_DLY GENMASK(31, 28) +#define SHU1_R1_CA_CMD2 0x00000fa8 + #define SHU1_R1_CA_CMD2_RG_RK1_RX_ARCA0_R_DLY GENMASK(5, 0) + #define SHU1_R1_CA_CMD2_RG_RK1_RX_ARCA0_F_DLY GENMASK(13, 8) + #define SHU1_R1_CA_CMD2_RG_RK1_RX_ARCA1_R_DLY GENMASK(21, 16) + #define SHU1_R1_CA_CMD2_RG_RK1_RX_ARCA1_F_DLY GENMASK(29, 24) +#define SHU1_R1_CA_CMD3 0x00000fac + #define SHU1_R1_CA_CMD3_RG_RK1_RX_ARCA2_R_DLY GENMASK(5, 0) + #define SHU1_R1_CA_CMD3_RG_RK1_RX_ARCA2_F_DLY GENMASK(13, 8) + #define SHU1_R1_CA_CMD3_RG_RK1_RX_ARCA3_R_DLY GENMASK(21, 16) + #define SHU1_R1_CA_CMD3_RG_RK1_RX_ARCA3_F_DLY GENMASK(29, 24) +#define SHU1_R1_CA_CMD4 0x00000fb0 + #define SHU1_R1_CA_CMD4_RG_RK1_RX_ARCA4_R_DLY GENMASK(5, 0) + #define SHU1_R1_CA_CMD4_RG_RK1_RX_ARCA4_F_DLY GENMASK(13, 8) + #define SHU1_R1_CA_CMD4_RG_RK1_RX_ARCA5_R_DLY GENMASK(21, 16) + #define SHU1_R1_CA_CMD4_RG_RK1_RX_ARCA5_F_DLY GENMASK(29, 24) +#define SHU1_R1_CA_CMD5 0x00000fb4 + #define SHU1_R1_CA_CMD5_RG_RK1_RX_ARCKE0_R_DLY GENMASK(5, 0) + #define SHU1_R1_CA_CMD5_RG_RK1_RX_ARCKE0_F_DLY GENMASK(13, 8) + #define SHU1_R1_CA_CMD5_RG_RK1_RX_ARCKE1_R_DLY GENMASK(21, 16) + #define SHU1_R1_CA_CMD5_RG_RK1_RX_ARCKE1_F_DLY GENMASK(29, 24) +#define SHU1_R1_CA_CMD6 0x00000fb8 + #define SHU1_R1_CA_CMD6_RG_RK1_RX_ARCKE2_R_DLY GENMASK(5, 0) + #define SHU1_R1_CA_CMD6_RG_RK1_RX_ARCKE2_F_DLY GENMASK(13, 8) + #define SHU1_R1_CA_CMD6_RG_RK1_RX_ARCS0_R_DLY GENMASK(21, 16) + #define SHU1_R1_CA_CMD6_RG_RK1_RX_ARCS0_F_DLY GENMASK(29, 24) +#define SHU1_R1_CA_CMD7 0x00000fbc + #define SHU1_R1_CA_CMD7_RG_RK1_RX_ARCS1_R_DLY GENMASK(5, 0) + #define SHU1_R1_CA_CMD7_RG_RK1_RX_ARCS1_F_DLY GENMASK(13, 8) + #define SHU1_R1_CA_CMD7_RG_RK1_RX_ARCS2_R_DLY GENMASK(21, 16) + #define SHU1_R1_CA_CMD7_RG_RK1_RX_ARCS2_F_DLY GENMASK(29, 24) +#define SHU1_R1_CA_CMD8 0x00000fc0 + #define SHU1_R1_CA_CMD8_RG_RK1_RX_ARCLK_R_DLY GENMASK(22, 16) + #define SHU1_R1_CA_CMD8_RG_RK1_RX_ARCLK_F_DLY GENMASK(30, 24) +#define SHU1_R1_CA_CMD9 0x00000fc4 + #define SHU1_R1_CA_CMD9_RG_RK1_ARPI_CS GENMASK(5, 0) + #define SHU1_R1_CA_CMD9_RG_RK1_ARPI_CMD GENMASK(13, 8) + #define SHU1_R1_CA_CMD9_RG_RK1_ARPI_CLK GENMASK(29, 24) +#define RFU_0XFC8 0x00000fc8 + #define RFU_0XFC8_RESERVED_0XFC8 GENMASK(31, 0) +#define RFU_0XFCC 0x00000fcc + #define RFU_0XFCC_RESERVED_0XFCC GENMASK(31, 0) +#define SHU1_R2_B0_DQ0 0x00001000 + #define SHU1_R2_B0_DQ0_RK2_TX_ARDQ0_DLY_B0 GENMASK(3, 0) + #define SHU1_R2_B0_DQ0_RK2_TX_ARDQ1_DLY_B0 GENMASK(7, 4) + #define SHU1_R2_B0_DQ0_RK2_TX_ARDQ2_DLY_B0 GENMASK(11, 8) + #define SHU1_R2_B0_DQ0_RK2_TX_ARDQ3_DLY_B0 GENMASK(15, 12) + #define SHU1_R2_B0_DQ0_RK2_TX_ARDQ4_DLY_B0 GENMASK(19, 16) + #define SHU1_R2_B0_DQ0_RK2_TX_ARDQ5_DLY_B0 GENMASK(23, 20) + #define SHU1_R2_B0_DQ0_RK2_TX_ARDQ6_DLY_B0 GENMASK(27, 24) + #define SHU1_R2_B0_DQ0_RK2_TX_ARDQ7_DLY_B0 GENMASK(31, 28) +#define SHU1_R2_B0_DQ1 0x00001004 + #define SHU1_R2_B0_DQ1_RK2_TX_ARDQM0_DLY_B0 GENMASK(3, 0) + #define SHU1_R2_B0_DQ1_RK2_TX_ARDQS0_DLYB_B0 GENMASK(19, 16) + #define SHU1_R2_B0_DQ1_RK2_TX_ARDQS0B_DLYB_B0 GENMASK(23, 20) + #define SHU1_R2_B0_DQ1_RK2_TX_ARDQS0_DLY_B0 GENMASK(27, 24) + #define SHU1_R2_B0_DQ1_RK2_TX_ARDQS0B_DLY_B0 GENMASK(31, 28) +#define SHU1_R2_B0_DQ2 0x00001008 + #define SHU1_R2_B0_DQ2_RK2_RX_ARDQ0_R_DLY_B0 GENMASK(5, 0) + #define SHU1_R2_B0_DQ2_RK2_RX_ARDQ0_F_DLY_B0 GENMASK(13, 8) + #define SHU1_R2_B0_DQ2_RK2_RX_ARDQ1_R_DLY_B0 GENMASK(21, 16) + #define SHU1_R2_B0_DQ2_RK2_RX_ARDQ1_F_DLY_B0 GENMASK(29, 24) +#define SHU1_R2_B0_DQ3 0x0000100c + #define SHU1_R2_B0_DQ3_RK2_RX_ARDQ2_R_DLY_B0 GENMASK(5, 0) + #define SHU1_R2_B0_DQ3_RK2_RX_ARDQ2_F_DLY_B0 GENMASK(13, 8) + #define SHU1_R2_B0_DQ3_RK2_RX_ARDQ3_R_DLY_B0 GENMASK(21, 16) + #define SHU1_R2_B0_DQ3_RK2_RX_ARDQ3_F_DLY_B0 GENMASK(29, 24) +#define SHU1_R2_B0_DQ4 0x00001010 + #define SHU1_R2_B0_DQ4_RK2_RX_ARDQ4_R_DLY_B0 GENMASK(5, 0) + #define SHU1_R2_B0_DQ4_RK2_RX_ARDQ4_F_DLY_B0 GENMASK(13, 8) + #define SHU1_R2_B0_DQ4_RK2_RX_ARDQ5_R_DLY_B0 GENMASK(21, 16) + #define SHU1_R2_B0_DQ4_RK2_RX_ARDQ5_F_DLY_B0 GENMASK(29, 24) +#define SHU1_R2_B0_DQ5 0x00001014 + #define SHU1_R2_B0_DQ5_RK2_RX_ARDQ6_R_DLY_B0 GENMASK(5, 0) + #define SHU1_R2_B0_DQ5_RK2_RX_ARDQ6_F_DLY_B0 GENMASK(13, 8) + #define SHU1_R2_B0_DQ5_RK2_RX_ARDQ7_R_DLY_B0 GENMASK(21, 16) + #define SHU1_R2_B0_DQ5_RK2_RX_ARDQ7_F_DLY_B0 GENMASK(29, 24) +#define SHU1_R2_B0_DQ6 0x00001018 + #define SHU1_R2_B0_DQ6_RK2_RX_ARDQM0_R_DLY_B0 GENMASK(5, 0) + #define SHU1_R2_B0_DQ6_RK2_RX_ARDQM0_F_DLY_B0 GENMASK(13, 8) + #define SHU1_R2_B0_DQ6_RK2_RX_ARDQS0_R_DLY_B0 GENMASK(22, 16) + #define SHU1_R2_B0_DQ6_RK2_RX_ARDQS0_F_DLY_B0 GENMASK(30, 24) +#define SHU1_R2_B0_DQ7 0x0000101c + #define SHU1_R2_B0_DQ7_RK2_ARPI_DQ_B0 GENMASK(13, 8) + #define SHU1_R2_B0_DQ7_RK2_ARPI_DQM_B0 GENMASK(21, 16) + #define SHU1_R2_B0_DQ7_RK2_ARPI_PBYTE_B0 GENMASK(29, 24) +#define RFU_0X1020 0x00001020 + #define RFU_0X1020_RESERVED_0X1020 GENMASK(31, 0) +#define RFU_0X1024 0x00001024 + #define RFU_0X1024_RESERVED_0X1024 GENMASK(31, 0) +#define RFU_0X1028 0x00001028 + #define RFU_0X1028_RESERVED_0X1028 GENMASK(31, 0) +#define RFU_0X102C 0x0000102c + #define RFU_0X102C_RESERVED_0X102C GENMASK(31, 0) +#define SHU1_R2_B1_DQ0 0x00001050 + #define SHU1_R2_B1_DQ0_RK2_TX_ARDQ0_DLY_B1 GENMASK(3, 0) + #define SHU1_R2_B1_DQ0_RK2_TX_ARDQ1_DLY_B1 GENMASK(7, 4) + #define SHU1_R2_B1_DQ0_RK2_TX_ARDQ2_DLY_B1 GENMASK(11, 8) + #define SHU1_R2_B1_DQ0_RK2_TX_ARDQ3_DLY_B1 GENMASK(15, 12) + #define SHU1_R2_B1_DQ0_RK2_TX_ARDQ4_DLY_B1 GENMASK(19, 16) + #define SHU1_R2_B1_DQ0_RK2_TX_ARDQ5_DLY_B1 GENMASK(23, 20) + #define SHU1_R2_B1_DQ0_RK2_TX_ARDQ6_DLY_B1 GENMASK(27, 24) + #define SHU1_R2_B1_DQ0_RK2_TX_ARDQ7_DLY_B1 GENMASK(31, 28) +#define SHU1_R2_B1_DQ1 0x00001054 + #define SHU1_R2_B1_DQ1_RK2_TX_ARDQM0_DLY_B1 GENMASK(3, 0) + #define SHU1_R2_B1_DQ1_RK2_TX_ARDQS0_DLY_B1 GENMASK(27, 24) + #define SHU1_R2_B1_DQ1_RK2_TX_ARDQS0B_DLY_B1 GENMASK(31, 28) +#define SHU1_R2_B1_DQ2 0x00001058 + #define SHU1_R2_B1_DQ2_RK2_RX_ARDQ0_R_DLY_B1 GENMASK(5, 0) + #define SHU1_R2_B1_DQ2_RK2_RX_ARDQ0_F_DLY_B1 GENMASK(13, 8) + #define SHU1_R2_B1_DQ2_RK2_RX_ARDQ1_R_DLY_B1 GENMASK(21, 16) + #define SHU1_R2_B1_DQ2_RK2_RX_ARDQ1_F_DLY_B1 GENMASK(29, 24) +#define SHU1_R2_B1_DQ3 0x0000105c + #define SHU1_R2_B1_DQ3_RK2_RX_ARDQ2_R_DLY_B1 GENMASK(5, 0) + #define SHU1_R2_B1_DQ3_RK2_RX_ARDQ2_F_DLY_B1 GENMASK(13, 8) + #define SHU1_R2_B1_DQ3_RK2_RX_ARDQ3_R_DLY_B1 GENMASK(21, 16) + #define SHU1_R2_B1_DQ3_RK2_RX_ARDQ3_F_DLY_B1 GENMASK(29, 24) +#define SHU1_R2_B1_DQ4 0x00001060 + #define SHU1_R2_B1_DQ4_RK2_RX_ARDQ4_R_DLY_B1 GENMASK(5, 0) + #define SHU1_R2_B1_DQ4_RK2_RX_ARDQ4_F_DLY_B1 GENMASK(13, 8) + #define SHU1_R2_B1_DQ4_RK2_RX_ARDQ5_R_DLY_B1 GENMASK(21, 16) + #define SHU1_R2_B1_DQ4_RK2_RX_ARDQ5_F_DLY_B1 GENMASK(29, 24) +#define SHU1_R2_B1_DQ5 0x00001064 + #define SHU1_R2_B1_DQ5_RK2_RX_ARDQ6_R_DLY_B1 GENMASK(5, 0) + #define SHU1_R2_B1_DQ5_RK2_RX_ARDQ6_F_DLY_B1 GENMASK(13, 8) + #define SHU1_R2_B1_DQ5_RK2_RX_ARDQ7_R_DLY_B1 GENMASK(21, 16) + #define SHU1_R2_B1_DQ5_RK2_RX_ARDQ7_F_DLY_B1 GENMASK(29, 24) +#define SHU1_R2_B1_DQ6 0x00001068 + #define SHU1_R2_B1_DQ6_RK2_RX_ARDQM0_R_DLY_B1 GENMASK(5, 0) + #define SHU1_R2_B1_DQ6_RK2_RX_ARDQM0_F_DLY_B1 GENMASK(13, 8) + #define SHU1_R2_B1_DQ6_RK2_RX_ARDQS0_R_DLY_B1 GENMASK(22, 16) + #define SHU1_R2_B1_DQ6_RK2_RX_ARDQS0_F_DLY_B1 GENMASK(30, 24) +#define SHU1_R2_B1_DQ7 0x0000106c + #define SHU1_R2_B1_DQ7_RK2_ARPI_DQ_B1 GENMASK(13, 8) + #define SHU1_R2_B1_DQ7_RK2_ARPI_DQM_B1 GENMASK(21, 16) + #define SHU1_R2_B1_DQ7_RK2_ARPI_PBYTE_B1 GENMASK(29, 24) +#define RFU_0X1070 0x00001070 + #define RFU_0X1070_RESERVED_0X1070 GENMASK(31, 0) +#define RFU_0X1074 0x00001074 + #define RFU_0X1074_RESERVED_0X1074 GENMASK(31, 0) +#define RFU_0X1078 0x00001078 + #define RFU_0X1078_RESERVED_0X1078 GENMASK(31, 0) +#define RFU_0X107C 0x0000107c + #define RFU_0X107C_RESERVED_0X107C GENMASK(31, 0) +#define SHU1_R2_CA_CMD0 0x000010a0 + #define SHU1_R2_CA_CMD0_RK2_TX_ARCA0_DLY GENMASK(3, 0) + #define SHU1_R2_CA_CMD0_RK2_TX_ARCA1_DLY GENMASK(7, 4) + #define SHU1_R2_CA_CMD0_RK2_TX_ARCA2_DLY GENMASK(11, 8) + #define SHU1_R2_CA_CMD0_RK2_TX_ARCA3_DLY GENMASK(15, 12) + #define SHU1_R2_CA_CMD0_RK2_TX_ARCA4_DLY GENMASK(19, 16) + #define SHU1_R2_CA_CMD0_RK2_TX_ARCA5_DLY GENMASK(23, 20) + #define SHU1_R2_CA_CMD0_RK2_TX_ARCLK_DLYB GENMASK(27, 24) + #define SHU1_R2_CA_CMD0_RK2_TX_ARCLKB_DLYB GENMASK(31, 28) +#define SHU1_R2_CA_CMD1 0x000010a4 + #define SHU1_R2_CA_CMD1_RK2_TX_ARCKE0_DLY GENMASK(3, 0) + #define SHU1_R2_CA_CMD1_RK2_TX_ARCKE1_DLY GENMASK(7, 4) + #define SHU1_R2_CA_CMD1_RK2_TX_ARCKE2_DLY GENMASK(11, 8) + #define SHU1_R2_CA_CMD1_RK2_TX_ARCS0_DLY GENMASK(15, 12) + #define SHU1_R2_CA_CMD1_RK2_TX_ARCS1_DLY GENMASK(19, 16) + #define SHU1_R2_CA_CMD1_RK2_TX_ARCS2_DLY GENMASK(23, 20) + #define SHU1_R2_CA_CMD1_RK2_TX_ARCLK_DLY GENMASK(27, 24) + #define SHU1_R2_CA_CMD1_RK2_TX_ARCLKB_DLY GENMASK(31, 28) +#define SHU1_R2_CA_CMD2 0x000010a8 + #define SHU1_R2_CA_CMD2_RG_RK2_RX_ARCA0_R_DLY GENMASK(5, 0) + #define SHU1_R2_CA_CMD2_RG_RK2_RX_ARCA0_F_DLY GENMASK(13, 8) + #define SHU1_R2_CA_CMD2_RG_RK2_RX_ARCA1_R_DLY GENMASK(21, 16) + #define SHU1_R2_CA_CMD2_RG_RK2_RX_ARCA1_F_DLY GENMASK(29, 24) +#define SHU1_R2_CA_CMD3 0x000010ac + #define SHU1_R2_CA_CMD3_RG_RK2_RX_ARCA2_R_DLY GENMASK(5, 0) + #define SHU1_R2_CA_CMD3_RG_RK2_RX_ARCA2_F_DLY GENMASK(13, 8) + #define SHU1_R2_CA_CMD3_RG_RK2_RX_ARCA3_R_DLY GENMASK(21, 16) + #define SHU1_R2_CA_CMD3_RG_RK2_RX_ARCA3_F_DLY GENMASK(29, 24) +#define SHU1_R2_CA_CMD4 0x000010b0 + #define SHU1_R2_CA_CMD4_RG_RK2_RX_ARCA4_R_DLY GENMASK(5, 0) + #define SHU1_R2_CA_CMD4_RG_RK2_RX_ARCA4_F_DLY GENMASK(13, 8) + #define SHU1_R2_CA_CMD4_RG_RK2_RX_ARCA5_R_DLY GENMASK(21, 16) + #define SHU1_R2_CA_CMD4_RG_RK2_RX_ARCA5_F_DLY GENMASK(29, 24) +#define SHU1_R2_CA_CMD5 0x000010b4 + #define SHU1_R2_CA_CMD5_RG_RK2_RX_ARCKE0_R_DLY GENMASK(5, 0) + #define SHU1_R2_CA_CMD5_RG_RK2_RX_ARCKE0_F_DLY GENMASK(13, 8) + #define SHU1_R2_CA_CMD5_RG_RK2_RX_ARCKE1_R_DLY GENMASK(21, 16) + #define SHU1_R2_CA_CMD5_RG_RK2_RX_ARCKE1_F_DLY GENMASK(29, 24) +#define SHU1_R2_CA_CMD6 0x000010b8 + #define SHU1_R2_CA_CMD6_RG_RK2_RX_ARCKE2_R_DLY GENMASK(5, 0) + #define SHU1_R2_CA_CMD6_RG_RK2_RX_ARCKE2_F_DLY GENMASK(13, 8) + #define SHU1_R2_CA_CMD6_RG_RK2_RX_ARCS0_R_DLY GENMASK(21, 16) + #define SHU1_R2_CA_CMD6_RG_RK2_RX_ARCS0_F_DLY GENMASK(29, 24) +#define SHU1_R2_CA_CMD7 0x000010bc + #define SHU1_R2_CA_CMD7_RG_RK2_RX_ARCS1_R_DLY GENMASK(5, 0) + #define SHU1_R2_CA_CMD7_RG_RK2_RX_ARCS1_F_DLY GENMASK(13, 8) + #define SHU1_R2_CA_CMD7_RG_RK2_RX_ARCS2_R_DLY GENMASK(21, 16) + #define SHU1_R2_CA_CMD7_RG_RK2_RX_ARCS2_F_DLY GENMASK(29, 24) +#define SHU1_R2_CA_CMD8 0x000010c0 + #define SHU1_R2_CA_CMD8_RG_RK2_RX_ARCLK_R_DLY GENMASK(22, 16) + #define SHU1_R2_CA_CMD8_RG_RK2_RX_ARCLK_F_DLY GENMASK(30, 24) +#define SHU1_R2_CA_CMD9 0x000010c4 + #define SHU1_R2_CA_CMD9_RG_RK2_ARPI_CS GENMASK(5, 0) + #define SHU1_R2_CA_CMD9_RG_RK2_ARPI_CMD GENMASK(13, 8) + #define SHU1_R2_CA_CMD9_RG_RK2_ARPI_CLK GENMASK(29, 24) +#define RFU_0X10C8 0x000010c8 + #define RFU_0X10C8_RESERVED_0X10C8 GENMASK(31, 0) +#define RFU_0X10CC 0x000010cc + #define RFU_0X10CC_RESERVED_0X10CC GENMASK(31, 0) +#define SHU2_B0_DQ0 0x00001100 + #define SHU2_B0_DQ0_RG_TX_ARDQS0_PRE_EN_B0 BIT(4) + #define SHU2_B0_DQ0_RG_TX_ARDQS0_DRVP_PRE_B0 GENMASK(10, 8) + #define SHU2_B0_DQ0_RG_TX_ARDQS0_DRVN_PRE_B0 GENMASK(14, 12) + #define SHU2_B0_DQ0_RG_TX_ARDQ_PRE_EN_B0 BIT(20) + #define SHU2_B0_DQ0_RG_TX_ARDQ_DRVP_PRE_B0 GENMASK(26, 24) + #define SHU2_B0_DQ0_RG_TX_ARDQ_DRVN_PRE_B0 GENMASK(30, 28) + #define SHU2_B0_DQ0_R_LP4Y_WDN_MODE_DQS0 BIT(31) +#define SHU2_B0_DQ1 0x00001104 + #define SHU2_B0_DQ1_RG_TX_ARDQ_DRVP_B0 GENMASK(4, 0) + #define SHU2_B0_DQ1_RG_TX_ARDQ_DRVN_B0 GENMASK(12, 8) + #define SHU2_B0_DQ1_RG_TX_ARDQ_ODTP_B0 GENMASK(20, 16) + #define SHU2_B0_DQ1_RG_TX_ARDQ_ODTN_B0 GENMASK(28, 24) +#define SHU2_B0_DQ2 0x00001108 + #define SHU2_B0_DQ2_RG_TX_ARDQS0_DRVP_B0 GENMASK(4, 0) + #define SHU2_B0_DQ2_RG_TX_ARDQS0_DRVN_B0 GENMASK(12, 8) + #define SHU2_B0_DQ2_RG_TX_ARDQS0_ODTP_B0 GENMASK(20, 16) + #define SHU2_B0_DQ2_RG_TX_ARDQS0_ODTN_B0 GENMASK(28, 24) +#define SHU2_B0_DQ3 0x0000110c + #define SHU2_B0_DQ3_RG_TX_ARDQS0_PU_B0 GENMASK(1, 0) + #define SHU2_B0_DQ3_RG_TX_ARDQS0_PU_PRE_B0 GENMASK(3, 2) + #define SHU2_B0_DQ3_RG_TX_ARDQS0_PDB_B0 GENMASK(5, 4) + #define SHU2_B0_DQ3_RG_TX_ARDQS0_PDB_PRE_B0 GENMASK(7, 6) + #define SHU2_B0_DQ3_RG_TX_ARDQ_PU_B0 GENMASK(9, 8) + #define SHU2_B0_DQ3_RG_TX_ARDQ_PU_PRE_B0 GENMASK(11, 10) + #define SHU2_B0_DQ3_RG_TX_ARDQ_PDB_B0 GENMASK(13, 12) + #define SHU2_B0_DQ3_RG_TX_ARDQ_PDB_PRE_B0 GENMASK(15, 14) +#define SHU2_B0_DQ4 0x00001110 + #define SHU2_B0_DQ4_RG_ARPI_AA_MCK_DL_B0 GENMASK(5, 0) + #define SHU2_B0_DQ4_RG_ARPI_AA_MCK_FB_DL_B0 GENMASK(13, 8) + #define SHU2_B0_DQ4_RG_ARPI_DA_MCK_FB_DL_B0 GENMASK(21, 16) +#define SHU2_B0_DQ5 0x00001114 + #define SHU2_B0_DQ5_RG_RX_ARDQ_VREF_SEL_B0 GENMASK(5, 0) + #define SHU2_B0_DQ5_RG_RX_ARDQ_VREF_BYPASS_B0 BIT(6) + #define SHU2_B0_DQ5_RG_ARPI_FB_B0 GENMASK(13, 8) + #define SHU2_B0_DQ5_RG_RX_ARDQS0_DQSIEN_DLY_B0 GENMASK(18, 16) + #define SHU2_B0_DQ5_DA_RX_ARDQS_DQSIEN_RB_DLY_B0 BIT(19) + #define SHU2_B0_DQ5_RG_RX_ARDQS0_DVS_DLY_B0 GENMASK(22, 20) + #define SHU2_B0_DQ5_RG_ARPI_MCTL_B0 GENMASK(29, 24) +#define SHU2_B0_DQ6 0x00001118 + #define SHU2_B0_DQ6_RG_ARPI_OFFSET_DQSIEN_B0 GENMASK(5, 0) + #define SHU2_B0_DQ6_RG_ARPI_RESERVE_B0 GENMASK(21, 6) + #define SHU2_B0_DQ6_RG_ARPI_MIDPI_CAP_SEL_B0 GENMASK(23, 22) + #define SHU2_B0_DQ6_RG_ARPI_MIDPI_VTH_SEL_B0 GENMASK(25, 24) + #define SHU2_B0_DQ6_RG_ARPI_MIDPI_EN_B0 BIT(26) + #define SHU2_B0_DQ6_RG_ARPI_MIDPI_CKDIV4_EN_B0 BIT(27) + #define SHU2_B0_DQ6_RG_ARPI_CAP_SEL_B0 GENMASK(29, 28) + #define SHU2_B0_DQ6_RG_ARPI_MIDPI_BYPASS_EN_B0 BIT(31) +#define SHU2_B0_DQ7 0x0000111c + #define SHU2_B0_DQ7_R_DMRANKRXDVS_B0 GENMASK(3, 0) + #define SHU2_B0_DQ7_MIDPI_ENABLE BIT(4) + #define SHU2_B0_DQ7_MIDPI_DIV4_ENABLE BIT(5) + #define SHU2_B0_DQ7_R_DMDQMDBI_EYE_SHU_B0 BIT(6) + #define SHU2_B0_DQ7_R_DMDQMDBI_SHU_B0 BIT(7) + #define SHU2_B0_DQ7_R_DMRXDVS_DQM_FLAGSEL_B0 GENMASK(11, 8) + #define SHU2_B0_DQ7_R_DMRXDVS_PBYTE_FLAG_OPT_B0 BIT(12) + #define SHU2_B0_DQ7_R_DMRXDVS_PBYTE_DQM_EN_B0 BIT(13) + #define SHU2_B0_DQ7_R_DMRXTRACK_DQM_EN_B0 BIT(14) + #define SHU2_B0_DQ7_R_DMRODTEN_B0 BIT(15) + #define SHU2_B0_DQ7_R_DMARPI_CG_FB2DLL_DCM_EN_B0 BIT(16) + #define SHU2_B0_DQ7_R_DMTX_ARPI_CG_DQ_NEW_B0 BIT(17) + #define SHU2_B0_DQ7_R_DMTX_ARPI_CG_DQS_NEW_B0 BIT(18) + #define SHU2_B0_DQ7_R_DMTX_ARPI_CG_DQM_NEW_B0 BIT(19) + #define SHU2_B0_DQ7_R_LP4Y_SDN_MODE_DQS0 BIT(20) + #define SHU2_B0_DQ7_R_DMRXRANK_DQ_EN_B0 BIT(24) + #define SHU2_B0_DQ7_R_DMRXRANK_DQ_LAT_B0 GENMASK(27, 25) + #define SHU2_B0_DQ7_R_DMRXRANK_DQS_EN_B0 BIT(28) + #define SHU2_B0_DQ7_R_DMRXRANK_DQS_LAT_B0 GENMASK(31, 29) +#define SHU2_B0_DQ8 0x00001120 + #define SHU2_B0_DQ8_R_DMRXDVS_UPD_FORCE_CYC_B0 GENMASK(14, 0) + #define SHU2_B0_DQ8_R_DMRXDVS_UPD_FORCE_EN_B0 BIT(15) + #define SHU2_B0_DQ8_R_DMRANK_RXDLY_PIPE_CG_IG_B0 BIT(19) + #define SHU2_B0_DQ8_R_RMRODTEN_CG_IG_B0 BIT(20) + #define SHU2_B0_DQ8_R_RMRX_TOPHY_CG_IG_B0 BIT(21) + #define SHU2_B0_DQ8_R_DMRXDVS_RDSEL_PIPE_CG_IG_B0 BIT(22) + #define SHU2_B0_DQ8_R_DMRXDVS_RDSEL_TOG_PIPE_CG_IG_B0 BIT(23) + #define SHU2_B0_DQ8_R_DMRXDLY_CG_IG_B0 BIT(24) + #define SHU2_B0_DQ8_R_DMSTBEN_SYNC_CG_IG_B0 BIT(25) + #define SHU2_B0_DQ8_R_DMDQSIEN_FLAG_SYNC_CG_IG_B0 BIT(26) + #define SHU2_B0_DQ8_R_DMDQSIEN_FLAG_PIPE_CG_IG_B0 BIT(27) + #define SHU2_B0_DQ8_R_DMDQSIEN_RDSEL_PIPE_CG_IG_B0 BIT(28) + #define SHU2_B0_DQ8_R_DMDQSIEN_RDSEL_TOG_PIPE_CG_IG_B0 BIT(29) + #define SHU2_B0_DQ8_R_DMRANK_PIPE_CG_IG_B0 BIT(30) + #define SHU2_B0_DQ8_R_DMRANK_CHG_PIPE_CG_IG_B0 BIT(31) +#define SHU2_B0_DQ9 0x00001124 + #define SHU2_B0_DQ9_RESERVED_0X1124 GENMASK(31, 0) +#define SHU2_B0_DQ10 0x00001128 + #define SHU2_B0_DQ10_RESERVED_0X1128 GENMASK(31, 0) +#define SHU2_B0_DQ11 0x0000112c + #define SHU2_B0_DQ11_RESERVED_0X112C GENMASK(31, 0) +#define SHU2_B0_DQ12 0x00001130 + #define SHU2_B0_DQ12_RESERVED_0X1130 GENMASK(31, 0) +#define SHU2_B0_DLL0 0x00001134 + #define SHU2_B0_DLL0_RG_ARPISM_MCK_SEL_B0_SHU BIT(0) + #define SHU2_B0_DLL0_B0_DLL0_RFU BIT(3) + #define SHU2_B0_DLL0_RG_ARDLL_FAST_PSJP_B0 BIT(4) + #define SHU2_B0_DLL0_RG_ARDLL_PHDIV_B0 BIT(9) + #define SHU2_B0_DLL0_RG_ARDLL_PHJUMP_EN_B0 BIT(10) + #define SHU2_B0_DLL0_RG_ARDLL_P_GAIN_B0 GENMASK(15, 12) + #define SHU2_B0_DLL0_RG_ARDLL_IDLECNT_B0 GENMASK(19, 16) + #define SHU2_B0_DLL0_RG_ARDLL_GAIN_B0 GENMASK(23, 20) + #define SHU2_B0_DLL0_RG_ARDLL_PHDET_IN_SWAP_B0 BIT(30) + #define SHU2_B0_DLL0_RG_ARDLL_PHDET_OUT_SEL_B0 BIT(31) +#define SHU2_B0_DLL1 0x00001138 + #define SHU2_B0_DLL1_RG_ARDLL_FASTPJ_CK_SEL_B0 BIT(0) + #define SHU2_B0_DLL1_RG_ARDLL_PS_EN_B0 BIT(1) + #define SHU2_B0_DLL1_RG_ARDLL_PD_CK_SEL_B0 BIT(2) + #define SHU2_B0_DLL1_RG_ARDQ_REV_B0 GENMASK(31, 8) +#define SHU2_B1_DQ0 0x00001180 + #define SHU2_B1_DQ0_RG_TX_ARDQS0_PRE_EN_B1 BIT(4) + #define SHU2_B1_DQ0_RG_TX_ARDQS0_DRVP_PRE_B1 GENMASK(10, 8) + #define SHU2_B1_DQ0_RG_TX_ARDQS0_DRVN_PRE_B1 GENMASK(14, 12) + #define SHU2_B1_DQ0_RG_TX_ARDQ_PRE_EN_B1 BIT(20) + #define SHU2_B1_DQ0_RG_TX_ARDQ_DRVP_PRE_B1 GENMASK(26, 24) + #define SHU2_B1_DQ0_RG_TX_ARDQ_DRVN_PRE_B1 GENMASK(30, 28) + #define SHU2_B1_DQ0_R_LP4Y_WDN_MODE_DQS1 BIT(31) +#define SHU2_B1_DQ1 0x00001184 + #define SHU2_B1_DQ1_RG_TX_ARDQ_DRVP_B1 GENMASK(4, 0) + #define SHU2_B1_DQ1_RG_TX_ARDQ_DRVN_B1 GENMASK(12, 8) + #define SHU2_B1_DQ1_RG_TX_ARDQ_ODTP_B1 GENMASK(20, 16) + #define SHU2_B1_DQ1_RG_TX_ARDQ_ODTN_B1 GENMASK(28, 24) +#define SHU2_B1_DQ2 0x00001188 + #define SHU2_B1_DQ2_RG_TX_ARDQS0_DRVP_B1 GENMASK(4, 0) + #define SHU2_B1_DQ2_RG_TX_ARDQS0_DRVN_B1 GENMASK(12, 8) + #define SHU2_B1_DQ2_RG_TX_ARDQS0_ODTP_B1 GENMASK(20, 16) + #define SHU2_B1_DQ2_RG_TX_ARDQS0_ODTN_B1 GENMASK(28, 24) +#define SHU2_B1_DQ3 0x0000118c + #define SHU2_B1_DQ3_RG_TX_ARDQS0_PU_B1 GENMASK(1, 0) + #define SHU2_B1_DQ3_RG_TX_ARDQS0_PU_PRE_B1 GENMASK(3, 2) + #define SHU2_B1_DQ3_RG_TX_ARDQS0_PDB_B1 GENMASK(5, 4) + #define SHU2_B1_DQ3_RG_TX_ARDQS0_PDB_PRE_B1 GENMASK(7, 6) + #define SHU2_B1_DQ3_RG_TX_ARDQ_PU_B1 GENMASK(9, 8) + #define SHU2_B1_DQ3_RG_TX_ARDQ_PU_PRE_B1 GENMASK(11, 10) + #define SHU2_B1_DQ3_RG_TX_ARDQ_PDB_B1 GENMASK(13, 12) + #define SHU2_B1_DQ3_RG_TX_ARDQ_PDB_PRE_B1 GENMASK(15, 14) +#define SHU2_B1_DQ4 0x00001190 + #define SHU2_B1_DQ4_RG_ARPI_AA_MCK_DL_B1 GENMASK(5, 0) + #define SHU2_B1_DQ4_RG_ARPI_AA_MCK_FB_DL_B1 GENMASK(13, 8) + #define SHU2_B1_DQ4_RG_ARPI_DA_MCK_FB_DL_B1 GENMASK(21, 16) +#define SHU2_B1_DQ5 0x00001194 + #define SHU2_B1_DQ5_RG_RX_ARDQ_VREF_SEL_B1 GENMASK(5, 0) + #define SHU2_B1_DQ5_RG_RX_ARDQ_VREF_BYPASS_B1 BIT(6) + #define SHU2_B1_DQ5_RG_ARPI_FB_B1 GENMASK(13, 8) + #define SHU2_B1_DQ5_RG_RX_ARDQS0_DQSIEN_DLY_B1 GENMASK(18, 16) + #define SHU2_B1_DQ5_DA_RX_ARDQS_DQSIEN_RB_DLY_B1 BIT(19) + #define SHU2_B1_DQ5_RG_RX_ARDQS0_DVS_DLY_B1 GENMASK(22, 20) + #define SHU2_B1_DQ5_RG_ARPI_MCTL_B1 GENMASK(29, 24) +#define SHU2_B1_DQ6 0x00001198 + #define SHU2_B1_DQ6_RG_ARPI_OFFSET_DQSIEN_B1 GENMASK(5, 0) + #define SHU2_B1_DQ6_RG_ARPI_RESERVE_B1 GENMASK(21, 6) + #define SHU2_B1_DQ6_RG_ARPI_MIDPI_CAP_SEL_B1 GENMASK(23, 22) + #define SHU2_B1_DQ6_RG_ARPI_MIDPI_VTH_SEL_B1 GENMASK(25, 24) + #define SHU2_B1_DQ6_RG_ARPI_MIDPI_EN_B1 BIT(26) + #define SHU2_B1_DQ6_RG_ARPI_MIDPI_CKDIV4_EN_B1 BIT(27) + #define SHU2_B1_DQ6_RG_ARPI_CAP_SEL_B1 GENMASK(29, 28) + #define SHU2_B1_DQ6_RG_ARPI_MIDPI_BYPASS_EN_B1 BIT(31) +#define SHU2_B1_DQ7 0x0000119c + #define SHU2_B1_DQ7_R_DMRANKRXDVS_B1 GENMASK(3, 0) + #define SHU2_B1_DQ7_R_DMDQMDBI_EYE_SHU_B1 BIT(6) + #define SHU2_B1_DQ7_R_DMDQMDBI_SHU_B1 BIT(7) + #define SHU2_B1_DQ7_R_DMRXDVS_DQM_FLAGSEL_B1 GENMASK(11, 8) + #define SHU2_B1_DQ7_R_DMRXDVS_PBYTE_FLAG_OPT_B1 BIT(12) + #define SHU2_B1_DQ7_R_DMRXDVS_PBYTE_DQM_EN_B1 BIT(13) + #define SHU2_B1_DQ7_R_DMRXTRACK_DQM_EN_B1 BIT(14) + #define SHU2_B1_DQ7_R_DMRODTEN_B1 BIT(15) + #define SHU2_B1_DQ7_R_DMARPI_CG_FB2DLL_DCM_EN_B1 BIT(16) + #define SHU2_B1_DQ7_R_DMTX_ARPI_CG_DQ_NEW_B1 BIT(17) + #define SHU2_B1_DQ7_R_DMTX_ARPI_CG_DQS_NEW_B1 BIT(18) + #define SHU2_B1_DQ7_R_DMTX_ARPI_CG_DQM_NEW_B1 BIT(19) + #define SHU2_B1_DQ7_R_LP4Y_SDN_MODE_DQS1 BIT(20) + #define SHU2_B1_DQ7_R_DMRXRANK_DQ_EN_B1 BIT(24) + #define SHU2_B1_DQ7_R_DMRXRANK_DQ_LAT_B1 GENMASK(27, 25) + #define SHU2_B1_DQ7_R_DMRXRANK_DQS_EN_B1 BIT(28) + #define SHU2_B1_DQ7_R_DMRXRANK_DQS_LAT_B1 GENMASK(31, 29) +#define SHU2_B1_DQ8 0x000011a0 + #define SHU2_B1_DQ8_R_DMRXDVS_UPD_FORCE_CYC_B1 GENMASK(14, 0) + #define SHU2_B1_DQ8_R_DMRXDVS_UPD_FORCE_EN_B1 BIT(15) + #define SHU2_B1_DQ8_R_DMRANK_RXDLY_PIPE_CG_IG_B1 BIT(19) + #define SHU2_B1_DQ8_R_RMRODTEN_CG_IG_B1 BIT(20) + #define SHU2_B1_DQ8_R_RMRX_TOPHY_CG_IG_B1 BIT(21) + #define SHU2_B1_DQ8_R_DMRXDVS_RDSEL_PIPE_CG_IG_B1 BIT(22) + #define SHU2_B1_DQ8_R_DMRXDVS_RDSEL_TOG_PIPE_CG_IG_B1 BIT(23) + #define SHU2_B1_DQ8_R_DMRXDLY_CG_IG_B1 BIT(24) + #define SHU2_B1_DQ8_R_DMSTBEN_SYNC_CG_IG_B1 BIT(25) + #define SHU2_B1_DQ8_R_DMDQSIEN_FLAG_SYNC_CG_IG_B1 BIT(26) + #define SHU2_B1_DQ8_R_DMDQSIEN_FLAG_PIPE_CG_IG_B1 BIT(27) + #define SHU2_B1_DQ8_R_DMDQSIEN_RDSEL_PIPE_CG_IG_B1 BIT(28) + #define SHU2_B1_DQ8_R_DMDQSIEN_RDSEL_TOG_PIPE_CG_IG_B1 BIT(29) + #define SHU2_B1_DQ8_R_DMRANK_PIPE_CG_IG_B1 BIT(30) + #define SHU2_B1_DQ8_R_DMRANK_CHG_PIPE_CG_IG_B1 BIT(31) +#define SHU2_B1_DQ9 0x000011a4 + #define SHU2_B1_DQ9_RESERVED_0X11A4 GENMASK(31, 0) +#define SHU2_B1_DQ10 0x000011a8 + #define SHU2_B1_DQ10_RESERVED_0X11A8 GENMASK(31, 0) +#define SHU2_B1_DQ11 0x000011ac + #define SHU2_B1_DQ11_RESERVED_0X11AC GENMASK(31, 0) +#define SHU2_B1_DQ12 0x000011b0 + #define SHU2_B1_DQ12_RESERVED_0X11B0 GENMASK(31, 0) +#define SHU2_B1_DLL0 0x000011b4 + #define SHU2_B1_DLL0_RG_ARPISM_MCK_SEL_B1_SHU BIT(0) + #define SHU2_B1_DLL0_B1_DLL0_RFU BIT(3) + #define SHU2_B1_DLL0_RG_ARDLL_FAST_PSJP_B1 BIT(4) + #define SHU2_B1_DLL0_RG_ARDLL_PHDIV_B1 BIT(9) + #define SHU2_B1_DLL0_RG_ARDLL_PHJUMP_EN_B1 BIT(10) + #define SHU2_B1_DLL0_RG_ARDLL_P_GAIN_B1 GENMASK(15, 12) + #define SHU2_B1_DLL0_RG_ARDLL_IDLECNT_B1 GENMASK(19, 16) + #define SHU2_B1_DLL0_RG_ARDLL_GAIN_B1 GENMASK(23, 20) + #define SHU2_B1_DLL0_RG_ARDLL_PHDET_IN_SWAP_B1 BIT(30) + #define SHU2_B1_DLL0_RG_ARDLL_PHDET_OUT_SEL_B1 BIT(31) +#define SHU2_B1_DLL1 0x000011b8 + #define SHU2_B1_DLL1_RG_ARDLL_FASTPJ_CK_SEL_B1 BIT(0) + #define SHU2_B1_DLL1_RG_ARDLL_PS_EN_B1 BIT(1) + #define SHU2_B1_DLL1_RG_ARDLL_PD_CK_SEL_B1 BIT(2) + #define SHU2_B1_DLL1_RG_ARDQ_REV_B1 GENMASK(31, 8) +#define SHU2_CA_CMD0 0x00001200 + #define SHU2_CA_CMD0_RG_TX_ARCLK_PRE_EN BIT(4) + #define SHU2_CA_CMD0_RG_TX_ARCLK_DRVP_PRE GENMASK(10, 8) + #define SHU2_CA_CMD0_RG_TX_ARCLK_DRVN_PRE GENMASK(14, 12) + #define SHU2_CA_CMD0_RG_CGEN_FMEM_CK_CG_DLL BIT(17) + #define SHU2_CA_CMD0_RG_FB_CK_MUX GENMASK(19, 18) + #define SHU2_CA_CMD0_RG_TX_ARCMD_PRE_EN BIT(20) + #define SHU2_CA_CMD0_RG_TX_ARCMD_DRVP_PRE GENMASK(26, 24) + #define SHU2_CA_CMD0_RG_TX_ARCMD_DRVN_PRE GENMASK(30, 28) + #define SHU2_CA_CMD0_R_LP4Y_WDN_MODE_CLK BIT(31) +#define SHU2_CA_CMD1 0x00001204 + #define SHU2_CA_CMD1_RG_TX_ARCMD_DRVP GENMASK(4, 0) + #define SHU2_CA_CMD1_RG_TX_ARCMD_DRVN GENMASK(12, 8) + #define SHU2_CA_CMD1_RG_TX_ARCMD_ODTP GENMASK(20, 16) + #define SHU2_CA_CMD1_RG_TX_ARCMD_ODTN GENMASK(28, 24) +#define SHU2_CA_CMD2 0x00001208 + #define SHU2_CA_CMD2_RG_TX_ARCLK_DRVP GENMASK(4, 0) + #define SHU2_CA_CMD2_RG_TX_ARCLK_DRVN GENMASK(12, 8) + #define SHU2_CA_CMD2_RG_TX_ARCLK_ODTP GENMASK(20, 16) + #define SHU2_CA_CMD2_RG_TX_ARCLK_ODTN GENMASK(28, 24) +#define SHU2_CA_CMD3 0x0000120c + #define SHU2_CA_CMD3_RG_TX_ARCLK_PU GENMASK(1, 0) + #define SHU2_CA_CMD3_RG_TX_ARCLK_PU_PRE GENMASK(3, 2) + #define SHU2_CA_CMD3_RG_TX_ARCLK_PDB GENMASK(5, 4) + #define SHU2_CA_CMD3_RG_TX_ARCLK_PDB_PRE GENMASK(7, 6) + #define SHU2_CA_CMD3_RG_TX_ARCMD_PU GENMASK(9, 8) + #define SHU2_CA_CMD3_RG_TX_ARCMD_PU_PRE GENMASK(11, 10) + #define SHU2_CA_CMD3_RG_TX_ARCMD_PDB GENMASK(13, 12) + #define SHU2_CA_CMD3_RG_TX_ARCMD_PDB_PRE GENMASK(15, 14) +#define SHU2_CA_CMD4 0x00001210 + #define SHU2_CA_CMD4_RG_ARPI_AA_MCK_DL_CA GENMASK(5, 0) + #define SHU2_CA_CMD4_RG_ARPI_AA_MCK_FB_DL_CA GENMASK(13, 8) + #define SHU2_CA_CMD4_RG_ARPI_DA_MCK_FB_DL_CA GENMASK(21, 16) +#define SHU2_CA_CMD5 0x00001214 + #define SHU2_CA_CMD5_RG_RX_ARCMD_VREF_SEL GENMASK(5, 0) + #define SHU2_CA_CMD5_RG_RX_ARCMD_VREF_BYPASS BIT(6) + #define SHU2_CA_CMD5_RG_ARPI_FB_CA GENMASK(13, 8) + #define SHU2_CA_CMD5_RG_RX_ARCLK_DQSIEN_DLY GENMASK(18, 16) + #define SHU2_CA_CMD5_DA_RX_ARCLK_DQSIEN_RB_DLY BIT(19) + #define SHU2_CA_CMD5_RG_RX_ARCLK_DVS_DLY GENMASK(22, 20) + #define SHU2_CA_CMD5_RG_ARPI_MCTL_CA GENMASK(29, 24) +#define SHU2_CA_CMD6 0x00001218 + #define SHU2_CA_CMD6_RG_ARPI_OFFSET_CLKIEN GENMASK(5, 0) + #define SHU2_CA_CMD6_RG_ARPI_RESERVE_CA GENMASK(21, 6) + #define SHU2_CA_CMD6_RG_ARPI_MIDPI_CAP_SEL_CA GENMASK(23, 22) + #define SHU2_CA_CMD6_RG_ARPI_MIDPI_VTH_SEL_CA GENMASK(25, 24) + #define SHU2_CA_CMD6_RG_ARPI_MIDPI_EN_CA BIT(26) + #define SHU2_CA_CMD6_RG_ARPI_MIDPI_CKDIV4_EN_CA BIT(27) + #define SHU2_CA_CMD6_RG_ARPI_CAP_SEL_CA GENMASK(29, 28) + #define SHU2_CA_CMD6_RG_ARPI_MIDPI_BYPASS_EN_CA BIT(31) +#define SHU2_CA_CMD7 0x0000121c + #define SHU2_CA_CMD7_R_DMRANKRXDVS_CA GENMASK(3, 0) + #define SHU2_CA_CMD7_R_DMRXDVS_PBYTE_FLAG_OPT_CA BIT(12) + #define SHU2_CA_CMD7_R_DMRODTEN_CA BIT(15) + #define SHU2_CA_CMD7_R_DMARPI_CG_FB2DLL_DCM_EN_CA BIT(16) + #define SHU2_CA_CMD7_R_DMTX_ARPI_CG_CMD_NEW BIT(17) + #define SHU2_CA_CMD7_R_DMTX_ARPI_CG_CLK_NEW BIT(18) + #define SHU2_CA_CMD7_R_DMTX_ARPI_CG_CS_NEW BIT(19) + #define SHU2_CA_CMD7_R_LP4Y_SDN_MODE_CLK BIT(20) + #define SHU2_CA_CMD7_R_DMRXRANK_CMD_EN BIT(24) + #define SHU2_CA_CMD7_R_DMRXRANK_CMD_LAT GENMASK(27, 25) + #define SHU2_CA_CMD7_R_DMRXRANK_CLK_EN BIT(28) + #define SHU2_CA_CMD7_R_DMRXRANK_CLK_LAT GENMASK(31, 29) +#define SHU2_CA_CMD8 0x00001220 + #define SHU2_CA_CMD8_R_DMRXDVS_UPD_FORCE_CYC_CA GENMASK(14, 0) + #define SHU2_CA_CMD8_R_DMRXDVS_UPD_FORCE_EN_CA BIT(15) + #define SHU2_CA_CMD8_R_DMRANK_RXDLY_PIPE_CG_IG_CA BIT(19) + #define SHU2_CA_CMD8_R_RMRODTEN_CG_IG_CA BIT(20) + #define SHU2_CA_CMD8_R_RMRX_TOPHY_CG_IG_CA BIT(21) + #define SHU2_CA_CMD8_R_DMRXDVS_RDSEL_PIPE_CG_IG_CA BIT(22) + #define SHU2_CA_CMD8_R_DMRXDVS_RDSEL_TOG_PIPE_CG_IG_CA BIT(23) + #define SHU2_CA_CMD8_R_DMRXDLY_CG_IG_CA BIT(24) + #define SHU2_CA_CMD8_R_DMSTBEN_SYNC_CG_IG_CA BIT(25) + #define SHU2_CA_CMD8_R_DMDQSIEN_FLAG_SYNC_CG_IG_CA BIT(26) + #define SHU2_CA_CMD8_R_DMDQSIEN_FLAG_PIPE_CG_IG_CA BIT(27) + #define SHU2_CA_CMD8_R_DMDQSIEN_RDSEL_PIPE_CG_IG_CA BIT(28) + #define SHU2_CA_CMD8_R_DMDQSIEN_RDSEL_TOG_PIPE_CG_IG_CA BIT(29) + #define SHU2_CA_CMD8_R_DMRANK_PIPE_CG_IG_CA BIT(30) + #define SHU2_CA_CMD8_R_DMRANK_CHG_PIPE_CG_IG_CA BIT(31) +#define SHU2_CA_CMD9 0x00001224 + #define SHU2_CA_CMD9_RESERVED_0X1224 GENMASK(31, 0) +#define SHU2_CA_CMD10 0x00001228 + #define SHU2_CA_CMD10_RESERVED_0X1228 GENMASK(31, 0) +#define SHU2_CA_CMD11 0x0000122c + #define SHU2_CA_CMD11_RG_RIMP_REV GENMASK(7, 0) + #define SHU2_CA_CMD11_RG_RIMP_VREF_SEL GENMASK(13, 8) + #define SHU2_CA_CMD11_RG_TX_ARCKE_DRVP GENMASK(21, 17) + #define SHU2_CA_CMD11_RG_TX_ARCKE_DRVN GENMASK(26, 22) +#define SHU2_CA_CMD12 0x00001230 + #define SHU2_CA_CMD12_RESERVED_0X1230 GENMASK(31, 0) +#define SHU2_CA_DLL0 0x00001234 + #define SHU2_CA_DLL0_RG_ARPISM_MCK_SEL_CA_SHU BIT(0) + #define SHU2_CA_DLL0_CA_DLL0_RFU BIT(3) + #define SHU2_CA_DLL0_RG_ARDLL_FAST_PSJP_CA BIT(4) + #define SHU2_CA_DLL0_RG_ARDLL_PHDIV_CA BIT(9) + #define SHU2_CA_DLL0_RG_ARDLL_PHJUMP_EN_CA BIT(10) + #define SHU2_CA_DLL0_RG_ARDLL_P_GAIN_CA GENMASK(15, 12) + #define SHU2_CA_DLL0_RG_ARDLL_IDLECNT_CA GENMASK(19, 16) + #define SHU2_CA_DLL0_RG_ARDLL_GAIN_CA GENMASK(23, 20) + #define SHU2_CA_DLL0_RG_ARDLL_PHDET_IN_SWAP_CA BIT(30) + #define SHU2_CA_DLL0_RG_ARDLL_PHDET_OUT_SEL_CA BIT(31) +#define SHU2_CA_DLL1 0x00001238 + #define SHU2_CA_DLL1_RG_ARDLL_FASTPJ_CK_SEL_CA BIT(0) + #define SHU2_CA_DLL1_RG_ARDLL_PS_EN_CA BIT(1) + #define SHU2_CA_DLL1_RG_ARDLL_PD_CK_SEL_CA BIT(2) + #define SHU2_CA_DLL1_RG_ARCMD_REV GENMASK(31, 8) +#define SHU2_MISC0 0x000012f0 + #define SHU2_MISC0_R_RX_PIPE_BYPASS_EN BIT(1) + #define SHU2_MISC0_RG_CMD_TXPIPE_BYPASS_EN BIT(2) + #define SHU2_MISC0_RG_CK_TXPIPE_BYPASS_EN BIT(3) + #define SHU2_MISC0_RG_RVREF_SEL_DQ GENMASK(21, 16) + #define SHU2_MISC0_RG_RVREF_DDR4_SEL BIT(22) + #define SHU2_MISC0_RG_RVREF_DDR3_SEL BIT(23) + #define SHU2_MISC0_RG_RVREF_SEL_CMD GENMASK(29, 24) +#define SHU2_R0_B0_DQ0 0x00001300 + #define SHU2_R0_B0_DQ0_RK0_TX_ARDQ0_DLY_B0 GENMASK(3, 0) + #define SHU2_R0_B0_DQ0_RK0_TX_ARDQ1_DLY_B0 GENMASK(7, 4) + #define SHU2_R0_B0_DQ0_RK0_TX_ARDQ2_DLY_B0 GENMASK(11, 8) + #define SHU2_R0_B0_DQ0_RK0_TX_ARDQ3_DLY_B0 GENMASK(15, 12) + #define SHU2_R0_B0_DQ0_RK0_TX_ARDQ4_DLY_B0 GENMASK(19, 16) + #define SHU2_R0_B0_DQ0_RK0_TX_ARDQ5_DLY_B0 GENMASK(23, 20) + #define SHU2_R0_B0_DQ0_RK0_TX_ARDQ6_DLY_B0 GENMASK(27, 24) + #define SHU2_R0_B0_DQ0_RK0_TX_ARDQ7_DLY_B0 GENMASK(31, 28) +#define SHU2_R0_B0_DQ1 0x00001304 + #define SHU2_R0_B0_DQ1_RK0_TX_ARDQM0_DLY_B0 GENMASK(3, 0) + #define SHU2_R0_B0_DQ1_RK0_TX_ARDQS0_DLYB_B0 GENMASK(19, 16) + #define SHU2_R0_B0_DQ1_RK0_TX_ARDQS0B_DLYB_B0 GENMASK(23, 20) + #define SHU2_R0_B0_DQ1_RK0_TX_ARDQS0_DLY_B0 GENMASK(27, 24) + #define SHU2_R0_B0_DQ1_RK0_TX_ARDQS0B_DLY_B0 GENMASK(31, 28) +#define SHU2_R0_B0_DQ2 0x00001308 + #define SHU2_R0_B0_DQ2_RK0_RX_ARDQ0_R_DLY_B0 GENMASK(5, 0) + #define SHU2_R0_B0_DQ2_RK0_RX_ARDQ0_F_DLY_B0 GENMASK(13, 8) + #define SHU2_R0_B0_DQ2_RK0_RX_ARDQ1_R_DLY_B0 GENMASK(21, 16) + #define SHU2_R0_B0_DQ2_RK0_RX_ARDQ1_F_DLY_B0 GENMASK(29, 24) +#define SHU2_R0_B0_DQ3 0x0000130c + #define SHU2_R0_B0_DQ3_RK0_RX_ARDQ2_R_DLY_B0 GENMASK(5, 0) + #define SHU2_R0_B0_DQ3_RK0_RX_ARDQ2_F_DLY_B0 GENMASK(13, 8) + #define SHU2_R0_B0_DQ3_RK0_RX_ARDQ3_R_DLY_B0 GENMASK(21, 16) + #define SHU2_R0_B0_DQ3_RK0_RX_ARDQ3_F_DLY_B0 GENMASK(29, 24) +#define SHU2_R0_B0_DQ4 0x00001310 + #define SHU2_R0_B0_DQ4_RK0_RX_ARDQ4_R_DLY_B0 GENMASK(5, 0) + #define SHU2_R0_B0_DQ4_RK0_RX_ARDQ4_F_DLY_B0 GENMASK(13, 8) + #define SHU2_R0_B0_DQ4_RK0_RX_ARDQ5_R_DLY_B0 GENMASK(21, 16) + #define SHU2_R0_B0_DQ4_RK0_RX_ARDQ5_F_DLY_B0 GENMASK(29, 24) +#define SHU2_R0_B0_DQ5 0x00001314 + #define SHU2_R0_B0_DQ5_RK0_RX_ARDQ6_R_DLY_B0 GENMASK(5, 0) + #define SHU2_R0_B0_DQ5_RK0_RX_ARDQ6_F_DLY_B0 GENMASK(13, 8) + #define SHU2_R0_B0_DQ5_RK0_RX_ARDQ7_R_DLY_B0 GENMASK(21, 16) + #define SHU2_R0_B0_DQ5_RK0_RX_ARDQ7_F_DLY_B0 GENMASK(29, 24) +#define SHU2_R0_B0_DQ6 0x00001318 + #define SHU2_R0_B0_DQ6_RK0_RX_ARDQM0_R_DLY_B0 GENMASK(5, 0) + #define SHU2_R0_B0_DQ6_RK0_RX_ARDQM0_F_DLY_B0 GENMASK(13, 8) + #define SHU2_R0_B0_DQ6_RK0_RX_ARDQS0_R_DLY_B0 GENMASK(22, 16) + #define SHU2_R0_B0_DQ6_RK0_RX_ARDQS0_F_DLY_B0 GENMASK(30, 24) +#define SHU2_R0_B0_DQ7 0x0000131c + #define SHU2_R0_B0_DQ7_RK0_ARPI_DQ_B0 GENMASK(13, 8) + #define SHU2_R0_B0_DQ7_RK0_ARPI_DQM_B0 GENMASK(21, 16) + #define SHU2_R0_B0_DQ7_RK0_ARPI_PBYTE_B0 GENMASK(29, 24) +#define RFU_0X1320 0x00001320 + #define RFU_0X1320_RESERVED_0X1320 GENMASK(31, 0) +#define RFU_0X1324 0x00001324 + #define RFU_0X1324_RESERVED_0X1324 GENMASK(31, 0) +#define RFU_0X1328 0x00001328 + #define RFU_0X1328_RESERVED_0X1328 GENMASK(31, 0) +#define RFU_0X132C 0x0000132c + #define RFU_0X132C_RESERVED_0X132C GENMASK(31, 0) +#define SHU2_R0_B1_DQ0 0x00001350 + #define SHU2_R0_B1_DQ0_RK0_TX_ARDQ0_DLY_B1 GENMASK(3, 0) + #define SHU2_R0_B1_DQ0_RK0_TX_ARDQ1_DLY_B1 GENMASK(7, 4) + #define SHU2_R0_B1_DQ0_RK0_TX_ARDQ2_DLY_B1 GENMASK(11, 8) + #define SHU2_R0_B1_DQ0_RK0_TX_ARDQ3_DLY_B1 GENMASK(15, 12) + #define SHU2_R0_B1_DQ0_RK0_TX_ARDQ4_DLY_B1 GENMASK(19, 16) + #define SHU2_R0_B1_DQ0_RK0_TX_ARDQ5_DLY_B1 GENMASK(23, 20) + #define SHU2_R0_B1_DQ0_RK0_TX_ARDQ6_DLY_B1 GENMASK(27, 24) + #define SHU2_R0_B1_DQ0_RK0_TX_ARDQ7_DLY_B1 GENMASK(31, 28) +#define SHU2_R0_B1_DQ1 0x00001354 + #define SHU2_R0_B1_DQ1_RK0_TX_ARDQM0_DLY_B1 GENMASK(3, 0) + #define SHU2_R0_B1_DQ1_RK0_TX_ARDQS0_DLYB_B1 GENMASK(19, 16) + #define SHU2_R0_B1_DQ1_RK0_TX_ARDQS0B_DLYB_B1 GENMASK(23, 20) + #define SHU2_R0_B1_DQ1_RK0_TX_ARDQS0_DLY_B1 GENMASK(27, 24) + #define SHU2_R0_B1_DQ1_RK0_TX_ARDQS0B_DLY_B1 GENMASK(31, 28) +#define SHU2_R0_B1_DQ2 0x00001358 + #define SHU2_R0_B1_DQ2_RK0_RX_ARDQ0_R_DLY_B1 GENMASK(5, 0) + #define SHU2_R0_B1_DQ2_RK0_RX_ARDQ0_F_DLY_B1 GENMASK(13, 8) + #define SHU2_R0_B1_DQ2_RK0_RX_ARDQ1_R_DLY_B1 GENMASK(21, 16) + #define SHU2_R0_B1_DQ2_RK0_RX_ARDQ1_F_DLY_B1 GENMASK(29, 24) +#define SHU2_R0_B1_DQ3 0x0000135c + #define SHU2_R0_B1_DQ3_RK0_RX_ARDQ2_R_DLY_B1 GENMASK(5, 0) + #define SHU2_R0_B1_DQ3_RK0_RX_ARDQ2_F_DLY_B1 GENMASK(13, 8) + #define SHU2_R0_B1_DQ3_RK0_RX_ARDQ3_R_DLY_B1 GENMASK(21, 16) + #define SHU2_R0_B1_DQ3_RK0_RX_ARDQ3_F_DLY_B1 GENMASK(29, 24) +#define SHU2_R0_B1_DQ4 0x00001360 + #define SHU2_R0_B1_DQ4_RK0_RX_ARDQ4_R_DLY_B1 GENMASK(5, 0) + #define SHU2_R0_B1_DQ4_RK0_RX_ARDQ4_F_DLY_B1 GENMASK(13, 8) + #define SHU2_R0_B1_DQ4_RK0_RX_ARDQ5_R_DLY_B1 GENMASK(21, 16) + #define SHU2_R0_B1_DQ4_RK0_RX_ARDQ5_F_DLY_B1 GENMASK(29, 24) +#define SHU2_R0_B1_DQ5 0x00001364 + #define SHU2_R0_B1_DQ5_RK0_RX_ARDQ6_R_DLY_B1 GENMASK(5, 0) + #define SHU2_R0_B1_DQ5_RK0_RX_ARDQ6_F_DLY_B1 GENMASK(13, 8) + #define SHU2_R0_B1_DQ5_RK0_RX_ARDQ7_R_DLY_B1 GENMASK(21, 16) + #define SHU2_R0_B1_DQ5_RK0_RX_ARDQ7_F_DLY_B1 GENMASK(29, 24) +#define SHU2_R0_B1_DQ6 0x00001368 + #define SHU2_R0_B1_DQ6_RK0_RX_ARDQM0_R_DLY_B1 GENMASK(5, 0) + #define SHU2_R0_B1_DQ6_RK0_RX_ARDQM0_F_DLY_B1 GENMASK(13, 8) + #define SHU2_R0_B1_DQ6_RK0_RX_ARDQS0_R_DLY_B1 GENMASK(22, 16) + #define SHU2_R0_B1_DQ6_RK0_RX_ARDQS0_F_DLY_B1 GENMASK(30, 24) +#define SHU2_R0_B1_DQ7 0x0000136c + #define SHU2_R0_B1_DQ7_RK0_ARPI_DQ_B1 GENMASK(13, 8) + #define SHU2_R0_B1_DQ7_RK0_ARPI_DQM_B1 GENMASK(21, 16) + #define SHU2_R0_B1_DQ7_RK0_ARPI_PBYTE_B1 GENMASK(29, 24) +#define RFU_0X1370 0x00001370 + #define RFU_0X1370_RESERVED_0X1370 GENMASK(31, 0) +#define RFU_0X1374 0x00001374 + #define RFU_0X1374_RESERVED_0X1374 GENMASK(31, 0) +#define RFU_0X1378 0x00001378 + #define RFU_0X1378_RESERVED_0X1378 GENMASK(31, 0) +#define RFU_0X137C 0x0000137c + #define RFU_0X137C_RESERVED_0X137C GENMASK(31, 0) +#define SHU2_R0_CA_CMD0 0x000013a0 + #define SHU2_R0_CA_CMD0_RK0_TX_ARCA0_DLY GENMASK(3, 0) + #define SHU2_R0_CA_CMD0_RK0_TX_ARCA1_DLY GENMASK(7, 4) + #define SHU2_R0_CA_CMD0_RK0_TX_ARCA2_DLY GENMASK(11, 8) + #define SHU2_R0_CA_CMD0_RK0_TX_ARCA3_DLY GENMASK(15, 12) + #define SHU2_R0_CA_CMD0_RK0_TX_ARCA4_DLY GENMASK(19, 16) + #define SHU2_R0_CA_CMD0_RK0_TX_ARCA5_DLY GENMASK(23, 20) + #define SHU2_R0_CA_CMD0_RK0_TX_ARCLK_DLYB GENMASK(27, 24) + #define SHU2_R0_CA_CMD0_RK0_TX_ARCLKB_DLYB GENMASK(31, 28) +#define SHU2_R0_CA_CMD1 0x000013a4 + #define SHU2_R0_CA_CMD1_RK0_TX_ARCKE0_DLY GENMASK(3, 0) + #define SHU2_R0_CA_CMD1_RK0_TX_ARCKE1_DLY GENMASK(7, 4) + #define SHU2_R0_CA_CMD1_RK0_TX_ARCKE2_DLY GENMASK(11, 8) + #define SHU2_R0_CA_CMD1_RK0_TX_ARCS0_DLY GENMASK(15, 12) + #define SHU2_R0_CA_CMD1_RK0_TX_ARCS1_DLY GENMASK(19, 16) + #define SHU2_R0_CA_CMD1_RK0_TX_ARCS2_DLY GENMASK(23, 20) + #define SHU2_R0_CA_CMD1_RK0_TX_ARCLK_DLY GENMASK(27, 24) + #define SHU2_R0_CA_CMD1_RK0_TX_ARCLKB_DLY GENMASK(31, 28) +#define SHU2_R0_CA_CMD2 0x000013a8 + #define SHU2_R0_CA_CMD2_RG_RK0_RX_ARCA0_R_DLY GENMASK(5, 0) + #define SHU2_R0_CA_CMD2_RG_RK0_RX_ARCA0_F_DLY GENMASK(13, 8) + #define SHU2_R0_CA_CMD2_RG_RK0_RX_ARCA1_R_DLY GENMASK(21, 16) + #define SHU2_R0_CA_CMD2_RG_RK0_RX_ARCA1_F_DLY GENMASK(29, 24) +#define SHU2_R0_CA_CMD3 0x000013ac + #define SHU2_R0_CA_CMD3_RG_RK0_RX_ARCA2_R_DLY GENMASK(5, 0) + #define SHU2_R0_CA_CMD3_RG_RK0_RX_ARCA2_F_DLY GENMASK(13, 8) + #define SHU2_R0_CA_CMD3_RG_RK0_RX_ARCA3_R_DLY GENMASK(21, 16) + #define SHU2_R0_CA_CMD3_RG_RK0_RX_ARCA3_F_DLY GENMASK(29, 24) +#define SHU2_R0_CA_CMD4 0x000013b0 + #define SHU2_R0_CA_CMD4_RG_RK0_RX_ARCA4_R_DLY GENMASK(5, 0) + #define SHU2_R0_CA_CMD4_RG_RK0_RX_ARCA4_F_DLY GENMASK(13, 8) + #define SHU2_R0_CA_CMD4_RG_RK0_RX_ARCA5_R_DLY GENMASK(21, 16) + #define SHU2_R0_CA_CMD4_RG_RK0_RX_ARCA5_F_DLY GENMASK(29, 24) +#define SHU2_R0_CA_CMD5 0x000013b4 + #define SHU2_R0_CA_CMD5_RG_RK0_RX_ARCKE0_R_DLY GENMASK(5, 0) + #define SHU2_R0_CA_CMD5_RG_RK0_RX_ARCKE0_F_DLY GENMASK(13, 8) + #define SHU2_R0_CA_CMD5_RG_RK0_RX_ARCKE1_R_DLY GENMASK(21, 16) + #define SHU2_R0_CA_CMD5_RG_RK0_RX_ARCKE1_F_DLY GENMASK(29, 24) +#define SHU2_R0_CA_CMD6 0x000013b8 + #define SHU2_R0_CA_CMD6_RG_RK0_RX_ARCKE2_R_DLY GENMASK(5, 0) + #define SHU2_R0_CA_CMD6_RG_RK0_RX_ARCKE2_F_DLY GENMASK(13, 8) + #define SHU2_R0_CA_CMD6_RG_RK0_RX_ARCS0_R_DLY GENMASK(21, 16) + #define SHU2_R0_CA_CMD6_RG_RK0_RX_ARCS0_F_DLY GENMASK(29, 24) +#define SHU2_R0_CA_CMD7 0x000013bc + #define SHU2_R0_CA_CMD7_RG_RK0_RX_ARCS1_R_DLY GENMASK(5, 0) + #define SHU2_R0_CA_CMD7_RG_RK0_RX_ARCS1_F_DLY GENMASK(13, 8) + #define SHU2_R0_CA_CMD7_RG_RK0_RX_ARCS2_R_DLY GENMASK(21, 16) + #define SHU2_R0_CA_CMD7_RG_RK0_RX_ARCS2_F_DLY GENMASK(29, 24) +#define SHU2_R0_CA_CMD8 0x000013c0 + #define SHU2_R0_CA_CMD8_RG_RK0_RX_ARCLK_R_DLY GENMASK(22, 16) + #define SHU2_R0_CA_CMD8_RG_RK0_RX_ARCLK_F_DLY GENMASK(30, 24) +#define SHU2_R0_CA_CMD9 0x000013c4 + #define SHU2_R0_CA_CMD9_RG_RK0_ARPI_CS GENMASK(5, 0) + #define SHU2_R0_CA_CMD9_RG_RK0_ARPI_CMD GENMASK(13, 8) + #define SHU2_R0_CA_CMD9_RG_RK0_ARPI_CLK GENMASK(29, 24) +#define RFU_0X13C8 0x000013c8 + #define RFU_0X13C8_RESERVED_0X13C8 GENMASK(31, 0) +#define RFU_0X13CC 0x000013cc + #define RFU_0X13CC_RESERVED_0X13CC GENMASK(31, 0) +#define SHU2_R1_B0_DQ0 0x00001400 + #define SHU2_R1_B0_DQ0_RK1_TX_ARDQ0_DLY_B0 GENMASK(3, 0) + #define SHU2_R1_B0_DQ0_RK1_TX_ARDQ1_DLY_B0 GENMASK(7, 4) + #define SHU2_R1_B0_DQ0_RK1_TX_ARDQ2_DLY_B0 GENMASK(11, 8) + #define SHU2_R1_B0_DQ0_RK1_TX_ARDQ3_DLY_B0 GENMASK(15, 12) + #define SHU2_R1_B0_DQ0_RK1_TX_ARDQ4_DLY_B0 GENMASK(19, 16) + #define SHU2_R1_B0_DQ0_RK1_TX_ARDQ5_DLY_B0 GENMASK(23, 20) + #define SHU2_R1_B0_DQ0_RK1_TX_ARDQ6_DLY_B0 GENMASK(27, 24) + #define SHU2_R1_B0_DQ0_RK1_TX_ARDQ7_DLY_B0 GENMASK(31, 28) +#define SHU2_R1_B0_DQ1 0x00001404 + #define SHU2_R1_B0_DQ1_RK1_TX_ARDQM0_DLY_B0 GENMASK(3, 0) + #define SHU2_R1_B0_DQ1_RK1_TX_ARDQS0_DLYB_B0 GENMASK(19, 16) + #define SHU2_R1_B0_DQ1_RK1_TX_ARDQS0B_DLYB_B0 GENMASK(23, 20) + #define SHU2_R1_B0_DQ1_RK1_TX_ARDQS0_DLY_B0 GENMASK(27, 24) + #define SHU2_R1_B0_DQ1_RK1_TX_ARDQS0B_DLY_B0 GENMASK(31, 28) +#define SHU2_R1_B0_DQ2 0x00001408 + #define SHU2_R1_B0_DQ2_RK1_RX_ARDQ0_R_DLY_B0 GENMASK(5, 0) + #define SHU2_R1_B0_DQ2_RK1_RX_ARDQ0_F_DLY_B0 GENMASK(13, 8) + #define SHU2_R1_B0_DQ2_RK1_RX_ARDQ1_R_DLY_B0 GENMASK(21, 16) + #define SHU2_R1_B0_DQ2_RK1_RX_ARDQ1_F_DLY_B0 GENMASK(29, 24) +#define SHU2_R1_B0_DQ3 0x0000140c + #define SHU2_R1_B0_DQ3_RK1_RX_ARDQ2_R_DLY_B0 GENMASK(5, 0) + #define SHU2_R1_B0_DQ3_RK1_RX_ARDQ2_F_DLY_B0 GENMASK(13, 8) + #define SHU2_R1_B0_DQ3_RK1_RX_ARDQ3_R_DLY_B0 GENMASK(21, 16) + #define SHU2_R1_B0_DQ3_RK1_RX_ARDQ3_F_DLY_B0 GENMASK(29, 24) +#define SHU2_R1_B0_DQ4 0x00001410 + #define SHU2_R1_B0_DQ4_RK1_RX_ARDQ4_R_DLY_B0 GENMASK(5, 0) + #define SHU2_R1_B0_DQ4_RK1_RX_ARDQ4_F_DLY_B0 GENMASK(13, 8) + #define SHU2_R1_B0_DQ4_RK1_RX_ARDQ5_R_DLY_B0 GENMASK(21, 16) + #define SHU2_R1_B0_DQ4_RK1_RX_ARDQ5_F_DLY_B0 GENMASK(29, 24) +#define SHU2_R1_B0_DQ5 0x00001414 + #define SHU2_R1_B0_DQ5_RK1_RX_ARDQ6_R_DLY_B0 GENMASK(5, 0) + #define SHU2_R1_B0_DQ5_RK1_RX_ARDQ6_F_DLY_B0 GENMASK(13, 8) + #define SHU2_R1_B0_DQ5_RK1_RX_ARDQ7_R_DLY_B0 GENMASK(21, 16) + #define SHU2_R1_B0_DQ5_RK1_RX_ARDQ7_F_DLY_B0 GENMASK(29, 24) +#define SHU2_R1_B0_DQ6 0x00001418 + #define SHU2_R1_B0_DQ6_RK1_RX_ARDQM0_R_DLY_B0 GENMASK(5, 0) + #define SHU2_R1_B0_DQ6_RK1_RX_ARDQM0_F_DLY_B0 GENMASK(13, 8) + #define SHU2_R1_B0_DQ6_RK1_RX_ARDQS0_R_DLY_B0 GENMASK(22, 16) + #define SHU2_R1_B0_DQ6_RK1_RX_ARDQS0_F_DLY_B0 GENMASK(30, 24) +#define SHU2_R1_B0_DQ7 0x0000141c + #define SHU2_R1_B0_DQ7_RK1_ARPI_DQ_B0 GENMASK(13, 8) + #define SHU2_R1_B0_DQ7_RK1_ARPI_DQM_B0 GENMASK(21, 16) + #define SHU2_R1_B0_DQ7_RK1_ARPI_PBYTE_B0 GENMASK(29, 24) +#define RFU_0X1420 0x00001420 + #define RFU_0X1420_RESERVED_0X1420 GENMASK(31, 0) +#define RFU_0X1424 0x00001424 + #define RFU_0X1424_RESERVED_0X1424 GENMASK(31, 0) +#define RFU_0X1428 0x00001428 + #define RFU_0X1428_RESERVED_0X1428 GENMASK(31, 0) +#define RFU_0X142C 0x0000142c + #define RFU_0X142C_RESERVED_0X142C GENMASK(31, 0) +#define SHU2_R1_B1_DQ0 0x00001450 + #define SHU2_R1_B1_DQ0_RK1_TX_ARDQ0_DLY_B1 GENMASK(3, 0) + #define SHU2_R1_B1_DQ0_RK1_TX_ARDQ1_DLY_B1 GENMASK(7, 4) + #define SHU2_R1_B1_DQ0_RK1_TX_ARDQ2_DLY_B1 GENMASK(11, 8) + #define SHU2_R1_B1_DQ0_RK1_TX_ARDQ3_DLY_B1 GENMASK(15, 12) + #define SHU2_R1_B1_DQ0_RK1_TX_ARDQ4_DLY_B1 GENMASK(19, 16) + #define SHU2_R1_B1_DQ0_RK1_TX_ARDQ5_DLY_B1 GENMASK(23, 20) + #define SHU2_R1_B1_DQ0_RK1_TX_ARDQ6_DLY_B1 GENMASK(27, 24) + #define SHU2_R1_B1_DQ0_RK1_TX_ARDQ7_DLY_B1 GENMASK(31, 28) +#define SHU2_R1_B1_DQ1 0x00001454 + #define SHU2_R1_B1_DQ1_RK1_TX_ARDQM0_DLY_B1 GENMASK(3, 0) + #define SHU2_R1_B1_DQ1_RK1_TX_ARDQS0_DLYB_B1 GENMASK(19, 16) + #define SHU2_R1_B1_DQ1_RK1_TX_ARDQS0B_DLYB_B1 GENMASK(23, 20) + #define SHU2_R1_B1_DQ1_RK1_TX_ARDQS0_DLY_B1 GENMASK(27, 24) + #define SHU2_R1_B1_DQ1_RK1_TX_ARDQS0B_DLY_B1 GENMASK(31, 28) +#define SHU2_R1_B1_DQ2 0x00001458 + #define SHU2_R1_B1_DQ2_RK1_RX_ARDQ0_R_DLY_B1 GENMASK(5, 0) + #define SHU2_R1_B1_DQ2_RK1_RX_ARDQ0_F_DLY_B1 GENMASK(13, 8) + #define SHU2_R1_B1_DQ2_RK1_RX_ARDQ1_R_DLY_B1 GENMASK(21, 16) + #define SHU2_R1_B1_DQ2_RK1_RX_ARDQ1_F_DLY_B1 GENMASK(29, 24) +#define SHU2_R1_B1_DQ3 0x0000145c + #define SHU2_R1_B1_DQ3_RK1_RX_ARDQ2_R_DLY_B1 GENMASK(5, 0) + #define SHU2_R1_B1_DQ3_RK1_RX_ARDQ2_F_DLY_B1 GENMASK(13, 8) + #define SHU2_R1_B1_DQ3_RK1_RX_ARDQ3_R_DLY_B1 GENMASK(21, 16) + #define SHU2_R1_B1_DQ3_RK1_RX_ARDQ3_F_DLY_B1 GENMASK(29, 24) +#define SHU2_R1_B1_DQ4 0x00001460 + #define SHU2_R1_B1_DQ4_RK1_RX_ARDQ4_R_DLY_B1 GENMASK(5, 0) + #define SHU2_R1_B1_DQ4_RK1_RX_ARDQ4_F_DLY_B1 GENMASK(13, 8) + #define SHU2_R1_B1_DQ4_RK1_RX_ARDQ5_R_DLY_B1 GENMASK(21, 16) + #define SHU2_R1_B1_DQ4_RK1_RX_ARDQ5_F_DLY_B1 GENMASK(29, 24) +#define SHU2_R1_B1_DQ5 0x00001464 + #define SHU2_R1_B1_DQ5_RK1_RX_ARDQ6_R_DLY_B1 GENMASK(5, 0) + #define SHU2_R1_B1_DQ5_RK1_RX_ARDQ6_F_DLY_B1 GENMASK(13, 8) + #define SHU2_R1_B1_DQ5_RK1_RX_ARDQ7_R_DLY_B1 GENMASK(21, 16) + #define SHU2_R1_B1_DQ5_RK1_RX_ARDQ7_F_DLY_B1 GENMASK(29, 24) +#define SHU2_R1_B1_DQ6 0x00001468 + #define SHU2_R1_B1_DQ6_RK1_RX_ARDQM0_R_DLY_B1 GENMASK(5, 0) + #define SHU2_R1_B1_DQ6_RK1_RX_ARDQM0_F_DLY_B1 GENMASK(13, 8) + #define SHU2_R1_B1_DQ6_RK1_RX_ARDQS0_R_DLY_B1 GENMASK(22, 16) + #define SHU2_R1_B1_DQ6_RK1_RX_ARDQS0_F_DLY_B1 GENMASK(30, 24) +#define SHU2_R1_B1_DQ7 0x0000146c + #define SHU2_R1_B1_DQ7_RK1_ARPI_DQ_B1 GENMASK(13, 8) + #define SHU2_R1_B1_DQ7_RK1_ARPI_DQM_B1 GENMASK(21, 16) + #define SHU2_R1_B1_DQ7_RK1_ARPI_PBYTE_B1 GENMASK(29, 24) +#define RFU_0X1470 0x00001470 + #define RFU_0X1470_RESERVED_0X1470 GENMASK(31, 0) +#define RFU_0X1474 0x00001474 + #define RFU_0X1474_RESERVED_0X1474 GENMASK(31, 0) +#define RFU_0X1478 0x00001478 + #define RFU_0X1478_RESERVED_0X1478 GENMASK(31, 0) +#define RFU_0X147C 0x0000147c + #define RFU_0X147C_RESERVED_0X147C GENMASK(31, 0) +#define SHU2_R1_CA_CMD0 0x000014a0 + #define SHU2_R1_CA_CMD0_RK1_TX_ARCA0_DLY GENMASK(3, 0) + #define SHU2_R1_CA_CMD0_RK1_TX_ARCA1_DLY GENMASK(7, 4) + #define SHU2_R1_CA_CMD0_RK1_TX_ARCA2_DLY GENMASK(11, 8) + #define SHU2_R1_CA_CMD0_RK1_TX_ARCA3_DLY GENMASK(15, 12) + #define SHU2_R1_CA_CMD0_RK1_TX_ARCA4_DLY GENMASK(19, 16) + #define SHU2_R1_CA_CMD0_RK1_TX_ARCA5_DLY GENMASK(23, 20) + #define SHU2_R1_CA_CMD0_RK1_TX_ARCLK_DLYB GENMASK(27, 24) + #define SHU2_R1_CA_CMD0_RK1_TX_ARCLKB_DLYB GENMASK(31, 28) +#define SHU2_R1_CA_CMD1 0x000014a4 + #define SHU2_R1_CA_CMD1_RK1_TX_ARCKE0_DLY GENMASK(3, 0) + #define SHU2_R1_CA_CMD1_RK1_TX_ARCKE1_DLY GENMASK(7, 4) + #define SHU2_R1_CA_CMD1_RK1_TX_ARCKE2_DLY GENMASK(11, 8) + #define SHU2_R1_CA_CMD1_RK1_TX_ARCS0_DLY GENMASK(15, 12) + #define SHU2_R1_CA_CMD1_RK1_TX_ARCS1_DLY GENMASK(19, 16) + #define SHU2_R1_CA_CMD1_RK1_TX_ARCS2_DLY GENMASK(23, 20) + #define SHU2_R1_CA_CMD1_RK1_TX_ARCLK_DLY GENMASK(27, 24) + #define SHU2_R1_CA_CMD1_RK1_TX_ARCLKB_DLY GENMASK(31, 28) +#define SHU2_R1_CA_CMD2 0x000014a8 + #define SHU2_R1_CA_CMD2_RG_RK1_RX_ARCA0_R_DLY GENMASK(5, 0) + #define SHU2_R1_CA_CMD2_RG_RK1_RX_ARCA0_F_DLY GENMASK(13, 8) + #define SHU2_R1_CA_CMD2_RG_RK1_RX_ARCA1_R_DLY GENMASK(21, 16) + #define SHU2_R1_CA_CMD2_RG_RK1_RX_ARCA1_F_DLY GENMASK(29, 24) +#define SHU2_R1_CA_CMD3 0x000014ac + #define SHU2_R1_CA_CMD3_RG_RK1_RX_ARCA2_R_DLY GENMASK(5, 0) + #define SHU2_R1_CA_CMD3_RG_RK1_RX_ARCA2_F_DLY GENMASK(13, 8) + #define SHU2_R1_CA_CMD3_RG_RK1_RX_ARCA3_R_DLY GENMASK(21, 16) + #define SHU2_R1_CA_CMD3_RG_RK1_RX_ARCA3_F_DLY GENMASK(29, 24) +#define SHU2_R1_CA_CMD4 0x000014b0 + #define SHU2_R1_CA_CMD4_RG_RK1_RX_ARCA4_R_DLY GENMASK(5, 0) + #define SHU2_R1_CA_CMD4_RG_RK1_RX_ARCA4_F_DLY GENMASK(13, 8) + #define SHU2_R1_CA_CMD4_RG_RK1_RX_ARCA5_R_DLY GENMASK(21, 16) + #define SHU2_R1_CA_CMD4_RG_RK1_RX_ARCA5_F_DLY GENMASK(29, 24) +#define SHU2_R1_CA_CMD5 0x000014b4 + #define SHU2_R1_CA_CMD5_RG_RK1_RX_ARCKE0_R_DLY GENMASK(5, 0) + #define SHU2_R1_CA_CMD5_RG_RK1_RX_ARCKE0_F_DLY GENMASK(13, 8) + #define SHU2_R1_CA_CMD5_RG_RK1_RX_ARCKE1_R_DLY GENMASK(21, 16) + #define SHU2_R1_CA_CMD5_RG_RK1_RX_ARCKE1_F_DLY GENMASK(29, 24) +#define SHU2_R1_CA_CMD6 0x000014b8 + #define SHU2_R1_CA_CMD6_RG_RK1_RX_ARCKE2_R_DLY GENMASK(5, 0) + #define SHU2_R1_CA_CMD6_RG_RK1_RX_ARCKE2_F_DLY GENMASK(13, 8) + #define SHU2_R1_CA_CMD6_RG_RK1_RX_ARCS0_R_DLY GENMASK(21, 16) + #define SHU2_R1_CA_CMD6_RG_RK1_RX_ARCS0_F_DLY GENMASK(29, 24) +#define SHU2_R1_CA_CMD7 0x000014bc + #define SHU2_R1_CA_CMD7_RG_RK1_RX_ARCS1_R_DLY GENMASK(5, 0) + #define SHU2_R1_CA_CMD7_RG_RK1_RX_ARCS1_F_DLY GENMASK(13, 8) + #define SHU2_R1_CA_CMD7_RG_RK1_RX_ARCS2_R_DLY GENMASK(21, 16) + #define SHU2_R1_CA_CMD7_RG_RK1_RX_ARCS2_F_DLY GENMASK(29, 24) +#define SHU2_R1_CA_CMD8 0x000014c0 + #define SHU2_R1_CA_CMD8_RG_RK1_RX_ARCLK_R_DLY GENMASK(22, 16) + #define SHU2_R1_CA_CMD8_RG_RK1_RX_ARCLK_F_DLY GENMASK(30, 24) +#define SHU2_R1_CA_CMD9 0x000014c4 + #define SHU2_R1_CA_CMD9_RG_RK1_ARPI_CS GENMASK(5, 0) + #define SHU2_R1_CA_CMD9_RG_RK1_ARPI_CMD GENMASK(13, 8) + #define SHU2_R1_CA_CMD9_RG_RK1_ARPI_CLK GENMASK(29, 24) +#define RFU_0X14C8 0x000014c8 + #define RFU_0X14C8_RESERVED_0X14C8 GENMASK(31, 0) +#define RFU_0X14CC 0x000014cc + #define RFU_0X14CC_RESERVED_0X14CC GENMASK(31, 0) +#define SHU2_R2_B0_DQ0 0x00001500 + #define SHU2_R2_B0_DQ0_RK2_TX_ARDQ0_DLY_B0 GENMASK(3, 0) + #define SHU2_R2_B0_DQ0_RK2_TX_ARDQ1_DLY_B0 GENMASK(7, 4) + #define SHU2_R2_B0_DQ0_RK2_TX_ARDQ2_DLY_B0 GENMASK(11, 8) + #define SHU2_R2_B0_DQ0_RK2_TX_ARDQ3_DLY_B0 GENMASK(15, 12) + #define SHU2_R2_B0_DQ0_RK2_TX_ARDQ4_DLY_B0 GENMASK(19, 16) + #define SHU2_R2_B0_DQ0_RK2_TX_ARDQ5_DLY_B0 GENMASK(23, 20) + #define SHU2_R2_B0_DQ0_RK2_TX_ARDQ6_DLY_B0 GENMASK(27, 24) + #define SHU2_R2_B0_DQ0_RK2_TX_ARDQ7_DLY_B0 GENMASK(31, 28) +#define SHU2_R2_B0_DQ1 0x00001504 + #define SHU2_R2_B0_DQ1_RK2_TX_ARDQM0_DLY_B0 GENMASK(3, 0) + #define SHU2_R2_B0_DQ1_RK2_TX_ARDQS0_DLYB_B0 GENMASK(19, 16) + #define SHU2_R2_B0_DQ1_RK2_TX_ARDQS0B_DLYB_B0 GENMASK(23, 20) + #define SHU2_R2_B0_DQ1_RK2_TX_ARDQS0_DLY_B0 GENMASK(27, 24) + #define SHU2_R2_B0_DQ1_RK2_TX_ARDQS0B_DLY_B0 GENMASK(31, 28) +#define SHU2_R2_B0_DQ2 0x00001508 + #define SHU2_R2_B0_DQ2_RK2_RX_ARDQ0_R_DLY_B0 GENMASK(5, 0) + #define SHU2_R2_B0_DQ2_RK2_RX_ARDQ0_F_DLY_B0 GENMASK(13, 8) + #define SHU2_R2_B0_DQ2_RK2_RX_ARDQ1_R_DLY_B0 GENMASK(21, 16) + #define SHU2_R2_B0_DQ2_RK2_RX_ARDQ1_F_DLY_B0 GENMASK(29, 24) +#define SHU2_R2_B0_DQ3 0x0000150c + #define SHU2_R2_B0_DQ3_RK2_RX_ARDQ2_R_DLY_B0 GENMASK(5, 0) + #define SHU2_R2_B0_DQ3_RK2_RX_ARDQ2_F_DLY_B0 GENMASK(13, 8) + #define SHU2_R2_B0_DQ3_RK2_RX_ARDQ3_R_DLY_B0 GENMASK(21, 16) + #define SHU2_R2_B0_DQ3_RK2_RX_ARDQ3_F_DLY_B0 GENMASK(29, 24) +#define SHU2_R2_B0_DQ4 0x00001510 + #define SHU2_R2_B0_DQ4_RK2_RX_ARDQ4_R_DLY_B0 GENMASK(5, 0) + #define SHU2_R2_B0_DQ4_RK2_RX_ARDQ4_F_DLY_B0 GENMASK(13, 8) + #define SHU2_R2_B0_DQ4_RK2_RX_ARDQ5_R_DLY_B0 GENMASK(21, 16) + #define SHU2_R2_B0_DQ4_RK2_RX_ARDQ5_F_DLY_B0 GENMASK(29, 24) +#define SHU2_R2_B0_DQ5 0x00001514 + #define SHU2_R2_B0_DQ5_RK2_RX_ARDQ6_R_DLY_B0 GENMASK(5, 0) + #define SHU2_R2_B0_DQ5_RK2_RX_ARDQ6_F_DLY_B0 GENMASK(13, 8) + #define SHU2_R2_B0_DQ5_RK2_RX_ARDQ7_R_DLY_B0 GENMASK(21, 16) + #define SHU2_R2_B0_DQ5_RK2_RX_ARDQ7_F_DLY_B0 GENMASK(29, 24) +#define SHU2_R2_B0_DQ6 0x00001518 + #define SHU2_R2_B0_DQ6_RK2_RX_ARDQM0_R_DLY_B0 GENMASK(5, 0) + #define SHU2_R2_B0_DQ6_RK2_RX_ARDQM0_F_DLY_B0 GENMASK(13, 8) + #define SHU2_R2_B0_DQ6_RK2_RX_ARDQS0_R_DLY_B0 GENMASK(22, 16) + #define SHU2_R2_B0_DQ6_RK2_RX_ARDQS0_F_DLY_B0 GENMASK(30, 24) +#define SHU2_R2_B0_DQ7 0x0000151c + #define SHU2_R2_B0_DQ7_RK2_ARPI_DQ_B0 GENMASK(13, 8) + #define SHU2_R2_B0_DQ7_RK2_ARPI_DQM_B0 GENMASK(21, 16) + #define SHU2_R2_B0_DQ7_RK2_ARPI_PBYTE_B0 GENMASK(29, 24) +#define RFU_0X1520 0x00001520 + #define RFU_0X1520_RESERVED_0X1520 GENMASK(31, 0) +#define RFU_0X1524 0x00001524 + #define RFU_0X1524_RESERVED_0X1524 GENMASK(31, 0) +#define RFU_0X1528 0x00001528 + #define RFU_0X1528_RESERVED_0X1528 GENMASK(31, 0) +#define RFU_0X152C 0x0000152c + #define RFU_0X152C_RESERVED_0X152C GENMASK(31, 0) +#define SHU2_R2_B1_DQ0 0x00001550 + #define SHU2_R2_B1_DQ0_RK2_TX_ARDQ0_DLY_B1 GENMASK(3, 0) + #define SHU2_R2_B1_DQ0_RK2_TX_ARDQ1_DLY_B1 GENMASK(7, 4) + #define SHU2_R2_B1_DQ0_RK2_TX_ARDQ2_DLY_B1 GENMASK(11, 8) + #define SHU2_R2_B1_DQ0_RK2_TX_ARDQ3_DLY_B1 GENMASK(15, 12) + #define SHU2_R2_B1_DQ0_RK2_TX_ARDQ4_DLY_B1 GENMASK(19, 16) + #define SHU2_R2_B1_DQ0_RK2_TX_ARDQ5_DLY_B1 GENMASK(23, 20) + #define SHU2_R2_B1_DQ0_RK2_TX_ARDQ6_DLY_B1 GENMASK(27, 24) + #define SHU2_R2_B1_DQ0_RK2_TX_ARDQ7_DLY_B1 GENMASK(31, 28) +#define SHU2_R2_B1_DQ1 0x00001554 + #define SHU2_R2_B1_DQ1_RK2_TX_ARDQM0_DLY_B1 GENMASK(3, 0) + #define SHU2_R2_B1_DQ1_RK2_TX_ARDQS0_DLYB_B1 GENMASK(19, 16) + #define SHU2_R2_B1_DQ1_RK2_TX_ARDQS0B_DLYB_B1 GENMASK(23, 20) + #define SHU2_R2_B1_DQ1_RK2_TX_ARDQS0_DLY_B1 GENMASK(27, 24) + #define SHU2_R2_B1_DQ1_RK2_TX_ARDQS0B_DLY_B1 GENMASK(31, 28) +#define SHU2_R2_B1_DQ2 0x00001558 + #define SHU2_R2_B1_DQ2_RK2_RX_ARDQ0_R_DLY_B1 GENMASK(5, 0) + #define SHU2_R2_B1_DQ2_RK2_RX_ARDQ0_F_DLY_B1 GENMASK(13, 8) + #define SHU2_R2_B1_DQ2_RK2_RX_ARDQ1_R_DLY_B1 GENMASK(21, 16) + #define SHU2_R2_B1_DQ2_RK2_RX_ARDQ1_F_DLY_B1 GENMASK(29, 24) +#define SHU2_R2_B1_DQ3 0x0000155c + #define SHU2_R2_B1_DQ3_RK2_RX_ARDQ2_R_DLY_B1 GENMASK(5, 0) + #define SHU2_R2_B1_DQ3_RK2_RX_ARDQ2_F_DLY_B1 GENMASK(13, 8) + #define SHU2_R2_B1_DQ3_RK2_RX_ARDQ3_R_DLY_B1 GENMASK(21, 16) + #define SHU2_R2_B1_DQ3_RK2_RX_ARDQ3_F_DLY_B1 GENMASK(29, 24) +#define SHU2_R2_B1_DQ4 0x00001560 + #define SHU2_R2_B1_DQ4_RK2_RX_ARDQ4_R_DLY_B1 GENMASK(5, 0) + #define SHU2_R2_B1_DQ4_RK2_RX_ARDQ4_F_DLY_B1 GENMASK(13, 8) + #define SHU2_R2_B1_DQ4_RK2_RX_ARDQ5_R_DLY_B1 GENMASK(21, 16) + #define SHU2_R2_B1_DQ4_RK2_RX_ARDQ5_F_DLY_B1 GENMASK(29, 24) +#define SHU2_R2_B1_DQ5 0x00001564 + #define SHU2_R2_B1_DQ5_RK2_RX_ARDQ6_R_DLY_B1 GENMASK(5, 0) + #define SHU2_R2_B1_DQ5_RK2_RX_ARDQ6_F_DLY_B1 GENMASK(13, 8) + #define SHU2_R2_B1_DQ5_RK2_RX_ARDQ7_R_DLY_B1 GENMASK(21, 16) + #define SHU2_R2_B1_DQ5_RK2_RX_ARDQ7_F_DLY_B1 GENMASK(29, 24) +#define SHU2_R2_B1_DQ6 0x00001568 + #define SHU2_R2_B1_DQ6_RK2_RX_ARDQM0_R_DLY_B1 GENMASK(5, 0) + #define SHU2_R2_B1_DQ6_RK2_RX_ARDQM0_F_DLY_B1 GENMASK(13, 8) + #define SHU2_R2_B1_DQ6_RK2_RX_ARDQS0_R_DLY_B1 GENMASK(22, 16) + #define SHU2_R2_B1_DQ6_RK2_RX_ARDQS0_F_DLY_B1 GENMASK(30, 24) +#define SHU2_R2_B1_DQ7 0x0000156c + #define SHU2_R2_B1_DQ7_RK2_ARPI_DQ_B1 GENMASK(13, 8) + #define SHU2_R2_B1_DQ7_RK2_ARPI_DQM_B1 GENMASK(21, 16) + #define SHU2_R2_B1_DQ7_RK2_ARPI_PBYTE_B1 GENMASK(29, 24) +#define RFU_0X1570 0x00001570 + #define RFU_0X1570_RESERVED_0X1570 GENMASK(31, 0) +#define RFU_0X1574 0x00001574 + #define RFU_0X1574_RESERVED_0X1574 GENMASK(31, 0) +#define RFU_0X1578 0x00001578 + #define RFU_0X1578_RESERVED_0X1578 GENMASK(31, 0) +#define RFU_0X157C 0x0000157c + #define RFU_0X157C_RESERVED_0X157C GENMASK(31, 0) +#define SHU2_R2_CA_CMD0 0x000015a0 + #define SHU2_R2_CA_CMD0_RK2_TX_ARCA0_DLY GENMASK(3, 0) + #define SHU2_R2_CA_CMD0_RK2_TX_ARCA1_DLY GENMASK(7, 4) + #define SHU2_R2_CA_CMD0_RK2_TX_ARCA2_DLY GENMASK(11, 8) + #define SHU2_R2_CA_CMD0_RK2_TX_ARCA3_DLY GENMASK(15, 12) + #define SHU2_R2_CA_CMD0_RK2_TX_ARCA4_DLY GENMASK(19, 16) + #define SHU2_R2_CA_CMD0_RK2_TX_ARCA5_DLY GENMASK(23, 20) + #define SHU2_R2_CA_CMD0_RK2_TX_ARCLK_DLYB GENMASK(27, 24) + #define SHU2_R2_CA_CMD0_RK2_TX_ARCLKB_DLYB GENMASK(31, 28) +#define SHU2_R2_CA_CMD1 0x000015a4 + #define SHU2_R2_CA_CMD1_RK2_TX_ARCKE0_DLY GENMASK(3, 0) + #define SHU2_R2_CA_CMD1_RK2_TX_ARCKE1_DLY GENMASK(7, 4) + #define SHU2_R2_CA_CMD1_RK2_TX_ARCKE2_DLY GENMASK(11, 8) + #define SHU2_R2_CA_CMD1_RK2_TX_ARCS0_DLY GENMASK(15, 12) + #define SHU2_R2_CA_CMD1_RK2_TX_ARCS1_DLY GENMASK(19, 16) + #define SHU2_R2_CA_CMD1_RK2_TX_ARCS2_DLY GENMASK(23, 20) + #define SHU2_R2_CA_CMD1_RK2_TX_ARCLK_DLY GENMASK(27, 24) + #define SHU2_R2_CA_CMD1_RK2_TX_ARCLKB_DLY GENMASK(31, 28) +#define SHU2_R2_CA_CMD2 0x000015a8 + #define SHU2_R2_CA_CMD2_RG_RK2_RX_ARCA0_R_DLY GENMASK(5, 0) + #define SHU2_R2_CA_CMD2_RG_RK2_RX_ARCA0_F_DLY GENMASK(13, 8) + #define SHU2_R2_CA_CMD2_RG_RK2_RX_ARCA1_R_DLY GENMASK(21, 16) + #define SHU2_R2_CA_CMD2_RG_RK2_RX_ARCA1_F_DLY GENMASK(29, 24) +#define SHU2_R2_CA_CMD3 0x000015ac + #define SHU2_R2_CA_CMD3_RG_RK2_RX_ARCA2_R_DLY GENMASK(5, 0) + #define SHU2_R2_CA_CMD3_RG_RK2_RX_ARCA2_F_DLY GENMASK(13, 8) + #define SHU2_R2_CA_CMD3_RG_RK2_RX_ARCA3_R_DLY GENMASK(21, 16) + #define SHU2_R2_CA_CMD3_RG_RK2_RX_ARCA3_F_DLY GENMASK(29, 24) +#define SHU2_R2_CA_CMD4 0x000015b0 + #define SHU2_R2_CA_CMD4_RG_RK2_RX_ARCA4_R_DLY GENMASK(5, 0) + #define SHU2_R2_CA_CMD4_RG_RK2_RX_ARCA4_F_DLY GENMASK(13, 8) + #define SHU2_R2_CA_CMD4_RG_RK2_RX_ARCA5_R_DLY GENMASK(21, 16) + #define SHU2_R2_CA_CMD4_RG_RK2_RX_ARCA5_F_DLY GENMASK(29, 24) +#define SHU2_R2_CA_CMD5 0x000015b4 + #define SHU2_R2_CA_CMD5_RG_RK2_RX_ARCKE0_R_DLY GENMASK(5, 0) + #define SHU2_R2_CA_CMD5_RG_RK2_RX_ARCKE0_F_DLY GENMASK(13, 8) + #define SHU2_R2_CA_CMD5_RG_RK2_RX_ARCKE1_R_DLY GENMASK(21, 16) + #define SHU2_R2_CA_CMD5_RG_RK2_RX_ARCKE1_F_DLY GENMASK(29, 24) +#define SHU2_R2_CA_CMD6 0x000015b8 + #define SHU2_R2_CA_CMD6_RG_RK2_RX_ARCKE2_R_DLY GENMASK(5, 0) + #define SHU2_R2_CA_CMD6_RG_RK2_RX_ARCKE2_F_DLY GENMASK(13, 8) + #define SHU2_R2_CA_CMD6_RG_RK2_RX_ARCS0_R_DLY GENMASK(21, 16) + #define SHU2_R2_CA_CMD6_RG_RK2_RX_ARCS0_F_DLY GENMASK(29, 24) +#define SHU2_R2_CA_CMD7 0x000015bc + #define SHU2_R2_CA_CMD7_RG_RK2_RX_ARCS1_R_DLY GENMASK(5, 0) + #define SHU2_R2_CA_CMD7_RG_RK2_RX_ARCS1_F_DLY GENMASK(13, 8) + #define SHU2_R2_CA_CMD7_RG_RK2_RX_ARCS2_R_DLY GENMASK(21, 16) + #define SHU2_R2_CA_CMD7_RG_RK2_RX_ARCS2_F_DLY GENMASK(29, 24) +#define SHU2_R2_CA_CMD8 0x000015c0 + #define SHU2_R2_CA_CMD8_RG_RK2_RX_ARCLK_R_DLY GENMASK(22, 16) + #define SHU2_R2_CA_CMD8_RG_RK2_RX_ARCLK_F_DLY GENMASK(30, 24) +#define SHU2_R2_CA_CMD9 0x000015c4 + #define SHU2_R2_CA_CMD9_RG_RK2_ARPI_CS GENMASK(5, 0) + #define SHU2_R2_CA_CMD9_RG_RK2_ARPI_CMD GENMASK(13, 8) + #define SHU2_R2_CA_CMD9_RG_RK2_ARPI_CLK GENMASK(29, 24) +#define RFU_0X15C8 0x000015c8 + #define RFU_0X15C8_RESERVED_0X15C8 GENMASK(31, 0) +#define RFU_0X15CC 0x000015cc + #define RFU_0X15CC_RESERVED_0X15CC GENMASK(31, 0) +#define SHU3_B0_DQ0 0x00001600 + #define SHU3_B0_DQ0_RG_TX_ARDQS0_PRE_EN_B0 BIT(4) + #define SHU3_B0_DQ0_RG_TX_ARDQS0_DRVP_PRE_B0 GENMASK(10, 8) + #define SHU3_B0_DQ0_RG_TX_ARDQS0_DRVN_PRE_B0 GENMASK(14, 12) + #define SHU3_B0_DQ0_RG_TX_ARDQ_PRE_EN_B0 BIT(20) + #define SHU3_B0_DQ0_RG_TX_ARDQ_DRVP_PRE_B0 GENMASK(26, 24) + #define SHU3_B0_DQ0_RG_TX_ARDQ_DRVN_PRE_B0 GENMASK(30, 28) + #define SHU3_B0_DQ0_R_LP4Y_WDN_MODE_DQS0 BIT(31) +#define SHU3_B0_DQ1 0x00001604 + #define SHU3_B0_DQ1_RG_TX_ARDQ_DRVP_B0 GENMASK(4, 0) + #define SHU3_B0_DQ1_RG_TX_ARDQ_DRVN_B0 GENMASK(12, 8) + #define SHU3_B0_DQ1_RG_TX_ARDQ_ODTP_B0 GENMASK(20, 16) + #define SHU3_B0_DQ1_RG_TX_ARDQ_ODTN_B0 GENMASK(28, 24) +#define SHU3_B0_DQ2 0x00001608 + #define SHU3_B0_DQ2_RG_TX_ARDQS0_DRVP_B0 GENMASK(4, 0) + #define SHU3_B0_DQ2_RG_TX_ARDQS0_DRVN_B0 GENMASK(12, 8) + #define SHU3_B0_DQ2_RG_TX_ARDQS0_ODTP_B0 GENMASK(20, 16) + #define SHU3_B0_DQ2_RG_TX_ARDQS0_ODTN_B0 GENMASK(28, 24) +#define SHU3_B0_DQ3 0x0000160c + #define SHU3_B0_DQ3_RG_TX_ARDQS0_PU_B0 GENMASK(1, 0) + #define SHU3_B0_DQ3_RG_TX_ARDQS0_PU_PRE_B0 GENMASK(3, 2) + #define SHU3_B0_DQ3_RG_TX_ARDQS0_PDB_B0 GENMASK(5, 4) + #define SHU3_B0_DQ3_RG_TX_ARDQS0_PDB_PRE_B0 GENMASK(7, 6) + #define SHU3_B0_DQ3_RG_TX_ARDQ_PU_B0 GENMASK(9, 8) + #define SHU3_B0_DQ3_RG_TX_ARDQ_PU_PRE_B0 GENMASK(11, 10) + #define SHU3_B0_DQ3_RG_TX_ARDQ_PDB_B0 GENMASK(13, 12) + #define SHU3_B0_DQ3_RG_TX_ARDQ_PDB_PRE_B0 GENMASK(15, 14) +#define SHU3_B0_DQ4 0x00001610 + #define SHU3_B0_DQ4_RG_ARPI_AA_MCK_DL_B0 GENMASK(5, 0) + #define SHU3_B0_DQ4_RG_ARPI_AA_MCK_FB_DL_B0 GENMASK(13, 8) + #define SHU3_B0_DQ4_RG_ARPI_DA_MCK_FB_DL_B0 GENMASK(21, 16) +#define SHU3_B0_DQ5 0x00001614 + #define SHU3_B0_DQ5_RG_RX_ARDQ_VREF_SEL_B0 GENMASK(5, 0) + #define SHU3_B0_DQ5_RG_RX_ARDQ_VREF_BYPASS_B0 BIT(6) + #define SHU3_B0_DQ5_RG_ARPI_FB_B0 GENMASK(13, 8) + #define SHU3_B0_DQ5_RG_RX_ARDQS0_DQSIEN_DLY_B0 GENMASK(18, 16) + #define SHU3_B0_DQ5_DA_RX_ARDQS_DQSIEN_RB_DLY_B0 BIT(19) + #define SHU3_B0_DQ5_RG_RX_ARDQS0_DVS_DLY_B0 GENMASK(22, 20) + #define SHU3_B0_DQ5_RG_ARPI_MCTL_B0 GENMASK(29, 24) +#define SHU3_B0_DQ6 0x00001618 + #define SHU3_B0_DQ6_RG_ARPI_OFFSET_DQSIEN_B0 GENMASK(5, 0) + #define SHU3_B0_DQ6_RG_ARPI_RESERVE_B0 GENMASK(21, 6) + #define SHU3_B0_DQ6_RG_ARPI_MIDPI_CAP_SEL_B0 GENMASK(23, 22) + #define SHU3_B0_DQ6_RG_ARPI_MIDPI_VTH_SEL_B0 GENMASK(25, 24) + #define SHU3_B0_DQ6_RG_ARPI_MIDPI_EN_B0 BIT(26) + #define SHU3_B0_DQ6_RG_ARPI_MIDPI_CKDIV4_EN_B0 BIT(27) + #define SHU3_B0_DQ6_RG_ARPI_CAP_SEL_B0 GENMASK(29, 28) + #define SHU3_B0_DQ6_RG_ARPI_MIDPI_BYPASS_EN_B0 BIT(31) +#define SHU3_B0_DQ7 0x0000161c + #define SHU3_B0_DQ7_R_DMRANKRXDVS_B0 GENMASK(3, 0) + #define SHU3_B0_DQ7_MIDPI_ENABLE BIT(4) + #define SHU3_B0_DQ7_MIDPI_DIV4_ENABLE BIT(5) + #define SHU3_B0_DQ7_R_DMDQMDBI_EYE_SHU_B0 BIT(6) + #define SHU3_B0_DQ7_R_DMDQMDBI_SHU_B0 BIT(7) + #define SHU3_B0_DQ7_R_DMRXDVS_DQM_FLAGSEL_B0 GENMASK(11, 8) + #define SHU3_B0_DQ7_R_DMRXDVS_PBYTE_FLAG_OPT_B0 BIT(12) + #define SHU3_B0_DQ7_R_DMRXDVS_PBYTE_DQM_EN_B0 BIT(13) + #define SHU3_B0_DQ7_R_DMRXTRACK_DQM_EN_B0 BIT(14) + #define SHU3_B0_DQ7_R_DMRODTEN_B0 BIT(15) + #define SHU3_B0_DQ7_R_DMARPI_CG_FB2DLL_DCM_EN_B0 BIT(16) + #define SHU3_B0_DQ7_R_DMTX_ARPI_CG_DQ_NEW_B0 BIT(17) + #define SHU3_B0_DQ7_R_DMTX_ARPI_CG_DQS_NEW_B0 BIT(18) + #define SHU3_B0_DQ7_R_DMTX_ARPI_CG_DQM_NEW_B0 BIT(19) + #define SHU3_B0_DQ7_R_LP4Y_SDN_MODE_DQS0 BIT(20) + #define SHU3_B0_DQ7_R_DMRXRANK_DQ_EN_B0 BIT(24) + #define SHU3_B0_DQ7_R_DMRXRANK_DQ_LAT_B0 GENMASK(27, 25) + #define SHU3_B0_DQ7_R_DMRXRANK_DQS_EN_B0 BIT(28) + #define SHU3_B0_DQ7_R_DMRXRANK_DQS_LAT_B0 GENMASK(31, 29) +#define SHU3_B0_DQ8 0x00001620 + #define SHU3_B0_DQ8_R_DMRXDVS_UPD_FORCE_CYC_B0 GENMASK(14, 0) + #define SHU3_B0_DQ8_R_DMRXDVS_UPD_FORCE_EN_B0 BIT(15) + #define SHU3_B0_DQ8_R_DMRANK_RXDLY_PIPE_CG_IG_B0 BIT(19) + #define SHU3_B0_DQ8_R_RMRODTEN_CG_IG_B0 BIT(20) + #define SHU3_B0_DQ8_R_RMRX_TOPHY_CG_IG_B0 BIT(21) + #define SHU3_B0_DQ8_R_DMRXDVS_RDSEL_PIPE_CG_IG_B0 BIT(22) + #define SHU3_B0_DQ8_R_DMRXDVS_RDSEL_TOG_PIPE_CG_IG_B0 BIT(23) + #define SHU3_B0_DQ8_R_DMRXDLY_CG_IG_B0 BIT(24) + #define SHU3_B0_DQ8_R_DMSTBEN_SYNC_CG_IG_B0 BIT(25) + #define SHU3_B0_DQ8_R_DMDQSIEN_FLAG_SYNC_CG_IG_B0 BIT(26) + #define SHU3_B0_DQ8_R_DMDQSIEN_FLAG_PIPE_CG_IG_B0 BIT(27) + #define SHU3_B0_DQ8_R_DMDQSIEN_RDSEL_PIPE_CG_IG_B0 BIT(28) + #define SHU3_B0_DQ8_R_DMDQSIEN_RDSEL_TOG_PIPE_CG_IG_B0 BIT(29) + #define SHU3_B0_DQ8_R_DMRANK_PIPE_CG_IG_B0 BIT(30) + #define SHU3_B0_DQ8_R_DMRANK_CHG_PIPE_CG_IG_B0 BIT(31) +#define SHU3_B0_DQ9 0x00001624 + #define SHU3_B0_DQ9_RESERVED_0X1624 GENMASK(31, 0) +#define SHU3_B0_DQ10 0x00001628 + #define SHU3_B0_DQ10_RESERVED_0X1628 GENMASK(31, 0) +#define SHU3_B0_DQ11 0x0000162c + #define SHU3_B0_DQ11_RESERVED_0X162C GENMASK(31, 0) +#define SHU3_B0_DQ12 0x00001630 + #define SHU3_B0_DQ12_RESERVED_0X1630 GENMASK(31, 0) +#define SHU3_B0_DLL0 0x00001634 + #define SHU3_B0_DLL0_RG_ARPISM_MCK_SEL_B0_SHU BIT(0) + #define SHU3_B0_DLL0_B0_DLL0_RFU BIT(3) + #define SHU3_B0_DLL0_RG_ARDLL_FAST_PSJP_B0 BIT(4) + #define SHU3_B0_DLL0_RG_ARDLL_PHDIV_B0 BIT(9) + #define SHU3_B0_DLL0_RG_ARDLL_PHJUMP_EN_B0 BIT(10) + #define SHU3_B0_DLL0_RG_ARDLL_P_GAIN_B0 GENMASK(15, 12) + #define SHU3_B0_DLL0_RG_ARDLL_IDLECNT_B0 GENMASK(19, 16) + #define SHU3_B0_DLL0_RG_ARDLL_GAIN_B0 GENMASK(23, 20) + #define SHU3_B0_DLL0_RG_ARDLL_PHDET_IN_SWAP_B0 BIT(30) + #define SHU3_B0_DLL0_RG_ARDLL_PHDET_OUT_SEL_B0 BIT(31) +#define SHU3_B0_DLL1 0x00001638 + #define SHU3_B0_DLL1_RG_ARDLL_FASTPJ_CK_SEL_B0 BIT(0) + #define SHU3_B0_DLL1_RG_ARDLL_PS_EN_B0 BIT(1) + #define SHU3_B0_DLL1_RG_ARDLL_PD_CK_SEL_B0 BIT(2) + #define SHU3_B0_DLL1_RG_ARDQ_REV_B0 GENMASK(31, 8) +#define SHU3_B1_DQ0 0x00001680 + #define SHU3_B1_DQ0_RG_TX_ARDQS0_PRE_EN_B1 BIT(4) + #define SHU3_B1_DQ0_RG_TX_ARDQS0_DRVP_PRE_B1 GENMASK(10, 8) + #define SHU3_B1_DQ0_RG_TX_ARDQS0_DRVN_PRE_B1 GENMASK(14, 12) + #define SHU3_B1_DQ0_RG_TX_ARDQ_PRE_EN_B1 BIT(20) + #define SHU3_B1_DQ0_RG_TX_ARDQ_DRVP_PRE_B1 GENMASK(26, 24) + #define SHU3_B1_DQ0_RG_TX_ARDQ_DRVN_PRE_B1 GENMASK(30, 28) + #define SHU3_B1_DQ0_R_LP4Y_WDN_MODE_DQS1 BIT(31) +#define SHU3_B1_DQ1 0x00001684 + #define SHU3_B1_DQ1_RG_TX_ARDQ_DRVP_B1 GENMASK(4, 0) + #define SHU3_B1_DQ1_RG_TX_ARDQ_DRVN_B1 GENMASK(12, 8) + #define SHU3_B1_DQ1_RG_TX_ARDQ_ODTP_B1 GENMASK(20, 16) + #define SHU3_B1_DQ1_RG_TX_ARDQ_ODTN_B1 GENMASK(28, 24) +#define SHU3_B1_DQ2 0x00001688 + #define SHU3_B1_DQ2_RG_TX_ARDQS0_DRVP_B1 GENMASK(4, 0) + #define SHU3_B1_DQ2_RG_TX_ARDQS0_DRVN_B1 GENMASK(12, 8) + #define SHU3_B1_DQ2_RG_TX_ARDQS0_ODTP_B1 GENMASK(20, 16) + #define SHU3_B1_DQ2_RG_TX_ARDQS0_ODTN_B1 GENMASK(28, 24) +#define SHU3_B1_DQ3 0x0000168c + #define SHU3_B1_DQ3_RG_TX_ARDQS0_PU_B1 GENMASK(1, 0) + #define SHU3_B1_DQ3_RG_TX_ARDQS0_PU_PRE_B1 GENMASK(3, 2) + #define SHU3_B1_DQ3_RG_TX_ARDQS0_PDB_B1 GENMASK(5, 4) + #define SHU3_B1_DQ3_RG_TX_ARDQS0_PDB_PRE_B1 GENMASK(7, 6) + #define SHU3_B1_DQ3_RG_TX_ARDQ_PU_B1 GENMASK(9, 8) + #define SHU3_B1_DQ3_RG_TX_ARDQ_PU_PRE_B1 GENMASK(11, 10) + #define SHU3_B1_DQ3_RG_TX_ARDQ_PDB_B1 GENMASK(13, 12) + #define SHU3_B1_DQ3_RG_TX_ARDQ_PDB_PRE_B1 GENMASK(15, 14) +#define SHU3_B1_DQ4 0x00001690 + #define SHU3_B1_DQ4_RG_ARPI_AA_MCK_DL_B1 GENMASK(5, 0) + #define SHU3_B1_DQ4_RG_ARPI_AA_MCK_FB_DL_B1 GENMASK(13, 8) + #define SHU3_B1_DQ4_RG_ARPI_DA_MCK_FB_DL_B1 GENMASK(21, 16) +#define SHU3_B1_DQ5 0x00001694 + #define SHU3_B1_DQ5_RG_RX_ARDQ_VREF_SEL_B1 GENMASK(5, 0) + #define SHU3_B1_DQ5_RG_RX_ARDQ_VREF_BYPASS_B1 BIT(6) + #define SHU3_B1_DQ5_RG_ARPI_FB_B1 GENMASK(13, 8) + #define SHU3_B1_DQ5_RG_RX_ARDQS0_DQSIEN_DLY_B1 GENMASK(18, 16) + #define SHU3_B1_DQ5_DA_RX_ARDQS_DQSIEN_RB_DLY_B1 BIT(19) + #define SHU3_B1_DQ5_RG_RX_ARDQS0_DVS_DLY_B1 GENMASK(22, 20) + #define SHU3_B1_DQ5_RG_ARPI_MCTL_B1 GENMASK(29, 24) +#define SHU3_B1_DQ6 0x00001698 + #define SHU3_B1_DQ6_RG_ARPI_OFFSET_DQSIEN_B1 GENMASK(5, 0) + #define SHU3_B1_DQ6_RG_ARPI_RESERVE_B1 GENMASK(21, 6) + #define SHU3_B1_DQ6_RG_ARPI_MIDPI_CAP_SEL_B1 GENMASK(23, 22) + #define SHU3_B1_DQ6_RG_ARPI_MIDPI_VTH_SEL_B1 GENMASK(25, 24) + #define SHU3_B1_DQ6_RG_ARPI_MIDPI_EN_B1 BIT(26) + #define SHU3_B1_DQ6_RG_ARPI_MIDPI_CKDIV4_EN_B1 BIT(27) + #define SHU3_B1_DQ6_RG_ARPI_CAP_SEL_B1 GENMASK(29, 28) + #define SHU3_B1_DQ6_RG_ARPI_MIDPI_BYPASS_EN_B1 BIT(31) +#define SHU3_B1_DQ7 0x0000169c + #define SHU3_B1_DQ7_R_DMRANKRXDVS_B1 GENMASK(3, 0) + #define SHU3_B1_DQ7_R_DMDQMDBI_EYE_SHU_B1 BIT(6) + #define SHU3_B1_DQ7_R_DMDQMDBI_SHU_B1 BIT(7) + #define SHU3_B1_DQ7_R_DMRXDVS_DQM_FLAGSEL_B1 GENMASK(11, 8) + #define SHU3_B1_DQ7_R_DMRXDVS_PBYTE_FLAG_OPT_B1 BIT(12) + #define SHU3_B1_DQ7_R_DMRXDVS_PBYTE_DQM_EN_B1 BIT(13) + #define SHU3_B1_DQ7_R_DMRXTRACK_DQM_EN_B1 BIT(14) + #define SHU3_B1_DQ7_R_DMRODTEN_B1 BIT(15) + #define SHU3_B1_DQ7_R_DMARPI_CG_FB2DLL_DCM_EN_B1 BIT(16) + #define SHU3_B1_DQ7_R_DMTX_ARPI_CG_DQ_NEW_B1 BIT(17) + #define SHU3_B1_DQ7_R_DMTX_ARPI_CG_DQS_NEW_B1 BIT(18) + #define SHU3_B1_DQ7_R_DMTX_ARPI_CG_DQM_NEW_B1 BIT(19) + #define SHU3_B1_DQ7_R_LP4Y_SDN_MODE_DQS1 BIT(20) + #define SHU3_B1_DQ7_R_DMRXRANK_DQ_EN_B1 BIT(24) + #define SHU3_B1_DQ7_R_DMRXRANK_DQ_LAT_B1 GENMASK(27, 25) + #define SHU3_B1_DQ7_R_DMRXRANK_DQS_EN_B1 BIT(28) + #define SHU3_B1_DQ7_R_DMRXRANK_DQS_LAT_B1 GENMASK(31, 29) +#define SHU3_B1_DQ8 0x000016a0 + #define SHU3_B1_DQ8_R_DMRXDVS_UPD_FORCE_CYC_B1 GENMASK(14, 0) + #define SHU3_B1_DQ8_R_DMRXDVS_UPD_FORCE_EN_B1 BIT(15) + #define SHU3_B1_DQ8_R_DMRANK_RXDLY_PIPE_CG_IG_B1 BIT(19) + #define SHU3_B1_DQ8_R_RMRODTEN_CG_IG_B1 BIT(20) + #define SHU3_B1_DQ8_R_RMRX_TOPHY_CG_IG_B1 BIT(21) + #define SHU3_B1_DQ8_R_DMRXDVS_RDSEL_PIPE_CG_IG_B1 BIT(22) + #define SHU3_B1_DQ8_R_DMRXDVS_RDSEL_TOG_PIPE_CG_IG_B1 BIT(23) + #define SHU3_B1_DQ8_R_DMRXDLY_CG_IG_B1 BIT(24) + #define SHU3_B1_DQ8_R_DMSTBEN_SYNC_CG_IG_B1 BIT(25) + #define SHU3_B1_DQ8_R_DMDQSIEN_FLAG_SYNC_CG_IG_B1 BIT(26) + #define SHU3_B1_DQ8_R_DMDQSIEN_FLAG_PIPE_CG_IG_B1 BIT(27) + #define SHU3_B1_DQ8_R_DMDQSIEN_RDSEL_PIPE_CG_IG_B1 BIT(28) + #define SHU3_B1_DQ8_R_DMDQSIEN_RDSEL_TOG_PIPE_CG_IG_B1 BIT(29) + #define SHU3_B1_DQ8_R_DMRANK_PIPE_CG_IG_B1 BIT(30) + #define SHU3_B1_DQ8_R_DMRANK_CHG_PIPE_CG_IG_B1 BIT(31) +#define SHU3_B1_DQ9 0x000016a4 + #define SHU3_B1_DQ9_RESERVED_0X16A4 GENMASK(31, 0) +#define SHU3_B1_DQ10 0x000016a8 + #define SHU3_B1_DQ10_RESERVED_0X16A8 GENMASK(31, 0) +#define SHU3_B1_DQ11 0x000016ac + #define SHU3_B1_DQ11_RESERVED_0X16AC GENMASK(31, 0) +#define SHU3_B1_DQ12 0x000016b0 + #define SHU3_B1_DQ12_RESERVED_0X16B0 GENMASK(31, 0) +#define SHU3_B1_DLL0 0x000016b4 + #define SHU3_B1_DLL0_RG_ARPISM_MCK_SEL_B1_SHU BIT(0) + #define SHU3_B1_DLL0_B1_DLL0_RFU BIT(3) + #define SHU3_B1_DLL0_RG_ARDLL_FAST_PSJP_B1 BIT(4) + #define SHU3_B1_DLL0_RG_ARDLL_PHDIV_B1 BIT(9) + #define SHU3_B1_DLL0_RG_ARDLL_PHJUMP_EN_B1 BIT(10) + #define SHU3_B1_DLL0_RG_ARDLL_P_GAIN_B1 GENMASK(15, 12) + #define SHU3_B1_DLL0_RG_ARDLL_IDLECNT_B1 GENMASK(19, 16) + #define SHU3_B1_DLL0_RG_ARDLL_GAIN_B1 GENMASK(23, 20) + #define SHU3_B1_DLL0_RG_ARDLL_PHDET_IN_SWAP_B1 BIT(30) + #define SHU3_B1_DLL0_RG_ARDLL_PHDET_OUT_SEL_B1 BIT(31) +#define SHU3_B1_DLL1 0x000016b8 + #define SHU3_B1_DLL1_RG_ARDLL_FASTPJ_CK_SEL_B1 BIT(0) + #define SHU3_B1_DLL1_RG_ARDLL_PS_EN_B1 BIT(1) + #define SHU3_B1_DLL1_RG_ARDLL_PD_CK_SEL_B1 BIT(2) + #define SHU3_B1_DLL1_RG_ARDQ_REV_B1 GENMASK(31, 8) +#define SHU3_CA_CMD0 0x00001700 + #define SHU3_CA_CMD0_RG_TX_ARCLK_PRE_EN BIT(4) + #define SHU3_CA_CMD0_RG_TX_ARCLK_DRVP_PRE GENMASK(10, 8) + #define SHU3_CA_CMD0_RG_TX_ARCLK_DRVN_PRE GENMASK(14, 12) + #define SHU3_CA_CMD0_RG_CGEN_FMEM_CK_CG_DLL BIT(17) + #define SHU3_CA_CMD0_RG_FB_CK_MUX GENMASK(19, 18) + #define SHU3_CA_CMD0_RG_TX_ARCMD_PRE_EN BIT(20) + #define SHU3_CA_CMD0_RG_TX_ARCMD_DRVP_PRE GENMASK(26, 24) + #define SHU3_CA_CMD0_RG_TX_ARCMD_DRVN_PRE GENMASK(30, 28) + #define SHU3_CA_CMD0_R_LP4Y_WDN_MODE_CLK BIT(31) +#define SHU3_CA_CMD1 0x00001704 + #define SHU3_CA_CMD1_RG_TX_ARCMD_DRVP GENMASK(4, 0) + #define SHU3_CA_CMD1_RG_TX_ARCMD_DRVN GENMASK(12, 8) + #define SHU3_CA_CMD1_RG_TX_ARCMD_ODTP GENMASK(20, 16) + #define SHU3_CA_CMD1_RG_TX_ARCMD_ODTN GENMASK(28, 24) +#define SHU3_CA_CMD2 0x00001708 + #define SHU3_CA_CMD2_RG_TX_ARCLK_DRVP GENMASK(4, 0) + #define SHU3_CA_CMD2_RG_TX_ARCLK_DRVN GENMASK(12, 8) + #define SHU3_CA_CMD2_RG_TX_ARCLK_ODTP GENMASK(20, 16) + #define SHU3_CA_CMD2_RG_TX_ARCLK_ODTN GENMASK(28, 24) +#define SHU3_CA_CMD3 0x0000170c + #define SHU3_CA_CMD3_RG_TX_ARCLK_PU GENMASK(1, 0) + #define SHU3_CA_CMD3_RG_TX_ARCLK_PU_PRE GENMASK(3, 2) + #define SHU3_CA_CMD3_RG_TX_ARCLK_PDB GENMASK(5, 4) + #define SHU3_CA_CMD3_RG_TX_ARCLK_PDB_PRE GENMASK(7, 6) + #define SHU3_CA_CMD3_RG_TX_ARCMD_PU GENMASK(9, 8) + #define SHU3_CA_CMD3_RG_TX_ARCMD_PU_PRE GENMASK(11, 10) + #define SHU3_CA_CMD3_RG_TX_ARCMD_PDB GENMASK(13, 12) + #define SHU3_CA_CMD3_RG_TX_ARCMD_PDB_PRE GENMASK(15, 14) +#define SHU3_CA_CMD4 0x00001710 + #define SHU3_CA_CMD4_RG_ARPI_AA_MCK_DL_CA GENMASK(5, 0) + #define SHU3_CA_CMD4_RG_ARPI_AA_MCK_FB_DL_CA GENMASK(13, 8) + #define SHU3_CA_CMD4_RG_ARPI_DA_MCK_FB_DL_CA GENMASK(21, 16) +#define SHU3_CA_CMD5 0x00001714 + #define SHU3_CA_CMD5_RG_RX_ARCMD_VREF_SEL GENMASK(5, 0) + #define SHU3_CA_CMD5_RG_RX_ARCMD_VREF_BYPASS BIT(6) + #define SHU3_CA_CMD5_RG_ARPI_FB_CA GENMASK(13, 8) + #define SHU3_CA_CMD5_RG_RX_ARCLK_DQSIEN_DLY GENMASK(18, 16) + #define SHU3_CA_CMD5_DA_RX_ARCLK_DQSIEN_RB_DLY BIT(19) + #define SHU3_CA_CMD5_RG_RX_ARCLK_DVS_DLY GENMASK(22, 20) + #define SHU3_CA_CMD5_RG_ARPI_MCTL_CA GENMASK(29, 24) +#define SHU3_CA_CMD6 0x00001718 + #define SHU3_CA_CMD6_RG_ARPI_OFFSET_CLKIEN GENMASK(5, 0) + #define SHU3_CA_CMD6_RG_ARPI_RESERVE_CA GENMASK(21, 6) + #define SHU3_CA_CMD6_RG_ARPI_MIDPI_CAP_SEL_CA GENMASK(23, 22) + #define SHU3_CA_CMD6_RG_ARPI_MIDPI_VTH_SEL_CA GENMASK(25, 24) + #define SHU3_CA_CMD6_RG_ARPI_MIDPI_EN_CA BIT(26) + #define SHU3_CA_CMD6_RG_ARPI_MIDPI_CKDIV4_EN_CA BIT(27) + #define SHU3_CA_CMD6_RG_ARPI_CAP_SEL_CA GENMASK(29, 28) + #define SHU3_CA_CMD6_RG_ARPI_MIDPI_BYPASS_EN_CA BIT(31) +#define SHU3_CA_CMD7 0x0000171c + #define SHU3_CA_CMD7_R_DMRANKRXDVS_CA GENMASK(3, 0) + #define SHU3_CA_CMD7_R_DMRXDVS_PBYTE_FLAG_OPT_CA BIT(12) + #define SHU3_CA_CMD7_R_DMRODTEN_CA BIT(15) + #define SHU3_CA_CMD7_R_DMARPI_CG_FB2DLL_DCM_EN_CA BIT(16) + #define SHU3_CA_CMD7_R_DMTX_ARPI_CG_CMD_NEW BIT(17) + #define SHU3_CA_CMD7_R_DMTX_ARPI_CG_CLK_NEW BIT(18) + #define SHU3_CA_CMD7_R_DMTX_ARPI_CG_CS_NEW BIT(19) + #define SHU3_CA_CMD7_R_LP4Y_SDN_MODE_CLK BIT(20) + #define SHU3_CA_CMD7_R_DMRXRANK_CMD_EN BIT(24) + #define SHU3_CA_CMD7_R_DMRXRANK_CMD_LAT GENMASK(27, 25) + #define SHU3_CA_CMD7_R_DMRXRANK_CLK_EN BIT(28) + #define SHU3_CA_CMD7_R_DMRXRANK_CLK_LAT GENMASK(31, 29) +#define SHU3_CA_CMD8 0x00001720 + #define SHU3_CA_CMD8_R_DMRXDVS_UPD_FORCE_CYC_CA GENMASK(14, 0) + #define SHU3_CA_CMD8_R_DMRXDVS_UPD_FORCE_EN_CA BIT(15) + #define SHU3_CA_CMD8_R_DMRANK_RXDLY_PIPE_CG_IG_CA BIT(19) + #define SHU3_CA_CMD8_R_RMRODTEN_CG_IG_CA BIT(20) + #define SHU3_CA_CMD8_R_RMRX_TOPHY_CG_IG_CA BIT(21) + #define SHU3_CA_CMD8_R_DMRXDVS_RDSEL_PIPE_CG_IG_CA BIT(22) + #define SHU3_CA_CMD8_R_DMRXDVS_RDSEL_TOG_PIPE_CG_IG_CA BIT(23) + #define SHU3_CA_CMD8_R_DMRXDLY_CG_IG_CA BIT(24) + #define SHU3_CA_CMD8_R_DMSTBEN_SYNC_CG_IG_CA BIT(25) + #define SHU3_CA_CMD8_R_DMDQSIEN_FLAG_SYNC_CG_IG_CA BIT(26) + #define SHU3_CA_CMD8_R_DMDQSIEN_FLAG_PIPE_CG_IG_CA BIT(27) + #define SHU3_CA_CMD8_R_DMDQSIEN_RDSEL_PIPE_CG_IG_CA BIT(28) + #define SHU3_CA_CMD8_R_DMDQSIEN_RDSEL_TOG_PIPE_CG_IG_CA BIT(29) + #define SHU3_CA_CMD8_R_DMRANK_PIPE_CG_IG_CA BIT(30) + #define SHU3_CA_CMD8_R_DMRANK_CHG_PIPE_CG_IG_CA BIT(31) +#define SHU3_CA_CMD9 0x00001724 + #define SHU3_CA_CMD9_RESERVED_0X1724 GENMASK(31, 0) +#define SHU3_CA_CMD10 0x00001728 + #define SHU3_CA_CMD10_RESERVED_0X1728 GENMASK(31, 0) +#define SHU3_CA_CMD11 0x0000172c + #define SHU3_CA_CMD11_RG_RIMP_REV GENMASK(7, 0) + #define SHU3_CA_CMD11_RG_RIMP_VREF_SEL GENMASK(13, 8) + #define SHU3_CA_CMD11_RG_TX_ARCKE_DRVP GENMASK(21, 17) + #define SHU3_CA_CMD11_RG_TX_ARCKE_DRVN GENMASK(26, 22) +#define SHU3_CA_CMD12 0x00001730 + #define SHU3_CA_CMD12_RESERVED_0X1730 GENMASK(31, 0) +#define SHU3_CA_DLL0 0x00001734 + #define SHU3_CA_DLL0_RG_ARPISM_MCK_SEL_CA_SHU BIT(0) + #define SHU3_CA_DLL0_CA_DLL0_RFU BIT(3) + #define SHU3_CA_DLL0_RG_ARDLL_FAST_PSJP_CA BIT(4) + #define SHU3_CA_DLL0_RG_ARDLL_PHDIV_CA BIT(9) + #define SHU3_CA_DLL0_RG_ARDLL_PHJUMP_EN_CA BIT(10) + #define SHU3_CA_DLL0_RG_ARDLL_P_GAIN_CA GENMASK(15, 12) + #define SHU3_CA_DLL0_RG_ARDLL_IDLECNT_CA GENMASK(19, 16) + #define SHU3_CA_DLL0_RG_ARDLL_GAIN_CA GENMASK(23, 20) + #define SHU3_CA_DLL0_RG_ARDLL_PHDET_IN_SWAP_CA BIT(30) + #define SHU3_CA_DLL0_RG_ARDLL_PHDET_OUT_SEL_CA BIT(31) +#define SHU3_CA_DLL1 0x00001738 + #define SHU3_CA_DLL1_RG_ARDLL_FASTPJ_CK_SEL_CA BIT(0) + #define SHU3_CA_DLL1_RG_ARDLL_PS_EN_CA BIT(1) + #define SHU3_CA_DLL1_RG_ARDLL_PD_CK_SEL_CA BIT(2) + #define SHU3_CA_DLL1_RG_ARCMD_REV GENMASK(31, 8) +#define SHU3_MISC0 0x000017f0 + #define SHU3_MISC0_R_RX_PIPE_BYPASS_EN BIT(1) + #define SHU3_MISC0_RG_CMD_TXPIPE_BYPASS_EN BIT(2) + #define SHU3_MISC0_RG_CK_TXPIPE_BYPASS_EN BIT(3) + #define SHU3_MISC0_RG_RVREF_SEL_DQ GENMASK(21, 16) + #define SHU3_MISC0_RG_RVREF_DDR4_SEL BIT(22) + #define SHU3_MISC0_RG_RVREF_DDR3_SEL BIT(23) + #define SHU3_MISC0_RG_RVREF_SEL_CMD GENMASK(29, 24) +#define SHU3_R0_B0_DQ0 0x00001800 + #define SHU3_R0_B0_DQ0_RK0_TX_ARDQ0_DLY_B0 GENMASK(3, 0) + #define SHU3_R0_B0_DQ0_RK0_TX_ARDQ1_DLY_B0 GENMASK(7, 4) + #define SHU3_R0_B0_DQ0_RK0_TX_ARDQ2_DLY_B0 GENMASK(11, 8) + #define SHU3_R0_B0_DQ0_RK0_TX_ARDQ3_DLY_B0 GENMASK(15, 12) + #define SHU3_R0_B0_DQ0_RK0_TX_ARDQ4_DLY_B0 GENMASK(19, 16) + #define SHU3_R0_B0_DQ0_RK0_TX_ARDQ5_DLY_B0 GENMASK(23, 20) + #define SHU3_R0_B0_DQ0_RK0_TX_ARDQ6_DLY_B0 GENMASK(27, 24) + #define SHU3_R0_B0_DQ0_RK0_TX_ARDQ7_DLY_B0 GENMASK(31, 28) +#define SHU3_R0_B0_DQ1 0x00001804 + #define SHU3_R0_B0_DQ1_RK0_TX_ARDQM0_DLY_B0 GENMASK(3, 0) + #define SHU3_R0_B0_DQ1_RK0_TX_ARDQS0_DLYB_B0 GENMASK(19, 16) + #define SHU3_R0_B0_DQ1_RK0_TX_ARDQS0B_DLYB_B0 GENMASK(23, 20) + #define SHU3_R0_B0_DQ1_RK0_TX_ARDQS0_DLY_B0 GENMASK(27, 24) + #define SHU3_R0_B0_DQ1_RK0_TX_ARDQS0B_DLY_B0 GENMASK(31, 28) +#define SHU3_R0_B0_DQ2 0x00001808 + #define SHU3_R0_B0_DQ2_RK0_RX_ARDQ0_R_DLY_B0 GENMASK(5, 0) + #define SHU3_R0_B0_DQ2_RK0_RX_ARDQ0_F_DLY_B0 GENMASK(13, 8) + #define SHU3_R0_B0_DQ2_RK0_RX_ARDQ1_R_DLY_B0 GENMASK(21, 16) + #define SHU3_R0_B0_DQ2_RK0_RX_ARDQ1_F_DLY_B0 GENMASK(29, 24) +#define SHU3_R0_B0_DQ3 0x0000180c + #define SHU3_R0_B0_DQ3_RK0_RX_ARDQ2_R_DLY_B0 GENMASK(5, 0) + #define SHU3_R0_B0_DQ3_RK0_RX_ARDQ2_F_DLY_B0 GENMASK(13, 8) + #define SHU3_R0_B0_DQ3_RK0_RX_ARDQ3_R_DLY_B0 GENMASK(21, 16) + #define SHU3_R0_B0_DQ3_RK0_RX_ARDQ3_F_DLY_B0 GENMASK(29, 24) +#define SHU3_R0_B0_DQ4 0x00001810 + #define SHU3_R0_B0_DQ4_RK0_RX_ARDQ4_R_DLY_B0 GENMASK(5, 0) + #define SHU3_R0_B0_DQ4_RK0_RX_ARDQ4_F_DLY_B0 GENMASK(13, 8) + #define SHU3_R0_B0_DQ4_RK0_RX_ARDQ5_R_DLY_B0 GENMASK(21, 16) + #define SHU3_R0_B0_DQ4_RK0_RX_ARDQ5_F_DLY_B0 GENMASK(29, 24) +#define SHU3_R0_B0_DQ5 0x00001814 + #define SHU3_R0_B0_DQ5_RK0_RX_ARDQ6_R_DLY_B0 GENMASK(5, 0) + #define SHU3_R0_B0_DQ5_RK0_RX_ARDQ6_F_DLY_B0 GENMASK(13, 8) + #define SHU3_R0_B0_DQ5_RK0_RX_ARDQ7_R_DLY_B0 GENMASK(21, 16) + #define SHU3_R0_B0_DQ5_RK0_RX_ARDQ7_F_DLY_B0 GENMASK(29, 24) +#define SHU3_R0_B0_DQ6 0x00001818 + #define SHU3_R0_B0_DQ6_RK0_RX_ARDQM0_R_DLY_B0 GENMASK(5, 0) + #define SHU3_R0_B0_DQ6_RK0_RX_ARDQM0_F_DLY_B0 GENMASK(13, 8) + #define SHU3_R0_B0_DQ6_RK0_RX_ARDQS0_R_DLY_B0 GENMASK(22, 16) + #define SHU3_R0_B0_DQ6_RK0_RX_ARDQS0_F_DLY_B0 GENMASK(30, 24) +#define SHU3_R0_B0_DQ7 0x0000181c + #define SHU3_R0_B0_DQ7_RK0_ARPI_DQ_B0 GENMASK(13, 8) + #define SHU3_R0_B0_DQ7_RK0_ARPI_DQM_B0 GENMASK(21, 16) + #define SHU3_R0_B0_DQ7_RK0_ARPI_PBYTE_B0 GENMASK(29, 24) +#define RFU_0X1820 0x00001820 + #define RFU_0X1820_RESERVED_0X1820 GENMASK(31, 0) +#define RFU_0X1824 0x00001824 + #define RFU_0X1824_RESERVED_0X1824 GENMASK(31, 0) +#define RFU_0X1828 0x00001828 + #define RFU_0X1828_RESERVED_0X1828 GENMASK(31, 0) +#define RFU_0X182C 0x0000182c + #define RFU_0X182C_RESERVED_0X182C GENMASK(31, 0) +#define SHU3_R0_B1_DQ0 0x00001850 + #define SHU3_R0_B1_DQ0_RK0_TX_ARDQ0_DLY_B1 GENMASK(3, 0) + #define SHU3_R0_B1_DQ0_RK0_TX_ARDQ1_DLY_B1 GENMASK(7, 4) + #define SHU3_R0_B1_DQ0_RK0_TX_ARDQ2_DLY_B1 GENMASK(11, 8) + #define SHU3_R0_B1_DQ0_RK0_TX_ARDQ3_DLY_B1 GENMASK(15, 12) + #define SHU3_R0_B1_DQ0_RK0_TX_ARDQ4_DLY_B1 GENMASK(19, 16) + #define SHU3_R0_B1_DQ0_RK0_TX_ARDQ5_DLY_B1 GENMASK(23, 20) + #define SHU3_R0_B1_DQ0_RK0_TX_ARDQ6_DLY_B1 GENMASK(27, 24) + #define SHU3_R0_B1_DQ0_RK0_TX_ARDQ7_DLY_B1 GENMASK(31, 28) +#define SHU3_R0_B1_DQ1 0x00001854 + #define SHU3_R0_B1_DQ1_RK0_TX_ARDQM0_DLY_B1 GENMASK(3, 0) + #define SHU3_R0_B1_DQ1_RK0_TX_ARDQS0_DLYB_B1 GENMASK(19, 16) + #define SHU3_R0_B1_DQ1_RK0_TX_ARDQS0B_DLYB_B1 GENMASK(23, 20) + #define SHU3_R0_B1_DQ1_RK0_TX_ARDQS0_DLY_B1 GENMASK(27, 24) + #define SHU3_R0_B1_DQ1_RK0_TX_ARDQS0B_DLY_B1 GENMASK(31, 28) +#define SHU3_R0_B1_DQ2 0x00001858 + #define SHU3_R0_B1_DQ2_RK0_RX_ARDQ0_R_DLY_B1 GENMASK(5, 0) + #define SHU3_R0_B1_DQ2_RK0_RX_ARDQ0_F_DLY_B1 GENMASK(13, 8) + #define SHU3_R0_B1_DQ2_RK0_RX_ARDQ1_R_DLY_B1 GENMASK(21, 16) + #define SHU3_R0_B1_DQ2_RK0_RX_ARDQ1_F_DLY_B1 GENMASK(29, 24) +#define SHU3_R0_B1_DQ3 0x0000185c + #define SHU3_R0_B1_DQ3_RK0_RX_ARDQ2_R_DLY_B1 GENMASK(5, 0) + #define SHU3_R0_B1_DQ3_RK0_RX_ARDQ2_F_DLY_B1 GENMASK(13, 8) + #define SHU3_R0_B1_DQ3_RK0_RX_ARDQ3_R_DLY_B1 GENMASK(21, 16) + #define SHU3_R0_B1_DQ3_RK0_RX_ARDQ3_F_DLY_B1 GENMASK(29, 24) +#define SHU3_R0_B1_DQ4 0x00001860 + #define SHU3_R0_B1_DQ4_RK0_RX_ARDQ4_R_DLY_B1 GENMASK(5, 0) + #define SHU3_R0_B1_DQ4_RK0_RX_ARDQ4_F_DLY_B1 GENMASK(13, 8) + #define SHU3_R0_B1_DQ4_RK0_RX_ARDQ5_R_DLY_B1 GENMASK(21, 16) + #define SHU3_R0_B1_DQ4_RK0_RX_ARDQ5_F_DLY_B1 GENMASK(29, 24) +#define SHU3_R0_B1_DQ5 0x00001864 + #define SHU3_R0_B1_DQ5_RK0_RX_ARDQ6_R_DLY_B1 GENMASK(5, 0) + #define SHU3_R0_B1_DQ5_RK0_RX_ARDQ6_F_DLY_B1 GENMASK(13, 8) + #define SHU3_R0_B1_DQ5_RK0_RX_ARDQ7_R_DLY_B1 GENMASK(21, 16) + #define SHU3_R0_B1_DQ5_RK0_RX_ARDQ7_F_DLY_B1 GENMASK(29, 24) +#define SHU3_R0_B1_DQ6 0x00001868 + #define SHU3_R0_B1_DQ6_RK0_RX_ARDQM0_R_DLY_B1 GENMASK(5, 0) + #define SHU3_R0_B1_DQ6_RK0_RX_ARDQM0_F_DLY_B1 GENMASK(13, 8) + #define SHU3_R0_B1_DQ6_RK0_RX_ARDQS0_R_DLY_B1 GENMASK(22, 16) + #define SHU3_R0_B1_DQ6_RK0_RX_ARDQS0_F_DLY_B1 GENMASK(30, 24) +#define SHU3_R0_B1_DQ7 0x0000186c + #define SHU3_R0_B1_DQ7_RK0_ARPI_DQ_B1 GENMASK(13, 8) + #define SHU3_R0_B1_DQ7_RK0_ARPI_DQM_B1 GENMASK(21, 16) + #define SHU3_R0_B1_DQ7_RK0_ARPI_PBYTE_B1 GENMASK(29, 24) +#define RFU_0X1870 0x00001870 + #define RFU_0X1870_RESERVED_0X1870 GENMASK(31, 0) +#define RFU_0X1874 0x00001874 + #define RFU_0X1874_RESERVED_0X1874 GENMASK(31, 0) +#define RFU_0X1878 0x00001878 + #define RFU_0X1878_RESERVED_0X1878 GENMASK(31, 0) +#define RFU_0X187C 0x0000187c + #define RFU_0X187C_RESERVED_0X187C GENMASK(31, 0) +#define SHU3_R0_CA_CMD0 0x000018a0 + #define SHU3_R0_CA_CMD0_RK0_TX_ARCA0_DLY GENMASK(3, 0) + #define SHU3_R0_CA_CMD0_RK0_TX_ARCA1_DLY GENMASK(7, 4) + #define SHU3_R0_CA_CMD0_RK0_TX_ARCA2_DLY GENMASK(11, 8) + #define SHU3_R0_CA_CMD0_RK0_TX_ARCA3_DLY GENMASK(15, 12) + #define SHU3_R0_CA_CMD0_RK0_TX_ARCA4_DLY GENMASK(19, 16) + #define SHU3_R0_CA_CMD0_RK0_TX_ARCA5_DLY GENMASK(23, 20) + #define SHU3_R0_CA_CMD0_RK0_TX_ARCLK_DLYB GENMASK(27, 24) + #define SHU3_R0_CA_CMD0_RK0_TX_ARCLKB_DLYB GENMASK(31, 28) +#define SHU3_R0_CA_CMD1 0x000018a4 + #define SHU3_R0_CA_CMD1_RK0_TX_ARCKE0_DLY GENMASK(3, 0) + #define SHU3_R0_CA_CMD1_RK0_TX_ARCKE1_DLY GENMASK(7, 4) + #define SHU3_R0_CA_CMD1_RK0_TX_ARCKE2_DLY GENMASK(11, 8) + #define SHU3_R0_CA_CMD1_RK0_TX_ARCS0_DLY GENMASK(15, 12) + #define SHU3_R0_CA_CMD1_RK0_TX_ARCS1_DLY GENMASK(19, 16) + #define SHU3_R0_CA_CMD1_RK0_TX_ARCS2_DLY GENMASK(23, 20) + #define SHU3_R0_CA_CMD1_RK0_TX_ARCLK_DLY GENMASK(27, 24) + #define SHU3_R0_CA_CMD1_RK0_TX_ARCLKB_DLY GENMASK(31, 28) +#define SHU3_R0_CA_CMD2 0x000018a8 + #define SHU3_R0_CA_CMD2_RG_RK0_RX_ARCA0_R_DLY GENMASK(5, 0) + #define SHU3_R0_CA_CMD2_RG_RK0_RX_ARCA0_F_DLY GENMASK(13, 8) + #define SHU3_R0_CA_CMD2_RG_RK0_RX_ARCA1_R_DLY GENMASK(21, 16) + #define SHU3_R0_CA_CMD2_RG_RK0_RX_ARCA1_F_DLY GENMASK(29, 24) +#define SHU3_R0_CA_CMD3 0x000018ac + #define SHU3_R0_CA_CMD3_RG_RK0_RX_ARCA2_R_DLY GENMASK(5, 0) + #define SHU3_R0_CA_CMD3_RG_RK0_RX_ARCA2_F_DLY GENMASK(13, 8) + #define SHU3_R0_CA_CMD3_RG_RK0_RX_ARCA3_R_DLY GENMASK(21, 16) + #define SHU3_R0_CA_CMD3_RG_RK0_RX_ARCA3_F_DLY GENMASK(29, 24) +#define SHU3_R0_CA_CMD4 0x000018b0 + #define SHU3_R0_CA_CMD4_RG_RK0_RX_ARCA4_R_DLY GENMASK(5, 0) + #define SHU3_R0_CA_CMD4_RG_RK0_RX_ARCA4_F_DLY GENMASK(13, 8) + #define SHU3_R0_CA_CMD4_RG_RK0_RX_ARCA5_R_DLY GENMASK(21, 16) + #define SHU3_R0_CA_CMD4_RG_RK0_RX_ARCA5_F_DLY GENMASK(29, 24) +#define SHU3_R0_CA_CMD5 0x000018b4 + #define SHU3_R0_CA_CMD5_RG_RK0_RX_ARCKE0_R_DLY GENMASK(5, 0) + #define SHU3_R0_CA_CMD5_RG_RK0_RX_ARCKE0_F_DLY GENMASK(13, 8) + #define SHU3_R0_CA_CMD5_RG_RK0_RX_ARCKE1_R_DLY GENMASK(21, 16) + #define SHU3_R0_CA_CMD5_RG_RK0_RX_ARCKE1_F_DLY GENMASK(29, 24) +#define SHU3_R0_CA_CMD6 0x000018b8 + #define SHU3_R0_CA_CMD6_RG_RK0_RX_ARCKE2_R_DLY GENMASK(5, 0) + #define SHU3_R0_CA_CMD6_RG_RK0_RX_ARCKE2_F_DLY GENMASK(13, 8) + #define SHU3_R0_CA_CMD6_RG_RK0_RX_ARCS0_R_DLY GENMASK(21, 16) + #define SHU3_R0_CA_CMD6_RG_RK0_RX_ARCS0_F_DLY GENMASK(29, 24) +#define SHU3_R0_CA_CMD7 0x000018bc + #define SHU3_R0_CA_CMD7_RG_RK0_RX_ARCS1_R_DLY GENMASK(5, 0) + #define SHU3_R0_CA_CMD7_RG_RK0_RX_ARCS1_F_DLY GENMASK(13, 8) + #define SHU3_R0_CA_CMD7_RG_RK0_RX_ARCS2_R_DLY GENMASK(21, 16) + #define SHU3_R0_CA_CMD7_RG_RK0_RX_ARCS2_F_DLY GENMASK(29, 24) +#define SHU3_R0_CA_CMD8 0x000018c0 + #define SHU3_R0_CA_CMD8_RG_RK0_RX_ARCLK_R_DLY GENMASK(22, 16) + #define SHU3_R0_CA_CMD8_RG_RK0_RX_ARCLK_F_DLY GENMASK(30, 24) +#define SHU3_R0_CA_CMD9 0x000018c4 + #define SHU3_R0_CA_CMD9_RG_RK0_ARPI_CS GENMASK(5, 0) + #define SHU3_R0_CA_CMD9_RG_RK0_ARPI_CMD GENMASK(13, 8) + #define SHU3_R0_CA_CMD9_RG_RK0_ARPI_CLK GENMASK(29, 24) +#define RFU_0X18C8 0x000018c8 + #define RFU_0X18C8_RESERVED_0X18C8 GENMASK(31, 0) +#define RFU_0X18CC 0x000018cc + #define RFU_0X18CC_RESERVED_0X18CC GENMASK(31, 0) +#define SHU3_R1_B0_DQ0 0x00001900 + #define SHU3_R1_B0_DQ0_RK1_TX_ARDQ0_DLY_B0 GENMASK(3, 0) + #define SHU3_R1_B0_DQ0_RK1_TX_ARDQ1_DLY_B0 GENMASK(7, 4) + #define SHU3_R1_B0_DQ0_RK1_TX_ARDQ2_DLY_B0 GENMASK(11, 8) + #define SHU3_R1_B0_DQ0_RK1_TX_ARDQ3_DLY_B0 GENMASK(15, 12) + #define SHU3_R1_B0_DQ0_RK1_TX_ARDQ4_DLY_B0 GENMASK(19, 16) + #define SHU3_R1_B0_DQ0_RK1_TX_ARDQ5_DLY_B0 GENMASK(23, 20) + #define SHU3_R1_B0_DQ0_RK1_TX_ARDQ6_DLY_B0 GENMASK(27, 24) + #define SHU3_R1_B0_DQ0_RK1_TX_ARDQ7_DLY_B0 GENMASK(31, 28) +#define SHU3_R1_B0_DQ1 0x00001904 + #define SHU3_R1_B0_DQ1_RK1_TX_ARDQM0_DLY_B0 GENMASK(3, 0) + #define SHU3_R1_B0_DQ1_RK1_TX_ARDQS0_DLYB_B0 GENMASK(19, 16) + #define SHU3_R1_B0_DQ1_RK1_TX_ARDQS0B_DLYB_B0 GENMASK(23, 20) + #define SHU3_R1_B0_DQ1_RK1_TX_ARDQS0_DLY_B0 GENMASK(27, 24) + #define SHU3_R1_B0_DQ1_RK1_TX_ARDQS0B_DLY_B0 GENMASK(31, 28) +#define SHU3_R1_B0_DQ2 0x00001908 + #define SHU3_R1_B0_DQ2_RK1_RX_ARDQ0_R_DLY_B0 GENMASK(5, 0) + #define SHU3_R1_B0_DQ2_RK1_RX_ARDQ0_F_DLY_B0 GENMASK(13, 8) + #define SHU3_R1_B0_DQ2_RK1_RX_ARDQ1_R_DLY_B0 GENMASK(21, 16) + #define SHU3_R1_B0_DQ2_RK1_RX_ARDQ1_F_DLY_B0 GENMASK(29, 24) +#define SHU3_R1_B0_DQ3 0x0000190c + #define SHU3_R1_B0_DQ3_RK1_RX_ARDQ2_R_DLY_B0 GENMASK(5, 0) + #define SHU3_R1_B0_DQ3_RK1_RX_ARDQ2_F_DLY_B0 GENMASK(13, 8) + #define SHU3_R1_B0_DQ3_RK1_RX_ARDQ3_R_DLY_B0 GENMASK(21, 16) + #define SHU3_R1_B0_DQ3_RK1_RX_ARDQ3_F_DLY_B0 GENMASK(29, 24) +#define SHU3_R1_B0_DQ4 0x00001910 + #define SHU3_R1_B0_DQ4_RK1_RX_ARDQ4_R_DLY_B0 GENMASK(5, 0) + #define SHU3_R1_B0_DQ4_RK1_RX_ARDQ4_F_DLY_B0 GENMASK(13, 8) + #define SHU3_R1_B0_DQ4_RK1_RX_ARDQ5_R_DLY_B0 GENMASK(21, 16) + #define SHU3_R1_B0_DQ4_RK1_RX_ARDQ5_F_DLY_B0 GENMASK(29, 24) +#define SHU3_R1_B0_DQ5 0x00001914 + #define SHU3_R1_B0_DQ5_RK1_RX_ARDQ6_R_DLY_B0 GENMASK(5, 0) + #define SHU3_R1_B0_DQ5_RK1_RX_ARDQ6_F_DLY_B0 GENMASK(13, 8) + #define SHU3_R1_B0_DQ5_RK1_RX_ARDQ7_R_DLY_B0 GENMASK(21, 16) + #define SHU3_R1_B0_DQ5_RK1_RX_ARDQ7_F_DLY_B0 GENMASK(29, 24) +#define SHU3_R1_B0_DQ6 0x00001918 + #define SHU3_R1_B0_DQ6_RK1_RX_ARDQM0_R_DLY_B0 GENMASK(5, 0) + #define SHU3_R1_B0_DQ6_RK1_RX_ARDQM0_F_DLY_B0 GENMASK(13, 8) + #define SHU3_R1_B0_DQ6_RK1_RX_ARDQS0_R_DLY_B0 GENMASK(22, 16) + #define SHU3_R1_B0_DQ6_RK1_RX_ARDQS0_F_DLY_B0 GENMASK(30, 24) +#define SHU3_R1_B0_DQ7 0x0000191c + #define SHU3_R1_B0_DQ7_RK1_ARPI_DQ_B0 GENMASK(13, 8) + #define SHU3_R1_B0_DQ7_RK1_ARPI_DQM_B0 GENMASK(21, 16) + #define SHU3_R1_B0_DQ7_RK1_ARPI_PBYTE_B0 GENMASK(29, 24) +#define RFU_0X1920 0x00001920 + #define RFU_0X1920_RESERVED_0X1920 GENMASK(31, 0) +#define RFU_0X1924 0x00001924 + #define RFU_0X1924_RESERVED_0X1924 GENMASK(31, 0) +#define RFU_0X1928 0x00001928 + #define RFU_0X1928_RESERVED_0X1928 GENMASK(31, 0) +#define RFU_0X192C 0x0000192c + #define RFU_0X192C_RESERVED_0X192C GENMASK(31, 0) +#define SHU3_R1_B1_DQ0 0x00001950 + #define SHU3_R1_B1_DQ0_RK1_TX_ARDQ0_DLY_B1 GENMASK(3, 0) + #define SHU3_R1_B1_DQ0_RK1_TX_ARDQ1_DLY_B1 GENMASK(7, 4) + #define SHU3_R1_B1_DQ0_RK1_TX_ARDQ2_DLY_B1 GENMASK(11, 8) + #define SHU3_R1_B1_DQ0_RK1_TX_ARDQ3_DLY_B1 GENMASK(15, 12) + #define SHU3_R1_B1_DQ0_RK1_TX_ARDQ4_DLY_B1 GENMASK(19, 16) + #define SHU3_R1_B1_DQ0_RK1_TX_ARDQ5_DLY_B1 GENMASK(23, 20) + #define SHU3_R1_B1_DQ0_RK1_TX_ARDQ6_DLY_B1 GENMASK(27, 24) + #define SHU3_R1_B1_DQ0_RK1_TX_ARDQ7_DLY_B1 GENMASK(31, 28) +#define SHU3_R1_B1_DQ1 0x00001954 + #define SHU3_R1_B1_DQ1_RK1_TX_ARDQM0_DLY_B1 GENMASK(3, 0) + #define SHU3_R1_B1_DQ1_RK1_TX_ARDQS0_DLYB_B1 GENMASK(19, 16) + #define SHU3_R1_B1_DQ1_RK1_TX_ARDQS0B_DLYB_B1 GENMASK(23, 20) + #define SHU3_R1_B1_DQ1_RK1_TX_ARDQS0_DLY_B1 GENMASK(27, 24) + #define SHU3_R1_B1_DQ1_RK1_TX_ARDQS0B_DLY_B1 GENMASK(31, 28) +#define SHU3_R1_B1_DQ2 0x00001958 + #define SHU3_R1_B1_DQ2_RK1_RX_ARDQ0_R_DLY_B1 GENMASK(5, 0) + #define SHU3_R1_B1_DQ2_RK1_RX_ARDQ0_F_DLY_B1 GENMASK(13, 8) + #define SHU3_R1_B1_DQ2_RK1_RX_ARDQ1_R_DLY_B1 GENMASK(21, 16) + #define SHU3_R1_B1_DQ2_RK1_RX_ARDQ1_F_DLY_B1 GENMASK(29, 24) +#define SHU3_R1_B1_DQ3 0x0000195c + #define SHU3_R1_B1_DQ3_RK1_RX_ARDQ2_R_DLY_B1 GENMASK(5, 0) + #define SHU3_R1_B1_DQ3_RK1_RX_ARDQ2_F_DLY_B1 GENMASK(13, 8) + #define SHU3_R1_B1_DQ3_RK1_RX_ARDQ3_R_DLY_B1 GENMASK(21, 16) + #define SHU3_R1_B1_DQ3_RK1_RX_ARDQ3_F_DLY_B1 GENMASK(29, 24) +#define SHU3_R1_B1_DQ4 0x00001960 + #define SHU3_R1_B1_DQ4_RK1_RX_ARDQ4_R_DLY_B1 GENMASK(5, 0) + #define SHU3_R1_B1_DQ4_RK1_RX_ARDQ4_F_DLY_B1 GENMASK(13, 8) + #define SHU3_R1_B1_DQ4_RK1_RX_ARDQ5_R_DLY_B1 GENMASK(21, 16) + #define SHU3_R1_B1_DQ4_RK1_RX_ARDQ5_F_DLY_B1 GENMASK(29, 24) +#define SHU3_R1_B1_DQ5 0x00001964 + #define SHU3_R1_B1_DQ5_RK1_RX_ARDQ6_R_DLY_B1 GENMASK(5, 0) + #define SHU3_R1_B1_DQ5_RK1_RX_ARDQ6_F_DLY_B1 GENMASK(13, 8) + #define SHU3_R1_B1_DQ5_RK1_RX_ARDQ7_R_DLY_B1 GENMASK(21, 16) + #define SHU3_R1_B1_DQ5_RK1_RX_ARDQ7_F_DLY_B1 GENMASK(29, 24) +#define SHU3_R1_B1_DQ6 0x00001968 + #define SHU3_R1_B1_DQ6_RK1_RX_ARDQM0_R_DLY_B1 GENMASK(5, 0) + #define SHU3_R1_B1_DQ6_RK1_RX_ARDQM0_F_DLY_B1 GENMASK(13, 8) + #define SHU3_R1_B1_DQ6_RK1_RX_ARDQS0_R_DLY_B1 GENMASK(22, 16) + #define SHU3_R1_B1_DQ6_RK1_RX_ARDQS0_F_DLY_B1 GENMASK(30, 24) +#define SHU3_R1_B1_DQ7 0x0000196c + #define SHU3_R1_B1_DQ7_RK1_ARPI_DQ_B1 GENMASK(13, 8) + #define SHU3_R1_B1_DQ7_RK1_ARPI_DQM_B1 GENMASK(21, 16) + #define SHU3_R1_B1_DQ7_RK1_ARPI_PBYTE_B1 GENMASK(29, 24) +#define RFU_0X1970 0x00001970 + #define RFU_0X1970_RESERVED_0X1970 GENMASK(31, 0) +#define RFU_0X1974 0x00001974 + #define RFU_0X1974_RESERVED_0X1974 GENMASK(31, 0) +#define RFU_0X1978 0x00001978 + #define RFU_0X1978_RESERVED_0X1978 GENMASK(31, 0) +#define RFU_0X197C 0x0000197c + #define RFU_0X197C_RESERVED_0X197C GENMASK(31, 0) +#define SHU3_R1_CA_CMD0 0x000019a0 + #define SHU3_R1_CA_CMD0_RK1_TX_ARCA0_DLY GENMASK(3, 0) + #define SHU3_R1_CA_CMD0_RK1_TX_ARCA1_DLY GENMASK(7, 4) + #define SHU3_R1_CA_CMD0_RK1_TX_ARCA2_DLY GENMASK(11, 8) + #define SHU3_R1_CA_CMD0_RK1_TX_ARCA3_DLY GENMASK(15, 12) + #define SHU3_R1_CA_CMD0_RK1_TX_ARCA4_DLY GENMASK(19, 16) + #define SHU3_R1_CA_CMD0_RK1_TX_ARCA5_DLY GENMASK(23, 20) + #define SHU3_R1_CA_CMD0_RK1_TX_ARCLK_DLYB GENMASK(27, 24) + #define SHU3_R1_CA_CMD0_RK1_TX_ARCLKB_DLYB GENMASK(31, 28) +#define SHU3_R1_CA_CMD1 0x000019a4 + #define SHU3_R1_CA_CMD1_RK1_TX_ARCKE0_DLY GENMASK(3, 0) + #define SHU3_R1_CA_CMD1_RK1_TX_ARCKE1_DLY GENMASK(7, 4) + #define SHU3_R1_CA_CMD1_RK1_TX_ARCKE2_DLY GENMASK(11, 8) + #define SHU3_R1_CA_CMD1_RK1_TX_ARCS0_DLY GENMASK(15, 12) + #define SHU3_R1_CA_CMD1_RK1_TX_ARCS1_DLY GENMASK(19, 16) + #define SHU3_R1_CA_CMD1_RK1_TX_ARCS2_DLY GENMASK(23, 20) + #define SHU3_R1_CA_CMD1_RK1_TX_ARCLK_DLY GENMASK(27, 24) + #define SHU3_R1_CA_CMD1_RK1_TX_ARCLKB_DLY GENMASK(31, 28) +#define SHU3_R1_CA_CMD2 0x000019a8 + #define SHU3_R1_CA_CMD2_RG_RK1_RX_ARCA0_R_DLY GENMASK(5, 0) + #define SHU3_R1_CA_CMD2_RG_RK1_RX_ARCA0_F_DLY GENMASK(13, 8) + #define SHU3_R1_CA_CMD2_RG_RK1_RX_ARCA1_R_DLY GENMASK(21, 16) + #define SHU3_R1_CA_CMD2_RG_RK1_RX_ARCA1_F_DLY GENMASK(29, 24) +#define SHU3_R1_CA_CMD3 0x000019ac + #define SHU3_R1_CA_CMD3_RG_RK1_RX_ARCA2_R_DLY GENMASK(5, 0) + #define SHU3_R1_CA_CMD3_RG_RK1_RX_ARCA2_F_DLY GENMASK(13, 8) + #define SHU3_R1_CA_CMD3_RG_RK1_RX_ARCA3_R_DLY GENMASK(21, 16) + #define SHU3_R1_CA_CMD3_RG_RK1_RX_ARCA3_F_DLY GENMASK(29, 24) +#define SHU3_R1_CA_CMD4 0x000019b0 + #define SHU3_R1_CA_CMD4_RG_RK1_RX_ARCA4_R_DLY GENMASK(5, 0) + #define SHU3_R1_CA_CMD4_RG_RK1_RX_ARCA4_F_DLY GENMASK(13, 8) + #define SHU3_R1_CA_CMD4_RG_RK1_RX_ARCA5_R_DLY GENMASK(21, 16) + #define SHU3_R1_CA_CMD4_RG_RK1_RX_ARCA5_F_DLY GENMASK(29, 24) +#define SHU3_R1_CA_CMD5 0x000019b4 + #define SHU3_R1_CA_CMD5_RG_RK1_RX_ARCKE0_R_DLY GENMASK(5, 0) + #define SHU3_R1_CA_CMD5_RG_RK1_RX_ARCKE0_F_DLY GENMASK(13, 8) + #define SHU3_R1_CA_CMD5_RG_RK1_RX_ARCKE1_R_DLY GENMASK(21, 16) + #define SHU3_R1_CA_CMD5_RG_RK1_RX_ARCKE1_F_DLY GENMASK(29, 24) +#define SHU3_R1_CA_CMD6 0x000019b8 + #define SHU3_R1_CA_CMD6_RG_RK1_RX_ARCKE2_R_DLY GENMASK(5, 0) + #define SHU3_R1_CA_CMD6_RG_RK1_RX_ARCKE2_F_DLY GENMASK(13, 8) + #define SHU3_R1_CA_CMD6_RG_RK1_RX_ARCS0_R_DLY GENMASK(21, 16) + #define SHU3_R1_CA_CMD6_RG_RK1_RX_ARCS0_F_DLY GENMASK(29, 24) +#define SHU3_R1_CA_CMD7 0x000019bc + #define SHU3_R1_CA_CMD7_RG_RK1_RX_ARCS1_R_DLY GENMASK(5, 0) + #define SHU3_R1_CA_CMD7_RG_RK1_RX_ARCS1_F_DLY GENMASK(13, 8) + #define SHU3_R1_CA_CMD7_RG_RK1_RX_ARCS2_R_DLY GENMASK(21, 16) + #define SHU3_R1_CA_CMD7_RG_RK1_RX_ARCS2_F_DLY GENMASK(29, 24) +#define SHU3_R1_CA_CMD8 0x000019c0 + #define SHU3_R1_CA_CMD8_RG_RK1_RX_ARCLK_R_DLY GENMASK(22, 16) + #define SHU3_R1_CA_CMD8_RG_RK1_RX_ARCLK_F_DLY GENMASK(30, 24) +#define SHU3_R1_CA_CMD9 0x000019c4 + #define SHU3_R1_CA_CMD9_RG_RK1_ARPI_CS GENMASK(5, 0) + #define SHU3_R1_CA_CMD9_RG_RK1_ARPI_CMD GENMASK(13, 8) + #define SHU3_R1_CA_CMD9_RG_RK1_ARPI_CLK GENMASK(29, 24) +#define RFU_0X19C8 0x000019c8 + #define RFU_0X19C8_RESERVED_0X19C8 GENMASK(31, 0) +#define RFU_0X19CC 0x000019cc + #define RFU_0X19CC_RESERVED_0X19CC GENMASK(31, 0) +#define SHU3_R2_B0_DQ0 0x00001a00 + #define SHU3_R2_B0_DQ0_RK2_TX_ARDQ0_DLY_B0 GENMASK(3, 0) + #define SHU3_R2_B0_DQ0_RK2_TX_ARDQ1_DLY_B0 GENMASK(7, 4) + #define SHU3_R2_B0_DQ0_RK2_TX_ARDQ2_DLY_B0 GENMASK(11, 8) + #define SHU3_R2_B0_DQ0_RK2_TX_ARDQ3_DLY_B0 GENMASK(15, 12) + #define SHU3_R2_B0_DQ0_RK2_TX_ARDQ4_DLY_B0 GENMASK(19, 16) + #define SHU3_R2_B0_DQ0_RK2_TX_ARDQ5_DLY_B0 GENMASK(23, 20) + #define SHU3_R2_B0_DQ0_RK2_TX_ARDQ6_DLY_B0 GENMASK(27, 24) + #define SHU3_R2_B0_DQ0_RK2_TX_ARDQ7_DLY_B0 GENMASK(31, 28) +#define SHU3_R2_B0_DQ1 0x00001a04 + #define SHU3_R2_B0_DQ1_RK2_TX_ARDQM0_DLY_B0 GENMASK(3, 0) + #define SHU3_R2_B0_DQ1_RK2_TX_ARDQS0_DLYB_B0 GENMASK(19, 16) + #define SHU3_R2_B0_DQ1_RK2_TX_ARDQS0B_DLYB_B0 GENMASK(23, 20) + #define SHU3_R2_B0_DQ1_RK2_TX_ARDQS0_DLY_B0 GENMASK(27, 24) + #define SHU3_R2_B0_DQ1_RK2_TX_ARDQS0B_DLY_B0 GENMASK(31, 28) +#define SHU3_R2_B0_DQ2 0x00001a08 + #define SHU3_R2_B0_DQ2_RK2_RX_ARDQ0_R_DLY_B0 GENMASK(5, 0) + #define SHU3_R2_B0_DQ2_RK2_RX_ARDQ0_F_DLY_B0 GENMASK(13, 8) + #define SHU3_R2_B0_DQ2_RK2_RX_ARDQ1_R_DLY_B0 GENMASK(21, 16) + #define SHU3_R2_B0_DQ2_RK2_RX_ARDQ1_F_DLY_B0 GENMASK(29, 24) +#define SHU3_R2_B0_DQ3 0x00001a0c + #define SHU3_R2_B0_DQ3_RK2_RX_ARDQ2_R_DLY_B0 GENMASK(5, 0) + #define SHU3_R2_B0_DQ3_RK2_RX_ARDQ2_F_DLY_B0 GENMASK(13, 8) + #define SHU3_R2_B0_DQ3_RK2_RX_ARDQ3_R_DLY_B0 GENMASK(21, 16) + #define SHU3_R2_B0_DQ3_RK2_RX_ARDQ3_F_DLY_B0 GENMASK(29, 24) +#define SHU3_R2_B0_DQ4 0x00001a10 + #define SHU3_R2_B0_DQ4_RK2_RX_ARDQ4_R_DLY_B0 GENMASK(5, 0) + #define SHU3_R2_B0_DQ4_RK2_RX_ARDQ4_F_DLY_B0 GENMASK(13, 8) + #define SHU3_R2_B0_DQ4_RK2_RX_ARDQ5_R_DLY_B0 GENMASK(21, 16) + #define SHU3_R2_B0_DQ4_RK2_RX_ARDQ5_F_DLY_B0 GENMASK(29, 24) +#define SHU3_R2_B0_DQ5 0x00001a14 + #define SHU3_R2_B0_DQ5_RK2_RX_ARDQ6_R_DLY_B0 GENMASK(5, 0) + #define SHU3_R2_B0_DQ5_RK2_RX_ARDQ6_F_DLY_B0 GENMASK(13, 8) + #define SHU3_R2_B0_DQ5_RK2_RX_ARDQ7_R_DLY_B0 GENMASK(21, 16) + #define SHU3_R2_B0_DQ5_RK2_RX_ARDQ7_F_DLY_B0 GENMASK(29, 24) +#define SHU3_R2_B0_DQ6 0x00001a18 + #define SHU3_R2_B0_DQ6_RK2_RX_ARDQM0_R_DLY_B0 GENMASK(5, 0) + #define SHU3_R2_B0_DQ6_RK2_RX_ARDQM0_F_DLY_B0 GENMASK(13, 8) + #define SHU3_R2_B0_DQ6_RK2_RX_ARDQS0_R_DLY_B0 GENMASK(22, 16) + #define SHU3_R2_B0_DQ6_RK2_RX_ARDQS0_F_DLY_B0 GENMASK(30, 24) +#define SHU3_R2_B0_DQ7 0x00001a1c + #define SHU3_R2_B0_DQ7_RK2_ARPI_DQ_B0 GENMASK(13, 8) + #define SHU3_R2_B0_DQ7_RK2_ARPI_DQM_B0 GENMASK(21, 16) + #define SHU3_R2_B0_DQ7_RK2_ARPI_PBYTE_B0 GENMASK(29, 24) +#define RFU_0X1A20 0x00001a20 + #define RFU_0X1A20_RESERVED_0X1A20 GENMASK(31, 0) +#define RFU_0X1A24 0x00001a24 + #define RFU_0X1A24_RESERVED_0X1A24 GENMASK(31, 0) +#define RFU_0X1A28 0x00001a28 + #define RFU_0X1A28_RESERVED_0X1A28 GENMASK(31, 0) +#define RFU_0X1A2C 0x00001a2c + #define RFU_0X1A2C_RESERVED_0X1A2C GENMASK(31, 0) +#define SHU3_R2_B1_DQ0 0x00001a50 + #define SHU3_R2_B1_DQ0_RK2_TX_ARDQ0_DLY_B1 GENMASK(3, 0) + #define SHU3_R2_B1_DQ0_RK2_TX_ARDQ1_DLY_B1 GENMASK(7, 4) + #define SHU3_R2_B1_DQ0_RK2_TX_ARDQ2_DLY_B1 GENMASK(11, 8) + #define SHU3_R2_B1_DQ0_RK2_TX_ARDQ3_DLY_B1 GENMASK(15, 12) + #define SHU3_R2_B1_DQ0_RK2_TX_ARDQ4_DLY_B1 GENMASK(19, 16) + #define SHU3_R2_B1_DQ0_RK2_TX_ARDQ5_DLY_B1 GENMASK(23, 20) + #define SHU3_R2_B1_DQ0_RK2_TX_ARDQ6_DLY_B1 GENMASK(27, 24) + #define SHU3_R2_B1_DQ0_RK2_TX_ARDQ7_DLY_B1 GENMASK(31, 28) +#define SHU3_R2_B1_DQ1 0x00001a54 + #define SHU3_R2_B1_DQ1_RK2_TX_ARDQM0_DLY_B1 GENMASK(3, 0) + #define SHU3_R2_B1_DQ1_RK2_TX_ARDQS0_DLYB_B1 GENMASK(19, 16) + #define SHU3_R2_B1_DQ1_RK2_TX_ARDQS0B_DLYB_B1 GENMASK(23, 20) + #define SHU3_R2_B1_DQ1_RK2_TX_ARDQS0_DLY_B1 GENMASK(27, 24) + #define SHU3_R2_B1_DQ1_RK2_TX_ARDQS0B_DLY_B1 GENMASK(31, 28) +#define SHU3_R2_B1_DQ2 0x00001a58 + #define SHU3_R2_B1_DQ2_RK2_RX_ARDQ0_R_DLY_B1 GENMASK(5, 0) + #define SHU3_R2_B1_DQ2_RK2_RX_ARDQ0_F_DLY_B1 GENMASK(13, 8) + #define SHU3_R2_B1_DQ2_RK2_RX_ARDQ1_R_DLY_B1 GENMASK(21, 16) + #define SHU3_R2_B1_DQ2_RK2_RX_ARDQ1_F_DLY_B1 GENMASK(29, 24) +#define SHU3_R2_B1_DQ3 0x00001a5c + #define SHU3_R2_B1_DQ3_RK2_RX_ARDQ2_R_DLY_B1 GENMASK(5, 0) + #define SHU3_R2_B1_DQ3_RK2_RX_ARDQ2_F_DLY_B1 GENMASK(13, 8) + #define SHU3_R2_B1_DQ3_RK2_RX_ARDQ3_R_DLY_B1 GENMASK(21, 16) + #define SHU3_R2_B1_DQ3_RK2_RX_ARDQ3_F_DLY_B1 GENMASK(29, 24) +#define SHU3_R2_B1_DQ4 0x00001a60 + #define SHU3_R2_B1_DQ4_RK2_RX_ARDQ4_R_DLY_B1 GENMASK(5, 0) + #define SHU3_R2_B1_DQ4_RK2_RX_ARDQ4_F_DLY_B1 GENMASK(13, 8) + #define SHU3_R2_B1_DQ4_RK2_RX_ARDQ5_R_DLY_B1 GENMASK(21, 16) + #define SHU3_R2_B1_DQ4_RK2_RX_ARDQ5_F_DLY_B1 GENMASK(29, 24) +#define SHU3_R2_B1_DQ5 0x00001a64 + #define SHU3_R2_B1_DQ5_RK2_RX_ARDQ6_R_DLY_B1 GENMASK(5, 0) + #define SHU3_R2_B1_DQ5_RK2_RX_ARDQ6_F_DLY_B1 GENMASK(13, 8) + #define SHU3_R2_B1_DQ5_RK2_RX_ARDQ7_R_DLY_B1 GENMASK(21, 16) + #define SHU3_R2_B1_DQ5_RK2_RX_ARDQ7_F_DLY_B1 GENMASK(29, 24) +#define SHU3_R2_B1_DQ6 0x00001a68 + #define SHU3_R2_B1_DQ6_RK2_RX_ARDQM0_R_DLY_B1 GENMASK(5, 0) + #define SHU3_R2_B1_DQ6_RK2_RX_ARDQM0_F_DLY_B1 GENMASK(13, 8) + #define SHU3_R2_B1_DQ6_RK2_RX_ARDQS0_R_DLY_B1 GENMASK(22, 16) + #define SHU3_R2_B1_DQ6_RK2_RX_ARDQS0_F_DLY_B1 GENMASK(30, 24) +#define SHU3_R2_B1_DQ7 0x00001a6c + #define SHU3_R2_B1_DQ7_RK2_ARPI_DQ_B1 GENMASK(13, 8) + #define SHU3_R2_B1_DQ7_RK2_ARPI_DQM_B1 GENMASK(21, 16) + #define SHU3_R2_B1_DQ7_RK2_ARPI_PBYTE_B1 GENMASK(29, 24) +#define RFU_0X1A70 0x00001a70 + #define RFU_0X1A70_RESERVED_0X1A70 GENMASK(31, 0) +#define RFU_0X1A74 0x00001a74 + #define RFU_0X1A74_RESERVED_0X1A74 GENMASK(31, 0) +#define RFU_0X1A78 0x00001a78 + #define RFU_0X1A78_RESERVED_0X1A78 GENMASK(31, 0) +#define RFU_0X1A7C 0x00001a7c + #define RFU_0X1A7C_RESERVED_0X1A7C GENMASK(31, 0) +#define SHU3_R2_CA_CMD0 0x00001aa0 + #define SHU3_R2_CA_CMD0_RK2_TX_ARCA0_DLY GENMASK(3, 0) + #define SHU3_R2_CA_CMD0_RK2_TX_ARCA1_DLY GENMASK(7, 4) + #define SHU3_R2_CA_CMD0_RK2_TX_ARCA2_DLY GENMASK(11, 8) + #define SHU3_R2_CA_CMD0_RK2_TX_ARCA3_DLY GENMASK(15, 12) + #define SHU3_R2_CA_CMD0_RK2_TX_ARCA4_DLY GENMASK(19, 16) + #define SHU3_R2_CA_CMD0_RK2_TX_ARCA5_DLY GENMASK(23, 20) + #define SHU3_R2_CA_CMD0_RK2_TX_ARCLK_DLYB GENMASK(27, 24) + #define SHU3_R2_CA_CMD0_RK2_TX_ARCLKB_DLYB GENMASK(31, 28) +#define SHU3_R2_CA_CMD1 0x00001aa4 + #define SHU3_R2_CA_CMD1_RK2_TX_ARCKE0_DLY GENMASK(3, 0) + #define SHU3_R2_CA_CMD1_RK2_TX_ARCKE1_DLY GENMASK(7, 4) + #define SHU3_R2_CA_CMD1_RK2_TX_ARCKE2_DLY GENMASK(11, 8) + #define SHU3_R2_CA_CMD1_RK2_TX_ARCS0_DLY GENMASK(15, 12) + #define SHU3_R2_CA_CMD1_RK2_TX_ARCS1_DLY GENMASK(19, 16) + #define SHU3_R2_CA_CMD1_RK2_TX_ARCS2_DLY GENMASK(23, 20) + #define SHU3_R2_CA_CMD1_RK2_TX_ARCLK_DLY GENMASK(27, 24) + #define SHU3_R2_CA_CMD1_RK2_TX_ARCLKB_DLY GENMASK(31, 28) +#define SHU3_R2_CA_CMD2 0x00001aa8 + #define SHU3_R2_CA_CMD2_RG_RK2_RX_ARCA0_R_DLY GENMASK(5, 0) + #define SHU3_R2_CA_CMD2_RG_RK2_RX_ARCA0_F_DLY GENMASK(13, 8) + #define SHU3_R2_CA_CMD2_RG_RK2_RX_ARCA1_R_DLY GENMASK(21, 16) + #define SHU3_R2_CA_CMD2_RG_RK2_RX_ARCA1_F_DLY GENMASK(29, 24) +#define SHU3_R2_CA_CMD3 0x00001aac + #define SHU3_R2_CA_CMD3_RG_RK2_RX_ARCA2_R_DLY GENMASK(5, 0) + #define SHU3_R2_CA_CMD3_RG_RK2_RX_ARCA2_F_DLY GENMASK(13, 8) + #define SHU3_R2_CA_CMD3_RG_RK2_RX_ARCA3_R_DLY GENMASK(21, 16) + #define SHU3_R2_CA_CMD3_RG_RK2_RX_ARCA3_F_DLY GENMASK(29, 24) +#define SHU3_R2_CA_CMD4 0x00001ab0 + #define SHU3_R2_CA_CMD4_RG_RK2_RX_ARCA4_R_DLY GENMASK(5, 0) + #define SHU3_R2_CA_CMD4_RG_RK2_RX_ARCA4_F_DLY GENMASK(13, 8) + #define SHU3_R2_CA_CMD4_RG_RK2_RX_ARCA5_R_DLY GENMASK(21, 16) + #define SHU3_R2_CA_CMD4_RG_RK2_RX_ARCA5_F_DLY GENMASK(29, 24) +#define SHU3_R2_CA_CMD5 0x00001ab4 + #define SHU3_R2_CA_CMD5_RG_RK2_RX_ARCKE0_R_DLY GENMASK(5, 0) + #define SHU3_R2_CA_CMD5_RG_RK2_RX_ARCKE0_F_DLY GENMASK(13, 8) + #define SHU3_R2_CA_CMD5_RG_RK2_RX_ARCKE1_R_DLY GENMASK(21, 16) + #define SHU3_R2_CA_CMD5_RG_RK2_RX_ARCKE1_F_DLY GENMASK(29, 24) +#define SHU3_R2_CA_CMD6 0x00001ab8 + #define SHU3_R2_CA_CMD6_RG_RK2_RX_ARCKE2_R_DLY GENMASK(5, 0) + #define SHU3_R2_CA_CMD6_RG_RK2_RX_ARCKE2_F_DLY GENMASK(13, 8) + #define SHU3_R2_CA_CMD6_RG_RK2_RX_ARCS0_R_DLY GENMASK(21, 16) + #define SHU3_R2_CA_CMD6_RG_RK2_RX_ARCS0_F_DLY GENMASK(29, 24) +#define SHU3_R2_CA_CMD7 0x00001abc + #define SHU3_R2_CA_CMD7_RG_RK2_RX_ARCS1_R_DLY GENMASK(5, 0) + #define SHU3_R2_CA_CMD7_RG_RK2_RX_ARCS1_F_DLY GENMASK(13, 8) + #define SHU3_R2_CA_CMD7_RG_RK2_RX_ARCS2_R_DLY GENMASK(21, 16) + #define SHU3_R2_CA_CMD7_RG_RK2_RX_ARCS2_F_DLY GENMASK(29, 24) +#define SHU3_R2_CA_CMD8 0x00001ac0 + #define SHU3_R2_CA_CMD8_RG_RK2_RX_ARCLK_R_DLY GENMASK(22, 16) + #define SHU3_R2_CA_CMD8_RG_RK2_RX_ARCLK_F_DLY GENMASK(30, 24) +#define SHU3_R2_CA_CMD9 0x00001ac4 + #define SHU3_R2_CA_CMD9_RG_RK2_ARPI_CS GENMASK(5, 0) + #define SHU3_R2_CA_CMD9_RG_RK2_ARPI_CMD GENMASK(13, 8) + #define SHU3_R2_CA_CMD9_RG_RK2_ARPI_CLK GENMASK(29, 24) +#define RFU_0X1AC8 0x00001ac8 + #define RFU_0X1AC8_RESERVED_0X1AC8 GENMASK(31, 0) +#define RFU_0X1ACC 0x00001acc + #define RFU_0X1ACC_RESERVED_0X1ACC GENMASK(31, 0) +#define SHU4_B0_DQ0 0x00001b00 + #define SHU4_B0_DQ0_RG_TX_ARDQS0_PRE_EN_B0 BIT(4) + #define SHU4_B0_DQ0_RG_TX_ARDQS0_DRVP_PRE_B0 GENMASK(10, 8) + #define SHU4_B0_DQ0_RG_TX_ARDQS0_DRVN_PRE_B0 GENMASK(14, 12) + #define SHU4_B0_DQ0_RG_TX_ARDQ_PRE_EN_B0 BIT(20) + #define SHU4_B0_DQ0_RG_TX_ARDQ_DRVP_PRE_B0 GENMASK(26, 24) + #define SHU4_B0_DQ0_RG_TX_ARDQ_DRVN_PRE_B0 GENMASK(30, 28) + #define SHU4_B0_DQ0_R_LP4Y_WDN_MODE_DQS0 BIT(31) +#define SHU4_B0_DQ1 0x00001b04 + #define SHU4_B0_DQ1_RG_TX_ARDQ_DRVP_B0 GENMASK(4, 0) + #define SHU4_B0_DQ1_RG_TX_ARDQ_DRVN_B0 GENMASK(12, 8) + #define SHU4_B0_DQ1_RG_TX_ARDQ_ODTP_B0 GENMASK(20, 16) + #define SHU4_B0_DQ1_RG_TX_ARDQ_ODTN_B0 GENMASK(28, 24) +#define SHU4_B0_DQ2 0x00001b08 + #define SHU4_B0_DQ2_RG_TX_ARDQS0_DRVP_B0 GENMASK(4, 0) + #define SHU4_B0_DQ2_RG_TX_ARDQS0_DRVN_B0 GENMASK(12, 8) + #define SHU4_B0_DQ2_RG_TX_ARDQS0_ODTP_B0 GENMASK(20, 16) + #define SHU4_B0_DQ2_RG_TX_ARDQS0_ODTN_B0 GENMASK(28, 24) +#define SHU4_B0_DQ3 0x00001b0c + #define SHU4_B0_DQ3_RG_TX_ARDQS0_PU_B0 GENMASK(1, 0) + #define SHU4_B0_DQ3_RG_TX_ARDQS0_PU_PRE_B0 GENMASK(3, 2) + #define SHU4_B0_DQ3_RG_TX_ARDQS0_PDB_B0 GENMASK(5, 4) + #define SHU4_B0_DQ3_RG_TX_ARDQS0_PDB_PRE_B0 GENMASK(7, 6) + #define SHU4_B0_DQ3_RG_TX_ARDQ_PU_B0 GENMASK(9, 8) + #define SHU4_B0_DQ3_RG_TX_ARDQ_PU_PRE_B0 GENMASK(11, 10) + #define SHU4_B0_DQ3_RG_TX_ARDQ_PDB_B0 GENMASK(13, 12) + #define SHU4_B0_DQ3_RG_TX_ARDQ_PDB_PRE_B0 GENMASK(15, 14) +#define SHU4_B0_DQ4 0x00001b10 + #define SHU4_B0_DQ4_RG_ARPI_AA_MCK_DL_B0 GENMASK(5, 0) + #define SHU4_B0_DQ4_RG_ARPI_AA_MCK_FB_DL_B0 GENMASK(13, 8) + #define SHU4_B0_DQ4_RG_ARPI_DA_MCK_FB_DL_B0 GENMASK(21, 16) +#define SHU4_B0_DQ5 0x00001b14 + #define SHU4_B0_DQ5_RG_RX_ARDQ_VREF_SEL_B0 GENMASK(5, 0) + #define SHU4_B0_DQ5_RG_RX_ARDQ_VREF_BYPASS_B0 BIT(6) + #define SHU4_B0_DQ5_RG_ARPI_FB_B0 GENMASK(13, 8) + #define SHU4_B0_DQ5_RG_RX_ARDQS0_DQSIEN_DLY_B0 GENMASK(18, 16) + #define SHU4_B0_DQ5_DA_RX_ARDQS_DQSIEN_RB_DLY_B0 BIT(19) + #define SHU4_B0_DQ5_RG_RX_ARDQS0_DVS_DLY_B0 GENMASK(22, 20) + #define SHU4_B0_DQ5_RG_ARPI_MCTL_B0 GENMASK(29, 24) +#define SHU4_B0_DQ6 0x00001b18 + #define SHU4_B0_DQ6_RG_ARPI_OFFSET_DQSIEN_B0 GENMASK(5, 0) + #define SHU4_B0_DQ6_RG_ARPI_RESERVE_B0 GENMASK(21, 6) + #define SHU4_B0_DQ6_RG_ARPI_MIDPI_CAP_SEL_B0 GENMASK(23, 22) + #define SHU4_B0_DQ6_RG_ARPI_MIDPI_VTH_SEL_B0 GENMASK(25, 24) + #define SHU4_B0_DQ6_RG_ARPI_MIDPI_EN_B0 BIT(26) + #define SHU4_B0_DQ6_RG_ARPI_MIDPI_CKDIV4_EN_B0 BIT(27) + #define SHU4_B0_DQ6_RG_ARPI_CAP_SEL_B0 GENMASK(29, 28) + #define SHU4_B0_DQ6_RG_ARPI_MIDPI_BYPASS_EN_B0 BIT(31) +#define SHU4_B0_DQ7 0x00001b1c + #define SHU4_B0_DQ7_R_DMRANKRXDVS_B0 GENMASK(3, 0) + #define SHU4_B0_DQ7_MIDPI_ENABLE BIT(4) + #define SHU4_B0_DQ7_MIDPI_DIV4_ENABLE BIT(5) + #define SHU4_B0_DQ7_R_DMDQMDBI_EYE_SHU_B0 BIT(6) + #define SHU4_B0_DQ7_R_DMDQMDBI_SHU_B0 BIT(7) + #define SHU4_B0_DQ7_R_DMRXDVS_DQM_FLAGSEL_B0 GENMASK(11, 8) + #define SHU4_B0_DQ7_R_DMRXDVS_PBYTE_FLAG_OPT_B0 BIT(12) + #define SHU4_B0_DQ7_R_DMRXDVS_PBYTE_DQM_EN_B0 BIT(13) + #define SHU4_B0_DQ7_R_DMRXTRACK_DQM_EN_B0 BIT(14) + #define SHU4_B0_DQ7_R_DMRODTEN_B0 BIT(15) + #define SHU4_B0_DQ7_R_DMARPI_CG_FB2DLL_DCM_EN_B0 BIT(16) + #define SHU4_B0_DQ7_R_DMTX_ARPI_CG_DQ_NEW_B0 BIT(17) + #define SHU4_B0_DQ7_R_DMTX_ARPI_CG_DQS_NEW_B0 BIT(18) + #define SHU4_B0_DQ7_R_DMTX_ARPI_CG_DQM_NEW_B0 BIT(19) + #define SHU4_B0_DQ7_R_LP4Y_SDN_MODE_DQS0 BIT(20) + #define SHU4_B0_DQ7_R_DMRXRANK_DQ_EN_B0 BIT(24) + #define SHU4_B0_DQ7_R_DMRXRANK_DQ_LAT_B0 GENMASK(27, 25) + #define SHU4_B0_DQ7_R_DMRXRANK_DQS_EN_B0 BIT(28) + #define SHU4_B0_DQ7_R_DMRXRANK_DQS_LAT_B0 GENMASK(31, 29) +#define SHU4_B0_DQ8 0x00001b20 + #define SHU4_B0_DQ8_R_DMRXDVS_UPD_FORCE_CYC_B0 GENMASK(14, 0) + #define SHU4_B0_DQ8_R_DMRXDVS_UPD_FORCE_EN_B0 BIT(15) + #define SHU4_B0_DQ8_R_DMRANK_RXDLY_PIPE_CG_IG_B0 BIT(19) + #define SHU4_B0_DQ8_R_RMRODTEN_CG_IG_B0 BIT(20) + #define SHU4_B0_DQ8_R_RMRX_TOPHY_CG_IG_B0 BIT(21) + #define SHU4_B0_DQ8_R_DMRXDVS_RDSEL_PIPE_CG_IG_B0 BIT(22) + #define SHU4_B0_DQ8_R_DMRXDVS_RDSEL_TOG_PIPE_CG_IG_B0 BIT(23) + #define SHU4_B0_DQ8_R_DMRXDLY_CG_IG_B0 BIT(24) + #define SHU4_B0_DQ8_R_DMSTBEN_SYNC_CG_IG_B0 BIT(25) + #define SHU4_B0_DQ8_R_DMDQSIEN_FLAG_SYNC_CG_IG_B0 BIT(26) + #define SHU4_B0_DQ8_R_DMDQSIEN_FLAG_PIPE_CG_IG_B0 BIT(27) + #define SHU4_B0_DQ8_R_DMDQSIEN_RDSEL_PIPE_CG_IG_B0 BIT(28) + #define SHU4_B0_DQ8_R_DMDQSIEN_RDSEL_TOG_PIPE_CG_IG_B0 BIT(29) + #define SHU4_B0_DQ8_R_DMRANK_PIPE_CG_IG_B0 BIT(30) + #define SHU4_B0_DQ8_R_DMRANK_CHG_PIPE_CG_IG_B0 BIT(31) +#define SHU4_B0_DQ9 0x00001b24 + #define SHU4_B0_DQ9_RESERVED_0X1B24 GENMASK(31, 0) +#define SHU4_B0_DQ10 0x00001b28 + #define SHU4_B0_DQ10_RESERVED_0X1B28 GENMASK(31, 0) +#define SHU4_B0_DQ11 0x00001b2c + #define SHU4_B0_DQ11_RESERVED_0X1B2C GENMASK(31, 0) +#define SHU4_B0_DQ12 0x00001b30 + #define SHU4_B0_DQ12_RESERVED_0X1B30 GENMASK(31, 0) +#define SHU4_B0_DLL0 0x00001b34 + #define SHU4_B0_DLL0_RG_ARPISM_MCK_SEL_B0_SHU BIT(0) + #define SHU4_B0_DLL0_B0_DLL0_RFU BIT(3) + #define SHU4_B0_DLL0_RG_ARDLL_FAST_PSJP_B0 BIT(4) + #define SHU4_B0_DLL0_RG_ARDLL_PHDIV_B0 BIT(9) + #define SHU4_B0_DLL0_RG_ARDLL_PHJUMP_EN_B0 BIT(10) + #define SHU4_B0_DLL0_RG_ARDLL_P_GAIN_B0 GENMASK(15, 12) + #define SHU4_B0_DLL0_RG_ARDLL_IDLECNT_B0 GENMASK(19, 16) + #define SHU4_B0_DLL0_RG_ARDLL_GAIN_B0 GENMASK(23, 20) + #define SHU4_B0_DLL0_RG_ARDLL_PHDET_IN_SWAP_B0 BIT(30) + #define SHU4_B0_DLL0_RG_ARDLL_PHDET_OUT_SEL_B0 BIT(31) +#define SHU4_B0_DLL1 0x00001b38 + #define SHU4_B0_DLL1_RG_ARDLL_FASTPJ_CK_SEL_B0 BIT(0) + #define SHU4_B0_DLL1_RG_ARDLL_PS_EN_B0 BIT(1) + #define SHU4_B0_DLL1_RG_ARDLL_PD_CK_SEL_B0 BIT(2) + #define SHU4_B0_DLL1_RG_ARDQ_REV_B0 GENMASK(31, 8) +#define SHU4_B1_DQ0 0x00001b80 + #define SHU4_B1_DQ0_RG_TX_ARDQS0_PRE_EN_B1 BIT(4) + #define SHU4_B1_DQ0_RG_TX_ARDQS0_DRVP_PRE_B1 GENMASK(10, 8) + #define SHU4_B1_DQ0_RG_TX_ARDQS0_DRVN_PRE_B1 GENMASK(14, 12) + #define SHU4_B1_DQ0_RG_TX_ARDQ_PRE_EN_B1 BIT(20) + #define SHU4_B1_DQ0_RG_TX_ARDQ_DRVP_PRE_B1 GENMASK(26, 24) + #define SHU4_B1_DQ0_RG_TX_ARDQ_DRVN_PRE_B1 GENMASK(30, 28) + #define SHU4_B1_DQ0_R_LP4Y_WDN_MODE_DQS1 BIT(31) +#define SHU4_B1_DQ1 0x00001b84 + #define SHU4_B1_DQ1_RG_TX_ARDQ_DRVP_B1 GENMASK(4, 0) + #define SHU4_B1_DQ1_RG_TX_ARDQ_DRVN_B1 GENMASK(12, 8) + #define SHU4_B1_DQ1_RG_TX_ARDQ_ODTP_B1 GENMASK(20, 16) + #define SHU4_B1_DQ1_RG_TX_ARDQ_ODTN_B1 GENMASK(28, 24) +#define SHU4_B1_DQ2 0x00001b88 + #define SHU4_B1_DQ2_RG_TX_ARDQS0_DRVP_B1 GENMASK(4, 0) + #define SHU4_B1_DQ2_RG_TX_ARDQS0_DRVN_B1 GENMASK(12, 8) + #define SHU4_B1_DQ2_RG_TX_ARDQS0_ODTP_B1 GENMASK(20, 16) + #define SHU4_B1_DQ2_RG_TX_ARDQS0_ODTN_B1 GENMASK(28, 24) +#define SHU4_B1_DQ3 0x00001b8c + #define SHU4_B1_DQ3_RG_TX_ARDQS0_PU_B1 GENMASK(1, 0) + #define SHU4_B1_DQ3_RG_TX_ARDQS0_PU_PRE_B1 GENMASK(3, 2) + #define SHU4_B1_DQ3_RG_TX_ARDQS0_PDB_B1 GENMASK(5, 4) + #define SHU4_B1_DQ3_RG_TX_ARDQS0_PDB_PRE_B1 GENMASK(7, 6) + #define SHU4_B1_DQ3_RG_TX_ARDQ_PU_B1 GENMASK(9, 8) + #define SHU4_B1_DQ3_RG_TX_ARDQ_PU_PRE_B1 GENMASK(11, 10) + #define SHU4_B1_DQ3_RG_TX_ARDQ_PDB_B1 GENMASK(13, 12) + #define SHU4_B1_DQ3_RG_TX_ARDQ_PDB_PRE_B1 GENMASK(15, 14) +#define SHU4_B1_DQ4 0x00001b90 + #define SHU4_B1_DQ4_RG_ARPI_AA_MCK_DL_B1 GENMASK(5, 0) + #define SHU4_B1_DQ4_RG_ARPI_AA_MCK_FB_DL_B1 GENMASK(13, 8) + #define SHU4_B1_DQ4_RG_ARPI_DA_MCK_FB_DL_B1 GENMASK(21, 16) +#define SHU4_B1_DQ5 0x00001b94 + #define SHU4_B1_DQ5_RG_RX_ARDQ_VREF_SEL_B1 GENMASK(5, 0) + #define SHU4_B1_DQ5_RG_RX_ARDQ_VREF_BYPASS_B1 BIT(6) + #define SHU4_B1_DQ5_RG_ARPI_FB_B1 GENMASK(13, 8) + #define SHU4_B1_DQ5_RG_RX_ARDQS0_DQSIEN_DLY_B1 GENMASK(18, 16) + #define SHU4_B1_DQ5_DA_RX_ARDQS_DQSIEN_RB_DLY_B1 BIT(19) + #define SHU4_B1_DQ5_RG_RX_ARDQS0_DVS_DLY_B1 GENMASK(22, 20) + #define SHU4_B1_DQ5_RG_ARPI_MCTL_B1 GENMASK(29, 24) +#define SHU4_B1_DQ6 0x00001b98 + #define SHU4_B1_DQ6_RG_ARPI_OFFSET_DQSIEN_B1 GENMASK(5, 0) + #define SHU4_B1_DQ6_RG_ARPI_RESERVE_B1 GENMASK(21, 6) + #define SHU4_B1_DQ6_RG_ARPI_MIDPI_CAP_SEL_B1 GENMASK(23, 22) + #define SHU4_B1_DQ6_RG_ARPI_MIDPI_VTH_SEL_B1 GENMASK(25, 24) + #define SHU4_B1_DQ6_RG_ARPI_MIDPI_EN_B1 BIT(26) + #define SHU4_B1_DQ6_RG_ARPI_MIDPI_CKDIV4_EN_B1 BIT(27) + #define SHU4_B1_DQ6_RG_ARPI_CAP_SEL_B1 GENMASK(29, 28) + #define SHU4_B1_DQ6_RG_ARPI_MIDPI_BYPASS_EN_B1 BIT(31) +#define SHU4_B1_DQ7 0x00001b9c + #define SHU4_B1_DQ7_R_DMRANKRXDVS_B1 GENMASK(3, 0) + #define SHU4_B1_DQ7_R_DMDQMDBI_EYE_SHU_B1 BIT(6) + #define SHU4_B1_DQ7_R_DMDQMDBI_SHU_B1 BIT(7) + #define SHU4_B1_DQ7_R_DMRXDVS_DQM_FLAGSEL_B1 GENMASK(11, 8) + #define SHU4_B1_DQ7_R_DMRXDVS_PBYTE_FLAG_OPT_B1 BIT(12) + #define SHU4_B1_DQ7_R_DMRXDVS_PBYTE_DQM_EN_B1 BIT(13) + #define SHU4_B1_DQ7_R_DMRXTRACK_DQM_EN_B1 BIT(14) + #define SHU4_B1_DQ7_R_DMRODTEN_B1 BIT(15) + #define SHU4_B1_DQ7_R_DMARPI_CG_FB2DLL_DCM_EN_B1 BIT(16) + #define SHU4_B1_DQ7_R_DMTX_ARPI_CG_DQ_NEW_B1 BIT(17) + #define SHU4_B1_DQ7_R_DMTX_ARPI_CG_DQS_NEW_B1 BIT(18) + #define SHU4_B1_DQ7_R_DMTX_ARPI_CG_DQM_NEW_B1 BIT(19) + #define SHU4_B1_DQ7_R_LP4Y_SDN_MODE_DQS1 BIT(20) + #define SHU4_B1_DQ7_R_DMRXRANK_DQ_EN_B1 BIT(24) + #define SHU4_B1_DQ7_R_DMRXRANK_DQ_LAT_B1 GENMASK(27, 25) + #define SHU4_B1_DQ7_R_DMRXRANK_DQS_EN_B1 BIT(28) + #define SHU4_B1_DQ7_R_DMRXRANK_DQS_LAT_B1 GENMASK(31, 29) +#define SHU4_B1_DQ8 0x00001ba0 + #define SHU4_B1_DQ8_R_DMRXDVS_UPD_FORCE_CYC_B1 GENMASK(14, 0) + #define SHU4_B1_DQ8_R_DMRXDVS_UPD_FORCE_EN_B1 BIT(15) + #define SHU4_B1_DQ8_R_DMRANK_RXDLY_PIPE_CG_IG_B1 BIT(19) + #define SHU4_B1_DQ8_R_RMRODTEN_CG_IG_B1 BIT(20) + #define SHU4_B1_DQ8_R_RMRX_TOPHY_CG_IG_B1 BIT(21) + #define SHU4_B1_DQ8_R_DMRXDVS_RDSEL_PIPE_CG_IG_B1 BIT(22) + #define SHU4_B1_DQ8_R_DMRXDVS_RDSEL_TOG_PIPE_CG_IG_B1 BIT(23) + #define SHU4_B1_DQ8_R_DMRXDLY_CG_IG_B1 BIT(24) + #define SHU4_B1_DQ8_R_DMSTBEN_SYNC_CG_IG_B1 BIT(25) + #define SHU4_B1_DQ8_R_DMDQSIEN_FLAG_SYNC_CG_IG_B1 BIT(26) + #define SHU4_B1_DQ8_R_DMDQSIEN_FLAG_PIPE_CG_IG_B1 BIT(27) + #define SHU4_B1_DQ8_R_DMDQSIEN_RDSEL_PIPE_CG_IG_B1 BIT(28) + #define SHU4_B1_DQ8_R_DMDQSIEN_RDSEL_TOG_PIPE_CG_IG_B1 BIT(29) + #define SHU4_B1_DQ8_R_DMRANK_PIPE_CG_IG_B1 BIT(30) + #define SHU4_B1_DQ8_R_DMRANK_CHG_PIPE_CG_IG_B1 BIT(31) +#define SHU4_B1_DQ9 0x00001ba4 + #define SHU4_B1_DQ9_RESERVED_0X1BA4 GENMASK(31, 0) +#define SHU4_B1_DQ10 0x00001ba8 + #define SHU4_B1_DQ10_RESERVED_0X1BA8 GENMASK(31, 0) +#define SHU4_B1_DQ11 0x00001bac + #define SHU4_B1_DQ11_RESERVED_0X1BAC GENMASK(31, 0) +#define SHU4_B1_DQ12 0x00001bb0 + #define SHU4_B1_DQ12_RESERVED_0X1BB0 GENMASK(31, 0) +#define SHU4_B1_DLL0 0x00001bb4 + #define SHU4_B1_DLL0_RG_ARPISM_MCK_SEL_B1_SHU BIT(0) + #define SHU4_B1_DLL0_B1_DLL0_RFU BIT(3) + #define SHU4_B1_DLL0_RG_ARDLL_FAST_PSJP_B1 BIT(4) + #define SHU4_B1_DLL0_RG_ARDLL_PHDIV_B1 BIT(9) + #define SHU4_B1_DLL0_RG_ARDLL_PHJUMP_EN_B1 BIT(10) + #define SHU4_B1_DLL0_RG_ARDLL_P_GAIN_B1 GENMASK(15, 12) + #define SHU4_B1_DLL0_RG_ARDLL_IDLECNT_B1 GENMASK(19, 16) + #define SHU4_B1_DLL0_RG_ARDLL_GAIN_B1 GENMASK(23, 20) + #define SHU4_B1_DLL0_RG_ARDLL_PHDET_IN_SWAP_B1 BIT(30) + #define SHU4_B1_DLL0_RG_ARDLL_PHDET_OUT_SEL_B1 BIT(31) +#define SHU4_B1_DLL1 0x00001bb8 + #define SHU4_B1_DLL1_RG_ARDLL_FASTPJ_CK_SEL_B1 BIT(0) + #define SHU4_B1_DLL1_RG_ARDLL_PS_EN_B1 BIT(1) + #define SHU4_B1_DLL1_RG_ARDLL_PD_CK_SEL_B1 BIT(2) + #define SHU4_B1_DLL1_RG_ARDQ_REV_B1 GENMASK(31, 8) +#define SHU4_CA_CMD0 0x00001c00 + #define SHU4_CA_CMD0_RG_TX_ARCLK_PRE_EN BIT(4) + #define SHU4_CA_CMD0_RG_TX_ARCLK_DRVP_PRE GENMASK(10, 8) + #define SHU4_CA_CMD0_RG_TX_ARCLK_DRVN_PRE GENMASK(14, 12) + #define SHU4_CA_CMD0_RG_CGEN_FMEM_CK_CG_DLL BIT(17) + #define SHU4_CA_CMD0_RG_FB_CK_MUX GENMASK(19, 18) + #define SHU4_CA_CMD0_RG_TX_ARCMD_PRE_EN BIT(20) + #define SHU4_CA_CMD0_RG_TX_ARCMD_DRVP_PRE GENMASK(26, 24) + #define SHU4_CA_CMD0_RG_TX_ARCMD_DRVN_PRE GENMASK(30, 28) + #define SHU4_CA_CMD0_R_LP4Y_WDN_MODE_CLK BIT(31) +#define SHU4_CA_CMD1 0x00001c04 + #define SHU4_CA_CMD1_RG_TX_ARCMD_DRVP GENMASK(4, 0) + #define SHU4_CA_CMD1_RG_TX_ARCMD_DRVN GENMASK(12, 8) + #define SHU4_CA_CMD1_RG_TX_ARCMD_ODTP GENMASK(20, 16) + #define SHU4_CA_CMD1_RG_TX_ARCMD_ODTN GENMASK(28, 24) +#define SHU4_CA_CMD2 0x00001c08 + #define SHU4_CA_CMD2_RG_TX_ARCLK_DRVP GENMASK(4, 0) + #define SHU4_CA_CMD2_RG_TX_ARCLK_DRVN GENMASK(12, 8) + #define SHU4_CA_CMD2_RG_TX_ARCLK_ODTP GENMASK(20, 16) + #define SHU4_CA_CMD2_RG_TX_ARCLK_ODTN GENMASK(28, 24) +#define SHU4_CA_CMD3 0x00001c0c + #define SHU4_CA_CMD3_RG_TX_ARCLK_PU GENMASK(1, 0) + #define SHU4_CA_CMD3_RG_TX_ARCLK_PU_PRE GENMASK(3, 2) + #define SHU4_CA_CMD3_RG_TX_ARCLK_PDB GENMASK(5, 4) + #define SHU4_CA_CMD3_RG_TX_ARCLK_PDB_PRE GENMASK(7, 6) + #define SHU4_CA_CMD3_RG_TX_ARCMD_PU GENMASK(9, 8) + #define SHU4_CA_CMD3_RG_TX_ARCMD_PU_PRE GENMASK(11, 10) + #define SHU4_CA_CMD3_RG_TX_ARCMD_PDB GENMASK(13, 12) + #define SHU4_CA_CMD3_RG_TX_ARCMD_PDB_PRE GENMASK(15, 14) +#define SHU4_CA_CMD4 0x00001c10 + #define SHU4_CA_CMD4_RG_ARPI_AA_MCK_DL_CA GENMASK(5, 0) + #define SHU4_CA_CMD4_RG_ARPI_AA_MCK_FB_DL_CA GENMASK(13, 8) + #define SHU4_CA_CMD4_RG_ARPI_DA_MCK_FB_DL_CA GENMASK(21, 16) +#define SHU4_CA_CMD5 0x00001c14 + #define SHU4_CA_CMD5_RG_RX_ARCMD_VREF_SEL GENMASK(5, 0) + #define SHU4_CA_CMD5_RG_RX_ARCMD_VREF_BYPASS BIT(6) + #define SHU4_CA_CMD5_RG_ARPI_FB_CA GENMASK(13, 8) + #define SHU4_CA_CMD5_RG_RX_ARCLK_DQSIEN_DLY GENMASK(18, 16) + #define SHU4_CA_CMD5_DA_RX_ARCLK_DQSIEN_RB_DLY BIT(19) + #define SHU4_CA_CMD5_RG_RX_ARCLK_DVS_DLY GENMASK(22, 20) + #define SHU4_CA_CMD5_RG_ARPI_MCTL_CA GENMASK(29, 24) +#define SHU4_CA_CMD6 0x00001c18 + #define SHU4_CA_CMD6_RG_ARPI_OFFSET_CLKIEN GENMASK(5, 0) + #define SHU4_CA_CMD6_RG_ARPI_RESERVE_CA GENMASK(21, 6) + #define SHU4_CA_CMD6_RG_ARPI_MIDPI_CAP_SEL_CA GENMASK(23, 22) + #define SHU4_CA_CMD6_RG_ARPI_MIDPI_VTH_SEL_CA GENMASK(25, 24) + #define SHU4_CA_CMD6_RG_ARPI_MIDPI_EN_CA BIT(26) + #define SHU4_CA_CMD6_RG_ARPI_MIDPI_CKDIV4_EN_CA BIT(27) + #define SHU4_CA_CMD6_RG_ARPI_CAP_SEL_CA GENMASK(29, 28) + #define SHU4_CA_CMD6_RG_ARPI_MIDPI_BYPASS_EN_CA BIT(31) +#define SHU4_CA_CMD7 0x00001c1c + #define SHU4_CA_CMD7_R_DMRANKRXDVS_CA GENMASK(3, 0) + #define SHU4_CA_CMD7_R_DMRXDVS_PBYTE_FLAG_OPT_CA BIT(12) + #define SHU4_CA_CMD7_R_DMRODTEN_CA BIT(15) + #define SHU4_CA_CMD7_R_DMARPI_CG_FB2DLL_DCM_EN_CA BIT(16) + #define SHU4_CA_CMD7_R_DMTX_ARPI_CG_CMD_NEW BIT(17) + #define SHU4_CA_CMD7_R_DMTX_ARPI_CG_CLK_NEW BIT(18) + #define SHU4_CA_CMD7_R_DMTX_ARPI_CG_CS_NEW BIT(19) + #define SHU4_CA_CMD7_R_LP4Y_SDN_MODE_CLK BIT(20) + #define SHU4_CA_CMD7_R_DMRXRANK_CMD_EN BIT(24) + #define SHU4_CA_CMD7_R_DMRXRANK_CMD_LAT GENMASK(27, 25) + #define SHU4_CA_CMD7_R_DMRXRANK_CLK_EN BIT(28) + #define SHU4_CA_CMD7_R_DMRXRANK_CLK_LAT GENMASK(31, 29) +#define SHU4_CA_CMD8 0x00001c20 + #define SHU4_CA_CMD8_R_DMRXDVS_UPD_FORCE_CYC_CA GENMASK(14, 0) + #define SHU4_CA_CMD8_R_DMRXDVS_UPD_FORCE_EN_CA BIT(15) + #define SHU4_CA_CMD8_R_DMRANK_RXDLY_PIPE_CG_IG_CA BIT(19) + #define SHU4_CA_CMD8_R_RMRODTEN_CG_IG_CA BIT(20) + #define SHU4_CA_CMD8_R_RMRX_TOPHY_CG_IG_CA BIT(21) + #define SHU4_CA_CMD8_R_DMRXDVS_RDSEL_PIPE_CG_IG_CA BIT(22) + #define SHU4_CA_CMD8_R_DMRXDVS_RDSEL_TOG_PIPE_CG_IG_CA BIT(23) + #define SHU4_CA_CMD8_R_DMRXDLY_CG_IG_CA BIT(24) + #define SHU4_CA_CMD8_R_DMSTBEN_SYNC_CG_IG_CA BIT(25) + #define SHU4_CA_CMD8_R_DMDQSIEN_FLAG_SYNC_CG_IG_CA BIT(26) + #define SHU4_CA_CMD8_R_DMDQSIEN_FLAG_PIPE_CG_IG_CA BIT(27) + #define SHU4_CA_CMD8_R_DMDQSIEN_RDSEL_PIPE_CG_IG_CA BIT(28) + #define SHU4_CA_CMD8_R_DMDQSIEN_RDSEL_TOG_PIPE_CG_IG_CA BIT(29) + #define SHU4_CA_CMD8_R_DMRANK_PIPE_CG_IG_CA BIT(30) + #define SHU4_CA_CMD8_R_DMRANK_CHG_PIPE_CG_IG_CA BIT(31) +#define SHU4_CA_CMD9 0x00001c24 + #define SHU4_CA_CMD9_RESERVED_0X1C24 GENMASK(31, 0) +#define SHU4_CA_CMD10 0x00001c28 + #define SHU4_CA_CMD10_RESERVED_0X1C28 GENMASK(31, 0) +#define SHU4_CA_CMD11 0x00001c2c + #define SHU4_CA_CMD11_RG_RIMP_REV GENMASK(7, 0) + #define SHU4_CA_CMD11_RG_RIMP_VREF_SEL GENMASK(13, 8) + #define SHU4_CA_CMD11_RG_TX_ARCKE_DRVP GENMASK(21, 17) + #define SHU4_CA_CMD11_RG_TX_ARCKE_DRVN GENMASK(26, 22) +#define SHU4_CA_CMD12 0x00001c30 + #define SHU4_CA_CMD12_RESERVED_0X1C30 GENMASK(31, 0) +#define SHU4_CA_DLL0 0x00001c34 + #define SHU4_CA_DLL0_RG_ARPISM_MCK_SEL_CA_SHU BIT(0) + #define SHU4_CA_DLL0_CA_DLL0_RFU BIT(3) + #define SHU4_CA_DLL0_RG_ARDLL_FAST_PSJP_CA BIT(4) + #define SHU4_CA_DLL0_RG_ARDLL_PHDIV_CA BIT(9) + #define SHU4_CA_DLL0_RG_ARDLL_PHJUMP_EN_CA BIT(10) + #define SHU4_CA_DLL0_RG_ARDLL_P_GAIN_CA GENMASK(15, 12) + #define SHU4_CA_DLL0_RG_ARDLL_IDLECNT_CA GENMASK(19, 16) + #define SHU4_CA_DLL0_RG_ARDLL_GAIN_CA GENMASK(23, 20) + #define SHU4_CA_DLL0_RG_ARDLL_PHDET_IN_SWAP_CA BIT(30) + #define SHU4_CA_DLL0_RG_ARDLL_PHDET_OUT_SEL_CA BIT(31) +#define SHU4_CA_DLL1 0x00001c38 + #define SHU4_CA_DLL1_RG_ARDLL_FASTPJ_CK_SEL_CA BIT(0) + #define SHU4_CA_DLL1_RG_ARDLL_PS_EN_CA BIT(1) + #define SHU4_CA_DLL1_RG_ARDLL_PD_CK_SEL_CA BIT(2) + #define SHU4_CA_DLL1_RG_ARCMD_REV GENMASK(31, 8) +#define SHU4_MISC0 0x00001cf0 + #define SHU4_MISC0_R_RX_PIPE_BYPASS_EN BIT(1) + #define SHU4_MISC0_RG_CMD_TXPIPE_BYPASS_EN BIT(2) + #define SHU4_MISC0_RG_CK_TXPIPE_BYPASS_EN BIT(3) + #define SHU4_MISC0_RG_RVREF_SEL_DQ GENMASK(21, 16) + #define SHU4_MISC0_RG_RVREF_DDR4_SEL BIT(22) + #define SHU4_MISC0_RG_RVREF_DDR3_SEL BIT(23) + #define SHU4_MISC0_RG_RVREF_SEL_CMD GENMASK(29, 24) +#define SHU4_R0_B0_DQ0 0x00001d00 + #define SHU4_R0_B0_DQ0_RK0_TX_ARDQ0_DLY_B0 GENMASK(3, 0) + #define SHU4_R0_B0_DQ0_RK0_TX_ARDQ1_DLY_B0 GENMASK(7, 4) + #define SHU4_R0_B0_DQ0_RK0_TX_ARDQ2_DLY_B0 GENMASK(11, 8) + #define SHU4_R0_B0_DQ0_RK0_TX_ARDQ3_DLY_B0 GENMASK(15, 12) + #define SHU4_R0_B0_DQ0_RK0_TX_ARDQ4_DLY_B0 GENMASK(19, 16) + #define SHU4_R0_B0_DQ0_RK0_TX_ARDQ5_DLY_B0 GENMASK(23, 20) + #define SHU4_R0_B0_DQ0_RK0_TX_ARDQ6_DLY_B0 GENMASK(27, 24) + #define SHU4_R0_B0_DQ0_RK0_TX_ARDQ7_DLY_B0 GENMASK(31, 28) +#define SHU4_R0_B0_DQ1 0x00001d04 + #define SHU4_R0_B0_DQ1_RK0_TX_ARDQM0_DLY_B0 GENMASK(3, 0) + #define SHU4_R0_B0_DQ1_RK0_TX_ARDQS0_DLYB_B0 GENMASK(19, 16) + #define SHU4_R0_B0_DQ1_RK0_TX_ARDQS0B_DLYB_B0 GENMASK(23, 20) + #define SHU4_R0_B0_DQ1_RK0_TX_ARDQS0_DLY_B0 GENMASK(27, 24) + #define SHU4_R0_B0_DQ1_RK0_TX_ARDQS0B_DLY_B0 GENMASK(31, 28) +#define SHU4_R0_B0_DQ2 0x00001d08 + #define SHU4_R0_B0_DQ2_RK0_RX_ARDQ0_R_DLY_B0 GENMASK(5, 0) + #define SHU4_R0_B0_DQ2_RK0_RX_ARDQ0_F_DLY_B0 GENMASK(13, 8) + #define SHU4_R0_B0_DQ2_RK0_RX_ARDQ1_R_DLY_B0 GENMASK(21, 16) + #define SHU4_R0_B0_DQ2_RK0_RX_ARDQ1_F_DLY_B0 GENMASK(29, 24) +#define SHU4_R0_B0_DQ3 0x00001d0c + #define SHU4_R0_B0_DQ3_RK0_RX_ARDQ2_R_DLY_B0 GENMASK(5, 0) + #define SHU4_R0_B0_DQ3_RK0_RX_ARDQ2_F_DLY_B0 GENMASK(13, 8) + #define SHU4_R0_B0_DQ3_RK0_RX_ARDQ3_R_DLY_B0 GENMASK(21, 16) + #define SHU4_R0_B0_DQ3_RK0_RX_ARDQ3_F_DLY_B0 GENMASK(29, 24) +#define SHU4_R0_B0_DQ4 0x00001d10 + #define SHU4_R0_B0_DQ4_RK0_RX_ARDQ4_R_DLY_B0 GENMASK(5, 0) + #define SHU4_R0_B0_DQ4_RK0_RX_ARDQ4_F_DLY_B0 GENMASK(13, 8) + #define SHU4_R0_B0_DQ4_RK0_RX_ARDQ5_R_DLY_B0 GENMASK(21, 16) + #define SHU4_R0_B0_DQ4_RK0_RX_ARDQ5_F_DLY_B0 GENMASK(29, 24) +#define SHU4_R0_B0_DQ5 0x00001d14 + #define SHU4_R0_B0_DQ5_RK0_RX_ARDQ6_R_DLY_B0 GENMASK(5, 0) + #define SHU4_R0_B0_DQ5_RK0_RX_ARDQ6_F_DLY_B0 GENMASK(13, 8) + #define SHU4_R0_B0_DQ5_RK0_RX_ARDQ7_R_DLY_B0 GENMASK(21, 16) + #define SHU4_R0_B0_DQ5_RK0_RX_ARDQ7_F_DLY_B0 GENMASK(29, 24) +#define SHU4_R0_B0_DQ6 0x00001d18 + #define SHU4_R0_B0_DQ6_RK0_RX_ARDQM0_R_DLY_B0 GENMASK(5, 0) + #define SHU4_R0_B0_DQ6_RK0_RX_ARDQM0_F_DLY_B0 GENMASK(13, 8) + #define SHU4_R0_B0_DQ6_RK0_RX_ARDQS0_R_DLY_B0 GENMASK(22, 16) + #define SHU4_R0_B0_DQ6_RK0_RX_ARDQS0_F_DLY_B0 GENMASK(30, 24) +#define SHU4_R0_B0_DQ7 0x00001d1c + #define SHU4_R0_B0_DQ7_RK0_ARPI_DQ_B0 GENMASK(13, 8) + #define SHU4_R0_B0_DQ7_RK0_ARPI_DQM_B0 GENMASK(21, 16) + #define SHU4_R0_B0_DQ7_RK0_ARPI_PBYTE_B0 GENMASK(29, 24) +#define RFU_0X1D20 0x00001d20 + #define RFU_0X1D20_RESERVED_0X1D20 GENMASK(31, 0) +#define RFU_0X1D24 0x00001d24 + #define RFU_0X1D24_RESERVED_0X1D24 GENMASK(31, 0) +#define RFU_0X1D28 0x00001d28 + #define RFU_0X1D28_RESERVED_0X1D28 GENMASK(31, 0) +#define RFU_0X1D2C 0x00001d2c + #define RFU_0X1D2C_RESERVED_0X1D2C GENMASK(31, 0) +#define SHU4_R0_B1_DQ0 0x00001d50 + #define SHU4_R0_B1_DQ0_RK0_TX_ARDQ0_DLY_B1 GENMASK(3, 0) + #define SHU4_R0_B1_DQ0_RK0_TX_ARDQ1_DLY_B1 GENMASK(7, 4) + #define SHU4_R0_B1_DQ0_RK0_TX_ARDQ2_DLY_B1 GENMASK(11, 8) + #define SHU4_R0_B1_DQ0_RK0_TX_ARDQ3_DLY_B1 GENMASK(15, 12) + #define SHU4_R0_B1_DQ0_RK0_TX_ARDQ4_DLY_B1 GENMASK(19, 16) + #define SHU4_R0_B1_DQ0_RK0_TX_ARDQ5_DLY_B1 GENMASK(23, 20) + #define SHU4_R0_B1_DQ0_RK0_TX_ARDQ6_DLY_B1 GENMASK(27, 24) + #define SHU4_R0_B1_DQ0_RK0_TX_ARDQ7_DLY_B1 GENMASK(31, 28) +#define SHU4_R0_B1_DQ1 0x00001d54 + #define SHU4_R0_B1_DQ1_RK0_TX_ARDQM0_DLY_B1 GENMASK(3, 0) + #define SHU4_R0_B1_DQ1_RK0_TX_ARDQS0_DLYB_B1 GENMASK(19, 16) + #define SHU4_R0_B1_DQ1_RK0_TX_ARDQS0B_DLYB_B1 GENMASK(23, 20) + #define SHU4_R0_B1_DQ1_RK0_TX_ARDQS0_DLY_B1 GENMASK(27, 24) + #define SHU4_R0_B1_DQ1_RK0_TX_ARDQS0B_DLY_B1 GENMASK(31, 28) +#define SHU4_R0_B1_DQ2 0x00001d58 + #define SHU4_R0_B1_DQ2_RK0_RX_ARDQ0_R_DLY_B1 GENMASK(5, 0) + #define SHU4_R0_B1_DQ2_RK0_RX_ARDQ0_F_DLY_B1 GENMASK(13, 8) + #define SHU4_R0_B1_DQ2_RK0_RX_ARDQ1_R_DLY_B1 GENMASK(21, 16) + #define SHU4_R0_B1_DQ2_RK0_RX_ARDQ1_F_DLY_B1 GENMASK(29, 24) +#define SHU4_R0_B1_DQ3 0x00001d5c + #define SHU4_R0_B1_DQ3_RK0_RX_ARDQ2_R_DLY_B1 GENMASK(5, 0) + #define SHU4_R0_B1_DQ3_RK0_RX_ARDQ2_F_DLY_B1 GENMASK(13, 8) + #define SHU4_R0_B1_DQ3_RK0_RX_ARDQ3_R_DLY_B1 GENMASK(21, 16) + #define SHU4_R0_B1_DQ3_RK0_RX_ARDQ3_F_DLY_B1 GENMASK(29, 24) +#define SHU4_R0_B1_DQ4 0x00001d60 + #define SHU4_R0_B1_DQ4_RK0_RX_ARDQ4_R_DLY_B1 GENMASK(5, 0) + #define SHU4_R0_B1_DQ4_RK0_RX_ARDQ4_F_DLY_B1 GENMASK(13, 8) + #define SHU4_R0_B1_DQ4_RK0_RX_ARDQ5_R_DLY_B1 GENMASK(21, 16) + #define SHU4_R0_B1_DQ4_RK0_RX_ARDQ5_F_DLY_B1 GENMASK(29, 24) +#define SHU4_R0_B1_DQ5 0x00001d64 + #define SHU4_R0_B1_DQ5_RK0_RX_ARDQ6_R_DLY_B1 GENMASK(5, 0) + #define SHU4_R0_B1_DQ5_RK0_RX_ARDQ6_F_DLY_B1 GENMASK(13, 8) + #define SHU4_R0_B1_DQ5_RK0_RX_ARDQ7_R_DLY_B1 GENMASK(21, 16) + #define SHU4_R0_B1_DQ5_RK0_RX_ARDQ7_F_DLY_B1 GENMASK(29, 24) +#define SHU4_R0_B1_DQ6 0x00001d68 + #define SHU4_R0_B1_DQ6_RK0_RX_ARDQM0_R_DLY_B1 GENMASK(5, 0) + #define SHU4_R0_B1_DQ6_RK0_RX_ARDQM0_F_DLY_B1 GENMASK(13, 8) + #define SHU4_R0_B1_DQ6_RK0_RX_ARDQS0_R_DLY_B1 GENMASK(22, 16) + #define SHU4_R0_B1_DQ6_RK0_RX_ARDQS0_F_DLY_B1 GENMASK(30, 24) +#define SHU4_R0_B1_DQ7 0x00001d6c + #define SHU4_R0_B1_DQ7_RK0_ARPI_DQ_B1 GENMASK(13, 8) + #define SHU4_R0_B1_DQ7_RK0_ARPI_DQM_B1 GENMASK(21, 16) + #define SHU4_R0_B1_DQ7_RK0_ARPI_PBYTE_B1 GENMASK(29, 24) +#define RFU_0X1D70 0x00001d70 + #define RFU_0X1D70_RESERVED_0X1D70 GENMASK(31, 0) +#define RFU_0X1D74 0x00001d74 + #define RFU_0X1D74_RESERVED_0X1D74 GENMASK(31, 0) +#define RFU_0X1D78 0x00001d78 + #define RFU_0X1D78_RESERVED_0X1D78 GENMASK(31, 0) +#define RFU_0X1D7C 0x00001d7c + #define RFU_0X1D7C_RESERVED_0X1D7C GENMASK(31, 0) +#define SHU4_R0_CA_CMD0 0x00001da0 + #define SHU4_R0_CA_CMD0_RK0_TX_ARCA0_DLY GENMASK(3, 0) + #define SHU4_R0_CA_CMD0_RK0_TX_ARCA1_DLY GENMASK(7, 4) + #define SHU4_R0_CA_CMD0_RK0_TX_ARCA2_DLY GENMASK(11, 8) + #define SHU4_R0_CA_CMD0_RK0_TX_ARCA3_DLY GENMASK(15, 12) + #define SHU4_R0_CA_CMD0_RK0_TX_ARCA4_DLY GENMASK(19, 16) + #define SHU4_R0_CA_CMD0_RK0_TX_ARCA5_DLY GENMASK(23, 20) + #define SHU4_R0_CA_CMD0_RK0_TX_ARCLK_DLYB GENMASK(27, 24) + #define SHU4_R0_CA_CMD0_RK0_TX_ARCLKB_DLYB GENMASK(31, 28) +#define SHU4_R0_CA_CMD1 0x00001da4 + #define SHU4_R0_CA_CMD1_RK0_TX_ARCKE0_DLY GENMASK(3, 0) + #define SHU4_R0_CA_CMD1_RK0_TX_ARCKE1_DLY GENMASK(7, 4) + #define SHU4_R0_CA_CMD1_RK0_TX_ARCKE2_DLY GENMASK(11, 8) + #define SHU4_R0_CA_CMD1_RK0_TX_ARCS0_DLY GENMASK(15, 12) + #define SHU4_R0_CA_CMD1_RK0_TX_ARCS1_DLY GENMASK(19, 16) + #define SHU4_R0_CA_CMD1_RK0_TX_ARCS2_DLY GENMASK(23, 20) + #define SHU4_R0_CA_CMD1_RK0_TX_ARCLK_DLY GENMASK(27, 24) + #define SHU4_R0_CA_CMD1_RK0_TX_ARCLKB_DLY GENMASK(31, 28) +#define SHU4_R0_CA_CMD2 0x00001da8 + #define SHU4_R0_CA_CMD2_RG_RK0_RX_ARCA0_R_DLY GENMASK(5, 0) + #define SHU4_R0_CA_CMD2_RG_RK0_RX_ARCA0_F_DLY GENMASK(13, 8) + #define SHU4_R0_CA_CMD2_RG_RK0_RX_ARCA1_R_DLY GENMASK(21, 16) + #define SHU4_R0_CA_CMD2_RG_RK0_RX_ARCA1_F_DLY GENMASK(29, 24) +#define SHU4_R0_CA_CMD3 0x00001dac + #define SHU4_R0_CA_CMD3_RG_RK0_RX_ARCA2_R_DLY GENMASK(5, 0) + #define SHU4_R0_CA_CMD3_RG_RK0_RX_ARCA2_F_DLY GENMASK(13, 8) + #define SHU4_R0_CA_CMD3_RG_RK0_RX_ARCA3_R_DLY GENMASK(21, 16) + #define SHU4_R0_CA_CMD3_RG_RK0_RX_ARCA3_F_DLY GENMASK(29, 24) +#define SHU4_R0_CA_CMD4 0x00001db0 + #define SHU4_R0_CA_CMD4_RG_RK0_RX_ARCA4_R_DLY GENMASK(5, 0) + #define SHU4_R0_CA_CMD4_RG_RK0_RX_ARCA4_F_DLY GENMASK(13, 8) + #define SHU4_R0_CA_CMD4_RG_RK0_RX_ARCA5_R_DLY GENMASK(21, 16) + #define SHU4_R0_CA_CMD4_RG_RK0_RX_ARCA5_F_DLY GENMASK(29, 24) +#define SHU4_R0_CA_CMD5 0x00001db4 + #define SHU4_R0_CA_CMD5_RG_RK0_RX_ARCKE0_R_DLY GENMASK(5, 0) + #define SHU4_R0_CA_CMD5_RG_RK0_RX_ARCKE0_F_DLY GENMASK(13, 8) + #define SHU4_R0_CA_CMD5_RG_RK0_RX_ARCKE1_R_DLY GENMASK(21, 16) + #define SHU4_R0_CA_CMD5_RG_RK0_RX_ARCKE1_F_DLY GENMASK(29, 24) +#define SHU4_R0_CA_CMD6 0x00001db8 + #define SHU4_R0_CA_CMD6_RG_RK0_RX_ARCKE2_R_DLY GENMASK(5, 0) + #define SHU4_R0_CA_CMD6_RG_RK0_RX_ARCKE2_F_DLY GENMASK(13, 8) + #define SHU4_R0_CA_CMD6_RG_RK0_RX_ARCS0_R_DLY GENMASK(21, 16) + #define SHU4_R0_CA_CMD6_RG_RK0_RX_ARCS0_F_DLY GENMASK(29, 24) +#define SHU4_R0_CA_CMD7 0x00001dbc + #define SHU4_R0_CA_CMD7_RG_RK0_RX_ARCS1_R_DLY GENMASK(5, 0) + #define SHU4_R0_CA_CMD7_RG_RK0_RX_ARCS1_F_DLY GENMASK(13, 8) + #define SHU4_R0_CA_CMD7_RG_RK0_RX_ARCS2_R_DLY GENMASK(21, 16) + #define SHU4_R0_CA_CMD7_RG_RK0_RX_ARCS2_F_DLY GENMASK(29, 24) +#define SHU4_R0_CA_CMD8 0x00001dc0 + #define SHU4_R0_CA_CMD8_RG_RK0_RX_ARCLK_R_DLY GENMASK(22, 16) + #define SHU4_R0_CA_CMD8_RG_RK0_RX_ARCLK_F_DLY GENMASK(30, 24) +#define SHU4_R0_CA_CMD9 0x00001dc4 + #define SHU4_R0_CA_CMD9_RG_RK0_ARPI_CS GENMASK(5, 0) + #define SHU4_R0_CA_CMD9_RG_RK0_ARPI_CMD GENMASK(13, 8) + #define SHU4_R0_CA_CMD9_RG_RK0_ARPI_CLK GENMASK(29, 24) +#define RFU_0X1DC8 0x00001dc8 + #define RFU_0X1DC8_RESERVED_0X1DC8 GENMASK(31, 0) +#define RFU_0X1DCC 0x00001dcc + #define RFU_0X1DCC_RESERVED_0X1DCC GENMASK(31, 0) +#define SHU4_R1_B0_DQ0 0x00001e00 + #define SHU4_R1_B0_DQ0_RK1_TX_ARDQ0_DLY_B0 GENMASK(3, 0) + #define SHU4_R1_B0_DQ0_RK1_TX_ARDQ1_DLY_B0 GENMASK(7, 4) + #define SHU4_R1_B0_DQ0_RK1_TX_ARDQ2_DLY_B0 GENMASK(11, 8) + #define SHU4_R1_B0_DQ0_RK1_TX_ARDQ3_DLY_B0 GENMASK(15, 12) + #define SHU4_R1_B0_DQ0_RK1_TX_ARDQ4_DLY_B0 GENMASK(19, 16) + #define SHU4_R1_B0_DQ0_RK1_TX_ARDQ5_DLY_B0 GENMASK(23, 20) + #define SHU4_R1_B0_DQ0_RK1_TX_ARDQ6_DLY_B0 GENMASK(27, 24) + #define SHU4_R1_B0_DQ0_RK1_TX_ARDQ7_DLY_B0 GENMASK(31, 28) +#define SHU4_R1_B0_DQ1 0x00001e04 + #define SHU4_R1_B0_DQ1_RK1_TX_ARDQM0_DLY_B0 GENMASK(3, 0) + #define SHU4_R1_B0_DQ1_RK1_TX_ARDQS0_DLYB_B0 GENMASK(19, 16) + #define SHU4_R1_B0_DQ1_RK1_TX_ARDQS0B_DLYB_B0 GENMASK(23, 20) + #define SHU4_R1_B0_DQ1_RK1_TX_ARDQS0_DLY_B0 GENMASK(27, 24) + #define SHU4_R1_B0_DQ1_RK1_TX_ARDQS0B_DLY_B0 GENMASK(31, 28) +#define SHU4_R1_B0_DQ2 0x00001e08 + #define SHU4_R1_B0_DQ2_RK1_RX_ARDQ0_R_DLY_B0 GENMASK(5, 0) + #define SHU4_R1_B0_DQ2_RK1_RX_ARDQ0_F_DLY_B0 GENMASK(13, 8) + #define SHU4_R1_B0_DQ2_RK1_RX_ARDQ1_R_DLY_B0 GENMASK(21, 16) + #define SHU4_R1_B0_DQ2_RK1_RX_ARDQ1_F_DLY_B0 GENMASK(29, 24) +#define SHU4_R1_B0_DQ3 0x00001e0c + #define SHU4_R1_B0_DQ3_RK1_RX_ARDQ2_R_DLY_B0 GENMASK(5, 0) + #define SHU4_R1_B0_DQ3_RK1_RX_ARDQ2_F_DLY_B0 GENMASK(13, 8) + #define SHU4_R1_B0_DQ3_RK1_RX_ARDQ3_R_DLY_B0 GENMASK(21, 16) + #define SHU4_R1_B0_DQ3_RK1_RX_ARDQ3_F_DLY_B0 GENMASK(29, 24) +#define SHU4_R1_B0_DQ4 0x00001e10 + #define SHU4_R1_B0_DQ4_RK1_RX_ARDQ4_R_DLY_B0 GENMASK(5, 0) + #define SHU4_R1_B0_DQ4_RK1_RX_ARDQ4_F_DLY_B0 GENMASK(13, 8) + #define SHU4_R1_B0_DQ4_RK1_RX_ARDQ5_R_DLY_B0 GENMASK(21, 16) + #define SHU4_R1_B0_DQ4_RK1_RX_ARDQ5_F_DLY_B0 GENMASK(29, 24) +#define SHU4_R1_B0_DQ5 0x00001e14 + #define SHU4_R1_B0_DQ5_RK1_RX_ARDQ6_R_DLY_B0 GENMASK(5, 0) + #define SHU4_R1_B0_DQ5_RK1_RX_ARDQ6_F_DLY_B0 GENMASK(13, 8) + #define SHU4_R1_B0_DQ5_RK1_RX_ARDQ7_R_DLY_B0 GENMASK(21, 16) + #define SHU4_R1_B0_DQ5_RK1_RX_ARDQ7_F_DLY_B0 GENMASK(29, 24) +#define SHU4_R1_B0_DQ6 0x00001e18 + #define SHU4_R1_B0_DQ6_RK1_RX_ARDQM0_R_DLY_B0 GENMASK(5, 0) + #define SHU4_R1_B0_DQ6_RK1_RX_ARDQM0_F_DLY_B0 GENMASK(13, 8) + #define SHU4_R1_B0_DQ6_RK1_RX_ARDQS0_R_DLY_B0 GENMASK(22, 16) + #define SHU4_R1_B0_DQ6_RK1_RX_ARDQS0_F_DLY_B0 GENMASK(30, 24) +#define SHU4_R1_B0_DQ7 0x00001e1c + #define SHU4_R1_B0_DQ7_RK1_ARPI_DQ_B0 GENMASK(13, 8) + #define SHU4_R1_B0_DQ7_RK1_ARPI_DQM_B0 GENMASK(21, 16) + #define SHU4_R1_B0_DQ7_RK1_ARPI_PBYTE_B0 GENMASK(29, 24) +#define RFU_0X1E20 0x00001e20 + #define RFU_0X1E20_RESERVED_0X1E20 GENMASK(31, 0) +#define RFU_0X1E24 0x00001e24 + #define RFU_0X1E24_RESERVED_0X1E24 GENMASK(31, 0) +#define RFU_0X1E28 0x00001e28 + #define RFU_0X1E28_RESERVED_0X1E28 GENMASK(31, 0) +#define RFU_0X1E2C 0x00001e2c + #define RFU_0X1E2C_RESERVED_0X1E2C GENMASK(31, 0) +#define SHU4_R1_B1_DQ0 0x00001e50 + #define SHU4_R1_B1_DQ0_RK1_TX_ARDQ0_DLY_B1 GENMASK(3, 0) + #define SHU4_R1_B1_DQ0_RK1_TX_ARDQ1_DLY_B1 GENMASK(7, 4) + #define SHU4_R1_B1_DQ0_RK1_TX_ARDQ2_DLY_B1 GENMASK(11, 8) + #define SHU4_R1_B1_DQ0_RK1_TX_ARDQ3_DLY_B1 GENMASK(15, 12) + #define SHU4_R1_B1_DQ0_RK1_TX_ARDQ4_DLY_B1 GENMASK(19, 16) + #define SHU4_R1_B1_DQ0_RK1_TX_ARDQ5_DLY_B1 GENMASK(23, 20) + #define SHU4_R1_B1_DQ0_RK1_TX_ARDQ6_DLY_B1 GENMASK(27, 24) + #define SHU4_R1_B1_DQ0_RK1_TX_ARDQ7_DLY_B1 GENMASK(31, 28) +#define SHU4_R1_B1_DQ1 0x00001e54 + #define SHU4_R1_B1_DQ1_RK1_TX_ARDQM0_DLY_B1 GENMASK(3, 0) + #define SHU4_R1_B1_DQ1_RK1_TX_ARDQS0_DLYB_B1 GENMASK(19, 16) + #define SHU4_R1_B1_DQ1_RK1_TX_ARDQS0B_DLYB_B1 GENMASK(23, 20) + #define SHU4_R1_B1_DQ1_RK1_TX_ARDQS0_DLY_B1 GENMASK(27, 24) + #define SHU4_R1_B1_DQ1_RK1_TX_ARDQS0B_DLY_B1 GENMASK(31, 28) +#define SHU4_R1_B1_DQ2 0x00001e58 + #define SHU4_R1_B1_DQ2_RK1_RX_ARDQ0_R_DLY_B1 GENMASK(5, 0) + #define SHU4_R1_B1_DQ2_RK1_RX_ARDQ0_F_DLY_B1 GENMASK(13, 8) + #define SHU4_R1_B1_DQ2_RK1_RX_ARDQ1_R_DLY_B1 GENMASK(21, 16) + #define SHU4_R1_B1_DQ2_RK1_RX_ARDQ1_F_DLY_B1 GENMASK(29, 24) +#define SHU4_R1_B1_DQ3 0x00001e5c + #define SHU4_R1_B1_DQ3_RK1_RX_ARDQ2_R_DLY_B1 GENMASK(5, 0) + #define SHU4_R1_B1_DQ3_RK1_RX_ARDQ2_F_DLY_B1 GENMASK(13, 8) + #define SHU4_R1_B1_DQ3_RK1_RX_ARDQ3_R_DLY_B1 GENMASK(21, 16) + #define SHU4_R1_B1_DQ3_RK1_RX_ARDQ3_F_DLY_B1 GENMASK(29, 24) +#define SHU4_R1_B1_DQ4 0x00001e60 + #define SHU4_R1_B1_DQ4_RK1_RX_ARDQ4_R_DLY_B1 GENMASK(5, 0) + #define SHU4_R1_B1_DQ4_RK1_RX_ARDQ4_F_DLY_B1 GENMASK(13, 8) + #define SHU4_R1_B1_DQ4_RK1_RX_ARDQ5_R_DLY_B1 GENMASK(21, 16) + #define SHU4_R1_B1_DQ4_RK1_RX_ARDQ5_F_DLY_B1 GENMASK(29, 24) +#define SHU4_R1_B1_DQ5 0x00001e64 + #define SHU4_R1_B1_DQ5_RK1_RX_ARDQ6_R_DLY_B1 GENMASK(5, 0) + #define SHU4_R1_B1_DQ5_RK1_RX_ARDQ6_F_DLY_B1 GENMASK(13, 8) + #define SHU4_R1_B1_DQ5_RK1_RX_ARDQ7_R_DLY_B1 GENMASK(21, 16) + #define SHU4_R1_B1_DQ5_RK1_RX_ARDQ7_F_DLY_B1 GENMASK(29, 24) +#define SHU4_R1_B1_DQ6 0x00001e68 + #define SHU4_R1_B1_DQ6_RK1_RX_ARDQM0_R_DLY_B1 GENMASK(5, 0) + #define SHU4_R1_B1_DQ6_RK1_RX_ARDQM0_F_DLY_B1 GENMASK(13, 8) + #define SHU4_R1_B1_DQ6_RK1_RX_ARDQS0_R_DLY_B1 GENMASK(22, 16) + #define SHU4_R1_B1_DQ6_RK1_RX_ARDQS0_F_DLY_B1 GENMASK(30, 24) +#define SHU4_R1_B1_DQ7 0x00001e6c + #define SHU4_R1_B1_DQ7_RK1_ARPI_DQ_B1 GENMASK(13, 8) + #define SHU4_R1_B1_DQ7_RK1_ARPI_DQM_B1 GENMASK(21, 16) + #define SHU4_R1_B1_DQ7_RK1_ARPI_PBYTE_B1 GENMASK(29, 24) +#define RFU_0X1E70 0x00001e70 + #define RFU_0X1E70_RESERVED_0X1E70 GENMASK(31, 0) +#define RFU_0X1E74 0x00001e74 + #define RFU_0X1E74_RESERVED_0X1E74 GENMASK(31, 0) +#define RFU_0X1E78 0x00001e78 + #define RFU_0X1E78_RESERVED_0X1E78 GENMASK(31, 0) +#define RFU_0X1E7C 0x00001e7c + #define RFU_0X1E7C_RESERVED_0X1E7C GENMASK(31, 0) +#define SHU4_R1_CA_CMD0 0x00001ea0 + #define SHU4_R1_CA_CMD0_RK1_TX_ARCA0_DLY GENMASK(3, 0) + #define SHU4_R1_CA_CMD0_RK1_TX_ARCA1_DLY GENMASK(7, 4) + #define SHU4_R1_CA_CMD0_RK1_TX_ARCA2_DLY GENMASK(11, 8) + #define SHU4_R1_CA_CMD0_RK1_TX_ARCA3_DLY GENMASK(15, 12) + #define SHU4_R1_CA_CMD0_RK1_TX_ARCA4_DLY GENMASK(19, 16) + #define SHU4_R1_CA_CMD0_RK1_TX_ARCA5_DLY GENMASK(23, 20) + #define SHU4_R1_CA_CMD0_RK1_TX_ARCLK_DLYB GENMASK(27, 24) + #define SHU4_R1_CA_CMD0_RK1_TX_ARCLKB_DLYB GENMASK(31, 28) +#define SHU4_R1_CA_CMD1 0x00001ea4 + #define SHU4_R1_CA_CMD1_RK1_TX_ARCKE0_DLY GENMASK(3, 0) + #define SHU4_R1_CA_CMD1_RK1_TX_ARCKE1_DLY GENMASK(7, 4) + #define SHU4_R1_CA_CMD1_RK1_TX_ARCKE2_DLY GENMASK(11, 8) + #define SHU4_R1_CA_CMD1_RK1_TX_ARCS0_DLY GENMASK(15, 12) + #define SHU4_R1_CA_CMD1_RK1_TX_ARCS1_DLY GENMASK(19, 16) + #define SHU4_R1_CA_CMD1_RK1_TX_ARCS2_DLY GENMASK(23, 20) + #define SHU4_R1_CA_CMD1_RK1_TX_ARCLK_DLY GENMASK(27, 24) + #define SHU4_R1_CA_CMD1_RK1_TX_ARCLKB_DLY GENMASK(31, 28) +#define SHU4_R1_CA_CMD2 0x00001ea8 + #define SHU4_R1_CA_CMD2_RG_RK1_RX_ARCA0_R_DLY GENMASK(5, 0) + #define SHU4_R1_CA_CMD2_RG_RK1_RX_ARCA0_F_DLY GENMASK(13, 8) + #define SHU4_R1_CA_CMD2_RG_RK1_RX_ARCA1_R_DLY GENMASK(21, 16) + #define SHU4_R1_CA_CMD2_RG_RK1_RX_ARCA1_F_DLY GENMASK(29, 24) +#define SHU4_R1_CA_CMD3 0x00001eac + #define SHU4_R1_CA_CMD3_RG_RK1_RX_ARCA2_R_DLY GENMASK(5, 0) + #define SHU4_R1_CA_CMD3_RG_RK1_RX_ARCA2_F_DLY GENMASK(13, 8) + #define SHU4_R1_CA_CMD3_RG_RK1_RX_ARCA3_R_DLY GENMASK(21, 16) + #define SHU4_R1_CA_CMD3_RG_RK1_RX_ARCA3_F_DLY GENMASK(29, 24) +#define SHU4_R1_CA_CMD4 0x00001eb0 + #define SHU4_R1_CA_CMD4_RG_RK1_RX_ARCA4_R_DLY GENMASK(5, 0) + #define SHU4_R1_CA_CMD4_RG_RK1_RX_ARCA4_F_DLY GENMASK(13, 8) + #define SHU4_R1_CA_CMD4_RG_RK1_RX_ARCA5_R_DLY GENMASK(21, 16) + #define SHU4_R1_CA_CMD4_RG_RK1_RX_ARCA5_F_DLY GENMASK(29, 24) +#define SHU4_R1_CA_CMD5 0x00001eb4 + #define SHU4_R1_CA_CMD5_RG_RK1_RX_ARCKE0_R_DLY GENMASK(5, 0) + #define SHU4_R1_CA_CMD5_RG_RK1_RX_ARCKE0_F_DLY GENMASK(13, 8) + #define SHU4_R1_CA_CMD5_RG_RK1_RX_ARCKE1_R_DLY GENMASK(21, 16) + #define SHU4_R1_CA_CMD5_RG_RK1_RX_ARCKE1_F_DLY GENMASK(29, 24) +#define SHU4_R1_CA_CMD6 0x00001eb8 + #define SHU4_R1_CA_CMD6_RG_RK1_RX_ARCKE2_R_DLY GENMASK(5, 0) + #define SHU4_R1_CA_CMD6_RG_RK1_RX_ARCKE2_F_DLY GENMASK(13, 8) + #define SHU4_R1_CA_CMD6_RG_RK1_RX_ARCS0_R_DLY GENMASK(21, 16) + #define SHU4_R1_CA_CMD6_RG_RK1_RX_ARCS0_F_DLY GENMASK(29, 24) +#define SHU4_R1_CA_CMD7 0x00001ebc + #define SHU4_R1_CA_CMD7_RG_RK1_RX_ARCS1_R_DLY GENMASK(5, 0) + #define SHU4_R1_CA_CMD7_RG_RK1_RX_ARCS1_F_DLY GENMASK(13, 8) + #define SHU4_R1_CA_CMD7_RG_RK1_RX_ARCS2_R_DLY GENMASK(21, 16) + #define SHU4_R1_CA_CMD7_RG_RK1_RX_ARCS2_F_DLY GENMASK(29, 24) +#define SHU4_R1_CA_CMD8 0x00001ec0 + #define SHU4_R1_CA_CMD8_RG_RK1_RX_ARCLK_R_DLY GENMASK(22, 16) + #define SHU4_R1_CA_CMD8_RG_RK1_RX_ARCLK_F_DLY GENMASK(30, 24) +#define SHU4_R1_CA_CMD9 0x00001ec4 + #define SHU4_R1_CA_CMD9_RG_RK1_ARPI_CS GENMASK(5, 0) + #define SHU4_R1_CA_CMD9_RG_RK1_ARPI_CMD GENMASK(13, 8) + #define SHU4_R1_CA_CMD9_RG_RK1_ARPI_CLK GENMASK(29, 24) +#define RFU_0X1EC8 0x00001ec8 + #define RFU_0X1EC8_RESERVED_0X1EC8 GENMASK(31, 0) +#define RFU_0X1ECC 0x00001ecc + #define RFU_0X1ECC_RESERVED_0X1ECC GENMASK(31, 0) +#define SHU4_R2_B0_DQ0 0x00001f00 + #define SHU4_R2_B0_DQ0_RK2_TX_ARDQ0_DLY_B0 GENMASK(3, 0) + #define SHU4_R2_B0_DQ0_RK2_TX_ARDQ1_DLY_B0 GENMASK(7, 4) + #define SHU4_R2_B0_DQ0_RK2_TX_ARDQ2_DLY_B0 GENMASK(11, 8) + #define SHU4_R2_B0_DQ0_RK2_TX_ARDQ3_DLY_B0 GENMASK(15, 12) + #define SHU4_R2_B0_DQ0_RK2_TX_ARDQ4_DLY_B0 GENMASK(19, 16) + #define SHU4_R2_B0_DQ0_RK2_TX_ARDQ5_DLY_B0 GENMASK(23, 20) + #define SHU4_R2_B0_DQ0_RK2_TX_ARDQ6_DLY_B0 GENMASK(27, 24) + #define SHU4_R2_B0_DQ0_RK2_TX_ARDQ7_DLY_B0 GENMASK(31, 28) +#define SHU4_R2_B0_DQ1 0x00001f04 + #define SHU4_R2_B0_DQ1_RK2_TX_ARDQM0_DLY_B0 GENMASK(3, 0) + #define SHU4_R2_B0_DQ1_RK2_TX_ARDQS0_DLYB_B0 GENMASK(19, 16) + #define SHU4_R2_B0_DQ1_RK2_TX_ARDQS0B_DLYB_B0 GENMASK(23, 20) + #define SHU4_R2_B0_DQ1_RK2_TX_ARDQS0_DLY_B0 GENMASK(27, 24) + #define SHU4_R2_B0_DQ1_RK2_TX_ARDQS0B_DLY_B0 GENMASK(31, 28) +#define SHU4_R2_B0_DQ2 0x00001f08 + #define SHU4_R2_B0_DQ2_RK2_RX_ARDQ0_R_DLY_B0 GENMASK(5, 0) + #define SHU4_R2_B0_DQ2_RK2_RX_ARDQ0_F_DLY_B0 GENMASK(13, 8) + #define SHU4_R2_B0_DQ2_RK2_RX_ARDQ1_R_DLY_B0 GENMASK(21, 16) + #define SHU4_R2_B0_DQ2_RK2_RX_ARDQ1_F_DLY_B0 GENMASK(29, 24) +#define SHU4_R2_B0_DQ3 0x00001f0c + #define SHU4_R2_B0_DQ3_RK2_RX_ARDQ2_R_DLY_B0 GENMASK(5, 0) + #define SHU4_R2_B0_DQ3_RK2_RX_ARDQ2_F_DLY_B0 GENMASK(13, 8) + #define SHU4_R2_B0_DQ3_RK2_RX_ARDQ3_R_DLY_B0 GENMASK(21, 16) + #define SHU4_R2_B0_DQ3_RK2_RX_ARDQ3_F_DLY_B0 GENMASK(29, 24) +#define SHU4_R2_B0_DQ4 0x00001f10 + #define SHU4_R2_B0_DQ4_RK2_RX_ARDQ4_R_DLY_B0 GENMASK(5, 0) + #define SHU4_R2_B0_DQ4_RK2_RX_ARDQ4_F_DLY_B0 GENMASK(13, 8) + #define SHU4_R2_B0_DQ4_RK2_RX_ARDQ5_R_DLY_B0 GENMASK(21, 16) + #define SHU4_R2_B0_DQ4_RK2_RX_ARDQ5_F_DLY_B0 GENMASK(29, 24) +#define SHU4_R2_B0_DQ5 0x00001f14 + #define SHU4_R2_B0_DQ5_RK2_RX_ARDQ6_R_DLY_B0 GENMASK(5, 0) + #define SHU4_R2_B0_DQ5_RK2_RX_ARDQ6_F_DLY_B0 GENMASK(13, 8) + #define SHU4_R2_B0_DQ5_RK2_RX_ARDQ7_R_DLY_B0 GENMASK(21, 16) + #define SHU4_R2_B0_DQ5_RK2_RX_ARDQ7_F_DLY_B0 GENMASK(29, 24) +#define SHU4_R2_B0_DQ6 0x00001f18 + #define SHU4_R2_B0_DQ6_RK2_RX_ARDQM0_R_DLY_B0 GENMASK(5, 0) + #define SHU4_R2_B0_DQ6_RK2_RX_ARDQM0_F_DLY_B0 GENMASK(13, 8) + #define SHU4_R2_B0_DQ6_RK2_RX_ARDQS0_R_DLY_B0 GENMASK(22, 16) + #define SHU4_R2_B0_DQ6_RK2_RX_ARDQS0_F_DLY_B0 GENMASK(30, 24) +#define SHU4_R2_B0_DQ7 0x00001f1c + #define SHU4_R2_B0_DQ7_RK2_ARPI_DQ_B0 GENMASK(13, 8) + #define SHU4_R2_B0_DQ7_RK2_ARPI_DQM_B0 GENMASK(21, 16) + #define SHU4_R2_B0_DQ7_RK2_ARPI_PBYTE_B0 GENMASK(29, 24) +#define RFU_0X1F20 0x00001f20 + #define RFU_0X1F20_RESERVED_0X1F20 GENMASK(31, 0) +#define RFU_0X1F24 0x00001f24 + #define RFU_0X1F24_RESERVED_0X1F24 GENMASK(31, 0) +#define RFU_0X1F28 0x00001f28 + #define RFU_0X1F28_RESERVED_0X1F28 GENMASK(31, 0) +#define RFU_0X1F2C 0x00001f2c + #define RFU_0X1F2C_RESERVED_0X1F2C GENMASK(31, 0) +#define SHU4_R2_B1_DQ0 0x00001f50 + #define SHU4_R2_B1_DQ0_RK2_TX_ARDQ0_DLY_B1 GENMASK(3, 0) + #define SHU4_R2_B1_DQ0_RK2_TX_ARDQ1_DLY_B1 GENMASK(7, 4) + #define SHU4_R2_B1_DQ0_RK2_TX_ARDQ2_DLY_B1 GENMASK(11, 8) + #define SHU4_R2_B1_DQ0_RK2_TX_ARDQ3_DLY_B1 GENMASK(15, 12) + #define SHU4_R2_B1_DQ0_RK2_TX_ARDQ4_DLY_B1 GENMASK(19, 16) + #define SHU4_R2_B1_DQ0_RK2_TX_ARDQ5_DLY_B1 GENMASK(23, 20) + #define SHU4_R2_B1_DQ0_RK2_TX_ARDQ6_DLY_B1 GENMASK(27, 24) + #define SHU4_R2_B1_DQ0_RK2_TX_ARDQ7_DLY_B1 GENMASK(31, 28) +#define SHU4_R2_B1_DQ1 0x00001f54 + #define SHU4_R2_B1_DQ1_RK2_TX_ARDQM0_DLY_B1 GENMASK(3, 0) + #define SHU4_R2_B1_DQ1_RK2_TX_ARDQS0_DLYB_B1 GENMASK(19, 16) + #define SHU4_R2_B1_DQ1_RK2_TX_ARDQS0B_DLYB_B1 GENMASK(23, 20) + #define SHU4_R2_B1_DQ1_RK2_TX_ARDQS0_DLY_B1 GENMASK(27, 24) + #define SHU4_R2_B1_DQ1_RK2_TX_ARDQS0B_DLY_B1 GENMASK(31, 28) +#define SHU4_R2_B1_DQ2 0x00001f58 + #define SHU4_R2_B1_DQ2_RK2_RX_ARDQ0_R_DLY_B1 GENMASK(5, 0) + #define SHU4_R2_B1_DQ2_RK2_RX_ARDQ0_F_DLY_B1 GENMASK(13, 8) + #define SHU4_R2_B1_DQ2_RK2_RX_ARDQ1_R_DLY_B1 GENMASK(21, 16) + #define SHU4_R2_B1_DQ2_RK2_RX_ARDQ1_F_DLY_B1 GENMASK(29, 24) +#define SHU4_R2_B1_DQ3 0x00001f5c + #define SHU4_R2_B1_DQ3_RK2_RX_ARDQ2_R_DLY_B1 GENMASK(5, 0) + #define SHU4_R2_B1_DQ3_RK2_RX_ARDQ2_F_DLY_B1 GENMASK(13, 8) + #define SHU4_R2_B1_DQ3_RK2_RX_ARDQ3_R_DLY_B1 GENMASK(21, 16) + #define SHU4_R2_B1_DQ3_RK2_RX_ARDQ3_F_DLY_B1 GENMASK(29, 24) +#define SHU4_R2_B1_DQ4 0x00001f60 + #define SHU4_R2_B1_DQ4_RK2_RX_ARDQ4_R_DLY_B1 GENMASK(5, 0) + #define SHU4_R2_B1_DQ4_RK2_RX_ARDQ4_F_DLY_B1 GENMASK(13, 8) + #define SHU4_R2_B1_DQ4_RK2_RX_ARDQ5_R_DLY_B1 GENMASK(21, 16) + #define SHU4_R2_B1_DQ4_RK2_RX_ARDQ5_F_DLY_B1 GENMASK(29, 24) +#define SHU4_R2_B1_DQ5 0x00001f64 + #define SHU4_R2_B1_DQ5_RK2_RX_ARDQ6_R_DLY_B1 GENMASK(5, 0) + #define SHU4_R2_B1_DQ5_RK2_RX_ARDQ6_F_DLY_B1 GENMASK(13, 8) + #define SHU4_R2_B1_DQ5_RK2_RX_ARDQ7_R_DLY_B1 GENMASK(21, 16) + #define SHU4_R2_B1_DQ5_RK2_RX_ARDQ7_F_DLY_B1 GENMASK(29, 24) +#define SHU4_R2_B1_DQ6 0x00001f68 + #define SHU4_R2_B1_DQ6_RK2_RX_ARDQM0_R_DLY_B1 GENMASK(5, 0) + #define SHU4_R2_B1_DQ6_RK2_RX_ARDQM0_F_DLY_B1 GENMASK(13, 8) + #define SHU4_R2_B1_DQ6_RK2_RX_ARDQS0_R_DLY_B1 GENMASK(22, 16) + #define SHU4_R2_B1_DQ6_RK2_RX_ARDQS0_F_DLY_B1 GENMASK(30, 24) +#define SHU4_R2_B1_DQ7 0x00001f6c + #define SHU4_R2_B1_DQ7_RK2_ARPI_DQ_B1 GENMASK(13, 8) + #define SHU4_R2_B1_DQ7_RK2_ARPI_DQM_B1 GENMASK(21, 16) + #define SHU4_R2_B1_DQ7_RK2_ARPI_PBYTE_B1 GENMASK(29, 24) +#define RFU_0X1F70 0x00001f70 + #define RFU_0X1F70_RESERVED_0X1F70 GENMASK(31, 0) +#define RFU_0X1F74 0x00001f74 + #define RFU_0X1F74_RESERVED_0X1F74 GENMASK(31, 0) +#define RFU_0X1F78 0x00001f78 + #define RFU_0X1F78_RESERVED_0X1F78 GENMASK(31, 0) +#define RFU_0X1F7C 0x00001f7c + #define RFU_0X1F7C_RESERVED_0X1F7C GENMASK(31, 0) +#define SHU4_R2_CA_CMD0 0x00001fa0 + #define SHU4_R2_CA_CMD0_RK2_TX_ARCA0_DLY GENMASK(3, 0) + #define SHU4_R2_CA_CMD0_RK2_TX_ARCA1_DLY GENMASK(7, 4) + #define SHU4_R2_CA_CMD0_RK2_TX_ARCA2_DLY GENMASK(11, 8) + #define SHU4_R2_CA_CMD0_RK2_TX_ARCA3_DLY GENMASK(15, 12) + #define SHU4_R2_CA_CMD0_RK2_TX_ARCA4_DLY GENMASK(19, 16) + #define SHU4_R2_CA_CMD0_RK2_TX_ARCA5_DLY GENMASK(23, 20) + #define SHU4_R2_CA_CMD0_RK2_TX_ARCLK_DLYB GENMASK(27, 24) + #define SHU4_R2_CA_CMD0_RK2_TX_ARCLKB_DLYB GENMASK(31, 28) +#define SHU4_R2_CA_CMD1 0x00001fa4 + #define SHU4_R2_CA_CMD1_RK2_TX_ARCKE0_DLY GENMASK(3, 0) + #define SHU4_R2_CA_CMD1_RK2_TX_ARCKE1_DLY GENMASK(7, 4) + #define SHU4_R2_CA_CMD1_RK2_TX_ARCKE2_DLY GENMASK(11, 8) + #define SHU4_R2_CA_CMD1_RK2_TX_ARCS0_DLY GENMASK(15, 12) + #define SHU4_R2_CA_CMD1_RK2_TX_ARCS1_DLY GENMASK(19, 16) + #define SHU4_R2_CA_CMD1_RK2_TX_ARCS2_DLY GENMASK(23, 20) + #define SHU4_R2_CA_CMD1_RK2_TX_ARCLK_DLY GENMASK(27, 24) + #define SHU4_R2_CA_CMD1_RK2_TX_ARCLKB_DLY GENMASK(31, 28) +#define SHU4_R2_CA_CMD2 0x00001fa8 + #define SHU4_R2_CA_CMD2_RG_RK2_RX_ARCA0_R_DLY GENMASK(5, 0) + #define SHU4_R2_CA_CMD2_RG_RK2_RX_ARCA0_F_DLY GENMASK(13, 8) + #define SHU4_R2_CA_CMD2_RG_RK2_RX_ARCA1_R_DLY GENMASK(21, 16) + #define SHU4_R2_CA_CMD2_RG_RK2_RX_ARCA1_F_DLY GENMASK(29, 24) +#define SHU4_R2_CA_CMD3 0x00001fac + #define SHU4_R2_CA_CMD3_RG_RK2_RX_ARCA2_R_DLY GENMASK(5, 0) + #define SHU4_R2_CA_CMD3_RG_RK2_RX_ARCA2_F_DLY GENMASK(13, 8) + #define SHU4_R2_CA_CMD3_RG_RK2_RX_ARCA3_R_DLY GENMASK(21, 16) + #define SHU4_R2_CA_CMD3_RG_RK2_RX_ARCA3_F_DLY GENMASK(29, 24) +#define SHU4_R2_CA_CMD4 0x00001fb0 + #define SHU4_R2_CA_CMD4_RG_RK2_RX_ARCA4_R_DLY GENMASK(5, 0) + #define SHU4_R2_CA_CMD4_RG_RK2_RX_ARCA4_F_DLY GENMASK(13, 8) + #define SHU4_R2_CA_CMD4_RG_RK2_RX_ARCA5_R_DLY GENMASK(21, 16) + #define SHU4_R2_CA_CMD4_RG_RK2_RX_ARCA5_F_DLY GENMASK(29, 24) +#define SHU4_R2_CA_CMD5 0x00001fb4 + #define SHU4_R2_CA_CMD5_RG_RK2_RX_ARCKE0_R_DLY GENMASK(5, 0) + #define SHU4_R2_CA_CMD5_RG_RK2_RX_ARCKE0_F_DLY GENMASK(13, 8) + #define SHU4_R2_CA_CMD5_RG_RK2_RX_ARCKE1_R_DLY GENMASK(21, 16) + #define SHU4_R2_CA_CMD5_RG_RK2_RX_ARCKE1_F_DLY GENMASK(29, 24) +#define SHU4_R2_CA_CMD6 0x00001fb8 + #define SHU4_R2_CA_CMD6_RG_RK2_RX_ARCKE2_R_DLY GENMASK(5, 0) + #define SHU4_R2_CA_CMD6_RG_RK2_RX_ARCKE2_F_DLY GENMASK(13, 8) + #define SHU4_R2_CA_CMD6_RG_RK2_RX_ARCS0_R_DLY GENMASK(21, 16) + #define SHU4_R2_CA_CMD6_RG_RK2_RX_ARCS0_F_DLY GENMASK(29, 24) +#define SHU4_R2_CA_CMD7 0x00001fbc + #define SHU4_R2_CA_CMD7_RG_RK2_RX_ARCS1_R_DLY GENMASK(5, 0) + #define SHU4_R2_CA_CMD7_RG_RK2_RX_ARCS1_F_DLY GENMASK(13, 8) + #define SHU4_R2_CA_CMD7_RG_RK2_RX_ARCS2_R_DLY GENMASK(21, 16) + #define SHU4_R2_CA_CMD7_RG_RK2_RX_ARCS2_F_DLY GENMASK(29, 24) +#define SHU4_R2_CA_CMD8 0x00001fc0 + #define SHU4_R2_CA_CMD8_RG_RK2_RX_ARCLK_R_DLY GENMASK(22, 16) + #define SHU4_R2_CA_CMD8_RG_RK2_RX_ARCLK_F_DLY GENMASK(30, 24) +#define SHU4_R2_CA_CMD9 0x00001fc4 + #define SHU4_R2_CA_CMD9_RG_RK2_ARPI_CS GENMASK(5, 0) + #define SHU4_R2_CA_CMD9_RG_RK2_ARPI_CMD GENMASK(13, 8) + #define SHU4_R2_CA_CMD9_RG_RK2_ARPI_CLK GENMASK(29, 24) +#define RFU_0X1FC8 0x00001fc8 + #define RFU_0X1FC8_RESERVED_0X1FC8 GENMASK(31, 0) +#define RFU_0X1FCC 0x00001fcc + #define RFU_0X1FCC_RESERVED_0X1FCC GENMASK(31, 0) + +#endif /*__DDRPHY_WO_PLL_REG_H__*/ diff --git a/src/vendorcode/mediatek/mt8192/include/dramc_actiming.h b/src/vendorcode/mediatek/mt8192/include/dramc_actiming.h new file mode 100644 index 000000000000..43d95d13ef58 --- /dev/null +++ b/src/vendorcode/mediatek/mt8192/include/dramc_actiming.h @@ -0,0 +1,400 @@ +/* SPDX-License-Identifier: BSD-3-Clause */ + +#ifndef _ACTIMING_H +#define _ACTIMING_H + +/***********************************************************************/ +/* Includes */ +/***********************************************************************/ +#include "dramc_register.h" + + +//Definitions to enable specific freq's LP4 ACTiming support (To save code size) +#define SUPPORT_LP5_DDR6400_ACTIM 0 +#define SUPPORT_LP5_DDR5500_ACTIM 0 +#define SUPPORT_LP5_DDR4266_ACTIM 0 +#define SUPPORT_LP5_DDR3200_ACTIM 0 +#define SUPPORT_LP4_DDR4266_ACTIM 1 +#define SUPPORT_LP4_DDR3733_ACTIM 1 +#define SUPPORT_LP4_DDR3200_ACTIM 1 +#define SUPPORT_LP4_DDR2667_ACTIM 0 +#define SUPPORT_LP4_DDR2400_ACTIM 1 +#define SUPPORT_LP4_DDR1866_ACTIM 1 +#define SUPPORT_LP4_DDR1600_ACTIM 1 +#define SUPPORT_LP4_DDR1333_ACTIM 0 +#define SUPPORT_LP4_DDR1200_ACTIM 1 +#define SUPPORT_LP4_DDR800_ACTIM 1 +#define SUPPORT_LP4_DDR400_ACTIM 0 + +/* Used to keep track the total number of LP4 ACTimings */ +/* Since READ_DBI is enable/disabled using preprocessor C define + * -> Save code size by excluding unneeded ACTimingTable entries + * Note 1: READ_DBI on/off is for (LP4 data rate >= DDR2667 (FSP1)) + * Must make sure DDR3733 is the 1st entry (DMCATRAIN_INTV is used) + */ +typedef enum +{ +#if SUPPORT_LP4_DDR4266_ACTIM +#if ENABLE_READ_DBI + AC_TIME_LP4_BYTE_DDR4266_RDBI_ON = 0, + AC_TIME_LP4_NORM_DDR4266_RDBI_ON, +#else //(ENABLE_READ_DBI == 0) + AC_TIME_LP4_BYTE_DDR4266_RDBI_OFF, + AC_TIME_LP4_NORM_DDR4266_RDBI_OFF, +#endif //ENABLE_READ_DBI +#endif + +#if SUPPORT_LP4_DDR3733_ACTIM +#if ENABLE_READ_DBI + AC_TIME_LP4_BYTE_DDR3733_RDBI_ON, + AC_TIME_LP4_NORM_DDR3733_RDBI_ON, +#else //(ENABLE_READ_DBI == 0) + AC_TIME_LP4_BYTE_DDR3733_RDBI_OFF, + AC_TIME_LP4_NORM_DDR3733_RDBI_OFF, +#endif //ENABLE_READ_DBI +#endif + +#if SUPPORT_LP4_DDR3200_ACTIM +#if ENABLE_READ_DBI + AC_TIME_LP4_BYTE_DDR3200_RDBI_ON, + AC_TIME_LP4_NORM_DDR3200_RDBI_ON, +#else //(ENABLE_READ_DBI == 0) + AC_TIME_LP4_BYTE_DDR3200_RDBI_OFF, + AC_TIME_LP4_NORM_DDR3200_RDBI_OFF, +#endif //ENABLE_READ_DBI +#endif + +#if SUPPORT_LP4_DDR2667_ACTIM +#if ENABLE_READ_DBI + AC_TIME_LP4_BYTE_DDR2667_RDBI_ON, + AC_TIME_LP4_NORM_DDR2667_RDBI_ON, +#else //(ENABLE_READ_DBI == 0) + AC_TIME_LP4_BYTE_DDR2667_RDBI_OFF, + AC_TIME_LP4_NORM_DDR2667_RDBI_OFF, +#endif //ENABLE_READ_DBI +#endif + +#if SUPPORT_LP4_DDR2400_ACTIM + AC_TIME_LP4_BYTE_DDR2400_RDBI_OFF, + AC_TIME_LP4_NORM_DDR2400_RDBI_OFF, +#endif + +#if SUPPORT_LP4_DDR1866_ACTIM + AC_TIME_LP4_BYTE_DDR1866_RDBI_OFF, + AC_TIME_LP4_NORM_DDR1866_RDBI_OFF, +#endif + +#if SUPPORT_LP4_DDR1600_ACTIM + AC_TIME_LP4_BYTE_DDR1600_RDBI_OFF, + AC_TIME_LP4_NORM_DDR1600_RDBI_OFF, + AC_TIME_LP4_BYTE_DDR1600_DIV4_RDBI_OFF, + AC_TIME_LP4_NORM_DDR1600_DIV4_RDBI_OFF, +#endif + +#if SUPPORT_LP4_DDR1333_ACTIM + AC_TIME_LP4_BYTE_DDR1333_RDBI_OFF, + AC_TIME_LP4_NORM_DDR1333_RDBI_OFF, +#endif + + +#if SUPPORT_LP4_DDR1200_ACTIM + AC_TIME_LP4_BYTE_DDR1200_RDBI_OFF, + AC_TIME_LP4_NORM_DDR1200_RDBI_OFF, + AC_TIME_LP4_BYTE_DDR1200_DIV4_RDBI_OFF, + AC_TIME_LP4_NORM_DDR1200_DIV4_RDBI_OFF, +#endif + +#if SUPPORT_LP4_DDR800_ACTIM + AC_TIME_LP4_BYTE_DDR800_RDBI_OFF, + AC_TIME_LP4_NORM_DDR800_RDBI_OFF, + AC_TIME_LP4_BYTE_DDR800_DIV4_RDBI_OFF, + AC_TIME_LP4_NORM_DDR800_DIV4_RDBI_OFF, +#endif + +#if SUPPORT_LP4_DDR400_ACTIM + AC_TIME_LP4_BYTE_DDR400_RDBI_OFF, + AC_TIME_LP4_NORM_DDR400_RDBI_OFF, +#endif + + AC_TIMING_NUMBER_LP4 +} AC_TIMING_LP4_COUNT_TYPE_T; + +#if (__LP5_COMBO__) +/* Used to keep track the total number of LP5 ACTimings */ +typedef enum +{ +#if SUPPORT_LP5_DDR6400_ACTIM +#if ENABLE_READ_DBI + AC_TIME_LP5_BYTE_DDR6400_RDBI_ON = 0, + AC_TIME_LP5_NORM_DDR6400_RDBI_ON, +#else //(ENABLE_READ_DBI == 0) + AC_TIME_LP5_BYTE_DDR6400_RDBI_OFF, + AC_TIME_LP5_NORM_DDR6400_RDBI_OFF, +#endif //ENABLE_READ_DBI +#endif + +#if SUPPORT_LP5_DDR5500_ACTIM +#if ((ENABLE_READ_DBI) || (LP5_DDR4266_RDBI_WORKAROUND)) + AC_TIME_LP5_BYTE_DDR5500_RDBI_ON, + AC_TIME_LP5_NORM_DDR5500_RDBI_ON, +#else + AC_TIME_LP5_BYTE_DDR5500_RDBI_OFF, + AC_TIME_LP5_NORM_DDR5500_RDBI_OFF, +#endif +#endif + +#if SUPPORT_LP5_DDR4266_ACTIM +#if ((ENABLE_READ_DBI) || (LP5_DDR4266_RDBI_WORKAROUND)) + AC_TIME_LP5_BYTE_DDR4266_RDBI_ON, + AC_TIME_LP5_NORM_DDR4266_RDBI_ON, +#else //(ENABLE_READ_DBI == 0) + AC_TIME_LP5_BYTE_DDR4266_RDBI_OFF, + AC_TIME_LP5_NORM_DDR4266_RDBI_OFF, +#endif //ENABLE_READ_DBI +#endif + +#if SUPPORT_LP5_DDR3200_ACTIM + AC_TIME_LP5_BYTE_DDR3200_RDBI_OFF, + AC_TIME_LP5_NORM_DDR3200_RDBI_OFF, +#endif + AC_TIMING_NUMBER_LP5 +} AC_TIMING_LP5_COUNT_TYPE_T; +#else +#define AC_TIMING_NUMBER_LP5 0 +#endif + +/* ACTiming struct declaration (declared here due Fld_wid for each register type) + * Should include all fields from ACTiming excel file (And update the correct values in UpdateACTimingReg() + * Note: DQSINCTL, DATLAT aren't in ACTiming excel file (internal delay parameters) + */ +typedef struct _ACTime_T_LP4 +{ + U8 dramType, cbtMode, readDBI; + U8 DivMode; + U16 freq; + U16 readLat, writeLat; + U16 dqsinctl, datlat; //DQSINCTL, DATLAT aren't in ACTiming excel file + + U16 tras; + U16 trp; + U16 trpab; + U16 trc; + U16 trfc; + U16 trfcpb; + U16 txp; + U16 trtp; + U16 trcd; + U16 twr; + U16 twtr; + U16 tpbr2pbr; + U16 tpbr2act; + U16 tr2mrw; + U16 tw2mrw; + U16 tmrr2mrw; + U16 tmrw; + U16 tmrd; + U16 tmrwckel; + U16 tpde; + U16 tpdx; + U16 tmrri; + U16 trrd; + U16 trrd_4266; + U16 tfaw; + U16 tfaw_4266; + U16 trtw_odt_off; + U16 trtw_odt_on; + U16 txrefcnt; + U16 tzqcs; + U16 xrtw2w_new_mode; + U16 xrtw2w_old_mode; + U16 xrtw2r_odt_on; + U16 xrtw2r_odt_off; + U16 xrtr2w_odt_on; + U16 xrtr2w_odt_off; + U16 xrtr2r_new_mode; + U16 xrtr2r_old_mode; + U16 tr2mrr; + U16 vrcgdis_prdcnt; + U16 hwset_mr2_op; + U16 hwset_mr13_op; + U16 hwset_vrcg_op; + U16 trcd_derate; + U16 trc_derate; + U16 tras_derate; + U16 trpab_derate; + U16 trp_derate; + U16 trrd_derate; + U16 trtpd; + U16 twtpd; + U16 tmrr2w_odt_off; + U16 tmrr2w_odt_on; + U16 ckeprd; + U16 ckelckcnt; + U16 zqlat2; + + //DRAMC_REG_SHU_AC_TIME_05T =================================== + U16 tras_05T; + U16 trp_05T; + U16 trpab_05T; + U16 trc_05T; + U16 trfc_05T; + U16 trfcpb_05T; + U16 txp_05T; + U16 trtp_05T; + U16 trcd_05T; + U16 twr_05T; + U16 twtr_05T; + U16 tpbr2pbr_05T; + U16 tpbr2act_05T; + U16 tr2mrw_05T; + U16 tw2mrw_05T; + U16 tmrr2mrw_05T; + U16 tmrw_05T; + U16 tmrd_05T; + U16 tmrwckel_05T; + U16 tpde_05T; + U16 tpdx_05T; + U16 tmrri_05T; + U16 trrd_05T; + U16 trrd_4266_05T; + U16 tfaw_05T; + U16 tfaw_4266_05T; + U16 trtw_odt_off_05T; + U16 trtw_odt_on_05T; + U16 trcd_derate_05T; + U16 trc_derate_05T; + U16 tras_derate_05T; + U16 trpab_derate_05T; + U16 trp_derate_05T; + U16 trrd_derate_05T; + U16 trtpd_05T; + U16 twtpd_05T; +} ACTime_T_LP4; + +typedef struct _ACTime_T_LP5 +{ + U8 dramType, cbtMode, readDBI; + U8 DivMode; + U16 freq; + U16 readLat, writeLat; + U16 dqsinctl, datlat; //DQSINCTL, DATLAT aren't in ACTiming excel file + + U16 tras; + U16 trp; + U16 trpab; + U16 trc; + U16 trfc; + U16 trfcpb; + U16 txp; + U16 trtp; + U16 trcd; + U16 twr; + U16 twtr; + U16 twtr_l; + U16 tpbr2pbr; + U16 tpbr2act; + U16 tr2mrw; + U16 tw2mrw; + U16 tmrr2mrw; + U16 tmrw; + U16 tmrd; + U16 tmrwckel; + U16 tpde; + U16 tpdx; + U16 tmrri; + U16 trrd; + U16 tfaw; + U16 tr2w_odt_off; + U16 tr2w_odt_on; + U16 txrefcnt; + U16 wckrdoff; + U16 wckwroff; + U16 tzqcs; + U16 xrtw2w_odt_off; + U16 xrtw2w_odt_on; + U16 xrtw2r_odt_off_otf_off; + U16 xrtw2r_odt_on_otf_off; + U16 xrtw2r_odt_off_otf_on; + U16 xrtw2r_odt_on_otf_on; + U16 xrtr2w_odt_on; + U16 xrtr2w_odt_off; + U16 xrtr2r_odt_off; + U16 xrtr2r_odt_on; + U16 xrtw2w_odt_off_wck; + U16 xrtw2w_odt_on_wck; + U16 xrtw2r_odt_off_wck; + U16 xrtw2r_odt_on_wck; + U16 xrtr2w_odt_off_wck; + U16 xrtr2w_odt_on_wck; + U16 xrtr2r_wck; + U16 tr2mrr; + U16 hwset_mr2_op; + U16 hwset_mr13_op; + U16 hwset_vrcg_op; + U16 vrcgdis_prdcnt; + U16 lp5_cmd1to2en; + U16 trtpd; + U16 twtpd; + U16 tmrr2w; + U16 ckeprd; + U16 ckelckcnt; + U16 tcsh_cscal; + U16 tcacsh; + U16 tcsh; + U16 trcd_derate; + U16 trc_derate; + U16 tras_derate; + U16 trpab_derate; + U16 trp_derate; + U16 trrd_derate; + U16 zqlat2; + + //DRAMC_REG_SHU_AC_TIME_05T =================================== + U16 tras_05T; + U16 trp_05T; + U16 trpab_05T; + U16 trc_05T; + U16 trfc_05T; + U16 trfcpb_05T; + U16 txp_05T; + U16 trtp_05T; + U16 trcd_05T; + U16 twr_05T; + U16 twtr_05T; + U16 twtr_l_05T; + U16 tr2mrw_05T; + U16 tw2mrw_05T; + U16 tmrr2mrw_05T; + U16 tmrw_05T; + U16 tmrd_05T; + U16 tmrwckel_05T; + U16 tpde_05T; + U16 tpdx_05T; + U16 tmrri_05T; + U16 trrd_05T; + U16 tfaw_05T; + U16 tr2w_odt_off_05T; + U16 tr2w_odt_on_05T; + U16 wckrdoff_05T; + U16 wckwroff_05T; + U16 trtpd_05T; + U16 twtpd_05T; + U16 tpbr2pbr_05T; + U16 tpbr2act_05T; + U16 trcd_derate_05T; + U16 trc_derate_05T; + U16 tras_derate_05T; + U16 trpab_derate_05T; + U16 trp_derate_05T; + U16 trrd_derate_05T; +} ACTime_T_LP5; + +//ACTimingTbl[] forward declaration +extern const ACTime_T_LP4 ACTimingTbl_LP4[AC_TIMING_NUMBER_LP4]; +extern const ACTime_T_LP5 ACTimingTbl_LP5[AC_TIMING_NUMBER_LP5]; + +extern U8 vDramcACTimingGetDatLat(DRAMC_CTX_T *p); +extern DRAM_STATUS_T DdrUpdateACTiming(DRAMC_CTX_T *p); +extern void vDramcACTimingOptimize(DRAMC_CTX_T *p); +extern DRAM_CBT_MODE_T vGet_Dram_CBT_Mode(DRAMC_CTX_T *p); +#endif diff --git a/src/vendorcode/mediatek/mt8192/include/dramc_ch0_nao_reg.h b/src/vendorcode/mediatek/mt8192/include/dramc_ch0_nao_reg.h new file mode 100644 index 000000000000..2b9a21768e08 --- /dev/null +++ b/src/vendorcode/mediatek/mt8192/include/dramc_ch0_nao_reg.h @@ -0,0 +1,1291 @@ +/* SPDX-License-Identifier: BSD-3-Clause */ + +#ifndef __DRAMC_CH0_NAO_REG_H__ +#define __DRAMC_CH0_NAO_REG_H__ + +/* ----------------- Register Definitions ------------------- */ +#define TESTMODE 0x00000000 + #define TESTMODE_TESTM_PAT0 GENMASK(31, 24) +#define LBWDAT0 0x00000004 + #define LBWDAT0_LBWDATA0 GENMASK(31, 0) +#define LBWDAT1 0x00000008 + #define LBWDAT1_LBWDATA1 GENMASK(31, 0) +#define LBWDAT2 0x0000000c + #define LBWDAT2_LBWDATA2 GENMASK(31, 0) +#define LBWDAT3 0x00000010 + #define LBWDAT3_LBWDATA3 GENMASK(31, 0) +#define CKPHCHK 0x00000020 + #define CKPHCHK_CKPHCHKCYC GENMASK(15, 0) + #define CKPHCHK_CKPHCNTEN BIT(31) +#define DMMONITOR 0x00000024 + #define DMMONITOR_JMTR_EN BIT(0) + #define DMMONITOR_MONPAUSE_SW BIT(2) + #define DMMONITOR_BUSMONEN_SW BIT(3) + #define DMMONITOR_WDQ_MON_OPT BIT(4) + #define DMMONITOR_REQQUE_MON_SREF_DIS BIT(8) + #define DMMONITOR_REQQUE_MON_SREF_REOR BIT(9) + #define DMMONITOR_REQQUE_MON_SREF_LLAT BIT(10) + #define DMMONITOR_REQQUE_MON_SREF_HPRI BIT(11) + #define DMMONITOR_REQQUE_MON_SREF_RW BIT(12) + #define DMMONITOR_JMTRCNT GENMASK(31, 16) +#define TESTCHIP_DMA1 0x00000030 + #define TESTCHIP_DMA1_DMAEN BIT(0) + #define TESTCHIP_DMA1_DMAPUREWREN BIT(1) + #define TESTCHIP_DMA1_DMAPURERDEN BIT(2) + #define TESTCHIP_DMA1_DMA_MWR BIT(3) + #define TESTCHIP_DMA1_DMABURSTLEN GENMASK(6, 4) + #define TESTCHIP_DMA1_DMAEN_LOOP BIT(8) + #define TESTCHIP_DMA1_DMAFIXPAT BIT(9) + #define TESTCHIP_DMA1_DMA_LP4MATAB_OPT BIT(12) +#define MISC_STATUSA 0x00000080 + #define MISC_STATUSA_WAIT_DLE BIT(0) + #define MISC_STATUSA_WRITE_DATA_BUFFER_EMPTY BIT(1) + #define MISC_STATUSA_REQQ_EMPTY BIT(2) + #define MISC_STATUSA_PG_VLD BIT(3) + #define MISC_STATUSA_REQQUE_DEPTH GENMASK(7, 4) + #define MISC_STATUSA_REFRESH_RATE GENMASK(10, 8) + #define MISC_STATUSA_DRAM_HWCFG BIT(12) + #define MISC_STATUSA_CKEO_PRE BIT(13) + #define MISC_STATUSA_CKE1O_PRE BIT(14) + #define MISC_STATUSA_SREF_STATE BIT(16) + #define MISC_STATUSA_SELFREF_SM GENMASK(19, 17) + #define MISC_STATUSA_REFRESH_OVER_CNT GENMASK(23, 20) + #define MISC_STATUSA_REFRESH_QUEUE_CNT GENMASK(27, 24) + #define MISC_STATUSA_REQDEPTH_UPD_DONE BIT(28) + #define MISC_STATUSA_MANUTXUPD_DONE BIT(29) + #define MISC_STATUSA_DRAMC_IDLE_STATUS BIT(30) + #define MISC_STATUSA_DRAMC_IDLE_DCM BIT(31) +#define SPECIAL_STATUS 0x00000084 + #define SPECIAL_STATUS_SPECIAL_COMMAND_ENABLE BIT(0) + #define SPECIAL_STATUS_H_ZQLAT_REQ BIT(1) + #define SPECIAL_STATUS_H_ZQLCAL_REQ BIT(2) + #define SPECIAL_STATUS_H_DQSOSCEN_REQ BIT(4) + #define SPECIAL_STATUS_DQSOSCEN_PERIOD BIT(5) + #define SPECIAL_STATUS_H_ZQCS_REQ BIT(6) + #define SPECIAL_STATUS_H_REFR_REQ BIT(7) + #define SPECIAL_STATUS_STBUPD_STOP BIT(8) + #define SPECIAL_STATUS_HW_ZQLAT_REQ BIT(9) + #define SPECIAL_STATUS_HW_ZQCAL_REQ BIT(10) + #define SPECIAL_STATUS_SPECIAL_STATUS BIT(11) + #define SPECIAL_STATUS_SCSM GENMASK(16, 12) + #define SPECIAL_STATUS_SCARB_SM GENMASK(24, 20) + #define SPECIAL_STATUS_SC_DRAMC_QUEUE_ACK BIT(28) + #define SPECIAL_STATUS_SREF_REQ_2Q BIT(30) + #define SPECIAL_STATUS_SREF_REQ BIT(31) +#define SPCMDRESP 0x00000088 + #define SPCMDRESP_MRW_RESPONSE BIT(0) + #define SPCMDRESP_MRR_RESPONSE BIT(1) + #define SPCMDRESP_PREA_RESPONSE BIT(2) + #define SPCMDRESP_AREF_RESPONSE BIT(3) + #define SPCMDRESP_ZQC_RESPONSE BIT(4) + #define SPCMDRESP_TCMD_RESPONSE BIT(5) + #define SPCMDRESP_ZQLAT_RESPONSE BIT(6) + #define SPCMDRESP_RDDQC_RESPONSE BIT(7) + #define SPCMDRESP_STEST_RESPONSE BIT(8) + #define SPCMDRESP_MPCMAN_RESPONSE BIT(9) + #define SPCMDRESP_DQSOSCEN_RESPONSE BIT(10) + #define SPCMDRESP_DQSOSCDIS_RESPONSE BIT(11) + #define SPCMDRESP_ACT_RESPONSE BIT(12) + #define SPCMDRESP_MPRW_RESPONSE BIT(13) + #define SPCMDRESP_DVFS_RESPONSE BIT(16) + #define SPCMDRESP_HW_ZQLAT_POP BIT(17) + #define SPCMDRESP_HW_ZQCAL_POP BIT(18) + #define SPCMDRESP_RDFIFO_RESPONSE BIT(30) + #define SPCMDRESP_WRFIFO_RESPONSE BIT(31) +#define MRR_STATUS 0x0000008c + #define MRR_STATUS_MRR_REG GENMASK(15, 0) + #define MRR_STATUS_MRR_SW_REG GENMASK(31, 16) +#define MRR_STATUS2 0x00000090 + #define MRR_STATUS2_MR4_REG GENMASK(15, 0) + #define MRR_STATUS2_SHUFFLE_MRW_VRCG_NORMAL_OK BIT(16) + #define MRR_STATUS2_TFC_OK BIT(17) + #define MRR_STATUS2_TCKFSPX_OK BIT(18) + #define MRR_STATUS2_TVRCG_EN_OK BIT(19) + #define MRR_STATUS2_TCKFSPE_OK BIT(20) + #define MRR_STATUS2_TVRCG_DIS_OK BIT(21) + #define MRR_STATUS2_PHY_SHUFFLE_PERIOD_GO_ZERO_OK BIT(22) + #define MRR_STATUS2_DVFS_STATE GENMASK(31, 24) +#define MRRDATA0 0x00000094 + #define MRRDATA0_MRR_DATA0 GENMASK(31, 0) +#define MRRDATA1 0x00000098 + #define MRRDATA1_MRR_DATA1 GENMASK(31, 0) +#define MRRDATA2 0x0000009c + #define MRRDATA2_MRR_DATA2 GENMASK(31, 0) +#define MRRDATA3 0x000000a0 + #define MRRDATA3_MRR_DATA3 GENMASK(31, 0) +#define DRS_STATUS 0x000000a8 + #define DRS_STATUS_DRS_MONERR_ACK BIT(8) + #define DRS_STATUS_DRS_MONERR_REQ BIT(9) + #define DRS_STATUS_RK1_DRS_REQ BIT(16) + #define DRS_STATUS_RK1_DRS_2Q BIT(17) + #define DRS_STATUS_RK1_DRSLY_REQ BIT(18) + #define DRS_STATUS_RK1_DRS_RDY BIT(19) + #define DRS_STATUS_RK1_DRS_ACK BIT(20) + #define DRS_STATUS_RK1_DRS_STATUS BIT(21) + #define DRS_STATUS_SELFREF_SM_RK1 GENMASK(26, 24) +#define JMETER_ST 0x000000bc + #define JMETER_ST_ZEROS_CNT GENMASK(14, 0) + #define JMETER_ST_ONES_CNT GENMASK(30, 16) + #define JMETER_ST_JMTR_DONE BIT(31) +#define TCMDO1LAT 0x000000c0 + #define TCMDO1LAT_TCMD_O1_LATCH_DATA0 GENMASK(5, 0) + #define TCMDO1LAT_TCMD_O1_LATCH_DATA1 GENMASK(13, 8) + #define TCMDO1LAT_CATRAIN_CMP_ERR0 GENMASK(21, 16) + #define TCMDO1LAT_CATRAIN_CMP_ERR GENMASK(29, 24) + #define TCMDO1LAT_CATRAIN_CMP_CPT BIT(31) +#define RDQC_CMP 0x000000c4 + #define RDQC_CMP_RDDQC_CMP0_ERR GENMASK(15, 0) + #define RDQC_CMP_RDDQC_CMP1_ERR GENMASK(31, 16) +#define CKPHCHK_STATUS 0x000000c8 + #define CKPHCHK_STATUS_CKPHCHK_STATUS GENMASK(15, 0) +#define HWMRR_PUSH2POP_CNT 0x0000010c + #define HWMRR_PUSH2POP_CNT_HWMRR_PUSH2POP_CNT GENMASK(31, 0) +#define HWMRR_STATUS 0x00000110 + #define HWMRR_STATUS_OV_P2P_CNT GENMASK(7, 0) + #define HWMRR_STATUS_MRR_CNT_UNDER_FULL BIT(30) + #define HWMRR_STATUS_MRR_CNT_OVER_FULL BIT(31) +#define HW_REFRATE_MON 0x00000114 + #define HW_REFRATE_MON_REFRESH_RATE_MIN_MON GENMASK(2, 0) + #define HW_REFRATE_MON_REFRESH_RATE_MAX_MON GENMASK(10, 8) +#define TESTRPT 0x00000120 + #define TESTRPT_DM_CMP_CPT_RK0 BIT(0) + #define TESTRPT_DM_CMP_CPT_RK1 BIT(1) + #define TESTRPT_DM_CMP_ERR_RK0 BIT(4) + #define TESTRPT_DM_CMP_ERR_RK1 BIT(5) + #define TESTRPT_DLE_CNT_OK_RK0 BIT(8) + #define TESTRPT_DLE_CNT_OK_RK1 BIT(9) + #define TESTRPT_TESTSTAT GENMASK(22, 20) + #define TESTRPT_LB_CMP_FAIL BIT(24) + #define TESTRPT_CALI_DONE_MON BIT(28) +#define CMP_ERR 0x00000124 + #define CMP_ERR_CMP_ERR GENMASK(31, 0) +#define TEST_ABIT_STATUS1 0x00000128 + #define TEST_ABIT_STATUS1_TEST_ABIT_ERR1 GENMASK(31, 0) +#define TEST_ABIT_STATUS2 0x0000012c + #define TEST_ABIT_STATUS2_TEST_ABIT_ERR2 GENMASK(31, 0) +#define TEST_ABIT_STATUS3 0x00000130 + #define TEST_ABIT_STATUS3_TEST_ABIT_ERR3 GENMASK(31, 0) +#define TEST_ABIT_STATUS4 0x00000134 + #define TEST_ABIT_STATUS4_TEST_ABIT_ERR4 GENMASK(31, 0) +#define DQSDLY0 0x00000150 + #define DQSDLY0_DEL0DLY GENMASK(6, 0) + #define DQSDLY0_DEL1DLY GENMASK(14, 8) + #define DQSDLY0_DEL2DLY GENMASK(22, 16) + #define DQSDLY0_DEL3DLY GENMASK(30, 24) +#define DQ_CAL_MAX_0 0x00000154 + #define DQ_CAL_MAX_0_DQ0_0_DLY_MAX GENMASK(7, 0) + #define DQ_CAL_MAX_0_DQ0_1_DLY_MAX GENMASK(15, 8) + #define DQ_CAL_MAX_0_DQ0_2_DLY_MAX GENMASK(23, 16) + #define DQ_CAL_MAX_0_DQ0_3_DLY_MAX GENMASK(31, 24) +#define DQ_CAL_MAX_1 0x00000158 + #define DQ_CAL_MAX_1_DQ0_4_DLY_MAX GENMASK(7, 0) + #define DQ_CAL_MAX_1_DQ0_5_DLY_MAX GENMASK(15, 8) + #define DQ_CAL_MAX_1_DQ0_6_DLY_MAX GENMASK(23, 16) + #define DQ_CAL_MAX_1_DQ0_7_DLY_MAX GENMASK(31, 24) +#define DQ_CAL_MAX_2 0x0000015c + #define DQ_CAL_MAX_2_DQ1_0_DLY_MAX GENMASK(7, 0) + #define DQ_CAL_MAX_2_DQ1_1_DLY_MAX GENMASK(15, 8) + #define DQ_CAL_MAX_2_DQ1_2_DLY_MAX GENMASK(23, 16) + #define DQ_CAL_MAX_2_DQ1_3_DLY_MAX GENMASK(31, 24) +#define DQ_CAL_MAX_3 0x00000160 + #define DQ_CAL_MAX_3_DQ1_4_DLY_MAX GENMASK(7, 0) + #define DQ_CAL_MAX_3_DQ1_5_DLY_MAX GENMASK(15, 8) + #define DQ_CAL_MAX_3_DQ1_6_DLY_MAX GENMASK(23, 16) + #define DQ_CAL_MAX_3_DQ1_7_DLY_MAX GENMASK(31, 24) +#define DQ_CAL_MAX_4 0x00000164 + #define DQ_CAL_MAX_4_DQ2_0_DLY_MAX GENMASK(7, 0) + #define DQ_CAL_MAX_4_DQ2_1_DLY_MAX GENMASK(15, 8) + #define DQ_CAL_MAX_4_DQ2_2_DLY_MAX GENMASK(23, 16) + #define DQ_CAL_MAX_4_DQ2_3_DLY_MAX GENMASK(31, 24) +#define DQ_CAL_MAX_5 0x00000168 + #define DQ_CAL_MAX_5_DQ2_4_DLY_MAX GENMASK(7, 0) + #define DQ_CAL_MAX_5_DQ2_5_DLY_MAX GENMASK(15, 8) + #define DQ_CAL_MAX_5_DQ2_6_DLY_MAX GENMASK(23, 16) + #define DQ_CAL_MAX_5_DQ2_7_DLY_MAX GENMASK(31, 24) +#define DQ_CAL_MAX_6 0x0000016c + #define DQ_CAL_MAX_6_DQ3_0_DLY_MAX GENMASK(7, 0) + #define DQ_CAL_MAX_6_DQ3_1_DLY_MAX GENMASK(15, 8) + #define DQ_CAL_MAX_6_DQ3_2_DLY_MAX GENMASK(23, 16) + #define DQ_CAL_MAX_6_DQ3_3_DLY_MAX GENMASK(31, 24) +#define DQ_CAL_MAX_7 0x00000170 + #define DQ_CAL_MAX_7_DQ3_4_DLY_MAX GENMASK(7, 0) + #define DQ_CAL_MAX_7_DQ3_5_DLY_MAX GENMASK(15, 8) + #define DQ_CAL_MAX_7_DQ3_6_DLY_MAX GENMASK(23, 16) + #define DQ_CAL_MAX_7_DQ3_7_DLY_MAX GENMASK(31, 24) +#define DQS_CAL_MIN_0 0x00000174 + #define DQS_CAL_MIN_0_DQS0_0_DLY_MIN GENMASK(7, 0) + #define DQS_CAL_MIN_0_DQS0_1_DLY_MIN GENMASK(15, 8) + #define DQS_CAL_MIN_0_DQS0_2_DLY_MIN GENMASK(23, 16) + #define DQS_CAL_MIN_0_DQS0_3_DLY_MIN GENMASK(31, 24) +#define DQS_CAL_MIN_1 0x00000178 + #define DQS_CAL_MIN_1_DQS0_4_DLY_MIN GENMASK(7, 0) + #define DQS_CAL_MIN_1_DQS0_5_DLY_MIN GENMASK(15, 8) + #define DQS_CAL_MIN_1_DQS0_6_DLY_MIN GENMASK(23, 16) + #define DQS_CAL_MIN_1_DQS0_7_DLY_MIN GENMASK(31, 24) +#define DQS_CAL_MIN_2 0x0000017c + #define DQS_CAL_MIN_2_DQS1_0_DLY_MIN GENMASK(7, 0) + #define DQS_CAL_MIN_2_DQS1_1_DLY_MIN GENMASK(15, 8) + #define DQS_CAL_MIN_2_DQS1_2_DLY_MIN GENMASK(23, 16) + #define DQS_CAL_MIN_2_DQS1_3_DLY_MIN GENMASK(31, 24) +#define DQS_CAL_MIN_3 0x00000180 + #define DQS_CAL_MIN_3_DQS1_4_DLY_MIN GENMASK(7, 0) + #define DQS_CAL_MIN_3_DQS1_5_DLY_MIN GENMASK(15, 8) + #define DQS_CAL_MIN_3_DQS1_6_DLY_MIN GENMASK(23, 16) + #define DQS_CAL_MIN_3_DQS1_7_DLY_MIN GENMASK(31, 24) +#define DQS_CAL_MIN_4 0x00000184 + #define DQS_CAL_MIN_4_DQS2_0_DLY_MIN GENMASK(7, 0) + #define DQS_CAL_MIN_4_DQS2_1_DLY_MIN GENMASK(15, 8) + #define DQS_CAL_MIN_4_DQS2_2_DLY_MIN GENMASK(23, 16) + #define DQS_CAL_MIN_4_DQS2_3_DLY_MIN GENMASK(31, 24) +#define DQS_CAL_MIN_5 0x00000188 + #define DQS_CAL_MIN_5_DQS2_4_DLY_MIN GENMASK(7, 0) + #define DQS_CAL_MIN_5_DQS2_5_DLY_MIN GENMASK(15, 8) + #define DQS_CAL_MIN_5_DQS2_6_DLY_MIN GENMASK(23, 16) + #define DQS_CAL_MIN_5_DQS2_7_DLY_MIN GENMASK(31, 24) +#define DQS_CAL_MIN_6 0x0000018c + #define DQS_CAL_MIN_6_DQS3_0_DLY_MIN GENMASK(7, 0) + #define DQS_CAL_MIN_6_DQS3_1_DLY_MIN GENMASK(15, 8) + #define DQS_CAL_MIN_6_DQS3_2_DLY_MIN GENMASK(23, 16) + #define DQS_CAL_MIN_6_DQS3_3_DLY_MIN GENMASK(31, 24) +#define DQS_CAL_MIN_7 0x00000190 + #define DQS_CAL_MIN_7_DQS3_4_DLY_MIN GENMASK(7, 0) + #define DQS_CAL_MIN_7_DQS3_5_DLY_MIN GENMASK(15, 8) + #define DQS_CAL_MIN_7_DQS3_6_DLY_MIN GENMASK(23, 16) + #define DQS_CAL_MIN_7_DQS3_7_DLY_MIN GENMASK(31, 24) +#define DQS_CAL_MAX_0 0x00000194 + #define DQS_CAL_MAX_0_DQS0_0_DLY_MAX GENMASK(7, 0) + #define DQS_CAL_MAX_0_DQS0_1_DLY_MAX GENMASK(15, 8) + #define DQS_CAL_MAX_0_DQS0_2_DLY_MAX GENMASK(23, 16) + #define DQS_CAL_MAX_0_DQS0_3_DLY_MAX GENMASK(31, 24) +#define DQS_CAL_MAX_1 0x00000198 + #define DQS_CAL_MAX_1_DQS0_4_DLY_MAX GENMASK(7, 0) + #define DQS_CAL_MAX_1_DQS0_5_DLY_MAX GENMASK(15, 8) + #define DQS_CAL_MAX_1_DQS0_6_DLY_MAX GENMASK(23, 16) + #define DQS_CAL_MAX_1_DQS0_7_DLY_MAX GENMASK(31, 24) +#define DQS_CAL_MAX_2 0x0000019c + #define DQS_CAL_MAX_2_DQS1_0_DLY_MAX GENMASK(7, 0) + #define DQS_CAL_MAX_2_DQS1_1_DLY_MAX GENMASK(15, 8) + #define DQS_CAL_MAX_2_DQS1_2_DLY_MAX GENMASK(23, 16) + #define DQS_CAL_MAX_2_DQS1_3_DLY_MAX GENMASK(31, 24) +#define DQS_CAL_MAX_3 0x000001a0 + #define DQS_CAL_MAX_3_DQS1_4_DLY_MAX GENMASK(7, 0) + #define DQS_CAL_MAX_3_DQS1_5_DLY_MAX GENMASK(15, 8) + #define DQS_CAL_MAX_3_DQS1_6_DLY_MAX GENMASK(23, 16) + #define DQS_CAL_MAX_3_DQS1_7_DLY_MAX GENMASK(31, 24) +#define DQS_CAL_MAX_4 0x000001a4 + #define DQS_CAL_MAX_4_DQS2_0_DLY_MAX GENMASK(7, 0) + #define DQS_CAL_MAX_4_DQS2_1_DLY_MAX GENMASK(15, 8) + #define DQS_CAL_MAX_4_DQS2_2_DLY_MAX GENMASK(23, 16) + #define DQS_CAL_MAX_4_DQS2_3_DLY_MAX GENMASK(31, 24) +#define DQS_CAL_MAX_5 0x000001a8 + #define DQS_CAL_MAX_5_DQS2_4_DLY_MAX GENMASK(7, 0) + #define DQS_CAL_MAX_5_DQS2_5_DLY_MAX GENMASK(15, 8) + #define DQS_CAL_MAX_5_DQS2_6_DLY_MAX GENMASK(23, 16) + #define DQS_CAL_MAX_5_DQS2_7_DLY_MAX GENMASK(31, 24) +#define DQS_CAL_MAX_6 0x000001ac + #define DQS_CAL_MAX_6_DQS3_0_DLY_MAX GENMASK(7, 0) + #define DQS_CAL_MAX_6_DQS3_1_DLY_MAX GENMASK(15, 8) + #define DQS_CAL_MAX_6_DQS3_2_DLY_MAX GENMASK(23, 16) + #define DQS_CAL_MAX_6_DQS3_3_DLY_MAX GENMASK(31, 24) +#define DQS_CAL_MAX_7 0x000001b0 + #define DQS_CAL_MAX_7_DQS3_4_DLY_MAX GENMASK(7, 0) + #define DQS_CAL_MAX_7_DQS3_5_DLY_MAX GENMASK(15, 8) + #define DQS_CAL_MAX_7_DQS3_6_DLY_MAX GENMASK(23, 16) + #define DQS_CAL_MAX_7_DQS3_7_DLY_MAX GENMASK(31, 24) +#define DQICAL0 0x000001b4 + #define DQICAL0_DQ0_DLY_MAX GENMASK(6, 0) + #define DQICAL0_DQ1_DLY_MAX GENMASK(14, 8) + #define DQICAL0_DQ2_DLY_MAX GENMASK(22, 16) + #define DQICAL0_DQ3_DLY_MAX GENMASK(30, 24) +#define DQICAL1 0x000001b8 + #define DQICAL1_DQS0_DLY_MIN GENMASK(6, 0) + #define DQICAL1_DQS1_DLY_MIN GENMASK(14, 8) + #define DQICAL1_DQS2_DLY_MIN GENMASK(22, 16) + #define DQICAL1_DQS3_DLY_MIN GENMASK(30, 24) +#define DQICAL2 0x000001bc + #define DQICAL2_DQS0_DLY_MAX GENMASK(6, 0) + #define DQICAL2_DQS1_DLY_MAX GENMASK(14, 8) + #define DQICAL2_DQS2_DLY_MAX GENMASK(22, 16) + #define DQICAL2_DQS3_DLY_MAX GENMASK(30, 24) +#define DQICAL3 0x000001c0 + #define DQICAL3_DQS0_DLY_AVG GENMASK(6, 0) + #define DQICAL3_DQS1_DLY_AVG GENMASK(14, 8) + #define DQICAL3_DQS2_DLY_AVG GENMASK(22, 16) + #define DQICAL3_DQS3_DLY_AVG GENMASK(30, 24) +#define TESTCHIP_DMA_STATUS1 0x00000200 + #define TESTCHIP_DMA_STATUS1_DMASTATUS BIT(0) + #define TESTCHIP_DMA_STATUS1_DMA_BUF_AVAIL BIT(2) + #define TESTCHIP_DMA_STATUS1_DMACMPERR BIT(3) + #define TESTCHIP_DMA_STATUS1_DMA_STATE GENMASK(7, 4) +#define TESTCHIP_DMA_STATUS2 0x00000204 + #define TESTCHIP_DMA_STATUS2_DMACMPERR_BIT GENMASK(31, 0) +#define TESTCHIP_DMA_STATUS3 0x00000208 + #define TESTCHIP_DMA_STATUS3_DMA_DATA_BUFFER0_31_0_ GENMASK(31, 0) +#define TESTCHIP_DMA_STATUS4 0x0000020c + #define TESTCHIP_DMA_STATUS4_DMA_DATA_BUFFER0_63_32_ GENMASK(31, 0) +#define TESTCHIP_DMA_STATUS5 0x00000210 + #define TESTCHIP_DMA_STATUS5_DMA_DATA_BUFFER0_95_64_ GENMASK(31, 0) +#define TESTCHIP_DMA_STATUS6 0x00000214 + #define TESTCHIP_DMA_STATUS6_DMA_DATA_BUFFER0_127_96_ GENMASK(31, 0) +#define TESTCHIP_DMA_STATUS7 0x00000218 + #define TESTCHIP_DMA_STATUS7_DMA_DATA_BUFFER1_31_0_ GENMASK(31, 0) +#define TESTCHIP_DMA_STATUS8 0x0000021c + #define TESTCHIP_DMA_STATUS8_DMA_DATA_BUFFER1_63_32_ GENMASK(31, 0) +#define TESTCHIP_DMA_STATUS9 0x00000220 + #define TESTCHIP_DMA_STATUS9_DMA_DATA_BUFFER1_95_64_ GENMASK(31, 0) +#define TESTCHIP_DMA_STATUS10 0x00000224 + #define TESTCHIP_DMA_STATUS10_DMA_DATA_BUFFE1_127_96_ GENMASK(31, 0) +#define TESTCHIP_DMA_STATUS11 0x00000228 + #define TESTCHIP_DMA_STATUS11_DMA_DATA_BUFFER2_31_0_ GENMASK(31, 0) +#define TESTCHIP_DMA_STATUS12 0x0000022c + #define TESTCHIP_DMA_STATUS12_DMA_DATA_BUFFER2_63_32_ GENMASK(31, 0) +#define TESTCHIP_DMA_STATUS13 0x00000230 + #define TESTCHIP_DMA_STATUS13_DMA_DATA_BUFFER2_95_64_ GENMASK(31, 0) +#define TESTCHIP_DMA_STATUS14 0x00000234 + #define TESTCHIP_DMA_STATUS14_DMA_DATA_BUFFER2_127_96_ GENMASK(31, 0) +#define TESTCHIP_DMA_STATUS15 0x00000238 + #define TESTCHIP_DMA_STATUS15_DMA_DATA_BUFFER3_31_0_ GENMASK(31, 0) +#define TESTCHIP_DMA_STATUS16 0x0000023c + #define TESTCHIP_DMA_STATUS16_DMA_DATA_BUFFER3_63_32_ GENMASK(31, 0) +#define TESTCHIP_DMA_STATUS17 0x00000240 + #define TESTCHIP_DMA_STATUS17_DMA_DATA_BUFFER3_95_64_ GENMASK(31, 0) +#define TESTCHIP_DMA_STATUS18 0x00000244 + #define TESTCHIP_DMA_STATUS18_DMA_DATA_BUFFER3_127_96_ GENMASK(31, 0) +#define TESTCHIP_DMA_STATUS19 0x00000248 + #define TESTCHIP_DMA_STATUS19_DMA_DATA_BUFFER4_31_0_ GENMASK(31, 0) +#define TESTCHIP_DMA_STATUS20 0x0000024c + #define TESTCHIP_DMA_STATUS20_DMA_DATA_BUFFER4_63_32_ GENMASK(31, 0) +#define TESTCHIP_DMA_STATUS21 0x00000250 + #define TESTCHIP_DMA_STATUS21_DMA_DATA_BUFFER4_95_64_ GENMASK(31, 0) +#define TESTCHIP_DMA_STATUS22 0x00000254 + #define TESTCHIP_DMA_STATUS22_DMA_DATA_BUFFER4_127_96_ GENMASK(31, 0) +#define TESTCHIP_DMA_STATUS23 0x00000258 + #define TESTCHIP_DMA_STATUS23_DMA_DATA_BUFFER5_31_0_ GENMASK(31, 0) +#define TESTCHIP_DMA_STATUS24 0x0000025c + #define TESTCHIP_DMA_STATUS24_DMA_DATA_BUFFER5_63_32_ GENMASK(31, 0) +#define TESTCHIP_DMA_STATUS25 0x00000260 + #define TESTCHIP_DMA_STATUS25_DMA_DATA_BUFFER5_95_64_ GENMASK(31, 0) +#define TESTCHIP_DMA_STATUS26 0x00000264 + #define TESTCHIP_DMA_STATUS26_DMA_DATA_BUFFER5_127_96_ GENMASK(31, 0) +#define TESTCHIP_DMA_STATUS27 0x00000268 + #define TESTCHIP_DMA_STATUS27_DMA_DATA_BUFFER6_31_0_ GENMASK(31, 0) +#define TESTCHIP_DMA_STATUS28 0x0000026c + #define TESTCHIP_DMA_STATUS28_DMA_DATA_BUFFER6_63_32_ GENMASK(31, 0) +#define TESTCHIP_DMA_STATUS29 0x00000270 + #define TESTCHIP_DMA_STATUS29_DMA_DATA_BUFFER6_95_64_ GENMASK(31, 0) +#define TESTCHIP_DMA_STATUS30 0x00000274 + #define TESTCHIP_DMA_STATUS30_DMA_DATA_BUFFER6_127_96_ GENMASK(31, 0) +#define TESTCHIP_DMA_STATUS31 0x00000278 + #define TESTCHIP_DMA_STATUS31_DMA_DATA_BUFFER7_31_0_ GENMASK(31, 0) +#define TESTCHIP_DMA_STATUS32 0x0000027c + #define TESTCHIP_DMA_STATUS32_DMA_DATA_BUFFER7_63_32_ GENMASK(31, 0) +#define TESTCHIP_DMA_STATUS33 0x00000280 + #define TESTCHIP_DMA_STATUS33_DMA_DATA_BUFFER7_95_64_ GENMASK(31, 0) +#define TESTCHIP_DMA_STATUS34 0x00000284 + #define TESTCHIP_DMA_STATUS34_DMA_DATA_BUFFER7_127_96_ GENMASK(31, 0) +#define REFRESH_POP_COUNTER 0x00000300 + #define REFRESH_POP_COUNTER_REFRESH_POP_COUNTER GENMASK(31, 0) +#define FREERUN_26M_COUNTER 0x00000304 + #define FREERUN_26M_COUNTER_FREERUN_26M_COUNTER GENMASK(31, 0) +#define DRAMC_IDLE_COUNTER 0x00000308 + #define DRAMC_IDLE_COUNTER_DRAMC_IDLE_COUNTER GENMASK(31, 0) +#define R2R_PAGE_HIT_COUNTER 0x0000030c + #define R2R_PAGE_HIT_COUNTER_R2R_PAGE_HIT_COUNTER GENMASK(31, 0) +#define R2R_PAGE_MISS_COUNTER 0x00000310 + #define R2R_PAGE_MISS_COUNTER_R2R_PAGE_MISS_COUNTER GENMASK(31, 0) +#define R2R_INTERBANK_COUNTER 0x00000314 + #define R2R_INTERBANK_COUNTER_R2R_INTERBANK_COUNTER GENMASK(31, 0) +#define R2W_PAGE_HIT_COUNTER 0x00000318 + #define R2W_PAGE_HIT_COUNTER_R2W_PAGE_HIT_COUNTER GENMASK(31, 0) +#define R2W_PAGE_MISS_COUNTER 0x0000031c + #define R2W_PAGE_MISS_COUNTER_R2W_PAGE_MISS_COUNTER GENMASK(31, 0) +#define R2W_INTERBANK_COUNTER 0x00000320 + #define R2W_INTERBANK_COUNTER_R2W_INTERBANK_COUNTER GENMASK(31, 0) +#define W2R_PAGE_HIT_COUNTER 0x00000324 + #define W2R_PAGE_HIT_COUNTER_W2R_PAGE_HIT_COUNTER GENMASK(31, 0) +#define W2R_PAGE_MISS_COUNTER 0x00000328 + #define W2R_PAGE_MISS_COUNTER_W2R_PAGE_MISS_COUNTER GENMASK(31, 0) +#define W2R_INTERBANK_COUNTER 0x0000032c + #define W2R_INTERBANK_COUNTER_W2R_INTERBANK_COUNTER GENMASK(31, 0) +#define W2W_PAGE_HIT_COUNTER 0x00000330 + #define W2W_PAGE_HIT_COUNTER_W2W_PAGE_HIT_COUNTER GENMASK(31, 0) +#define W2W_PAGE_MISS_COUNTER 0x00000334 + #define W2W_PAGE_MISS_COUNTER_W2W_PAGE_MISS_COUNTER GENMASK(31, 0) +#define W2W_INTERBANK_COUNTER 0x00000338 + #define W2W_INTERBANK_COUNTER_W2W_INTERBANK_COUNTER GENMASK(31, 0) +#define RK0_PRE_STANDBY_COUNTER 0x0000033c + #define RK0_PRE_STANDBY_COUNTER_RK0_PRE_STANDBY_COUNTER GENMASK(31, 0) +#define RK0_PRE_POWERDOWN_COUNTER 0x00000340 + #define RK0_PRE_POWERDOWN_COUNTER_RK0_PRE_POWERDOWN_COUNTER GENMASK(31, 0) +#define RK0_ACT_STANDBY_COUNTER 0x00000344 + #define RK0_ACT_STANDBY_COUNTER_RK0_ACT_STANDBY_COUNTER GENMASK(31, 0) +#define RK0_ACT_POWERDOWN_COUNTER 0x00000348 + #define RK0_ACT_POWERDOWN_COUNTER_RK0_ACT_POWERDOWN_COUNTER GENMASK(31, 0) +#define RK1_PRE_STANDBY_COUNTER 0x0000034c + #define RK1_PRE_STANDBY_COUNTER_RK1_PRE_STANDBY_COUNTER GENMASK(31, 0) +#define RK1_PRE_POWERDOWN_COUNTER 0x00000350 + #define RK1_PRE_POWERDOWN_COUNTER_RK1_PRE_POWERDOWN_COUNTER GENMASK(31, 0) +#define RK1_ACT_STANDBY_COUNTER 0x00000354 + #define RK1_ACT_STANDBY_COUNTER_RK1_ACT_STANDBY_COUNTER GENMASK(31, 0) +#define RK1_ACT_POWERDOWN_COUNTER 0x00000358 + #define RK1_ACT_POWERDOWN_COUNTER_RK1_ACT_POWERDOWN_COUNTER GENMASK(31, 0) +#define RK2_PRE_STANDBY_COUNTER 0x0000035c + #define RK2_PRE_STANDBY_COUNTER_RK2_PRE_STANDBY_COUNTER GENMASK(31, 0) +#define RK2_PRE_POWERDOWN_COUNTER 0x00000360 + #define RK2_PRE_POWERDOWN_COUNTER_RK2_PRE_POWERDOWN_COUNTER GENMASK(31, 0) +#define RK2_ACT_STANDBY_COUNTER 0x00000364 + #define RK2_ACT_STANDBY_COUNTER_RK2_ACT_STANDBY_COUNTER GENMASK(31, 0) +#define RK2_ACT_POWERDOWN_COUNTER 0x00000368 + #define RK2_ACT_POWERDOWN_COUNTER_RK2_ACT_POWERDOWN_COUNTER GENMASK(31, 0) +#define DQ0_TOGGLE_COUNTER 0x0000036c + #define DQ0_TOGGLE_COUNTER_DQ0_TOGGLE_COUNTER GENMASK(31, 0) +#define DQ1_TOGGLE_COUNTER 0x00000370 + #define DQ1_TOGGLE_COUNTER_DQ1_TOGGLE_COUNTER GENMASK(31, 0) +#define DQ2_TOGGLE_COUNTER 0x00000374 + #define DQ2_TOGGLE_COUNTER_DQ2_TOGGLE_COUNTER GENMASK(31, 0) +#define DQ3_TOGGLE_COUNTER 0x00000378 + #define DQ3_TOGGLE_COUNTER_DQ3_TOGGLE_COUNTER GENMASK(31, 0) +#define DQ0_TOGGLE_COUNTER_R 0x0000037c + #define DQ0_TOGGLE_COUNTER_R_DQ0_TOGGLE_COUNTER_R GENMASK(31, 0) +#define DQ1_TOGGLE_COUNTER_R 0x00000380 + #define DQ1_TOGGLE_COUNTER_R_DQ1_TOGGLE_COUNTER_R GENMASK(31, 0) +#define DQ2_TOGGLE_COUNTER_R 0x00000384 + #define DQ2_TOGGLE_COUNTER_R_DQ2_TOGGLE_COUNTER_R GENMASK(31, 0) +#define DQ3_TOGGLE_COUNTER_R 0x00000388 + #define DQ3_TOGGLE_COUNTER_R_DQ3_TOGGLE_COUNTER_R GENMASK(31, 0) +#define READ_BYTES_COUNTER 0x0000038c + #define READ_BYTES_COUNTER_READ_BYTES_COUNTER GENMASK(31, 0) +#define WRITE_BYTES_COUNTER 0x00000390 + #define WRITE_BYTES_COUNTER_WRITE_BYTES_COUNTER GENMASK(31, 0) +#define MAX_SREF_REQ_TO_ACK_LATENCY_COUNTER 0x00000394 + #define MAX_SREF_REQ_TO_ACK_LATENCY_COUNTER_SREF_REQTOACK_MAX_COUNTER GENMASK(31, 0) +#define MAX_RK1_DRS_LONG_REQ_TO_ACK_LATENCY_COUNTER 0x00000398 + #define MAX_RK1_DRS_LONG_REQ_TO_ACK_LATENCY_COUNTER_DRS_LONG_REQTOACK_MAX_COUNTER GENMASK(31, 0) +#define MAX_RK1_DRS_REQ_TO_ACK_LATENCY_COUNTER 0x0000039c + #define MAX_RK1_DRS_REQ_TO_ACK_LATENCY_COUNTER_DRS_REQTOACK_MAX_COUNTER GENMASK(31, 0) +#define DRAMC_IDLE_DCM_COUNTER 0x000003a0 + #define DRAMC_IDLE_DCM_COUNTER_DRAMC_IDLE_DCM_COUNTER GENMASK(31, 0) +#define DDRPHY_CLK_EN_COUNTER 0x000003a4 + #define DDRPHY_CLK_EN_COUNTER_DDRPHY_CLK_EN_COUNTER GENMASK(31, 0) +#define DDRPHY_CLK_EN_COMB_COUNTER 0x000003a8 + #define DDRPHY_CLK_EN_COMB_COUNTER_DDRPHY_CLK_EN_COMB_COUNTER GENMASK(31, 0) +#define LAT_COUNTER_CMD0 0x000003c0 + #define LAT_COUNTER_CMD0_LAT_CMD0_CNT_MAX GENMASK(15, 0) + #define LAT_COUNTER_CMD0_LAT_CMD0_CNT_MAX_HPRI BIT(16) + #define LAT_COUNTER_CMD0_LAT_CMD0_CNT_MAX_LLAT BIT(17) + #define LAT_COUNTER_CMD0_LAT_CMD0_CNT_MAX_REORDER BIT(18) +#define LAT_COUNTER_CMD1 0x000003c4 + #define LAT_COUNTER_CMD1_LAT_CMD1_CNT_MAX GENMASK(15, 0) + #define LAT_COUNTER_CMD1_LAT_CMD1_CNT_MAX_HPRI BIT(16) + #define LAT_COUNTER_CMD1_LAT_CMD1_CNT_MAX_LLAT BIT(17) + #define LAT_COUNTER_CMD1_LAT_CMD1_CNT_MAX_REORDER BIT(18) +#define LAT_COUNTER_CMD2 0x000003c8 + #define LAT_COUNTER_CMD2_LAT_CMD2_CNT_MAX GENMASK(15, 0) + #define LAT_COUNTER_CMD2_LAT_CMD2_CNT_MAX_HPRI BIT(16) + #define LAT_COUNTER_CMD2_LAT_CMD2_CNT_MAX_LLAT BIT(17) + #define LAT_COUNTER_CMD2_LAT_CMD2_CNT_MAX_REORDER BIT(18) +#define LAT_COUNTER_CMD3 0x000003cc + #define LAT_COUNTER_CMD3_LAT_CMD3_CNT_MAX GENMASK(15, 0) + #define LAT_COUNTER_CMD3_LAT_CMD3_CNT_MAX_HPRI BIT(16) + #define LAT_COUNTER_CMD3_LAT_CMD3_CNT_MAX_LLAT BIT(17) + #define LAT_COUNTER_CMD3_LAT_CMD3_CNT_MAX_REORDER BIT(18) +#define LAT_COUNTER_CMD4 0x000003d0 + #define LAT_COUNTER_CMD4_LAT_CMD4_CNT_MAX GENMASK(15, 0) + #define LAT_COUNTER_CMD4_LAT_CMD4_CNT_MAX_HPRI BIT(16) + #define LAT_COUNTER_CMD4_LAT_CMD4_CNT_MAX_LLAT BIT(17) + #define LAT_COUNTER_CMD4_LAT_CMD4_CNT_MAX_REORDER BIT(18) +#define LAT_COUNTER_CMD5 0x000003d4 + #define LAT_COUNTER_CMD5_LAT_CMD5_CNT_MAX GENMASK(15, 0) + #define LAT_COUNTER_CMD5_LAT_CMD5_CNT_MAX_HPRI BIT(16) + #define LAT_COUNTER_CMD5_LAT_CMD5_CNT_MAX_LLAT BIT(17) + #define LAT_COUNTER_CMD5_LAT_CMD5_CNT_MAX_REORDER BIT(18) +#define LAT_COUNTER_CMD6 0x000003d8 + #define LAT_COUNTER_CMD6_LAT_CMD6_CNT_MAX GENMASK(15, 0) + #define LAT_COUNTER_CMD6_LAT_CMD6_CNT_MAX_HPRI BIT(16) + #define LAT_COUNTER_CMD6_LAT_CMD6_CNT_MAX_LLAT BIT(17) + #define LAT_COUNTER_CMD6_LAT_CMD6_CNT_MAX_REORDER BIT(18) +#define LAT_COUNTER_CMD7 0x000003dc + #define LAT_COUNTER_CMD7_LAT_CMD7_CNT_MAX GENMASK(15, 0) + #define LAT_COUNTER_CMD7_LAT_CMD7_CNT_MAX_HPRI BIT(16) + #define LAT_COUNTER_CMD7_LAT_CMD7_CNT_MAX_LLAT BIT(17) + #define LAT_COUNTER_CMD7_LAT_CMD7_CNT_MAX_REORDER BIT(18) +#define LAT_COUNTER_AVER 0x000003e0 + #define LAT_COUNTER_AVER_LAT_CMD_AVER_CNT GENMASK(31, 0) +#define LAT_COUNTER_NUM 0x000003e4 + #define LAT_COUNTER_NUM_LAT_CMD_NUM GENMASK(15, 0) +#define LAT_COUNTER_BLOCK_ALE 0x000003e8 + #define LAT_COUNTER_BLOCK_ALE_CTO_BLOCK_CNT_MAX GENMASK(15, 0) +#define DQSSAMPLEV 0x00000400 + #define DQSSAMPLEV_SAMPLE_OUT1_DQS0 BIT(0) + #define DQSSAMPLEV_SAMPLE_OUT1_DQS1 BIT(1) + #define DQSSAMPLEV_SAMPLE_OUT1_DQS2 BIT(2) + #define DQSSAMPLEV_SAMPLE_OUT1_DQS3 BIT(3) + #define DQSSAMPLEV_PI_OVERFLOW GENMASK(15, 12) +#define DQSGNWCNT0 0x00000408 + #define DQSGNWCNT0_DQS0F_GATING_COUNTER GENMASK(7, 0) + #define DQSGNWCNT0_DQS0R_GATING_COUNTER GENMASK(15, 8) + #define DQSGNWCNT0_DQS1F_GATING_COUNTER GENMASK(23, 16) + #define DQSGNWCNT0_DQS1R_GATING_COUNTER GENMASK(31, 24) +#define DQSGNWCNT1 0x0000040c + #define DQSGNWCNT1_DQS2F_GATING_COUNTER GENMASK(7, 0) + #define DQSGNWCNT1_DQS2R_GATING_COUNTER GENMASK(15, 8) + #define DQSGNWCNT1_DQS3F_GATING_COUNTER GENMASK(23, 16) + #define DQSGNWCNT1_DQS3R_GATING_COUNTER GENMASK(31, 24) +#define DQSGNWCNT2 0x00000410 + #define DQSGNWCNT2_DQS0F_POS_GATING_COUNTER GENMASK(7, 0) + #define DQSGNWCNT2_DQS0R_POS_GATING_COUNTER GENMASK(15, 8) + #define DQSGNWCNT2_DQS0F_PRE_GATING_COUNTER GENMASK(23, 16) + #define DQSGNWCNT2_DQS0R_PRE_GATING_COUNTER GENMASK(31, 24) +#define DQSGNWCNT3 0x00000414 + #define DQSGNWCNT3_DQS1F_POS_GATING_COUNTER GENMASK(7, 0) + #define DQSGNWCNT3_DQS1R_POS_GATING_COUNTER GENMASK(15, 8) + #define DQSGNWCNT3_DQS1F_PRE_GATING_COUNTER GENMASK(23, 16) + #define DQSGNWCNT3_DQS1R_PRE_GATING_COUNTER GENMASK(31, 24) +#define DQSGNWCNT4 0x00000418 + #define DQSGNWCNT4_DQS2F_POS_GATING_COUNTER GENMASK(7, 0) + #define DQSGNWCNT4_DQS2R_POS_GATING_COUNTER GENMASK(15, 8) + #define DQSGNWCNT4_DQS2F_PRE_GATING_COUNTER GENMASK(23, 16) + #define DQSGNWCNT4_DQS2R_PRE_GATING_COUNTER GENMASK(31, 24) +#define DQSGNWCNT5 0x0000041c + #define DQSGNWCNT5_DQS3F_POS_GATING_COUNTER GENMASK(7, 0) + #define DQSGNWCNT5_DQS3R_POS_GATING_COUNTER GENMASK(15, 8) + #define DQSGNWCNT5_DQS3F_PRE_GATING_COUNTER GENMASK(23, 16) + #define DQSGNWCNT5_DQS3R_PRE_GATING_COUNTER GENMASK(31, 24) +#define TOGGLE_CNT 0x00000420 + #define TOGGLE_CNT_TOGGLE_CNT GENMASK(31, 0) +#define DQS0_ERR_CNT 0x00000424 + #define DQS0_ERR_CNT_DQS0_ERR_CNT GENMASK(31, 0) +#define DQ_ERR_CNT0 0x00000428 + #define DQ_ERR_CNT0_DQ_ERR_CNT0 GENMASK(31, 0) +#define DQS1_ERR_CNT 0x0000042c + #define DQS1_ERR_CNT_DQS1_ERR_CNT GENMASK(31, 0) +#define DQ_ERR_CNT1 0x00000430 + #define DQ_ERR_CNT1_DQ_ERR_CNT1 GENMASK(31, 0) +#define DQS2_ERR_CNT 0x00000434 + #define DQS2_ERR_CNT_DQS2_ERR_CNT GENMASK(31, 0) +#define DQ_ERR_CNT2 0x00000438 + #define DQ_ERR_CNT2_DQ_ERR_CNT2 GENMASK(31, 0) +#define DQS3_ERR_CNT 0x0000043c + #define DQS3_ERR_CNT_DQS3_ERR_CNT GENMASK(31, 0) +#define DQ_ERR_CNT3 0x00000440 + #define DQ_ERR_CNT3_DQ_ERR_CNT3 GENMASK(31, 0) +#define IORGCNT 0x00000450 + #define IORGCNT_IO_RING_COUNTER_K GENMASK(15, 0) + #define IORGCNT_IO_RING_COUNTER GENMASK(31, 16) +#define DQSG_RETRY_STATE 0x00000454 + #define DQSG_RETRY_STATE_DQSG_RETRY_1ST_ST GENMASK(7, 0) + #define DQSG_RETRY_STATE_DQSG_RETRY_2ND_ST GENMASK(15, 8) + #define DQSG_RETRY_STATE_DQSG_RETRY_3RD_ST GENMASK(23, 16) + #define DQSG_RETRY_STATE_DQSG_RETRY_4TH_ST GENMASK(31, 24) +#define DQSG_RETRY_STATE1 0x00000458 + #define DQSG_RETRY_STATE1_RETRY_DONE_ALL BIT(0) + #define DQSG_RETRY_STATE1_SELPH_RODTEN_USABLE BIT(1) + #define DQSG_RETRY_STATE1_TDQSCK_DONE BIT(4) + #define DQSG_RETRY_STATE1_IMPCAL_N_ERROR BIT(8) + #define DQSG_RETRY_STATE1_IMPCAL_P_ERROR BIT(9) + #define DQSG_RETRY_STATE1_IMPCAL_DONE BIT(10) + #define DQSG_RETRY_STATE1_STB_GATING_ERR BIT(16) + #define DQSG_RETRY_STATE1_R_OTHER_SHU_GP_GATING_ERR GENMASK(18, 17) + #define DQSG_RETRY_STATE1_R_MPDIV_SHU_GP_GATING_ERR GENMASK(21, 19) + #define DQSG_RETRY_STATE1_DQSG_RETRY_5TH_ST GENMASK(31, 24) +#define IMPCAL_STATUS1 0x00000460 + #define IMPCAL_STATUS1_DRVNDQ_SAVE2 GENMASK(4, 0) + #define IMPCAL_STATUS1_DRVPDQ_SAVE2 GENMASK(9, 5) + #define IMPCAL_STATUS1_DRVNDQS_SAVE1 GENMASK(14, 10) + #define IMPCAL_STATUS1_DRVPDQS_SAVE1 GENMASK(19, 15) + #define IMPCAL_STATUS1_DRVNDQS_SAVE2 GENMASK(24, 20) + #define IMPCAL_STATUS1_DRVPDQS_SAVE2 GENMASK(29, 25) +#define IMPCAL_STATUS2 0x00000464 + #define IMPCAL_STATUS2_DRVNCMD_SAVE1 GENMASK(4, 0) + #define IMPCAL_STATUS2_DRVPCMD_SAVE1 GENMASK(9, 5) + #define IMPCAL_STATUS2_DRVNCMD_SAVE2 GENMASK(14, 10) + #define IMPCAL_STATUS2_DRVPCMD_SAVE2 GENMASK(19, 15) + #define IMPCAL_STATUS2_DRVNDQ_SAVE1 GENMASK(24, 20) + #define IMPCAL_STATUS2_DRVPDQ_SAVE1 GENMASK(29, 25) +#define DQDRV_STATUS 0x00000468 + #define DQDRV_STATUS_DRVNDQ_2 GENMASK(4, 0) + #define DQDRV_STATUS_DRVPDQ_2 GENMASK(9, 5) + #define DQDRV_STATUS_DRVNDQS_1 GENMASK(14, 10) + #define DQDRV_STATUS_DRVPDQS_1 GENMASK(19, 15) + #define DQDRV_STATUS_DRVNDQS_2 GENMASK(24, 20) + #define DQDRV_STATUS_DRVPDQS_2 GENMASK(29, 25) +#define CMDDRV_STATUS 0x0000046c + #define CMDDRV_STATUS_DRVNCMD_1 GENMASK(4, 0) + #define CMDDRV_STATUS_DRVPCMD_1 GENMASK(9, 5) + #define CMDDRV_STATUS_DRVNCMD_2 GENMASK(14, 10) + #define CMDDRV_STATUS_DRVPCMD_2 GENMASK(19, 15) + #define CMDDRV_STATUS_DRVNDQ_1 GENMASK(24, 20) + #define CMDDRV_STATUS_DRVPDQ_1 GENMASK(29, 25) +#define CMDDRV1 0x00000470 + #define CMDDRV1_CMDDRV1 GENMASK(31, 0) +#define CMDDRV2 0x00000474 + #define CMDDRV2_CMDDRV2 GENMASK(31, 0) +#define RK0_DQSOSC_STATUS 0x00000600 + #define RK0_DQSOSC_STATUS_MR18_REG GENMASK(15, 0) + #define RK0_DQSOSC_STATUS_MR19_REG GENMASK(31, 16) +#define RK0_DQSOSC_DELTA 0x00000604 + #define RK0_DQSOSC_DELTA_ABS_RK0_DQSOSC_DELTA GENMASK(15, 0) + #define RK0_DQSOSC_DELTA_SIGN_RK0_DQSOSC_DELTA BIT(16) + #define RK0_DQSOSC_DELTA_DQSOCSR_RESPONSE BIT(17) + #define RK0_DQSOSC_DELTA_H_DQSOSCLSBR_REQ BIT(18) + #define RK0_DQSOSC_DELTA_DQSOSC_INT_RK0 BIT(19) +#define RK0_DQSOSC_DELTA2 0x00000608 + #define RK0_DQSOSC_DELTA2_ABS_RK0_DQSOSC_B1_DELTA GENMASK(15, 0) + #define RK0_DQSOSC_DELTA2_SIGN_RK0_DQSOSC_B1_DELTA BIT(16) +#define RK0_CURRENT_TX_SETTING1 0x00000610 + #define RK0_CURRENT_TX_SETTING1_REG_TX_DLY_DQ0_MOD GENMASK(2, 0) + #define RK0_CURRENT_TX_SETTING1_REG_TX_DLY_DQ1_MOD GENMASK(6, 4) + #define RK0_CURRENT_TX_SETTING1_REG_TX_DLY_DQ2_MOD GENMASK(10, 8) + #define RK0_CURRENT_TX_SETTING1_REG_TX_DLY_DQ3_MOD GENMASK(14, 12) + #define RK0_CURRENT_TX_SETTING1_REG_TX_DLY_DQM0_MOD GENMASK(18, 16) + #define RK0_CURRENT_TX_SETTING1_REG_TX_DLY_DQM1_MOD GENMASK(22, 20) + #define RK0_CURRENT_TX_SETTING1_REG_TX_DLY_DQM2_MOD GENMASK(26, 24) + #define RK0_CURRENT_TX_SETTING1_REG_TX_DLY_DQM3_MOD GENMASK(30, 28) +#define RK0_CURRENT_TX_SETTING2 0x00000614 + #define RK0_CURRENT_TX_SETTING2_REG_DLY_DQ0_MOD GENMASK(2, 0) + #define RK0_CURRENT_TX_SETTING2_REG_DLY_DQ1_MOD GENMASK(6, 4) + #define RK0_CURRENT_TX_SETTING2_REG_DLY_DQ2_MOD GENMASK(10, 8) + #define RK0_CURRENT_TX_SETTING2_REG_DLY_DQ3_MOD GENMASK(14, 12) + #define RK0_CURRENT_TX_SETTING2_REG_DLY_DQM0_MOD GENMASK(18, 16) + #define RK0_CURRENT_TX_SETTING2_REG_DLY_DQM1_MOD GENMASK(22, 20) + #define RK0_CURRENT_TX_SETTING2_REG_DLY_DQM2_MOD GENMASK(26, 24) + #define RK0_CURRENT_TX_SETTING2_REG_DLY_DQM3_MOD GENMASK(30, 28) +#define RK0_CURRENT_TX_SETTING3 0x00000618 + #define RK0_CURRENT_TX_SETTING3_REG_TX_DLY_OEN_DQ0_MOD GENMASK(2, 0) + #define RK0_CURRENT_TX_SETTING3_REG_TX_DLY_OEN_DQ1_MOD GENMASK(6, 4) + #define RK0_CURRENT_TX_SETTING3_REG_TX_DLY_OEN_DQ2_MOD GENMASK(10, 8) + #define RK0_CURRENT_TX_SETTING3_REG_TX_DLY_OEN_DQ3_MOD GENMASK(14, 12) + #define RK0_CURRENT_TX_SETTING3_REG_TX_DLY_OEN_DQM0_MOD GENMASK(18, 16) + #define RK0_CURRENT_TX_SETTING3_REG_TX_DLY_OEN_DQM1_MOD GENMASK(22, 20) + #define RK0_CURRENT_TX_SETTING3_REG_TX_DLY_OEN_DQM2_MOD GENMASK(26, 24) + #define RK0_CURRENT_TX_SETTING3_REG_TX_DLY_OEN_DQM3_MOD GENMASK(30, 28) +#define RK0_CURRENT_TX_SETTING4 0x0000061c + #define RK0_CURRENT_TX_SETTING4_REG_DLY_OEN_DQ0_MOD GENMASK(2, 0) + #define RK0_CURRENT_TX_SETTING4_REG_DLY_OEN_DQ1_MOD GENMASK(6, 4) + #define RK0_CURRENT_TX_SETTING4_REG_DLY_OEN_DQ2_MOD GENMASK(10, 8) + #define RK0_CURRENT_TX_SETTING4_REG_DLY_OEN_DQ3_MOD GENMASK(14, 12) + #define RK0_CURRENT_TX_SETTING4_REG_DLY_OEN_DQM0_MOD GENMASK(18, 16) + #define RK0_CURRENT_TX_SETTING4_REG_DLY_OEN_DQM1_MOD GENMASK(22, 20) + #define RK0_CURRENT_TX_SETTING4_REG_DLY_OEN_DQM2_MOD GENMASK(26, 24) + #define RK0_CURRENT_TX_SETTING4_REG_DLY_OEN_DQM3_MOD GENMASK(30, 28) +#define RK0_DUMMY_RD_DATA0 0x00000620 + #define RK0_DUMMY_RD_DATA0_DUMMY_RD_RK0_DATA0 GENMASK(31, 0) +#define RK0_DUMMY_RD_DATA1 0x00000624 + #define RK0_DUMMY_RD_DATA1_DUMMY_RD_RK0_DATA1 GENMASK(31, 0) +#define RK0_DUMMY_RD_DATA2 0x00000628 + #define RK0_DUMMY_RD_DATA2_DUMMY_RD_RK0_DATA2 GENMASK(31, 0) +#define RK0_DUMMY_RD_DATA3 0x0000062c + #define RK0_DUMMY_RD_DATA3_DUMMY_RD_RK0_DATA3 GENMASK(31, 0) +#define RK0_B0_STB_MAX_MIN_DLY 0x00000630 + #define RK0_B0_STB_MAX_MIN_DLY_RK0_B0_STBEN_MIN_DLY GENMASK(11, 0) + #define RK0_B0_STB_MAX_MIN_DLY_RK0_B0_STBEN_MAX_DLY GENMASK(27, 16) +#define RK0_B1_STB_MAX_MIN_DLY 0x00000634 + #define RK0_B1_STB_MAX_MIN_DLY_RK0_B1_STBEN_MIN_DLY GENMASK(11, 0) + #define RK0_B1_STB_MAX_MIN_DLY_RK0_B1_STBEN_MAX_DLY GENMASK(27, 16) +#define RK0_B2_STB_MAX_MIN_DLY 0x00000638 + #define RK0_B2_STB_MAX_MIN_DLY_RK0_B2_STBEN_MIN_DLY GENMASK(11, 0) + #define RK0_B2_STB_MAX_MIN_DLY_RK0_B2_STBEN_MAX_DLY GENMASK(27, 16) +#define RK0_B3_STB_MAX_MIN_DLY 0x0000063c + #define RK0_B3_STB_MAX_MIN_DLY_RK0_B3_STBEN_MIN_DLY GENMASK(11, 0) + #define RK0_B3_STB_MAX_MIN_DLY_RK0_B3_STBEN_MAX_DLY GENMASK(27, 16) +#define RK0_DQSIENDLY 0x00000640 + #define RK0_DQSIENDLY_R0DQS0IENDLY GENMASK(6, 0) + #define RK0_DQSIENDLY_R0DQS1IENDLY GENMASK(14, 8) + #define RK0_DQSIENDLY_R0DQS2IENDLY GENMASK(22, 16) + #define RK0_DQSIENDLY_R0DQS3IENDLY GENMASK(30, 24) +#define RK0_DQSIENUIDLY 0x00000644 + #define RK0_DQSIENUIDLY_R0DQS0IENUIDLY GENMASK(5, 0) + #define RK0_DQSIENUIDLY_R0DQS1IENUIDLY GENMASK(13, 8) + #define RK0_DQSIENUIDLY_R0DQS2IENUIDLY GENMASK(21, 16) + #define RK0_DQSIENUIDLY_R0DQS3IENUIDLY GENMASK(29, 24) +#define RK0_DQSIENUIDLY_P1 0x00000648 + #define RK0_DQSIENUIDLY_P1_R0DQS0IENUIDLY_P1 GENMASK(5, 0) + #define RK0_DQSIENUIDLY_P1_R0DQS1IENUIDLY_P1 GENMASK(13, 8) + #define RK0_DQSIENUIDLY_P1_R0DQS2IENUIDLY_P1 GENMASK(21, 16) + #define RK0_DQSIENUIDLY_P1_R0DQS3IENUIDLY_P1 GENMASK(29, 24) +#define RK0_DQS_STBCALDEC_CNT1 0x00000650 + #define RK0_DQS_STBCALDEC_CNT1_RK0_DQS0_STBCALDEC_CNT GENMASK(15, 0) + #define RK0_DQS_STBCALDEC_CNT1_RK0_DQS1_STBCALDEC_CNT GENMASK(31, 16) +#define RK0_DQS_STBCALDEC_CNT2 0x00000654 + #define RK0_DQS_STBCALDEC_CNT2_RK0_DQS2_STBCALDEC_CNT GENMASK(15, 0) + #define RK0_DQS_STBCALDEC_CNT2_RK0_DQS3_STBCALDEC_CNT GENMASK(31, 16) +#define RK0_DQS_STBCALINC_CNT1 0x00000658 + #define RK0_DQS_STBCALINC_CNT1_RK0_DQS0_STBCALINC_CNT GENMASK(15, 0) + #define RK0_DQS_STBCALINC_CNT1_RK0_DQS1_STBCALINC_CNT GENMASK(31, 16) +#define RK0_DQS_STBCALINC_CNT2 0x0000065c + #define RK0_DQS_STBCALINC_CNT2_RK0_DQS2_STBCALINC_CNT GENMASK(15, 0) + #define RK0_DQS_STBCALINC_CNT2_RK0_DQS3_STBCALINC_CNT GENMASK(31, 16) +#define RK0_PI_DQ_CAL 0x00000660 + #define RK0_PI_DQ_CAL_RK0_ARPI_DQ_B0_CAL GENMASK(5, 0) + #define RK0_PI_DQ_CAL_RK0_ARPI_DQ_B1_CAL GENMASK(13, 8) + #define RK0_PI_DQ_CAL_PI_DQ_ADJ_RK0 GENMASK(21, 16) + #define RK0_PI_DQ_CAL_PI_DQ_ADJ_RK0_OVERFLOW BIT(22) + #define RK0_PI_DQ_CAL_RK0_B0_PI_CHANGE_DBG BIT(23) + #define RK0_PI_DQ_CAL_PI_DQ_ADJ_RK0_B1 GENMASK(29, 24) + #define RK0_PI_DQ_CAL_PI_DQ_ADJ_RK0_B1_OVERFLOW BIT(30) + #define RK0_PI_DQ_CAL_RK0_B1_PI_CHANGE_DBG BIT(31) +#define RK0_DQSG_RETRY_FLAG 0x00000664 + #define RK0_DQSG_RETRY_FLAG_RK0_RETRY_DONE0 BIT(0) + #define RK0_DQSG_RETRY_FLAG_RK0_RETRY_DONE1 BIT(1) + #define RK0_DQSG_RETRY_FLAG_RK0_RETRY_DONE2 BIT(2) + #define RK0_DQSG_RETRY_FLAG_RK0_RETRY_DONE3 BIT(3) + #define RK0_DQSG_RETRY_FLAG_RK0_RETRY_FAIL0 BIT(16) + #define RK0_DQSG_RETRY_FLAG_RK0_RETRY_FAIL1 BIT(17) + #define RK0_DQSG_RETRY_FLAG_RK0_RETRY_FAIL2 BIT(18) + #define RK0_DQSG_RETRY_FLAG_RK0_RETRY_FAIL3 BIT(19) +#define RK0_PI_DQM_CAL 0x00000668 + #define RK0_PI_DQM_CAL_RK0_ARPI_DQM_B0_CAL GENMASK(5, 0) + #define RK0_PI_DQM_CAL_RK0_ARPI_DQM_B1_CAL GENMASK(13, 8) +#define RK0_DQS0_STBCAL_CNT 0x00000670 + #define RK0_DQS0_STBCAL_CNT_R0_DQS0_STBCAL_CNT GENMASK(16, 0) +#define RK0_DQS1_STBCAL_CNT 0x00000674 + #define RK0_DQS1_STBCAL_CNT_R0_DQS1_STBCAL_CNT GENMASK(16, 0) +#define RK0_DQS2_STBCAL_CNT 0x00000678 + #define RK0_DQS2_STBCAL_CNT_R0_DQS2_STBCAL_CNT GENMASK(16, 0) +#define RK0_DQS3_STBCAL_CNT 0x0000067c + #define RK0_DQS3_STBCAL_CNT_R0_DQS3_STBCAL_CNT GENMASK(16, 0) +#define RK0_B01_STB_DBG_INFO_00 0x00000680 + #define RK0_B01_STB_DBG_INFO_00_RK0_B0_STB_DBG_INFO_00 GENMASK(15, 0) + #define RK0_B01_STB_DBG_INFO_00_RK0_B1_STB_DBG_INFO_00 GENMASK(31, 16) +#define RK0_B01_STB_DBG_INFO_01 0x00000684 + #define RK0_B01_STB_DBG_INFO_01_RK0_B0_STB_DBG_INFO_01 GENMASK(15, 0) + #define RK0_B01_STB_DBG_INFO_01_RK0_B1_STB_DBG_INFO_01 GENMASK(31, 16) +#define RK0_B01_STB_DBG_INFO_02 0x00000688 + #define RK0_B01_STB_DBG_INFO_02_RK0_B0_STB_DBG_INFO_02 GENMASK(15, 0) + #define RK0_B01_STB_DBG_INFO_02_RK0_B1_STB_DBG_INFO_02 GENMASK(31, 16) +#define RK0_B01_STB_DBG_INFO_03 0x0000068c + #define RK0_B01_STB_DBG_INFO_03_RK0_B0_STB_DBG_INFO_03 GENMASK(15, 0) + #define RK0_B01_STB_DBG_INFO_03_RK0_B1_STB_DBG_INFO_03 GENMASK(31, 16) +#define RK0_B01_STB_DBG_INFO_04 0x00000690 + #define RK0_B01_STB_DBG_INFO_04_RK0_B0_STB_DBG_INFO_04 GENMASK(15, 0) + #define RK0_B01_STB_DBG_INFO_04_RK0_B1_STB_DBG_INFO_04 GENMASK(31, 16) +#define RK0_B01_STB_DBG_INFO_05 0x00000694 + #define RK0_B01_STB_DBG_INFO_05_RK0_B0_STB_DBG_INFO_05 GENMASK(15, 0) + #define RK0_B01_STB_DBG_INFO_05_RK0_B1_STB_DBG_INFO_05 GENMASK(31, 16) +#define RK0_B01_STB_DBG_INFO_06 0x00000698 + #define RK0_B01_STB_DBG_INFO_06_RK0_B0_STB_DBG_INFO_06 GENMASK(15, 0) + #define RK0_B01_STB_DBG_INFO_06_RK0_B1_STB_DBG_INFO_06 GENMASK(31, 16) +#define RK0_B01_STB_DBG_INFO_07 0x0000069c + #define RK0_B01_STB_DBG_INFO_07_RK0_B0_STB_DBG_INFO_07 GENMASK(15, 0) + #define RK0_B01_STB_DBG_INFO_07_RK0_B1_STB_DBG_INFO_07 GENMASK(31, 16) +#define RK0_B01_STB_DBG_INFO_08 0x000006a0 + #define RK0_B01_STB_DBG_INFO_08_RK0_B0_STB_DBG_INFO_08 GENMASK(15, 0) + #define RK0_B01_STB_DBG_INFO_08_RK0_B1_STB_DBG_INFO_08 GENMASK(31, 16) +#define RK0_B01_STB_DBG_INFO_09 0x000006a4 + #define RK0_B01_STB_DBG_INFO_09_RK0_B0_STB_DBG_INFO_09 GENMASK(15, 0) + #define RK0_B01_STB_DBG_INFO_09_RK0_B1_STB_DBG_INFO_09 GENMASK(31, 16) +#define RK0_B01_STB_DBG_INFO_10 0x000006a8 + #define RK0_B01_STB_DBG_INFO_10_RK0_B0_STB_DBG_INFO_10 GENMASK(15, 0) + #define RK0_B01_STB_DBG_INFO_10_RK0_B1_STB_DBG_INFO_10 GENMASK(31, 16) +#define RK0_B01_STB_DBG_INFO_11 0x000006ac + #define RK0_B01_STB_DBG_INFO_11_RK0_B0_STB_DBG_INFO_11 GENMASK(15, 0) + #define RK0_B01_STB_DBG_INFO_11_RK0_B1_STB_DBG_INFO_11 GENMASK(31, 16) +#define RK0_B01_STB_DBG_INFO_12 0x000006b0 + #define RK0_B01_STB_DBG_INFO_12_RK0_B0_STB_DBG_INFO_12 GENMASK(15, 0) + #define RK0_B01_STB_DBG_INFO_12_RK0_B1_STB_DBG_INFO_12 GENMASK(31, 16) +#define RK0_B01_STB_DBG_INFO_13 0x000006b4 + #define RK0_B01_STB_DBG_INFO_13_RK0_B0_STB_DBG_INFO_13 GENMASK(15, 0) + #define RK0_B01_STB_DBG_INFO_13_RK0_B1_STB_DBG_INFO_13 GENMASK(31, 16) +#define RK0_B01_STB_DBG_INFO_14 0x000006b8 + #define RK0_B01_STB_DBG_INFO_14_RK0_B0_STB_DBG_INFO_14 GENMASK(15, 0) + #define RK0_B01_STB_DBG_INFO_14_RK0_B1_STB_DBG_INFO_14 GENMASK(31, 16) +#define RK0_B01_STB_DBG_INFO_15 0x000006bc + #define RK0_B01_STB_DBG_INFO_15_RK0_B0_STB_DBG_INFO_15 GENMASK(15, 0) + #define RK0_B01_STB_DBG_INFO_15_RK0_B1_STB_DBG_INFO_15 GENMASK(31, 16) +#define RK0_B23_STB_DBG_INFO_00 0x000006c0 + #define RK0_B23_STB_DBG_INFO_00_RK0_B2_STB_DBG_INFO_00 GENMASK(15, 0) + #define RK0_B23_STB_DBG_INFO_00_RK0_B3_STB_DBG_INFO_00 GENMASK(31, 16) +#define RK0_B23_STB_DBG_INFO_01 0x000006c4 + #define RK0_B23_STB_DBG_INFO_01_RK0_B2_STB_DBG_INFO_01 GENMASK(15, 0) + #define RK0_B23_STB_DBG_INFO_01_RK0_B3_STB_DBG_INFO_01 GENMASK(31, 16) +#define RK0_B23_STB_DBG_INFO_02 0x000006c8 + #define RK0_B23_STB_DBG_INFO_02_RK0_B2_STB_DBG_INFO_02 GENMASK(15, 0) + #define RK0_B23_STB_DBG_INFO_02_RK0_B3_STB_DBG_INFO_02 GENMASK(31, 16) +#define RK0_B23_STB_DBG_INFO_03 0x000006cc + #define RK0_B23_STB_DBG_INFO_03_RK0_B2_STB_DBG_INFO_03 GENMASK(15, 0) + #define RK0_B23_STB_DBG_INFO_03_RK0_B3_STB_DBG_INFO_03 GENMASK(31, 16) +#define RK0_B23_STB_DBG_INFO_04 0x000006d0 + #define RK0_B23_STB_DBG_INFO_04_RK0_B2_STB_DBG_INFO_04 GENMASK(15, 0) + #define RK0_B23_STB_DBG_INFO_04_RK0_B3_STB_DBG_INFO_04 GENMASK(31, 16) +#define RK0_B23_STB_DBG_INFO_05 0x000006d4 + #define RK0_B23_STB_DBG_INFO_05_RK0_B2_STB_DBG_INFO_05 GENMASK(15, 0) + #define RK0_B23_STB_DBG_INFO_05_RK0_B3_STB_DBG_INFO_05 GENMASK(31, 16) +#define RK0_B23_STB_DBG_INFO_06 0x000006d8 + #define RK0_B23_STB_DBG_INFO_06_RK0_B2_STB_DBG_INFO_06 GENMASK(15, 0) + #define RK0_B23_STB_DBG_INFO_06_RK0_B3_STB_DBG_INFO_06 GENMASK(31, 16) +#define RK0_B23_STB_DBG_INFO_07 0x000006dc + #define RK0_B23_STB_DBG_INFO_07_RK0_B2_STB_DBG_INFO_07 GENMASK(15, 0) + #define RK0_B23_STB_DBG_INFO_07_RK0_B3_STB_DBG_INFO_07 GENMASK(31, 16) +#define RK0_B23_STB_DBG_INFO_08 0x000006e0 + #define RK0_B23_STB_DBG_INFO_08_RK0_B2_STB_DBG_INFO_08 GENMASK(15, 0) + #define RK0_B23_STB_DBG_INFO_08_RK0_B3_STB_DBG_INFO_08 GENMASK(31, 16) +#define RK0_B23_STB_DBG_INFO_09 0x000006e4 + #define RK0_B23_STB_DBG_INFO_09_RK0_B2_STB_DBG_INFO_09 GENMASK(15, 0) + #define RK0_B23_STB_DBG_INFO_09_RK0_B3_STB_DBG_INFO_09 GENMASK(31, 16) +#define RK0_B23_STB_DBG_INFO_10 0x000006e8 + #define RK0_B23_STB_DBG_INFO_10_RK0_B2_STB_DBG_INFO_10 GENMASK(15, 0) + #define RK0_B23_STB_DBG_INFO_10_RK0_B3_STB_DBG_INFO_10 GENMASK(31, 16) +#define RK0_B23_STB_DBG_INFO_11 0x000006ec + #define RK0_B23_STB_DBG_INFO_11_RK0_B2_STB_DBG_INFO_11 GENMASK(15, 0) + #define RK0_B23_STB_DBG_INFO_11_RK0_B3_STB_DBG_INFO_11 GENMASK(31, 16) +#define RK0_B23_STB_DBG_INFO_12 0x000006f0 + #define RK0_B23_STB_DBG_INFO_12_RK0_B2_STB_DBG_INFO_12 GENMASK(15, 0) + #define RK0_B23_STB_DBG_INFO_12_RK0_B3_STB_DBG_INFO_12 GENMASK(31, 16) +#define RK0_B23_STB_DBG_INFO_13 0x000006f4 + #define RK0_B23_STB_DBG_INFO_13_RK0_B2_STB_DBG_INFO_13 GENMASK(15, 0) + #define RK0_B23_STB_DBG_INFO_13_RK0_B3_STB_DBG_INFO_13 GENMASK(31, 16) +#define RK0_B23_STB_DBG_INFO_14 0x000006f8 + #define RK0_B23_STB_DBG_INFO_14_RK0_B2_STB_DBG_INFO_14 GENMASK(15, 0) + #define RK0_B23_STB_DBG_INFO_14_RK0_B3_STB_DBG_INFO_14 GENMASK(31, 16) +#define RK0_B23_STB_DBG_INFO_15 0x000006fc + #define RK0_B23_STB_DBG_INFO_15_RK0_B2_STB_DBG_INFO_15 GENMASK(15, 0) + #define RK0_B23_STB_DBG_INFO_15_RK0_B3_STB_DBG_INFO_15 GENMASK(31, 16) +#define RK1_DQSOSC_STATUS 0x00000700 + #define RK1_DQSOSC_STATUS_MR18_REG_RK1 GENMASK(15, 0) + #define RK1_DQSOSC_STATUS_MR19_REG_RK1 GENMASK(31, 16) +#define RK1_DQSOSC_DELTA 0x00000704 + #define RK1_DQSOSC_DELTA_ABS_RK1_DQSOSC_DELTA GENMASK(15, 0) + #define RK1_DQSOSC_DELTA_SIGN_RK1_DQSOSC_DELTA BIT(16) + #define RK1_DQSOSC_DELTA_DQSOSCR_RK1_RESPONSE BIT(17) + #define RK1_DQSOSC_DELTA_H_DQSOSCLSBR_RK1_REQ BIT(18) + #define RK1_DQSOSC_DELTA_DQSOSC_INT_RK1 BIT(19) +#define RK1_DQSOSC_DELTA2 0x00000708 + #define RK1_DQSOSC_DELTA2_ABS_RK1_DQSOSC_B1_DELTA GENMASK(15, 0) + #define RK1_DQSOSC_DELTA2_SIGN_RK1_DQSOSC_B1_DELTA BIT(16) +#define RK1_CURRENT_TX_SETTING1 0x00000710 + #define RK1_CURRENT_TX_SETTING1_REG_TX_DLY_R1DQ0_MOD GENMASK(2, 0) + #define RK1_CURRENT_TX_SETTING1_REG_TX_DLY_R1DQ1_MOD GENMASK(6, 4) + #define RK1_CURRENT_TX_SETTING1_REG_TX_DLY_R1DQ2_MOD GENMASK(10, 8) + #define RK1_CURRENT_TX_SETTING1_REG_TX_DLY_R1DQ3_MOD GENMASK(14, 12) + #define RK1_CURRENT_TX_SETTING1_REG_TX_DLY_R1DQM0_MOD GENMASK(18, 16) + #define RK1_CURRENT_TX_SETTING1_REG_TX_DLY_R1DQM1_MOD GENMASK(22, 20) + #define RK1_CURRENT_TX_SETTING1_REG_TX_DLY_R1DQM2_MOD GENMASK(26, 24) + #define RK1_CURRENT_TX_SETTING1_REG_TX_DLY_R1DQM3_MOD GENMASK(30, 28) +#define RK1_CURRENT_TX_SETTING2 0x00000714 + #define RK1_CURRENT_TX_SETTING2_REG_DLY_R1DQ0_MOD GENMASK(2, 0) + #define RK1_CURRENT_TX_SETTING2_REG_DLY_R1DQ1_MOD GENMASK(6, 4) + #define RK1_CURRENT_TX_SETTING2_REG_DLY_R1DQ2_MOD GENMASK(10, 8) + #define RK1_CURRENT_TX_SETTING2_REG_DLY_R1DQ3_MOD GENMASK(14, 12) + #define RK1_CURRENT_TX_SETTING2_REG_DLY_R1DQM0_MOD GENMASK(18, 16) + #define RK1_CURRENT_TX_SETTING2_REG_DLY_R1DQM1_MOD GENMASK(22, 20) + #define RK1_CURRENT_TX_SETTING2_REG_DLY_R1DQM2_MOD GENMASK(26, 24) + #define RK1_CURRENT_TX_SETTING2_REG_DLY_R1DQM3_MOD GENMASK(30, 28) +#define RK1_CURRENT_TX_SETTING3 0x00000718 + #define RK1_CURRENT_TX_SETTING3_REG_TX_DLY_OEN_R1DQ0_MOD GENMASK(2, 0) + #define RK1_CURRENT_TX_SETTING3_REG_TX_DLY_OEN_R1DQ1_MOD GENMASK(6, 4) + #define RK1_CURRENT_TX_SETTING3_REG_TX_DLY_OEN_R1DQ2_MOD GENMASK(10, 8) + #define RK1_CURRENT_TX_SETTING3_REG_TX_DLY_OEN_R1DQ3_MOD GENMASK(14, 12) + #define RK1_CURRENT_TX_SETTING3_REG_TX_DLY_OEN_R1DQM0_MOD GENMASK(18, 16) + #define RK1_CURRENT_TX_SETTING3_REG_TX_DLY_OEN_R1DQM1_MOD GENMASK(22, 20) + #define RK1_CURRENT_TX_SETTING3_REG_TX_DLY_OEN_R1DQM2_MOD GENMASK(26, 24) + #define RK1_CURRENT_TX_SETTING3_REG_TX_DLY_OEN_R1DQM3_MOD GENMASK(30, 28) +#define RK1_CURRENT_TX_SETTING4 0x0000071c + #define RK1_CURRENT_TX_SETTING4_REG_DLY_OEN_R1DQ0_MOD GENMASK(2, 0) + #define RK1_CURRENT_TX_SETTING4_REG_DLY_OEN_R1DQ1_MOD GENMASK(6, 4) + #define RK1_CURRENT_TX_SETTING4_REG_DLY_OEN_R1DQ2_MOD GENMASK(10, 8) + #define RK1_CURRENT_TX_SETTING4_REG_DLY_OEN_R1DQ3_MOD GENMASK(14, 12) + #define RK1_CURRENT_TX_SETTING4_REG_DLY_OEN_R1DQM0_MOD GENMASK(18, 16) + #define RK1_CURRENT_TX_SETTING4_REG_DLY_OEN_R1DQM1_MOD GENMASK(22, 20) + #define RK1_CURRENT_TX_SETTING4_REG_DLY_OEN_R1DQM2_MOD GENMASK(26, 24) + #define RK1_CURRENT_TX_SETTING4_REG_DLY_OEN_R1DQM3_MOD GENMASK(30, 28) +#define RK1_DUMMY_RD_DATA0 0x00000720 + #define RK1_DUMMY_RD_DATA0_DUMMY_RD_RK1_DATA0 GENMASK(31, 0) +#define RK1_DUMMY_RD_DATA1 0x00000724 + #define RK1_DUMMY_RD_DATA1_DUMMY_RD_RK1_DATA1 GENMASK(31, 0) +#define RK1_DUMMY_RD_DATA2 0x00000728 + #define RK1_DUMMY_RD_DATA2_DUMMY_RD_RK1_DATA2 GENMASK(31, 0) +#define RK1_DUMMY_RD_DATA3 0x0000072c + #define RK1_DUMMY_RD_DATA3_DUMMY_RD_RK1_DATA3 GENMASK(31, 0) +#define RK1_B0_STB_MAX_MIN_DLY 0x00000730 + #define RK1_B0_STB_MAX_MIN_DLY_RK1_B0_STBEN_MIN_DLY GENMASK(11, 0) + #define RK1_B0_STB_MAX_MIN_DLY_RK1_B0_STBEN_MAX_DLY GENMASK(27, 16) +#define RK1_B1_STB_MAX_MIN_DLY 0x00000734 + #define RK1_B1_STB_MAX_MIN_DLY_RK1_B1_STBEN_MIN_DLY GENMASK(11, 0) + #define RK1_B1_STB_MAX_MIN_DLY_RK1_B1_STBEN_MAX_DLY GENMASK(27, 16) +#define RK1_B2_STB_MAX_MIN_DLY 0x00000738 + #define RK1_B2_STB_MAX_MIN_DLY_RK1_B2_STBEN_MIN_DLY GENMASK(11, 0) + #define RK1_B2_STB_MAX_MIN_DLY_RK1_B2_STBEN_MAX_DLY GENMASK(27, 16) +#define RK1_B3_STB_MAX_MIN_DLY 0x0000073c + #define RK1_B3_STB_MAX_MIN_DLY_RK1_B3_STBEN_MIN_DLY GENMASK(11, 0) + #define RK1_B3_STB_MAX_MIN_DLY_RK1_B3_STBEN_MAX_DLY GENMASK(27, 16) +#define RK1_DQSIENDLY 0x00000740 + #define RK1_DQSIENDLY_R1DQS0IENDLY GENMASK(6, 0) + #define RK1_DQSIENDLY_R1DQS1IENDLY GENMASK(14, 8) + #define RK1_DQSIENDLY_R1DQS2IENDLY GENMASK(22, 16) + #define RK1_DQSIENDLY_R1DQS3IENDLY GENMASK(30, 24) +#define RK1_DQSIENUIDLY 0x00000744 + #define RK1_DQSIENUIDLY_R1DQS0IENUIDLY GENMASK(5, 0) + #define RK1_DQSIENUIDLY_R1DQS1IENUIDLY GENMASK(13, 8) + #define RK1_DQSIENUIDLY_R1DQS2IENUIDLY GENMASK(21, 16) + #define RK1_DQSIENUIDLY_R1DQS3IENUIDLY GENMASK(29, 24) +#define RK1_DQSIENUIDLY_P1 0x00000748 + #define RK1_DQSIENUIDLY_P1_R1DQS0IENUIDLY_P1 GENMASK(5, 0) + #define RK1_DQSIENUIDLY_P1_R1DQS1IENUIDLY_P1 GENMASK(13, 8) + #define RK1_DQSIENUIDLY_P1_R1DQS2IENUIDLY_P1 GENMASK(21, 16) + #define RK1_DQSIENUIDLY_P1_R1DQS3IENUIDLY_P1 GENMASK(29, 24) +#define RK1_DQS_STBCALDEC_CNT1 0x00000750 + #define RK1_DQS_STBCALDEC_CNT1_RK1_DQS0_STBCALDEC_CNT GENMASK(15, 0) + #define RK1_DQS_STBCALDEC_CNT1_RK1_DQS1_STBCALDEC_CNT GENMASK(31, 16) +#define RK1_DQS_STBCALDEC_CNT2 0x00000754 + #define RK1_DQS_STBCALDEC_CNT2_RK1_DQS2_STBCALDEC_CNT GENMASK(15, 0) + #define RK1_DQS_STBCALDEC_CNT2_RK1_DQS3_STBCALDEC_CNT GENMASK(31, 16) +#define RK1_DQS_STBCALINC_CNT1 0x00000758 + #define RK1_DQS_STBCALINC_CNT1_RK1_DQS0_STBCALINC_CNT GENMASK(15, 0) + #define RK1_DQS_STBCALINC_CNT1_RK1_DQS1_STBCALINC_CNT GENMASK(31, 16) +#define RK1_DQS_STBCALINC_CNT2 0x0000075c + #define RK1_DQS_STBCALINC_CNT2_RK1_DQS2_STBCALINC_CNT GENMASK(15, 0) + #define RK1_DQS_STBCALINC_CNT2_RK1_DQS3_STBCALINC_CNT GENMASK(31, 16) +#define RK1_PI_DQ_CAL 0x00000760 + #define RK1_PI_DQ_CAL_RK1_ARPI_DQ_B0_CAL GENMASK(5, 0) + #define RK1_PI_DQ_CAL_RK1_ARPI_DQ_B1_CAL GENMASK(13, 8) + #define RK1_PI_DQ_CAL_PI_DQ_ADJ_RK1 GENMASK(21, 16) + #define RK1_PI_DQ_CAL_PI_DQ_ADJ_RK1_FLOW BIT(22) + #define RK1_PI_DQ_CAL_RK1_B0_PI_CHANGE_DBG BIT(23) + #define RK1_PI_DQ_CAL_PI_DQ_ADJ_RK1_B1 GENMASK(29, 24) + #define RK1_PI_DQ_CAL_PI_DQ_ADJ_RK1_B1_FLOW BIT(30) + #define RK1_PI_DQ_CAL_RK1_B1_PI_CHANGE_DBG BIT(31) +#define RK1_DQSG_RETRY_FLAG 0x00000764 + #define RK1_DQSG_RETRY_FLAG_RK1_RETRY_DONE0 BIT(0) + #define RK1_DQSG_RETRY_FLAG_RK1_RETRY_DONE1 BIT(1) + #define RK1_DQSG_RETRY_FLAG_RK1_RETRY_DONE2 BIT(2) + #define RK1_DQSG_RETRY_FLAG_RK1_RETRY_DONE3 BIT(3) + #define RK1_DQSG_RETRY_FLAG_RK1_RETRY_FAIL0 BIT(16) + #define RK1_DQSG_RETRY_FLAG_RK1_RETRY_FAIL1 BIT(17) + #define RK1_DQSG_RETRY_FLAG_RK1_RETRY_FAIL2 BIT(18) + #define RK1_DQSG_RETRY_FLAG_RK1_RETRY_FAIL3 BIT(19) +#define RK1_PI_DQM_CAL 0x00000768 + #define RK1_PI_DQM_CAL_RK1_ARPI_DQM_B0_CAL GENMASK(5, 0) + #define RK1_PI_DQM_CAL_RK1_ARPI_DQM_B1_CAL GENMASK(13, 8) +#define RK1_DQS0_STBCAL_CNT 0x00000770 + #define RK1_DQS0_STBCAL_CNT_R1_DQS0_STBCAL_CNT GENMASK(16, 0) +#define RK1_DQS1_STBCAL_CNT 0x00000774 + #define RK1_DQS1_STBCAL_CNT_R1_DQS1_STBCAL_CNT GENMASK(16, 0) +#define RK1_DQS2_STBCAL_CNT 0x00000778 + #define RK1_DQS2_STBCAL_CNT_R1_DQS2_STBCAL_CNT GENMASK(16, 0) +#define RK1_DQS3_STBCAL_CNT 0x0000077c + #define RK1_DQS3_STBCAL_CNT_R1_DQS3_STBCAL_CNT GENMASK(16, 0) +#define RK1_B01_STB_DBG_INFO_00 0x00000780 + #define RK1_B01_STB_DBG_INFO_00_RK1_B0_STB_DBG_INFO_00 GENMASK(15, 0) + #define RK1_B01_STB_DBG_INFO_00_RK1_B1_STB_DBG_INFO_00 GENMASK(31, 16) +#define RK1_B01_STB_DBG_INFO_01 0x00000784 + #define RK1_B01_STB_DBG_INFO_01_RK1_B0_STB_DBG_INFO_01 GENMASK(15, 0) + #define RK1_B01_STB_DBG_INFO_01_RK1_B1_STB_DBG_INFO_01 GENMASK(31, 16) +#define RK1_B01_STB_DBG_INFO_02 0x00000788 + #define RK1_B01_STB_DBG_INFO_02_RK1_B0_STB_DBG_INFO_02 GENMASK(15, 0) + #define RK1_B01_STB_DBG_INFO_02_RK1_B1_STB_DBG_INFO_02 GENMASK(31, 16) +#define RK1_B01_STB_DBG_INFO_03 0x0000078c + #define RK1_B01_STB_DBG_INFO_03_RK1_B0_STB_DBG_INFO_03 GENMASK(15, 0) + #define RK1_B01_STB_DBG_INFO_03_RK1_B1_STB_DBG_INFO_03 GENMASK(31, 16) +#define RK1_B01_STB_DBG_INFO_04 0x00000790 + #define RK1_B01_STB_DBG_INFO_04_RK1_B0_STB_DBG_INFO_04 GENMASK(15, 0) + #define RK1_B01_STB_DBG_INFO_04_RK1_B1_STB_DBG_INFO_04 GENMASK(31, 16) +#define RK1_B01_STB_DBG_INFO_05 0x00000794 + #define RK1_B01_STB_DBG_INFO_05_RK1_B0_STB_DBG_INFO_05 GENMASK(15, 0) + #define RK1_B01_STB_DBG_INFO_05_RK1_B1_STB_DBG_INFO_05 GENMASK(31, 16) +#define RK1_B01_STB_DBG_INFO_06 0x00000798 + #define RK1_B01_STB_DBG_INFO_06_RK1_B0_STB_DBG_INFO_06 GENMASK(15, 0) + #define RK1_B01_STB_DBG_INFO_06_RK1_B1_STB_DBG_INFO_06 GENMASK(31, 16) +#define RK1_B01_STB_DBG_INFO_07 0x0000079c + #define RK1_B01_STB_DBG_INFO_07_RK1_B0_STB_DBG_INFO_07 GENMASK(15, 0) + #define RK1_B01_STB_DBG_INFO_07_RK1_B1_STB_DBG_INFO_07 GENMASK(31, 16) +#define RK1_B01_STB_DBG_INFO_08 0x000007a0 + #define RK1_B01_STB_DBG_INFO_08_RK1_B0_STB_DBG_INFO_08 GENMASK(15, 0) + #define RK1_B01_STB_DBG_INFO_08_RK1_B1_STB_DBG_INFO_08 GENMASK(31, 16) +#define RK1_B01_STB_DBG_INFO_09 0x000007a4 + #define RK1_B01_STB_DBG_INFO_09_RK1_B0_STB_DBG_INFO_09 GENMASK(15, 0) + #define RK1_B01_STB_DBG_INFO_09_RK1_B1_STB_DBG_INFO_09 GENMASK(31, 16) +#define RK1_B01_STB_DBG_INFO_10 0x000007a8 + #define RK1_B01_STB_DBG_INFO_10_RK1_B0_STB_DBG_INFO_10 GENMASK(15, 0) + #define RK1_B01_STB_DBG_INFO_10_RK1_B1_STB_DBG_INFO_10 GENMASK(31, 16) +#define RK1_B01_STB_DBG_INFO_11 0x000007ac + #define RK1_B01_STB_DBG_INFO_11_RK1_B0_STB_DBG_INFO_11 GENMASK(15, 0) + #define RK1_B01_STB_DBG_INFO_11_RK1_B1_STB_DBG_INFO_11 GENMASK(31, 16) +#define RK1_B01_STB_DBG_INFO_12 0x000007b0 + #define RK1_B01_STB_DBG_INFO_12_RK1_B0_STB_DBG_INFO_12 GENMASK(15, 0) + #define RK1_B01_STB_DBG_INFO_12_RK1_B1_STB_DBG_INFO_12 GENMASK(31, 16) +#define RK1_B01_STB_DBG_INFO_13 0x000007b4 + #define RK1_B01_STB_DBG_INFO_13_RK1_B0_STB_DBG_INFO_13 GENMASK(15, 0) + #define RK1_B01_STB_DBG_INFO_13_RK1_B1_STB_DBG_INFO_13 GENMASK(31, 16) +#define RK1_B01_STB_DBG_INFO_14 0x000007b8 + #define RK1_B01_STB_DBG_INFO_14_RK1_B0_STB_DBG_INFO_14 GENMASK(15, 0) + #define RK1_B01_STB_DBG_INFO_14_RK1_B1_STB_DBG_INFO_14 GENMASK(31, 16) +#define RK1_B01_STB_DBG_INFO_15 0x000007bc + #define RK1_B01_STB_DBG_INFO_15_RK1_B0_STB_DBG_INFO_15 GENMASK(15, 0) + #define RK1_B01_STB_DBG_INFO_15_RK1_B1_STB_DBG_INFO_15 GENMASK(31, 16) +#define RK1_B23_STB_DBG_INFO_00 0x000007c0 + #define RK1_B23_STB_DBG_INFO_00_RK1_B2_STB_DBG_INFO_00 GENMASK(15, 0) + #define RK1_B23_STB_DBG_INFO_00_RK1_B3_STB_DBG_INFO_00 GENMASK(31, 16) +#define RK1_B23_STB_DBG_INFO_01 0x000007c4 + #define RK1_B23_STB_DBG_INFO_01_RK1_B2_STB_DBG_INFO_01 GENMASK(15, 0) + #define RK1_B23_STB_DBG_INFO_01_RK1_B3_STB_DBG_INFO_01 GENMASK(31, 16) +#define RK1_B23_STB_DBG_INFO_02 0x000007c8 + #define RK1_B23_STB_DBG_INFO_02_RK1_B2_STB_DBG_INFO_02 GENMASK(15, 0) + #define RK1_B23_STB_DBG_INFO_02_RK1_B3_STB_DBG_INFO_02 GENMASK(31, 16) +#define RK1_B23_STB_DBG_INFO_03 0x000007cc + #define RK1_B23_STB_DBG_INFO_03_RK1_B2_STB_DBG_INFO_03 GENMASK(15, 0) + #define RK1_B23_STB_DBG_INFO_03_RK1_B3_STB_DBG_INFO_03 GENMASK(31, 16) +#define RK1_B23_STB_DBG_INFO_04 0x000007d0 + #define RK1_B23_STB_DBG_INFO_04_RK1_B2_STB_DBG_INFO_04 GENMASK(15, 0) + #define RK1_B23_STB_DBG_INFO_04_RK1_B3_STB_DBG_INFO_04 GENMASK(31, 16) +#define RK1_B23_STB_DBG_INFO_05 0x000007d4 + #define RK1_B23_STB_DBG_INFO_05_RK1_B2_STB_DBG_INFO_05 GENMASK(15, 0) + #define RK1_B23_STB_DBG_INFO_05_RK1_B3_STB_DBG_INFO_05 GENMASK(31, 16) +#define RK1_B23_STB_DBG_INFO_06 0x000007d8 + #define RK1_B23_STB_DBG_INFO_06_RK1_B2_STB_DBG_INFO_06 GENMASK(15, 0) + #define RK1_B23_STB_DBG_INFO_06_RK1_B3_STB_DBG_INFO_06 GENMASK(31, 16) +#define RK1_B23_STB_DBG_INFO_07 0x000007dc + #define RK1_B23_STB_DBG_INFO_07_RK1_B2_STB_DBG_INFO_07 GENMASK(15, 0) + #define RK1_B23_STB_DBG_INFO_07_RK1_B3_STB_DBG_INFO_07 GENMASK(31, 16) +#define RK1_B23_STB_DBG_INFO_08 0x000007e0 + #define RK1_B23_STB_DBG_INFO_08_RK1_B2_STB_DBG_INFO_08 GENMASK(15, 0) + #define RK1_B23_STB_DBG_INFO_08_RK1_B3_STB_DBG_INFO_08 GENMASK(31, 16) +#define RK1_B23_STB_DBG_INFO_09 0x000007e4 + #define RK1_B23_STB_DBG_INFO_09_RK1_B2_STB_DBG_INFO_09 GENMASK(15, 0) + #define RK1_B23_STB_DBG_INFO_09_RK1_B3_STB_DBG_INFO_09 GENMASK(31, 16) +#define RK1_B23_STB_DBG_INFO_10 0x000007e8 + #define RK1_B23_STB_DBG_INFO_10_RK1_B2_STB_DBG_INFO_10 GENMASK(15, 0) + #define RK1_B23_STB_DBG_INFO_10_RK1_B3_STB_DBG_INFO_10 GENMASK(31, 16) +#define RK1_B23_STB_DBG_INFO_11 0x000007ec + #define RK1_B23_STB_DBG_INFO_11_RK1_B2_STB_DBG_INFO_11 GENMASK(15, 0) + #define RK1_B23_STB_DBG_INFO_11_RK1_B3_STB_DBG_INFO_11 GENMASK(31, 16) +#define RK1_B23_STB_DBG_INFO_12 0x000007f0 + #define RK1_B23_STB_DBG_INFO_12_RK1_B2_STB_DBG_INFO_12 GENMASK(15, 0) + #define RK1_B23_STB_DBG_INFO_12_RK1_B3_STB_DBG_INFO_12 GENMASK(31, 16) +#define RK1_B23_STB_DBG_INFO_13 0x000007f4 + #define RK1_B23_STB_DBG_INFO_13_RK1_B2_STB_DBG_INFO_13 GENMASK(15, 0) + #define RK1_B23_STB_DBG_INFO_13_RK1_B3_STB_DBG_INFO_13 GENMASK(31, 16) +#define RK1_B23_STB_DBG_INFO_14 0x000007f8 + #define RK1_B23_STB_DBG_INFO_14_RK1_B2_STB_DBG_INFO_14 GENMASK(15, 0) + #define RK1_B23_STB_DBG_INFO_14_RK1_B3_STB_DBG_INFO_14 GENMASK(31, 16) +#define RK1_B23_STB_DBG_INFO_15 0x000007fc + #define RK1_B23_STB_DBG_INFO_15_RK1_B2_STB_DBG_INFO_15 GENMASK(15, 0) + #define RK1_B23_STB_DBG_INFO_15_RK1_B3_STB_DBG_INFO_15 GENMASK(31, 16) +#define RK2_DQSOSC_STATUS 0x00000800 + #define RK2_DQSOSC_STATUS_MR18_REG_RK2 GENMASK(15, 0) + #define RK2_DQSOSC_STATUS_MR19_REG_RK2 GENMASK(31, 16) +#define RK2_DQSOSC_DELTA 0x00000804 + #define RK2_DQSOSC_DELTA_ABS_RK2_DQSOSC_DELTA GENMASK(15, 0) + #define RK2_DQSOSC_DELTA_SIGN_RK2_DQSOSC_DELTA BIT(16) + #define RK2_DQSOSC_DELTA_DQSOSCR_RK2_RESPONSE BIT(17) + #define RK2_DQSOSC_DELTA_H_DQSOSCLSBR_RK2_REQ BIT(18) + #define RK2_DQSOSC_DELTA_DQSOSC_INT_RK2 BIT(19) +#define RK2_DQSOSC_DELTA2 0x00000808 + #define RK2_DQSOSC_DELTA2_ABS_RK2_DQSOSC_B1_DELTA GENMASK(15, 0) + #define RK2_DQSOSC_DELTA2_SIGN_RK2_DQSOSC_B1_DELTA BIT(16) +#define RK2_CURRENT_TX_SETTING1 0x00000810 + #define RK2_CURRENT_TX_SETTING1_REG_TX_DLY_R2DQ0_MOD GENMASK(2, 0) + #define RK2_CURRENT_TX_SETTING1_REG_TX_DLY_R2DQ1_MOD GENMASK(6, 4) + #define RK2_CURRENT_TX_SETTING1_REG_TX_DLY_R2DQ2_MOD GENMASK(10, 8) + #define RK2_CURRENT_TX_SETTING1_REG_TX_DLY_R2DQ3_MOD GENMASK(14, 12) + #define RK2_CURRENT_TX_SETTING1_REG_TX_DLY_R2DQM0_MOD GENMASK(18, 16) + #define RK2_CURRENT_TX_SETTING1_REG_TX_DLY_R2DQM1_MOD GENMASK(22, 20) + #define RK2_CURRENT_TX_SETTING1_REG_TX_DLY_R2DQM2_MOD GENMASK(26, 24) + #define RK2_CURRENT_TX_SETTING1_REG_TX_DLY_R2DQM3_MOD GENMASK(30, 28) +#define RK2_CURRENT_TX_SETTING2 0x00000814 + #define RK2_CURRENT_TX_SETTING2_REG_DLY_R2DQ0_MOD GENMASK(2, 0) + #define RK2_CURRENT_TX_SETTING2_REG_DLY_R2DQ1_MOD GENMASK(6, 4) + #define RK2_CURRENT_TX_SETTING2_REG_DLY_R2DQ2_MOD GENMASK(10, 8) + #define RK2_CURRENT_TX_SETTING2_REG_DLY_R2DQ3_MOD GENMASK(14, 12) + #define RK2_CURRENT_TX_SETTING2_REG_DLY_R2DQM0_MOD GENMASK(18, 16) + #define RK2_CURRENT_TX_SETTING2_REG_DLY_R2DQM1_MOD GENMASK(22, 20) + #define RK2_CURRENT_TX_SETTING2_REG_DLY_R2DQM2_MOD GENMASK(26, 24) + #define RK2_CURRENT_TX_SETTING2_REG_DLY_R2DQM3_MOD GENMASK(30, 28) +#define RK2_CURRENT_TX_SETTING3 0x00000818 + #define RK2_CURRENT_TX_SETTING3_REG_TX_DLY_OEN_R2DQ0_MOD GENMASK(2, 0) + #define RK2_CURRENT_TX_SETTING3_REG_TX_DLY_OEN_R2DQ1_MOD GENMASK(6, 4) + #define RK2_CURRENT_TX_SETTING3_REG_TX_DLY_OEN_R2DQ2_MOD GENMASK(10, 8) + #define RK2_CURRENT_TX_SETTING3_REG_TX_DLY_OEN_R2DQ3_MOD GENMASK(14, 12) + #define RK2_CURRENT_TX_SETTING3_REG_TX_DLY_OEN_R2DQM0_MOD GENMASK(18, 16) + #define RK2_CURRENT_TX_SETTING3_REG_TX_DLY_OEN_R2DQM1_MOD GENMASK(22, 20) + #define RK2_CURRENT_TX_SETTING3_REG_TX_DLY_OEN_R2DQM2_MOD GENMASK(26, 24) + #define RK2_CURRENT_TX_SETTING3_REG_TX_DLY_OEN_R2DQM3_MOD GENMASK(30, 28) +#define RK2_CURRENT_TX_SETTING4 0x0000081c + #define RK2_CURRENT_TX_SETTING4_REG_DLY_OEN_R2DQ0_MOD GENMASK(2, 0) + #define RK2_CURRENT_TX_SETTING4_REG_DLY_OEN_R2DQ1_MOD GENMASK(6, 4) + #define RK2_CURRENT_TX_SETTING4_REG_DLY_OEN_R2DQ2_MOD GENMASK(10, 8) + #define RK2_CURRENT_TX_SETTING4_REG_DLY_OEN_R2DQ3_MOD GENMASK(14, 12) + #define RK2_CURRENT_TX_SETTING4_REG_DLY_OEN_R2DQM0_MOD GENMASK(18, 16) + #define RK2_CURRENT_TX_SETTING4_REG_DLY_OEN_R2DQM1_MOD GENMASK(22, 20) + #define RK2_CURRENT_TX_SETTING4_REG_DLY_OEN_R2DQM2_MOD GENMASK(26, 24) + #define RK2_CURRENT_TX_SETTING4_REG_DLY_OEN_R2DQM3_MOD GENMASK(30, 28) +#define RK2_DUMMY_RD_DATA0 0x00000820 + #define RK2_DUMMY_RD_DATA0_DUMMY_RD_RK2_DATA0 GENMASK(31, 0) +#define RK2_DUMMY_RD_DATA1 0x00000824 + #define RK2_DUMMY_RD_DATA1_DUMMY_RD_RK2_DATA1 GENMASK(31, 0) +#define RK2_DUMMY_RD_DATA2 0x00000828 + #define RK2_DUMMY_RD_DATA2_DUMMY_RD_RK2_DATA2 GENMASK(31, 0) +#define RK2_DUMMY_RD_DATA3 0x0000082c + #define RK2_DUMMY_RD_DATA3_DUMMY_RD_RK2_DATA3 GENMASK(31, 0) +#define RK2_B0_STB_MAX_MIN_DLY 0x00000830 + #define RK2_B0_STB_MAX_MIN_DLY_RK2_B0_STBEN_MIN_DLY GENMASK(11, 0) + #define RK2_B0_STB_MAX_MIN_DLY_RK2_B0_STBEN_MAX_DLY GENMASK(27, 16) +#define RK2_B1_STB_MAX_MIN_DLY 0x00000834 + #define RK2_B1_STB_MAX_MIN_DLY_RK2_B1_STBEN_MIN_DLY GENMASK(11, 0) + #define RK2_B1_STB_MAX_MIN_DLY_RK2_B1_STBEN_MAX_DLY GENMASK(27, 16) +#define RK2_B2_STB_MAX_MIN_DLY 0x00000838 + #define RK2_B2_STB_MAX_MIN_DLY_RK2_B2_STBEN_MIN_DLY GENMASK(11, 0) + #define RK2_B2_STB_MAX_MIN_DLY_RK2_B2_STBEN_MAX_DLY GENMASK(27, 16) +#define RK2_B3_STB_MAX_MIN_DLY 0x0000083c + #define RK2_B3_STB_MAX_MIN_DLY_RK2_B3_STBEN_MIN_DLY GENMASK(11, 0) + #define RK2_B3_STB_MAX_MIN_DLY_RK2_B3_STBEN_MAX_DLY GENMASK(27, 16) +#define RK2_DQSIENDLY 0x00000840 + #define RK2_DQSIENDLY_R2DQS0IENDLY GENMASK(6, 0) + #define RK2_DQSIENDLY_R2DQS1IENDLY GENMASK(14, 8) + #define RK2_DQSIENDLY_R2DQS2IENDLY GENMASK(22, 16) + #define RK2_DQSIENDLY_R2DQS3IENDLY GENMASK(30, 24) +#define RK2_DQSIENUIDLY 0x00000844 + #define RK2_DQSIENUIDLY_R2DQS0IENUIDLY GENMASK(5, 0) + #define RK2_DQSIENUIDLY_R2DQS1IENUIDLY GENMASK(13, 8) + #define RK2_DQSIENUIDLY_R2DQS2IENUIDLY GENMASK(21, 16) + #define RK2_DQSIENUIDLY_R2DQS3IENUIDLY GENMASK(29, 24) +#define RK2_DQSIENUIDLY_P1 0x00000848 + #define RK2_DQSIENUIDLY_P1_R2DQS0IENUIDLY_P1 GENMASK(5, 0) + #define RK2_DQSIENUIDLY_P1_R2DQS1IENUIDLY_P1 GENMASK(13, 8) + #define RK2_DQSIENUIDLY_P1_R2DQS2IENUIDLY_P1 GENMASK(21, 16) + #define RK2_DQSIENUIDLY_P1_R2DQS3IENUIDLY_P1 GENMASK(29, 24) +#define RK2_DQS_STBCALDEC_CNT1 0x00000850 + #define RK2_DQS_STBCALDEC_CNT1_RK2_DQS0_STBCALDEC_CNT GENMASK(15, 0) + #define RK2_DQS_STBCALDEC_CNT1_RK2_DQS1_STBCALDEC_CNT GENMASK(31, 16) +#define RK2_DQS_STBCALDEC_CNT2 0x00000854 + #define RK2_DQS_STBCALDEC_CNT2_RK2_DQS2_STBCALDEC_CNT GENMASK(15, 0) + #define RK2_DQS_STBCALDEC_CNT2_RK2_DQS3_STBCALDEC_CNT GENMASK(31, 16) +#define RK2_DQS_STBCALINC_CNT1 0x00000858 + #define RK2_DQS_STBCALINC_CNT1_RK2_DQS0_STBCALINC_CNT GENMASK(15, 0) + #define RK2_DQS_STBCALINC_CNT1_RK2_DQS1_STBCALINC_CNT GENMASK(31, 16) +#define RK2_DQS_STBCALINC_CNT2 0x0000085c + #define RK2_DQS_STBCALINC_CNT2_RK2_DQS2_STBCALINC_CNT GENMASK(15, 0) + #define RK2_DQS_STBCALINC_CNT2_RK2_DQS3_STBCALINC_CNT GENMASK(31, 16) +#define RK2_PI_DQ_CAL 0x00000860 + #define RK2_PI_DQ_CAL_RK2_ARPI_DQ_B0_CAL GENMASK(5, 0) + #define RK2_PI_DQ_CAL_RK2_ARPI_DQ_B1_CAL GENMASK(13, 8) + #define RK2_PI_DQ_CAL_PI_DQ_ADJ_RK2 GENMASK(21, 16) + #define RK2_PI_DQ_CAL_PI_DQ_ADJ_RK2_OVERFLOW BIT(22) + #define RK2_PI_DQ_CAL_PI_DQ_ADJ_RK2_B1 GENMASK(29, 24) + #define RK2_PI_DQ_CAL_PI_DQ_ADJ_RK2_B1_OVERFLOW BIT(30) +#define RK2_DQSG_RETRY_FLAG 0x00000864 + #define RK2_DQSG_RETRY_FLAG_RK2_RETRY_DONE0 BIT(0) + #define RK2_DQSG_RETRY_FLAG_RK2_RETRY_DONE1 BIT(1) + #define RK2_DQSG_RETRY_FLAG_RK2_RETRY_DONE2 BIT(2) + #define RK2_DQSG_RETRY_FLAG_RK2_RETRY_DONE3 BIT(3) + #define RK2_DQSG_RETRY_FLAG_RK2_RETRY_FAIL0 BIT(16) + #define RK2_DQSG_RETRY_FLAG_RK2_RETRY_FAIL1 BIT(17) + #define RK2_DQSG_RETRY_FLAG_RK2_RETRY_FAIL2 BIT(18) + #define RK2_DQSG_RETRY_FLAG_RK2_RETRY_FAIL3 BIT(19) +#define RK2_PI_DQM_CAL 0x00000868 + #define RK2_PI_DQM_CAL_RK2_ARPI_DQM_B0_CAL GENMASK(5, 0) + #define RK2_PI_DQM_CAL_RK2_ARPI_DQM_B1_CAL GENMASK(13, 8) +#define RK2_DQS0_STBCAL_CNT 0x00000870 + #define RK2_DQS0_STBCAL_CNT_R2_DQS0_STBCAL_CNT GENMASK(16, 0) +#define RK2_DQS1_STBCAL_CNT 0x00000874 + #define RK2_DQS1_STBCAL_CNT_R2_DQS1_STBCAL_CNT GENMASK(16, 0) +#define RK2_DQS2_STBCAL_CNT 0x00000878 + #define RK2_DQS2_STBCAL_CNT_R2_DQS2_STBCAL_CNT GENMASK(16, 0) +#define RK2_DQS3_STBCAL_CNT 0x0000087c + #define RK2_DQS3_STBCAL_CNT_R2_DQS3_STBCAL_CNT GENMASK(16, 0) +#define RK2_B01_STB_DBG_INFO_00 0x00000880 + #define RK2_B01_STB_DBG_INFO_00_RK2_B0_STB_DBG_INFO_00 GENMASK(15, 0) + #define RK2_B01_STB_DBG_INFO_00_RK2_B1_STB_DBG_INFO_00 GENMASK(31, 16) +#define RK2_B01_STB_DBG_INFO_01 0x00000884 + #define RK2_B01_STB_DBG_INFO_01_RK2_B0_STB_DBG_INFO_01 GENMASK(15, 0) + #define RK2_B01_STB_DBG_INFO_01_RK2_B1_STB_DBG_INFO_01 GENMASK(31, 16) +#define RK2_B01_STB_DBG_INFO_02 0x00000888 + #define RK2_B01_STB_DBG_INFO_02_RK2_B0_STB_DBG_INFO_02 GENMASK(15, 0) + #define RK2_B01_STB_DBG_INFO_02_RK2_B1_STB_DBG_INFO_02 GENMASK(31, 16) +#define RK2_B01_STB_DBG_INFO_03 0x0000088c + #define RK2_B01_STB_DBG_INFO_03_RK2_B0_STB_DBG_INFO_03 GENMASK(15, 0) + #define RK2_B01_STB_DBG_INFO_03_RK2_B1_STB_DBG_INFO_03 GENMASK(31, 16) +#define RK2_B01_STB_DBG_INFO_04 0x00000890 + #define RK2_B01_STB_DBG_INFO_04_RK2_B0_STB_DBG_INFO_04 GENMASK(15, 0) + #define RK2_B01_STB_DBG_INFO_04_RK2_B1_STB_DBG_INFO_04 GENMASK(31, 16) +#define RK2_B01_STB_DBG_INFO_05 0x00000894 + #define RK2_B01_STB_DBG_INFO_05_RK2_B0_STB_DBG_INFO_05 GENMASK(15, 0) + #define RK2_B01_STB_DBG_INFO_05_RK2_B1_STB_DBG_INFO_05 GENMASK(31, 16) +#define RK2_B01_STB_DBG_INFO_06 0x00000898 + #define RK2_B01_STB_DBG_INFO_06_RK2_B0_STB_DBG_INFO_06 GENMASK(15, 0) + #define RK2_B01_STB_DBG_INFO_06_RK2_B1_STB_DBG_INFO_06 GENMASK(31, 16) +#define RK2_B01_STB_DBG_INFO_07 0x0000089c + #define RK2_B01_STB_DBG_INFO_07_RK2_B0_STB_DBG_INFO_07 GENMASK(15, 0) + #define RK2_B01_STB_DBG_INFO_07_RK2_B1_STB_DBG_INFO_07 GENMASK(31, 16) +#define RK2_B01_STB_DBG_INFO_08 0x000008a0 + #define RK2_B01_STB_DBG_INFO_08_RK2_B0_STB_DBG_INFO_08 GENMASK(15, 0) + #define RK2_B01_STB_DBG_INFO_08_RK2_B1_STB_DBG_INFO_08 GENMASK(31, 16) +#define RK2_B01_STB_DBG_INFO_09 0x000008a4 + #define RK2_B01_STB_DBG_INFO_09_RK2_B0_STB_DBG_INFO_09 GENMASK(15, 0) + #define RK2_B01_STB_DBG_INFO_09_RK2_B1_STB_DBG_INFO_09 GENMASK(31, 16) +#define RK2_B01_STB_DBG_INFO_10 0x000008a8 + #define RK2_B01_STB_DBG_INFO_10_RK2_B0_STB_DBG_INFO_10 GENMASK(15, 0) + #define RK2_B01_STB_DBG_INFO_10_RK2_B1_STB_DBG_INFO_10 GENMASK(31, 16) +#define RK2_B01_STB_DBG_INFO_11 0x000008ac + #define RK2_B01_STB_DBG_INFO_11_RK2_B0_STB_DBG_INFO_11 GENMASK(15, 0) + #define RK2_B01_STB_DBG_INFO_11_RK2_B1_STB_DBG_INFO_11 GENMASK(31, 16) +#define RK2_B01_STB_DBG_INFO_12 0x000008b0 + #define RK2_B01_STB_DBG_INFO_12_RK2_B0_STB_DBG_INFO_12 GENMASK(15, 0) + #define RK2_B01_STB_DBG_INFO_12_RK2_B1_STB_DBG_INFO_12 GENMASK(31, 16) +#define RK2_B01_STB_DBG_INFO_13 0x000008b4 + #define RK2_B01_STB_DBG_INFO_13_RK2_B0_STB_DBG_INFO_13 GENMASK(15, 0) + #define RK2_B01_STB_DBG_INFO_13_RK2_B1_STB_DBG_INFO_13 GENMASK(31, 16) +#define RK2_B01_STB_DBG_INFO_14 0x000008b8 + #define RK2_B01_STB_DBG_INFO_14_RK2_B0_STB_DBG_INFO_14 GENMASK(15, 0) + #define RK2_B01_STB_DBG_INFO_14_RK2_B1_STB_DBG_INFO_14 GENMASK(31, 16) +#define RK2_B01_STB_DBG_INFO_15 0x000008bc + #define RK2_B01_STB_DBG_INFO_15_RK2_B0_STB_DBG_INFO_15 GENMASK(15, 0) + #define RK2_B01_STB_DBG_INFO_15_RK2_B1_STB_DBG_INFO_15 GENMASK(31, 16) +#define RK2_B23_STB_DBG_INFO_00 0x000008c0 + #define RK2_B23_STB_DBG_INFO_00_RK2_B2_STB_DBG_INFO_00 GENMASK(15, 0) + #define RK2_B23_STB_DBG_INFO_00_RK2_B3_STB_DBG_INFO_00 GENMASK(31, 16) +#define RK2_B23_STB_DBG_INFO_01 0x000008c4 + #define RK2_B23_STB_DBG_INFO_01_RK2_B2_STB_DBG_INFO_01 GENMASK(15, 0) + #define RK2_B23_STB_DBG_INFO_01_RK2_B3_STB_DBG_INFO_01 GENMASK(31, 16) +#define RK2_B23_STB_DBG_INFO_02 0x000008c8 + #define RK2_B23_STB_DBG_INFO_02_RK2_B2_STB_DBG_INFO_02 GENMASK(15, 0) + #define RK2_B23_STB_DBG_INFO_02_RK2_B3_STB_DBG_INFO_02 GENMASK(31, 16) +#define RK2_B23_STB_DBG_INFO_03 0x000008cc + #define RK2_B23_STB_DBG_INFO_03_RK2_B2_STB_DBG_INFO_03 GENMASK(15, 0) + #define RK2_B23_STB_DBG_INFO_03_RK2_B3_STB_DBG_INFO_03 GENMASK(31, 16) +#define RK2_B23_STB_DBG_INFO_04 0x000008d0 + #define RK2_B23_STB_DBG_INFO_04_RK2_B2_STB_DBG_INFO_04 GENMASK(15, 0) + #define RK2_B23_STB_DBG_INFO_04_RK2_B3_STB_DBG_INFO_04 GENMASK(31, 16) +#define RK2_B23_STB_DBG_INFO_05 0x000008d4 + #define RK2_B23_STB_DBG_INFO_05_RK2_B2_STB_DBG_INFO_05 GENMASK(15, 0) + #define RK2_B23_STB_DBG_INFO_05_RK2_B3_STB_DBG_INFO_05 GENMASK(31, 16) +#define RK2_B23_STB_DBG_INFO_06 0x000008d8 + #define RK2_B23_STB_DBG_INFO_06_RK2_B2_STB_DBG_INFO_06 GENMASK(15, 0) + #define RK2_B23_STB_DBG_INFO_06_RK2_B3_STB_DBG_INFO_06 GENMASK(31, 16) +#define RK2_B23_STB_DBG_INFO_07 0x000008dc + #define RK2_B23_STB_DBG_INFO_07_RK2_B2_STB_DBG_INFO_07 GENMASK(15, 0) + #define RK2_B23_STB_DBG_INFO_07_RK2_B3_STB_DBG_INFO_07 GENMASK(31, 16) +#define RK2_B23_STB_DBG_INFO_08 0x000008e0 + #define RK2_B23_STB_DBG_INFO_08_RK2_B2_STB_DBG_INFO_08 GENMASK(15, 0) + #define RK2_B23_STB_DBG_INFO_08_RK2_B3_STB_DBG_INFO_08 GENMASK(31, 16) +#define RK2_B23_STB_DBG_INFO_09 0x000008e4 + #define RK2_B23_STB_DBG_INFO_09_RK2_B2_STB_DBG_INFO_09 GENMASK(15, 0) + #define RK2_B23_STB_DBG_INFO_09_RK2_B3_STB_DBG_INFO_09 GENMASK(31, 16) +#define RK2_B23_STB_DBG_INFO_10 0x000008e8 + #define RK2_B23_STB_DBG_INFO_10_RK2_B2_STB_DBG_INFO_10 GENMASK(15, 0) + #define RK2_B23_STB_DBG_INFO_10_RK2_B3_STB_DBG_INFO_10 GENMASK(31, 16) +#define RK2_B23_STB_DBG_INFO_11 0x000008ec + #define RK2_B23_STB_DBG_INFO_11_RK2_B2_STB_DBG_INFO_11 GENMASK(15, 0) + #define RK2_B23_STB_DBG_INFO_11_RK2_B3_STB_DBG_INFO_11 GENMASK(31, 16) +#define RK2_B23_STB_DBG_INFO_12 0x000008f0 + #define RK2_B23_STB_DBG_INFO_12_RK2_B2_STB_DBG_INFO_12 GENMASK(15, 0) + #define RK2_B23_STB_DBG_INFO_12_RK2_B3_STB_DBG_INFO_12 GENMASK(31, 16) +#define RK2_B23_STB_DBG_INFO_13 0x000008f4 + #define RK2_B23_STB_DBG_INFO_13_RK2_B2_STB_DBG_INFO_13 GENMASK(15, 0) + #define RK2_B23_STB_DBG_INFO_13_RK2_B3_STB_DBG_INFO_13 GENMASK(31, 16) +#define RK2_B23_STB_DBG_INFO_14 0x000008f8 + #define RK2_B23_STB_DBG_INFO_14_RK2_B2_STB_DBG_INFO_14 GENMASK(15, 0) + #define RK2_B23_STB_DBG_INFO_14_RK2_B3_STB_DBG_INFO_14 GENMASK(31, 16) +#define RK2_B23_STB_DBG_INFO_15 0x000008fc + #define RK2_B23_STB_DBG_INFO_15_RK2_B2_STB_DBG_INFO_15 GENMASK(15, 0) + #define RK2_B23_STB_DBG_INFO_15_RK2_B3_STB_DBG_INFO_15 GENMASK(31, 16) +#define DVFS_DBG0 0x00000c00 + #define DVFS_DBG0_CUT_PHY_ST_SHU_MASK GENMASK(18, 0) +#define DVFS_DBG1 0x00000c04 + #define DVFS_DBG1_PLL_SEL_MASK BIT(0) + #define DVFS_DBG1_MPDIV_SHU_GP_MASK GENMASK(6, 4) + #define DVFS_DBG1_PICG_SHUFFLE_MASK BIT(8) + #define DVFS_DBG1_SHUFFLE_PHY_STATE_START_MASK BIT(9) + #define DVFS_DBG1_SHUFFLE_PHY_STATE_DONE_MASK BIT(10) + #define DVFS_DBG1_SHUFFLE_PERIOD_MASK BIT(11) + +#endif /*__DRAMC_CH0_NAO_REG_H__*/ diff --git a/src/vendorcode/mediatek/mt8192/include/dramc_ch0_reg.h b/src/vendorcode/mediatek/mt8192/include/dramc_ch0_reg.h new file mode 100644 index 000000000000..4e9eae40e9da --- /dev/null +++ b/src/vendorcode/mediatek/mt8192/include/dramc_ch0_reg.h @@ -0,0 +1,3922 @@ +/* SPDX-License-Identifier: BSD-3-Clause */ + +#ifndef __DRAMC_CH0_REG_H__ +#define __DRAMC_CH0_REG_H__ + +/* ----------------- Register Definitions ------------------- */ +#define DDRCONF0 0x00000000 + #define DDRCONF0_RDATRST BIT(0) + #define DDRCONF0_DMSW_RST BIT(1) + #define DDRCONF0_WDT_DBG_RST BIT(2) + #define DDRCONF0_FIFOLEN GENMASK(5, 4) + #define DDRCONF0_DRAMEN BIT(7) + #define DDRCONF0_RDQSIEN BIT(8) + #define DDRCONF0_DQSGCGM BIT(9) + #define DDRCONF0_APBL2 BIT(10) + #define DDRCONF0_BG4EN BIT(11) + #define DDRCONF0_BK8EN BIT(12) + #define DDRCONF0_BC4OTF_OPT BIT(13) + #define DDRCONF0_AG0MWR BIT(14) + #define DDRCONF0_BC4OTF BIT(15) + #define DDRCONF0_GDDR3RST BIT(16) + #define DDRCONF0_DM16BPHSEL BIT(17) + #define DDRCONF0_DM16BITSWAP BIT(18) + #define DDRCONF0_DQ4BMUX BIT(19) + #define DDRCONF0_DM64BITEN BIT(20) + #define DDRCONF0_DM16BITFULL BIT(21) + #define DDRCONF0_DM4TO1MODE BIT(22) + #define DDRCONF0_GDDR3EN BIT(23) + #define DDRCONF0_LPDDR2EN BIT(24) + #define DDRCONF0_LPDDR3EN BIT(25) + #define DDRCONF0_LPDDR4EN BIT(26) + #define DDRCONF0_LPDDR2_NO_INT BIT(27) + #define DDRCONF0_DDR2EN BIT(28) + #define DDRCONF0_DDR3EN BIT(29) + #define DDRCONF0_DDR4EN BIT(30) + #define DDRCONF0_DRAMC_SW_RST BIT(31) +#define DRAMCTRL 0x00000004 + #define DRAMCTRL_CTOREQ_HPRI_OPT BIT(0) + #define DRAMCTRL_ADRDECEN_TARKMODE BIT(1) + #define DRAMCTRL_ADRDECEN BIT(2) + #define DRAMCTRL_ADRBIT3DEC BIT(3) + #define DRAMCTRL_TMRR2WDIS BIT(4) + #define DRAMCTRL_RANK_ASYM BIT(7) + #define DRAMCTRL_WDATRGO BIT(8) + #define DRAMCTRL_CLKWITRFC BIT(9) + #define DRAMCTRL_CHKFORPRE BIT(10) + #define DRAMCTRL_ASYNCEN BIT(12) + #define DRAMCTRL_DYNMWREN BIT(13) + #define DRAMCTRL_ALEBLOCK BIT(14) + #define DRAMCTRL_TMRRICHKDIS BIT(15) + #define DRAMCTRL_DMRCDRSV BIT(16) + #define DRAMCTRL_TMRRIBYRK_DIS BIT(17) + #define DRAMCTRL_ZQCALL BIT(18) + #define DRAMCTRL_PREALL_OPTION BIT(19) + #define DRAMCTRL_TCMD GENMASK(22, 20) + #define DRAMCTRL_MRRIOPT BIT(23) + #define DRAMCTRL_FW2R BIT(24) + #define DRAMCTRL_REQQUE_DEPTH_UPD BIT(25) + #define DRAMCTRL_REQQUE_THD_EN BIT(26) + #define DRAMCTRL_REQQUE_MAXCNT_CHG BIT(27) + #define DRAMCTRL_PREA_RK GENMASK(29, 28) + #define DRAMCTRL_IDLE_COND_OPT BIT(30) +#define MISCTL0 0x00000008 + #define MISCTL0_R_DMCA_IDLE_EN BIT(0) + #define MISCTL0_IDLE_CNT_OPT BIT(16) + #define MISCTL0_PAGDIS BIT(17) + #define MISCTL0_IDLEDCM_CNT_OPT BIT(18) + #define MISCTL0_REFA_ARB_EN2 BIT(19) + #define MISCTL0_WRBYTE_CNT_OPT BIT(20) + #define MISCTL0_REFA_ARB_EN_OPTION BIT(21) + #define MISCTL0_REORDER_MASK_E1T BIT(22) + #define MISCTL0_PBC_ARB_E1T BIT(23) + #define MISCTL0_PBC_ARB_EN BIT(24) + #define MISCTL0_REFA_ARB_EN BIT(25) + #define MISCTL0_REFP_ARB_EN BIT(26) + #define MISCTL0_EMIPREEN BIT(27) + #define MISCTL0_REFP_ARB_EN2 BIT(31) +#define PERFCTL0 0x0000000c + #define PERFCTL0_DUALSCHEN BIT(0) + #define PERFCTL0_DISRDPHASE1 BIT(1) + #define PERFCTL0_XRT_05T_OPT BIT(2) + #define PERFCTL0_AIDCHKEN BIT(3) + #define PERFCTL0_RWOFOEN BIT(4) + #define PERFCTL0_RWOFOWNUM GENMASK(7, 5) + #define PERFCTL0_RWHPRIEN BIT(8) + #define PERFCTL0_RWLLATEN BIT(9) + #define PERFCTL0_RWAGEEN BIT(10) + #define PERFCTL0_EMILLATEN BIT(11) + #define PERFCTL0_LASTCMDOPT BIT(12) + #define PERFCTL0_RWHPRICTL BIT(13) + #define PERFCTL0_WFLUSHEN BIT(14) + #define PERFCTL0_RWSPLIT BIT(15) + #define PERFCTL0_MWHPRIEN BIT(17) + #define PERFCTL0_REORDER_MODE BIT(18) + #define PERFCTL0_REORDEREN BIT(19) + #define PERFCTL0_SBR_MASK_OPT BIT(20) + #define PERFCTL0_SBR_MASK_OPT2 BIT(21) + #define PERFCTL0_MAFIXHIGH BIT(22) + #define PERFCTL0_TESTWRHIGH BIT(23) + #define PERFCTL0_RECORDER_MASK_OPT BIT(24) + #define PERFCTL0_MDMCU_MASK_EN BIT(25) + #define PERFCTL0_WRFIFO_OPT BIT(26) + #define PERFCTL0_WRFIO_MODE2 BIT(27) + #define PERFCTL0_RDFIFOEN BIT(30) + #define PERFCTL0_WRFIFOEN BIT(31) +#define ARBCTL 0x00000010 + #define ARBCTL_MAXPENDCNT GENMASK(7, 0) + #define ARBCTL_RDATACNTDIS BIT(8) + #define ARBCTL_WDATACNTDIS BIT(9) + #define ARBCTL_RSV_SA0 BIT(10) + #define ARBCTL_RSV_SA1 BIT(11) + #define ARBCTL_RSV_SA2 BIT(12) + #define ARBCTL_RSV_SA3 BIT(13) + #define ARBCTL_RSV_DRAM_CBT BIT(13) //cc add + #define ARBCTL_RSV_DRAM_TYPE GENMASK(12, 10)//cc add + #define ARBCTL_DBIWR_IMP_EN BIT(14) + #define ARBCTL_DBIWR_PINMUX_EN BIT(15) + #define ARBCTL_DBIWR_OPT_B0 GENMASK(23, 16) + #define ARBCTL_DBIWR_OPT_bit1_0 GENMASK(17, 16)//cc add + #define ARBCTL_DBIWR_OPT_bit7 GENMASK(23, 23)//cc add + #define ARBCTL_DBIWR_OPT_B1 GENMASK(31, 24) + #define ARBCTL_DBIWR_OPT_bit9_8 GENMASK(25, 24)//cc add + #define ARBCTL_DBIWR_OPT_bit15 GENMASK(31, 31)//cc add +#define RSTMASK 0x0000001c + #define RSTMASK_WDATKEY0 BIT(0) + #define RSTMASK_WDATKEY1 BIT(1) + #define RSTMASK_WDATKEY2 BIT(2) + #define RSTMASK_WDATKEY3 BIT(3) + #define RSTMASK_WDATKEY4 BIT(4) + #define RSTMASK_WDATKEY5 BIT(5) + #define RSTMASK_WDATKEY6 BIT(6) + #define RSTMASK_WDATKEY7 BIT(7) + #define RSTMASK_WDATITLV BIT(8) + #define RSTMASK_RSV_SA_BU2 GENMASK(15, 12) //cc add + #define RSTMASK_RSV_DRAM_CBT_MIXED GENMASK(14, 13) //cc add + #define RSTMASK_RSV_DRAM_SUPPORT_RANK_NUM BIT(12) //cc add + #define RSTMASK_RETRY_DATRST_MASK BIT(21) + #define RSTMASK_DVFS_SYNC_MASK_FOR_PHY BIT(24) + #define RSTMASK_GT_SYNC_MASK_FOR_PHY BIT(25) + #define RSTMASK_DVFS_SYNC_MASK BIT(26) + #define RSTMASK_GTDMW_SYNC_MASK BIT(27) + #define RSTMASK_GT_SYNC_MASK BIT(28) + #define RSTMASK_DAT_SYNC_MASK BIT(29) + #define RSTMASK_PHY_SYNC_MASK BIT(30) + #define RSTMASK_R_DMSHU_RDATRST_MASK BIT(31) +#define PADCTRL 0x00000020 + #define PADCTRL_DQIENQKEND GENMASK(1, 0) + #define PADCTRL_DQIENLATEBEGIN BIT(3) + #define PADCTRL_DISDMOEDIS BIT(8) + #define PADCTRL_DRAMOEN BIT(12) + #define PADCTRL_FIXDQIEN GENMASK(19, 16) + #define PADCTRL_DISDQIEN GENMASK(23, 20) + #define PADCTRL_PINMUX GENMASK(30, 28) +#define CKECTRL 0x00000024 + #define CKECTRL_CKEBYCTL BIT(0) + #define CKECTRL_CKE2RANK_OPT3 BIT(1) + #define CKECTRL_CKE2FIXON BIT(2) + #define CKECTRL_CKE2FIXOFF BIT(3) + #define CKECTRL_CKE1FIXON BIT(4) + #define CKECTRL_CKE1FIXOFF BIT(5) + #define CKECTRL_CKEFIXON BIT(6) + #define CKECTRL_CKEFIXOFF BIT(7) + #define CKECTRL_CKE2RANK_OPT5 BIT(8) + #define CKECTRL_CKE2RANK_OPT6 BIT(9) + #define CKECTRL_CKE2RANK_OPT7 BIT(10) + #define CKECTRL_CKE2RANK_OPT8 BIT(11) + #define CKECTRL_CKEEXTEND BIT(12) + #define CKECTRL_CKETIMER_SEL BIT(13) + #define CKECTRL_FASTWAKE_SEL BIT(14) + #define CKECTRL_CKEWAKE_SEL BIT(15) + #define CKECTRL_CKEWAKE_SEL2 BIT(16) + #define CKECTRL_CKE2RANK_OPT9 BIT(17) + #define CKECTRL_CKE2RANK_OPT10 BIT(18) + #define CKECTRL_CKE2RANK_OPT11 BIT(19) + #define CKECTRL_CKE2RANK_OPT12 BIT(20) + #define CKECTRL_CKE2RANK_OPT13 BIT(21) + #define CKECTRL_CKEPBDIS BIT(22) + #define CKECTRL_CKELCKFIX BIT(23) + #define CKECTRL_CKELCKCNT GENMASK(26, 24) + #define CKECTRL_RUNTIMEMRRCKEFIX BIT(27) + #define CKECTRL_RUNTIMEMRRMIODIS BIT(28) + #define CKECTRL_CKE_H2L_OPT BIT(29) + #define CKECTRL_CKEON BIT(31) +#define DRSCTRL 0x00000028 + #define DRSCTRL_DRSDIS BIT(0) + #define DRSCTRL_DRSBLOCKOPT BIT(1) + #define DRSCTRL_DRSPB2AB_OPT BIT(2) + #define DRSCTRL_DRSRK1_SW BIT(3) + #define DRSCTRL_DRSMON_CLR BIT(4) + #define DRSCTRL_DRSCLR_EN BIT(5) + #define DRSCTRL_DRSACKWAITREF BIT(6) + #define DRSCTRL_DRSCLR_RK0_EN BIT(7) + #define DRSCTRL_DRSDLY GENMASK(11, 8) + #define DRSCTRL_DRS_CNTX GENMASK(18, 12) + #define DRSCTRL_DRS_SELFWAKE_DMYRD_DIS BIT(19) + #define DRSCTRL_DRS_DMYRD_MIOCK_OPT BIT(20) + #define DRSCTRL_DRSOPT2 BIT(21) + #define DRSCTRL_DRS_MR4_OPT_B BIT(24) + #define DRSCTRL_RK_SCINPUT_OPT BIT(29) +#define RKCFG 0x00000034 + #define RKCFG_TXRANK GENMASK(1, 0) + #define RKCFG_CKE2RANK_OPT2 BIT(2) + #define RKCFG_TXRANKFIX BIT(3) + #define RKCFG_RKMODE GENMASK(6, 4) + #define RKCFG_RKSWAP BIT(7) + #define RKCFG_DM3RANK BIT(8) + #define RKCFG_RANKRDY_OPT BIT(9) + #define RKCFG_MRS2RK BIT(10) + #define RKCFG_DQSOSC2RK BIT(11) + #define RKCFG_CKE2RANK BIT(12) + #define RKCFG_CS2RANK BIT(13) + #define RKCFG_SHU2RKOPT BIT(14) + #define RKCFG_CKE2RANK_OPT BIT(15) + #define RKCFG_RKSIZE GENMASK(18, 16) + #define RKCFG_DMCKEWAKE BIT(19) + #define RKCFG_RK0SRF BIT(20) + #define RKCFG_RK1SRF BIT(21) + #define RKCFG_RK2SRF BIT(22) + #define RKCFG_SRF_ENTER_MASK_OPT BIT(23) + #define RKCFG_RK0DPD BIT(24) + #define RKCFG_RK1DPD BIT(25) + #define RKCFG_RK2DPD BIT(26) + #define RKCFG_RK0DPDX BIT(28) + #define RKCFG_RK1DPDX BIT(29) + #define RKCFG_RK2DPDX BIT(30) + #define RKCFG_CS0FORCE BIT(31) +#define DRAMC_PD_CTRL 0x00000038 + #define DRAMC_PD_CTRL_DCMEN BIT(0) + #define DRAMC_PD_CTRL_DCMEN2 BIT(1) + #define DRAMC_PD_CTRL_DCMENNOTRFC BIT(2) + #define DRAMC_PD_CTRL_PHYCLK_REFWKEN BIT(4) + #define DRAMC_PD_CTRL_COMBPHY_CLKENSAME BIT(5) + #define DRAMC_PD_CTRL_DCMREF_OPT BIT(8) + #define DRAMC_PD_CTRL_PG_DCM_OPT BIT(9) + #define DRAMC_PD_CTRL_COMB_DCM BIT(10) + #define DRAMC_PD_CTRL_RDPERIODON BIT(19) + #define DRAMC_PD_CTRL_DQIEN_BUFFEN_OPT GENMASK(21, 20) + #define DRAMC_PD_CTRL_MIOCKCTRLOFF BIT(26) + #define DRAMC_PD_CTRL_DISSTOP26M BIT(27) + #define DRAMC_PD_CTRL_PHYCLKDYNGEN BIT(30) + #define DRAMC_PD_CTRL_COMBCLKCTRL BIT(31) +#define CLKAR 0x0000003c + #define CLKAR_REQQUE_PACG_DIS GENMASK(14, 0) + #define CLKAR_SELPH_CMD_CG_DIS BIT(15) + #define CLKAR_RDATCKAR BIT(16) + #define CLKAR_SRF_CLKRUN BIT(17) + #define CLKAR_IDLE_OPT BIT(18) + #define CLKAR_PSELAR BIT(19) + #define CLKAR_BCLKAR BIT(20) + #define CLKAR_SELPH_4LCG_DIS BIT(21) + #define CLKAR_SELPH_CG_DIS BIT(22) + #define CLKAR_TESTCLKRUN BIT(23) + #define CLKAR_PHYGLUECLKRUN BIT(24) + #define CLKAR_DWCLKRUN BIT(25) + #define CLKAR_REFCLKRUN BIT(26) + #define CLKAR_REQQUECLKRUN BIT(27) + #define CLKAR_SEQCLKRUN BIT(28) + #define CLKAR_CALCKAR BIT(29) + #define CLKAR_CMDCKAR BIT(30) + #define CLKAR_RDYCKAR BIT(31) +#define CLKCTRL 0x00000040 + #define CLKCTRL_PSEL_CNT GENMASK(5, 0) + #define CLKCTRL_SEQCLKRUN3 BIT(7) + #define CLKCTRL_SEQCLKRUN2 BIT(8) + #define CLKCTRL_CLK_EN_0 BIT(28) + #define CLKCTRL_CLK_EN_1 BIT(29) +#define SELFREF_HWSAVE_FLAG 0x00000044 + #define SELFREF_HWSAVE_FLAG_SELFREF_HWSAVE_FLAG_FROM_AO BIT(0) +#define SREFCTRL 0x00000048 + #define SREFCTRL_HMRRSEL_CGAR BIT(12) + #define SREFCTRL_RDDQSOSC_CGAR BIT(13) + #define SREFCTRL_SCARB_SM_CGAR BIT(14) + #define SREFCTRL_SCSM_CGAR BIT(15) + #define SREFCTRL_SRFPD_DIS BIT(16) + #define SREFCTRL_DQSOSC_THRD_OPT BIT(17) + #define SREFCTRL_DQSOSC_C2R_OPT BIT(18) + #define SREFCTRL_SREF3_OPTION BIT(20) + #define SREFCTRL_SREF3_OPTION1 BIT(21) + #define SREFCTRL_SREF2_OPTION BIT(22) + #define SREFCTRL_SREFDLY GENMASK(27, 24) + #define SREFCTRL_SREF_HW_EN BIT(30) + #define SREFCTRL_SELFREF BIT(31) +#define REFCTRL0 0x0000004c + #define REFCTRL0_DLLFRZ BIT(0) + #define REFCTRL0_UPDBYWR BIT(1) + #define REFCTRL0_DRVCGWREF BIT(2) + #define REFCTRL0_DQDRVSWUPD BIT(3) + #define REFCTRL0_RFRINTCTL BIT(5) + #define REFCTRL0_RFRINTEN BIT(6) + #define REFCTRL0_REFOVERCNT_RST BIT(7) + #define REFCTRL0_DMPGVLD_IG BIT(8) + #define REFCTRL0_REFMODE_MANUAL BIT(10) + #define REFCTRL0_REFMODE_MANUAL_TRIG BIT(11) + #define REFCTRL0_DISBYREFNUM GENMASK(14, 12) + #define REFCTRL0_PBREF_DISBYREFNUM BIT(16) + #define REFCTRL0_PBREF_DISBYRATE BIT(17) + #define REFCTRL0_PBREFEN BIT(18) + #define REFCTRL0_ADVREF_CNT GENMASK(23, 20) + #define REFCTRL0_REF_PREGATE_CNT GENMASK(27, 24) + #define REFCTRL0_REFNA_OPT BIT(28) + #define REFCTRL0_REFDIS BIT(29) + #define REFCTRL0_REFFRERUN BIT(30) + #define REFCTRL0_REFBW_FREN BIT(31) +#define REFCTRL1 0x00000050 + #define REFCTRL1_SLEFREF_AUTOSAVE_EN BIT(0) + #define REFCTRL1_SREF_PRD_OPT BIT(1) + #define REFCTRL1_PSEL_OPT2 BIT(2) + #define REFCTRL1_PSEL_OPT3 BIT(3) + #define REFCTRL1_PRE8REF BIT(4) + #define REFCTRL1_REF_QUE_AUTOSAVE_EN BIT(5) + #define REFCTRL1_PSEL_OPT1 BIT(6) + #define REFCTRL1_SREF_CG_OPT BIT(7) + #define REFCTRL1_MPENDREF_CNT GENMASK(10, 8) + #define REFCTRL1_REFRATE_MON_CLR BIT(11) + #define REFCTRL1_REFRATE_MANUAL GENMASK(30, 28) + #define REFCTRL1_REFRATE_MANUAL_RATE_TRIG BIT(31) +#define REFRATRE_FILTER 0x00000054 + #define REFRATRE_FILTER_REFRATE_FIL0 GENMASK(2, 0) + #define REFRATRE_FILTER_REFRATE_FIL1 GENMASK(6, 4) + #define REFRATRE_FILTER_REFRATE_FIL2 GENMASK(10, 8) + #define REFRATRE_FILTER_REFRATE_FIL3 GENMASK(14, 12) + #define REFRATRE_FILTER_PB2AB_OPT BIT(15) + #define REFRATRE_FILTER_REFRATE_FIL4 GENMASK(18, 16) + #define REFRATRE_FILTER_REFRATE_FIL5 GENMASK(22, 20) + #define REFRATRE_FILTER_PB2AB_OPT1 BIT(23) + #define REFRATRE_FILTER_REFRATE_FIL6 GENMASK(26, 24) + #define REFRATRE_FILTER_REFRATE_FIL7 GENMASK(30, 28) + #define REFRATRE_FILTER_REFRATE_FILEN BIT(31) +#define ZQCS 0x00000058 + #define ZQCS_ZQCSOP GENMASK(7, 0) + #define ZQCS_ZQCSAD GENMASK(15, 8) + #define ZQCS_ZQCS_MASK_SEL GENMASK(18, 16) + #define ZQCS_ZQCS_MASK_SEL_CGAR BIT(19) + #define ZQCS_ZQMASK_CGAR BIT(20) + #define ZQCS_ZQCSMASK_OPT BIT(21) + #define ZQCS_ZQ_SRF_OPT BIT(22) + #define ZQCS_ZQCSMASK BIT(30) + #define ZQCS_ZQCSDUAL BIT(31) +#define MRS 0x0000005c + #define MRS_MRSOP GENMASK(7, 0) + #define MRS_MRSMA GENMASK(20, 8) + #define MRS_MRSBA GENMASK(23, 21) + #define MRS_MRSRK GENMASK(25, 24) + #define MRS_MRRRK GENMASK(27, 26) + #define MRS_MPCRK GENMASK(29, 28) + #define MRS_MRSBG GENMASK(31, 30) +#define SPCMD 0x00000060 + #define SPCMD_MRWEN BIT(0) + #define SPCMD_MRREN BIT(1) + #define SPCMD_PREAEN BIT(2) + #define SPCMD_AREFEN BIT(3) + #define SPCMD_ZQCEN BIT(4) + #define SPCMD_TCMDEN BIT(5) + #define SPCMD_ZQLATEN BIT(6) + #define SPCMD_RDDQCEN BIT(7) + #define SPCMD_DQSGCNTEN BIT(8) + #define SPCMD_DQSGCNTRST BIT(9) + #define SPCMD_DQSOSCENEN BIT(10) + #define SPCMD_DQSOSCDISEN BIT(11) + #define SPCMD_ACTEN BIT(12) + #define SPCMD_MPRWEN BIT(13) +#define SPCMDCTRL 0x00000064 + #define SPCMDCTRL_SC_PG_UPD_OPT BIT(0)//cc add + #define SPCMDCTRL_SC_PG_MAN_DIS BIT(1)//cc add + #define SPCMDCTRL_SPREA_EN BIT(2)//cc add + #define SPCMDCTRL_SCARB_PRI_OPT BIT(4) + #define SPCMDCTRL_MRRSWUPD BIT(5) + #define SPCMDCTRL_R_DMDVFSMRW_EN BIT(6) + #define SPCMDCTRL_DPDWOSC BIT(7) + #define SPCMDCTRL_SC_PG_MPRW_DIS BIT(10)//cc add + #define SPCMDCTRL_SC_PG_STCMD_AREF_DIS BIT(9)//cc add + #define SPCMDCTRL_SC_PG_OPT2_DIS BIT(8)//cc add + #define SPCMDCTRL_RDDQCDIS BIT(11) + #define SPCMDCTRL_HMR4_TOG_OPT BIT(18)//cc add + #define SPCMDCTRL_SCPRE BIT(19) + #define SPCMDCTRL_ZQCS_NONMASK_CLR BIT(20) + #define SPCMDCTRL_ZQCS_MASK_FIX BIT(21) + #define SPCMDCTRL_ZQCS_MASK_VALUE BIT(22) + #define SPCMDCTRL_SRFMR4_CNTKEEP_B BIT(24) + #define SPCMDCTRL_MRWWOPRA BIT(25) + #define SPCMDCTRL_CLR_EN BIT(26) + #define SPCMDCTRL_MRRREFUPD_B BIT(27) + #define SPCMDCTRL_REFR_BLOCKEN BIT(28) + #define SPCMDCTRL_REFRDIS BIT(29) + #define SPCMDCTRL_ZQCALDISB BIT(30) + #define SPCMDCTRL_ZQCSDISB BIT(31) +#define PPR_CTRL 0x00000068 + #define PPR_CTRL_ACTEN_BK GENMASK(14, 12) + #define PPR_CTRL_ACTEN_ROW GENMASK(31, 16) +#define MPC_OPTION 0x0000006c + #define MPC_OPTION_MPC_BLOCKALE_OPT BIT(0) + #define MPC_OPTION_MPC_BLOCKALE_OPT1 BIT(1) + #define MPC_OPTION_MPC_BLOCKALE_OPT2 BIT(2) + #define MPC_OPTION_ZQ_BLOCKALE_OPT BIT(3) + #define MPC_OPTION_RW2ZQLAT_OPT BIT(4) + #define MPC_OPTION_MPCOP GENMASK(14, 8) + #define MPC_OPTION_MPCMANEN BIT(15) + #define MPC_OPTION_MPCMAN_CAS2EN BIT(16) + #define MPC_OPTION_MPCRKEN BIT(17) +#define REFQUE_CNT 0x00000070 + #define REFQUE_CNT_REFRESH_QUEUE_CNT_FROM_AO GENMASK(3, 0) +#define HW_MRR_FUN 0x00000074 + #define HW_MRR_FUN_TMRR_ENA BIT(0) + #define HW_MRR_FUN_TRCDMRR_EN BIT(1) + #define HW_MRR_FUN_TRPMRR_EN BIT(2) + #define HW_MRR_FUN_MANTMRR_EN BIT(3) + #define HW_MRR_FUN_MANTMRR GENMASK(7, 4) + #define HW_MRR_FUN_BUFEN_RFC_OPT BIT(8) + #define HW_MRR_FUN_MRR_REQNOPUSH_DIS BIT(9) + #define HW_MRR_FUN_MRR_BLOCK_NOR_DIS BIT(10) + #define HW_MRR_FUN_MRR_HW_HIPRI BIT(11) + #define HW_MRR_FUN_MRR_SPCMD_WAKE_DIS BIT(12) + #define HW_MRR_FUN_TMRR_OE_OPT_DIS BIT(13) + #define HW_MRR_FUN_MRR_PUSH2POP_ENA BIT(16) + #define HW_MRR_FUN_MRR_PUSH2POP_CLR BIT(17) + #define HW_MRR_FUN_MRR_PUSH2POP_ST_CLR BIT(18) + #define HW_MRR_FUN_MRR_PUSH2POP_SEL GENMASK(22, 20) + #define HW_MRR_FUN_MRR_SBR3_BKVA_DIS BIT(23) + #define HW_MRR_FUN_MRR_DDRCLKCOMB_DIS BIT(24) + #define HW_MRR_FUN_TRPRCD_DIS_OPT1 BIT(25) + #define HW_MRR_FUN_TRPRCD_OPT2 BIT(26) + #define HW_MRR_FUN_MRR_SBR2_QHIT_DIS BIT(27) + #define HW_MRR_FUN_MRR_INPUT_BANK GENMASK(30, 28) + #define HW_MRR_FUN_MRR_TZQCS_DIS BIT(31) +#define MRR_BIT_MUX1 0x00000078 + #define MRR_BIT_MUX1_MRR_BIT0_SEL GENMASK(4, 0) + #define MRR_BIT_MUX1_MRR_BIT1_SEL GENMASK(12, 8) + #define MRR_BIT_MUX1_MRR_BIT2_SEL GENMASK(20, 16) + #define MRR_BIT_MUX1_MRR_BIT3_SEL GENMASK(28, 24) +#define MRR_BIT_MUX2 0x0000007c + #define MRR_BIT_MUX2_MRR_BIT4_SEL GENMASK(4, 0) + #define MRR_BIT_MUX2_MRR_BIT5_SEL GENMASK(12, 8) + #define MRR_BIT_MUX2_MRR_BIT6_SEL GENMASK(20, 16) + #define MRR_BIT_MUX2_MRR_BIT7_SEL GENMASK(28, 24) +#define MRR_BIT_MUX3 0x00000080 + #define MRR_BIT_MUX3_MRR_BIT8_SEL GENMASK(4, 0) + #define MRR_BIT_MUX3_MRR_BIT9_SEL GENMASK(12, 8) + #define MRR_BIT_MUX3_MRR_BIT10_SEL GENMASK(20, 16) + #define MRR_BIT_MUX3_MRR_BIT11_SEL GENMASK(28, 24) +#define MRR_BIT_MUX4 0x00000084 + #define MRR_BIT_MUX4_MRR_BIT12_SEL GENMASK(4, 0) + #define MRR_BIT_MUX4_MRR_BIT13_SEL GENMASK(12, 8) + #define MRR_BIT_MUX4_MRR_BIT14_SEL GENMASK(20, 16) + #define MRR_BIT_MUX4_MRR_BIT15_SEL GENMASK(28, 24) +#define TEST2_5 0x0000008c + #define TEST2_5_TEST2_BASE_2 GENMASK(31, 4) +#define TEST2_0 0x00000090 + #define TEST2_0_TEST2_PAT1 GENMASK(7, 0) + #define TEST2_0_TEST2_PAT0 GENMASK(15, 8) +#define TEST2_1 0x00000094 + #define TEST2_1_TEST2_BASE GENMASK(31, 4) +#define TEST2_2 0x00000098 + #define TEST2_2_TEST2_OFF GENMASK(31, 4) +#define TEST2_3 0x0000009c + #define TEST2_3_TESTCNT GENMASK(3, 0) + #define TEST2_3_DQSICALEN BIT(4) + #define TEST2_3_DQSICALUPD BIT(5) + #define TEST2_3_PSTWR2 BIT(6) + #define TEST2_3_TESTAUDPAT BIT(7) + #define TEST2_3_DQSICALSTP GENMASK(10, 8) + #define TEST2_3_DQDLYAUTO BIT(11) + #define TEST2_3_MANUDLLFRZ BIT(12) + #define TEST2_3_MANUDQSUPD BIT(13) + #define TEST2_3_DQSUPDMODE BIT(14) + #define TEST2_3_DRDELSWEN BIT(19) + #define TEST2_3_DRDELSWSEL GENMASK(22, 20) + #define TEST2_3_MDQS BIT(23) + #define TEST2_3_DMPAT32 BIT(24) + #define TEST2_3_TESTADR_SHIFT BIT(25) + #define TEST2_3_TAHPRI_B BIT(26) + #define TEST2_3_TESTLP BIT(27) + #define TEST2_3_TEST2WREN2_HW_EN BIT(28) + #define TEST2_3_TEST1 BIT(29) + #define TEST2_3_TEST2R BIT(30) + #define TEST2_3_TEST2W BIT(31) +#define TEST2_4 0x000000a0 + #define TEST2_4_TESTAUDINC GENMASK(4, 0) + #define TEST2_4_TEST2DISSCRAM BIT(5) + #define TEST2_4_TESTSSOPAT BIT(6) + #define TEST2_4_TESTSSOXTALKPAT BIT(7) + #define TEST2_4_TESTAUDINIT GENMASK(12, 8) + #define TEST2_4_TESTAUDBITINV BIT(14) + #define TEST2_4_TESTAUDMODE BIT(15) + #define TEST2_4_TESTXTALKPAT BIT(16) + #define TEST2_4_TEST_REQ_LEN1 BIT(17) + #define TEST2_4_DISMASK BIT(20) + #define TEST2_4_DQCALDIS BIT(22) + #define TEST2_4_NEGDQS BIT(23) + #define TEST2_4_TESTAGENTRK GENMASK(25, 24) + #define TEST2_4_TESTAGENTRKSEL GENMASK(30, 28) +#define WDT_DBG_SIGNAL 0x000000a4 + #define WDT_DBG_SIGNAL_LATCH_RD_TEST_DM_CMP_CPT2_RK0 BIT(0) + #define WDT_DBG_SIGNAL_LATCH_RD_TEST_DM_CMP_CPT2_RK1 BIT(1) + #define WDT_DBG_SIGNAL_LATCH_RD_TEST_DM_CMP_ERR2_RK0 BIT(2) + #define WDT_DBG_SIGNAL_LATCH_RD_TEST_DM_CMP_ERR2_RK1 BIT(3) + #define WDT_DBG_SIGNAL_LATCH_RD_TEST_DLE_CNT_OK2_RK0 BIT(4) + #define WDT_DBG_SIGNAL_LATCH_RD_TEST_DLE_CNT_OK2_RK1 BIT(5) + #define WDT_DBG_SIGNAL_LATCH_RDWR_TEST_DM_CMP_CPT2_RK0 BIT(8) + #define WDT_DBG_SIGNAL_LATCH_RDWR_TEST_DM_CMP_CPT2_RK1 BIT(9) + #define WDT_DBG_SIGNAL_LATCH_RDWR_TEST_DM_CMP_ERR2_RK0 BIT(10) + #define WDT_DBG_SIGNAL_LATCH_RDWR_TEST_DM_CMP_ERR2_RK1 BIT(11) + #define WDT_DBG_SIGNAL_LATCH_RDWR_TEST_DLE_CNT_OK2_RK0 BIT(12) + #define WDT_DBG_SIGNAL_LATCH_RDWR_TEST_DLE_CNT_OK2_RK1 BIT(13) + #define WDT_DBG_SIGNAL_LATCH_DRAMC_GATING_ERROR BIT(14) +#define LBTEST 0x000000ac + #define LBTEST_LBTEST_IGB0 BIT(0) + #define LBTEST_LBTEST_IGB1 BIT(1) + #define LBTEST_LBTEST_IGB2 BIT(2) + #define LBTEST_LBTEST_IGB3 BIT(3) + #define LBTEST_LBTEST BIT(4) + #define LBTEST_LBTEST_MODE BIT(5) + #define LBTEST_R_EXTLB_DRAMC_CONF_I GENMASK(12, 8) + #define LBTEST_OCDPAT GENMASK(23, 16) + #define LBTEST_OCDADJ BIT(24) + #define LBTEST_RDCOLADR BIT(29) + #define LBTEST_RDWRDATA BIT(30) + #define LBTEST_RDTGDATA BIT(31) +#define CATRAINING1 0x000000b0 + #define CATRAINING1_CATRAINEN BIT(1) + #define CATRAINING1_CATRAINMRS BIT(2) + #define CATRAINING1_TESTCATRAIN BIT(5) + #define CATRAINING1_CSTRAIN_OPTION BIT(6) + #define CATRAINING1_CATRAINCSEXT BIT(13) + #define CATRAINING1_CATRAINLAT GENMASK(23, 20) + #define CATRAINING1_CATRAIN_INTV GENMASK(31, 24) +#define CATRAINING2 0x000000b4 + #define CATRAINING2_CATRAINCA GENMASK(15, 0) + #define CATRAINING2_CATRAINCA_Y GENMASK(31, 16) +#define WRITE_LEV 0x000000bc + #define WRITE_LEV_WRITE_LEVEL_EN BIT(0) + #define WRITE_LEV_DDRPHY_COMB_CG_SEL BIT(2) + #define WRITE_LEV_BYTEMODECBTEN BIT(3) + #define WRITE_LEV_BTCBTFIXDQSOE BIT(4) + #define WRITE_LEV_CBTMASKDQSOE BIT(5) + #define WRITE_LEV_DQS_OE_WLEV_OP BIT(6) + #define WRITE_LEV_DQS_WLEV BIT(7) + #define WRITE_LEV_DQSBX_G GENMASK(11, 8) + #define WRITE_LEV_DQSBY_G GENMASK(15, 12) + #define WRITE_LEV_DQS_SEL GENMASK(19, 16) + #define WRITE_LEV_DMVREFCA GENMASK(27, 20) + #define WRITE_LEV_DQS_OE_OP1_DIS BIT(28) + #define WRITE_LEV_DQS_OE_OP2_EN BIT(29) +#define MR_GOLDEN 0x000000c0 + #define MR_GOLDEN_MR20_GOLDEN GENMASK(7, 0) + #define MR_GOLDEN_MR15_GOLDEN GENMASK(15, 8) + #define MR_GOLDEN_MR40_GOLDEN GENMASK(23, 16) + #define MR_GOLDEN_MR32_GOLDEN GENMASK(31, 24) +#define SLP4_TESTMODE 0x000000c4 + #define SLP4_TESTMODE_CA0_TEST GENMASK(3, 0) + #define SLP4_TESTMODE_CA1_TEST GENMASK(7, 4) + #define SLP4_TESTMODE_CA2_TEST GENMASK(11, 8) + #define SLP4_TESTMODE_CA3_TEST GENMASK(15, 12) + #define SLP4_TESTMODE_CA4_TEST GENMASK(19, 16) + #define SLP4_TESTMODE_CA5_TEST GENMASK(23, 20) + #define SLP4_TESTMODE_STESTEN BIT(24) + #define SLP4_TESTMODE_SPEC_MODE BIT(25) + #define SLP4_TESTMODE_ARPI_CAL_E2OPT BIT(26) + #define SLP4_TESTMODE_TX_DLY_CAL_E2OPT BIT(27) +#define DQSOSCR 0x000000c8 + #define DQSOSCR_DQSOSC_INTEN BIT(0) + #define DQSOSCR_RK2_BYTE_MODE BIT(1) + #define DQSOSCR_TXUPD_BLOCK_SEL GENMASK(3, 2) + #define DQSOSCR_TXUPD_BLOCK_OPT BIT(4) + #define DQSOSCR_TXUPDMODE BIT(5) + #define DQSOSCR_MANUTXUPD BIT(6) + #define DQSOSCR_ARUIDQ_SW BIT(7) + #define DQSOSCR_DQS2DQ_UPD_BLOCK_CNT GENMASK(12, 8) + #define DQSOSCR_TDQS2DQ_UPD_BLOCKING BIT(13) + #define DQSOSCR_DQS2DQ_UPD_MON_OPT BIT(14) + #define DQSOSCR_DQS2DQ_UPD_MON_CNT_SEL GENMASK(16, 15) + #define DQSOSCR_TXUPD_IDLE_SEL GENMASK(18, 17) + #define DQSOSCR_TXUPD_ABREF_SEL GENMASK(20, 19) + #define DQSOSCR_TXUPD_IDLE_OPT BIT(21) + #define DQSOSCR_DQS2DQ_SHU_HW_CAL_DIS BIT(22) + #define DQSOSCR_SREF_TXUI_RELOAD_OPT BIT(23) + #define DQSOSCR_DQSOSCRDIS BIT(24) + #define DQSOSCR_RK1_BYTE_MODE BIT(25) + #define DQSOSCR_RK0_BYTE_MODE BIT(26) + #define DQSOSCR_SREF_TXPI_RELOAD_OPT BIT(27) + #define DQSOSCR_EMPTY_WRITE_OPT BIT(28) + #define DQSOSCR_TXUPD_ABREF_OPT BIT(29) + #define DQSOSCR_DQSOSCLOPAD BIT(30) + #define DQSOSCR_DQSOSC_CALEN BIT(31) +#define DUMMY_RD 0x000000d0 + #define DUMMY_RD_SREF_DMYRD_MASK BIT(0) + #define DUMMY_RD_DMYRDOFOEN BIT(1) + #define DUMMY_RD_DUMMY_RD_SW BIT(4) + #define DUMMY_RD_DMYWR_LPRI_EN BIT(5) + #define DUMMY_RD_DMY_WR_DBG BIT(6) + #define DUMMY_RD_DMY_RD_DBG BIT(7) + #define DUMMY_RD_DUMMY_RD_CNT0 BIT(8) + #define DUMMY_RD_DUMMY_RD_CNT1 BIT(9) + #define DUMMY_RD_DUMMY_RD_CNT2 BIT(10) + #define DUMMY_RD_DUMMY_RD_CNT3 BIT(11) + #define DUMMY_RD_DUMMY_RD_CNT4 BIT(12) + #define DUMMY_RD_DUMMY_RD_CNT5 BIT(13) + #define DUMMY_RD_DUMMY_RD_CNT6 BIT(14) + #define DUMMY_RD_DUMMY_RD_CNT7 BIT(15) + #define DUMMY_RD_RANK_NUM GENMASK(17, 16) + #define DUMMY_RD_DUMMY_RD_EN BIT(20) + #define DUMMY_RD_SREF_DMYRD_EN BIT(21) + #define DUMMY_RD_DQSG_DMYRD_EN BIT(22) + #define DUMMY_RD_DQSG_DMYWR_EN BIT(23) + #define DUMMY_RD_DUMMY_RD_PA_OPT BIT(24) + #define DUMMY_RD_DMY_RD_RX_TRACK BIT(25) + #define DUMMY_RD_DMYRD_HPRI_DIS BIT(26) + #define DUMMY_RD_DMYRD_REORDER_DIS BIT(27) +#define SHUCTRL 0x000000d4 + #define SHUCTRL_R_SHUFFLE_BLOCK_OPT GENMASK(1, 0) + #define SHUCTRL_DVFS_CG_OPT BIT(2) + #define SHUCTRL_VRCG_EN BIT(4) + #define SHUCTRL_SHU_PHYRST_SEL BIT(5) + #define SHUCTRL_R_DVFS_PICG_MARGIN2 GENMASK(7, 6) + #define SHUCTRL_DMSHU_CNT GENMASK(13, 8) + #define SHUCTRL_SHUCTRL_RESERVED GENMASK(15, 14) + #define SHUCTRL_LPSM_BYPASS_B BIT(16) + #define SHUCTRL_R_DRAMC_CHA BIT(17) + #define SHUCTRL_DVFS_CHB_SEL_B BIT(18) + #define SHUCTRL_R_NEW_SHU_MUX_SPM BIT(19) + #define SHUCTRL_R_MPDIV_SHU_GP GENMASK(22, 20) + #define SHUCTRL_R_OTHER_SHU_GP GENMASK(25, 24) + #define SHUCTRL_R_DVFS_PICG_MARGIN3 GENMASK(27, 26) + #define SHUCTRL_DMSHU_LOW BIT(29) + #define SHUCTRL_DMSHU_DRAMC BIT(31) +#define SHUCTRL1 0x000000d8 + #define SHUCTRL1_FC_PRDCNT GENMASK(7, 0) + #define SHUCTRL1_CKFSPE_PRDCNT GENMASK(15, 8) + #define SHUCTRL1_CKFSPX_PRDCNT GENMASK(23, 16) + #define SHUCTRL1_VRCGEN_PRDCNT GENMASK(31, 24) +#define SHUCTRL2 0x000000dc + #define SHUCTRL2_R_DLL_IDLE GENMASK(6, 0) + #define SHUCTRL2_R_DVFS_FSM_CLR BIT(7) + #define SHUCTRL2_R_DVFS_SREF_OPT BIT(8) + #define SHUCTRL2_R_DVFS_CDC_OPTION BIT(9) + #define SHUCTRL2_R_DVFS_PICG_MARGIN GENMASK(11, 10) + #define SHUCTRL2_R_DVFS_DLL_CHA BIT(12) + #define SHUCTRL2_R_CDC_MUX_SEL_OPTION BIT(13) + #define SHUCTRL2_R_DVFS_PARK_N BIT(14) + #define SHUCTRL2_R_DVFS_OPTION BIT(15) + #define SHUCTRL2_SHU_PERIOD_GO_ZERO_CNT GENMASK(23, 16) + #define SHUCTRL2_HWSET_WLRL BIT(24) + #define SHUCTRL2_MR13_SHU_EN BIT(25) + #define SHUCTRL2_R_DVFS_RG_CDC_TX_SEL BIT(26) + #define SHUCTRL2_R_DVFS_RG_CDC_SYNC_ENABLE BIT(27) + #define SHUCTRL2_R_SHU_RESTORE BIT(28) + #define SHUCTRL2_SHU_CLK_MASK BIT(29) + #define SHUCTRL2_DVFS_CKE_OPT BIT(30) + #define SHUCTRL2_SHORTQ_OPT BIT(31) +#define SHUCTRL3 0x000000e0 + #define SHUCTRL3_VRCGDIS_MRSMA GENMASK(12, 0) + #define SHUCTRL3_VRCGDISOP GENMASK(23, 16) + #define SHUCTRL3_VRCGDIS_PRDCNT GENMASK(31, 24) +#define SHUSTATUS 0x000000e4 + #define SHUSTATUS_SHUFFLE_END BIT(0) + #define SHUSTATUS_SHUFFLE_START_LOW BIT(1) + #define SHUSTATUS_SHUFFLE_START_LOW_THREE BIT(2) + #define SHUSTATUS_SHUFFLE_LEVEL GENMASK(2, 1) //cc add + #define SHUSTATUS_MPDIV_SHU_GP GENMASK(6, 4) +#define BYPASS_FSPOP 0x00000100 + #define BYPASS_FSPOP_BPFSP_SHU0 GENMASK(3, 0) + #define BYPASS_FSPOP_BPFSP_SHU1 GENMASK(7, 4) + #define BYPASS_FSPOP_BPFSP_SHU2 GENMASK(11, 8) + #define BYPASS_FSPOP_BPFSP_SHU3 GENMASK(15, 12) + #define BYPASS_FSPOP_BPFSP_OPT BIT(16) +#define STBCAL 0x00000200 + #define STBCAL_PIMASK_RKCHG_OPT BIT(0) + #define STBCAL_PIMASK_RKCHG_EXT GENMASK(3, 1) + #define STBCAL_STBDLELAST_OPT BIT(4) + #define STBCAL_DLLFRZIDLE4XUPD BIT(5) + #define STBCAL_FASTDQSG2X BIT(6) + #define STBCAL_FASTDQSGUPD BIT(7) + #define STBCAL_STBDLELAST_PULSE GENMASK(11, 8) + #define STBCAL_STBDLELAST_FILTER BIT(12) + #define STBCAL_STBUPDSTOP BIT(13) + #define STBCAL_CG_RKEN BIT(14) + #define STBCAL_STBSTATE_OPT BIT(15) + #define STBCAL_PHYVALID_IG BIT(16) + #define STBCAL_SREF_DQSGUPD BIT(17) + #define STBCAL_STBCNTRST BIT(18) + #define STBCAL_RKCHGMASKDIS BIT(19) + #define STBCAL_PICGEN BIT(20) + #define STBCAL_REFUICHG BIT(21) + #define STBCAL_STB_SELPHYCALEN BIT(22) + #define STBCAL_STBCAL2R BIT(23) + #define STBCAL_STBCALEN BIT(24) + #define STBCAL_STBDLYOUT_OPT BIT(25) + #define STBCAL_PICHGBLOCK_NORD BIT(26) + #define STBCAL_STB_DQIEN_IG BIT(27) + #define STBCAL_DQSIENCG_CHG_EN BIT(28) + #define STBCAL_DQSIENCG_NORMAL_EN BIT(29) + #define STBCAL_DQSIENMODE_SELPH BIT(30) + #define STBCAL_DQSIENMODE BIT(31) +#define STBCAL1 0x00000204 + #define STBCAL1_DIS_PI_TRACK_AS_NOT_RD BIT(2) + #define STBCAL1_STBEN_LP3_DIV2_EN BIT(3) + #define STBCAL1_STBCNT_MODESEL BIT(4) + #define STBCAL1_DQSIEN_7UI_EN BIT(5) + #define STBCAL1_STB_SHIFT_DTCOUT_IG BIT(6) + #define STBCAL1_INPUTRXTRACK_BLOCK BIT(7) + #define STBCAL1_STB_FLAGCLR BIT(8) + #define STBCAL1_STB_DLLFRZ_IG BIT(9) + #define STBCAL1_STBENCMPEN BIT(10) + #define STBCAL1_STBCNT_LATCH_EN BIT(11) + #define STBCAL1_DLLFRZ_MON_PBREF_OPT BIT(12) + #define STBCAL1_DLLFRZ_BLOCKLONG BIT(13) + #define STBCAL1_DQSERRCNT_DIS BIT(14) + #define STBCAL1_STBCNT_SW_RST BIT(15) + #define STBCAL1_STBCAL_FILTER GENMASK(31, 16) +#define STBCAL2 0x00000208 + #define STBCAL2_STB_PIDLYCG_IG BIT(0) + #define STBCAL2_STB_UIDLYCG_IG BIT(1) + #define STBCAL2_STB_DBG_EN GENMASK(7, 4) + #define STBCAL2_STB_DBG_EN_B1 BIT(5)//[5:5] + #define STBCAL2_STB_DBG_EN_B0 BIT(4)//[4:4] + #define STBCAL2_STB_DBG_CG_AO BIT(8) + #define STBCAL2_STB_DBG_UIPI_UPD_OPT BIT(9) + #define STBCAL2_DQSGCNT_BYP_REF BIT(10) + #define STBCAL2_STB_DRS_MASK_HW_SAVE BIT(12) + #define STBCAL2_STB_DRS_RK1_FLAG_SYNC_RK0_EN BIT(13) + #define STBCAL2_STB_PICG_EARLY_1T_EN BIT(16) + #define STBCAL2_STB_GERRSTOP BIT(28) + #define STBCAL2_STB_GERR_RST BIT(29) + #define STBCAL2_STB_GERR_B01 BIT(30) + #define STBCAL2_STB_GERR_B23 BIT(31) +#define EYESCAN 0x0000020c + #define EYESCAN_REG_SW_RST BIT(0) + #define EYESCAN_RG_RX_EYE_SCAN_EN BIT(1) + #define EYESCAN_RG_RX_MIOCK_JIT_EN BIT(2) + #define EYESCAN_EYESCAN_RD_SEL_OPT BIT(4) + #define EYESCAN_EYESCAN_CHK_OPT BIT(6) + #define EYESCAN_EYESCAN_TOG_OPT BIT(7) + #define EYESCAN_EYESCAN_DQ_SYNC_EN BIT(8) + #define EYESCAN_EYESCAN_NEW_DQ_SYNC_EN BIT(9) + #define EYESCAN_EYESCAN_DQS_SYNC_EN BIT(10) + #define EYESCAN_DCBLNCEN BIT(12) + #define EYESCAN_DCBLNCINS BIT(13) + #define EYESCAN_RX_DQ_EYE_SEL GENMASK(19, 16) + #define EYESCAN_RX_DQ_EYE_SEL_B1 GENMASK(23, 20) + #define EYESCAN_RX_DQ_EYE_SEL_B2 GENMASK(27, 24) + #define EYESCAN_RX_DQ_EYE_SEL_B3 GENMASK(31, 28) +#define DVFSDLL 0x00000210 + #define DVFSDLL_DLL_LOCK_SHU_EN BIT(0) + #define DVFSDLL_R_BYPASS_1ST_DLL_SHU1 BIT(1) + #define DVFSDLL_R_BYPASS_1ST_DLL_SHU2 BIT(2) + #define DVFSDLL_R_BYPASS_1ST_DLL_SHU3 BIT(3) + #define DVFSDLL_R_BYPASS_1ST_DLL_SHU4 BIT(4) + #define DVFSDLL_R_DDRPHY_SHUFFLE_DEBUG_ENABLE BIT(5) + #define DVFSDLL_R_RETRY_SAV_MSK BIT(6) + #define DVFSDLL_RG_DLL_SHUFFLE BIT(7) + #define DVFSDLL_DLL_IDLE_SHU2 GENMASK(14, 8) + #define DVFSDLL_DLL_IDLE_SHU3 GENMASK(22, 16) + #define DVFSDLL_R_DMSHUFFLE_CHANGE_FREQ_OPT BIT(24) + #define DVFSDLL_R_DVFS_DLL_MARGIN GENMASK(29, 28) + #define DVFSDLL_R_DVFS_SYNC_MODULE_RST_SEL BIT(31) +#define PRE_TDQSCK1 0x00000218 + #define PRE_TDQSCK1_FREQ_RATIO_TX_9 GENMASK(4, 0) + #define PRE_TDQSCK1_FREQ_RATIO_TX_10 GENMASK(9, 5) + #define PRE_TDQSCK1_FREQ_RATIO_TX_11 GENMASK(14, 10) + #define PRE_TDQSCK1_TX_TRACKING_OPT BIT(15) + #define PRE_TDQSCK1_SW_UP_TX_NOW_CASE BIT(16) + #define PRE_TDQSCK1_TXUIPI_CAL_CGAR BIT(17) + #define PRE_TDQSCK1_SHU_PRELOAD_TX_START BIT(18) + #define PRE_TDQSCK1_SHU_PRELOAD_TX_HW BIT(19) + #define PRE_TDQSCK1_APHY_CG_OPT1 BIT(20) + #define PRE_TDQSCK1_TDQSCK_HW_SW_UP_SEL BIT(22) + #define PRE_TDQSCK1_TDQSCK_SW_UP_CASE BIT(23) + #define PRE_TDQSCK1_TDQSCK_SW_SAVE BIT(24) + #define PRE_TDQSCK1_TDQSCK_REG_DVFS BIT(25) + #define PRE_TDQSCK1_TDQSCK_PRECAL_HW BIT(26) + #define PRE_TDQSCK1_TDQSCK_PRECAL_START BIT(27) + #define PRE_TDQSCK1_R_DQBUG_RANK_SEL GENMASK(29, 28) + #define PRE_TDQSCK1_R_DQBUG_BYTE_SEL GENMASK(31, 30) +#define PRE_TDQSCK2 0x0000021c + #define PRE_TDQSCK2_TDDQSCK_JUMP_RATIO3 GENMASK(7, 0) + #define PRE_TDQSCK2_TDDQSCK_JUMP_RATIO2 GENMASK(15, 8) + #define PRE_TDQSCK2_TDDQSCK_JUMP_RATIO1 GENMASK(23, 16) + #define PRE_TDQSCK2_TDDQSCK_JUMP_RATIO0 GENMASK(31, 24) +#define PRE_TDQSCK3 0x00000220 + #define PRE_TDQSCK3_TDDQSCK_JUMP_RATIO7 GENMASK(7, 0) + #define PRE_TDQSCK3_TDDQSCK_JUMP_RATIO6 GENMASK(15, 8) + #define PRE_TDQSCK3_TDDQSCK_JUMP_RATIO5 GENMASK(23, 16) + #define PRE_TDQSCK3_TDDQSCK_JUMP_RATIO4 GENMASK(31, 24) +#define PRE_TDQSCK4 0x00000224 + #define PRE_TDQSCK4_TDDQSCK_JUMP_RATIO11 GENMASK(7, 0) + #define PRE_TDQSCK4_TDDQSCK_JUMP_RATIO10 GENMASK(15, 8) + #define PRE_TDQSCK4_TDDQSCK_JUMP_RATIO9 GENMASK(23, 16) + #define PRE_TDQSCK4_TDDQSCK_JUMP_RATIO8 GENMASK(31, 24) +#define IMPCAL 0x0000022c + #define IMPCAL_DRV_ECO_OPT BIT(10) + #define IMPCAL_IMPCAL_CHGDRV_ECO_OPT BIT(11) + #define IMPCAL_IMPCAL_SM_ECO_OPT BIT(12) + #define IMPCAL_IMPCAL_ECO_OPT BIT(13) + #define IMPCAL_DIS_SUS_CH1_DRV BIT(14) + #define IMPCAL_DIS_SUS_CH0_DRV BIT(15) + #define IMPCAL_DIS_SHU_DRV BIT(16) + #define IMPCAL_IMPCAL_DRVUPDOPT BIT(17) + #define IMPCAL_IMPCAL_USING_SYNC BIT(18) + #define IMPCAL_IMPCAL_BYPASS_UP_CA_DRV BIT(19) + #define IMPCAL_IMPCAL_HWSAVE_EN BIT(20) + #define IMPCAL_IMPCAL_CALI_ENN BIT(21) + #define IMPCAL_IMPCAL_CALI_ENP BIT(22) + #define IMPCAL_IMPCAL_CALI_EN BIT(23) + #define IMPCAL_IMPCAL_IMPPDN BIT(24) + #define IMPCAL_IMPCAL_IMPPDP BIT(25) + #define IMPCAL_IMPCAL_NEW_OLD_SL BIT(26) + #define IMPCAL_IMPCAL_CMP_DIREC GENMASK(28, 27) + #define IMPCAL_IMPCAL_SWVALUE_EN BIT(29) + #define IMPCAL_IMPCAL_EN BIT(30) + #define IMPCAL_IMPCAL_HW BIT(31) +#define IMPEDAMCE_CTRL1 0x00000230 + #define IMPEDAMCE_CTRL1_DQS1_OFF GENMASK(9, 0) + #define IMPEDAMCE_CTRL1_DOS2_OFF GENMASK(19, 10) + #define IMPEDAMCE_CTRL1_DQS1_OFF_SUB GENMASK(29, 28) + #define IMPEDAMCE_CTRL1_DQS2_OFF_SUB GENMASK(31, 30) +#define IMPEDAMCE_CTRL2 0x00000234 + #define IMPEDAMCE_CTRL2_DQ1_OFF GENMASK(9, 0) + #define IMPEDAMCE_CTRL2_DQ2_OFF GENMASK(19, 10) + #define IMPEDAMCE_CTRL2_DQ1_OFF_SUB GENMASK(29, 28) + #define IMPEDAMCE_CTRL2_DQ2_OFF_SUB GENMASK(31, 30) +#define IMPEDAMCE_CTRL3 0x00000238 + #define IMPEDAMCE_CTRL3_CMD1_OFF GENMASK(9, 0) + #define IMPEDAMCE_CTRL3_CMD2_OFF GENMASK(19, 10) + #define IMPEDAMCE_CTRL3_CMD1_OFF_SUB GENMASK(29, 28) + #define IMPEDAMCE_CTRL3_CMD2_OFF_SUB GENMASK(31, 30) +#define IMPEDAMCE_CTRL4 0x0000023c + #define IMPEDAMCE_CTRL4_DQC1_OFF GENMASK(9, 0) + #define IMPEDAMCE_CTRL4_DQC2_OFF GENMASK(19, 10) + #define IMPEDAMCE_CTRL4_DQC1_OFF_SUB GENMASK(29, 28) + #define IMPEDAMCE_CTRL4_DQC2_OFF_SUB GENMASK(31, 30) +#define DRAMC_DBG_SEL1 0x00000240 + #define DRAMC_DBG_SEL1_DEBUG_SEL_0 GENMASK(15, 0) + #define DRAMC_DBG_SEL1_DEBUG_SEL_1 GENMASK(31, 16) +#define DRAMC_DBG_SEL2 0x00000244 + #define DRAMC_DBG_SEL2_DEBUG_SEL_2 GENMASK(15, 0) + #define DRAMC_DBG_SEL2_DEBUG_SEL_3 GENMASK(31, 16) +#define RK0_DQSOSC 0x00000300 + #define RK0_DQSOSC_R_DMDQS2DQ_FILT_OPT BIT(29) + #define RK0_DQSOSC_DQSOSCR_RK0EN BIT(30) + #define RK0_DQSOSC_DQSOSC_RK0INTCLR BIT(31) +#define RK0_DUMMY_RD_WDATA0 0x00000318 + #define RK0_DUMMY_RD_WDATA0_DMY_RD_RK0_WDATA0 GENMASK(31, 0) +#define RK0_DUMMY_RD_WDATA1 0x0000031c + #define RK0_DUMMY_RD_WDATA1_DMY_RD_RK0_WDATA1 GENMASK(31, 0) +#define RK0_DUMMY_RD_WDATA2 0x00000320 + #define RK0_DUMMY_RD_WDATA2_DMY_RD_RK0_WDATA2 GENMASK(31, 0) +#define RK0_DUMMY_RD_WDATA3 0x00000324 + #define RK0_DUMMY_RD_WDATA3_DMY_RD_RK0_WDATA3 GENMASK(31, 0) +#define RK0_DUMMY_RD_ADR 0x00000328 + #define RK0_DUMMY_RD_ADR_DMY_RD_RK0_ROW_ADR GENMASK(16, 0) + #define RK0_DUMMY_RD_ADR_DMY_RD_RK0_COL_ADR GENMASK(27, 17) + #define RK0_DUMMY_RD_ADR_DMY_RD_RK0_LEN GENMASK(31, 28) +#define RK0_DUMMY_RD_BK 0x0000032c + #define RK0_DUMMY_RD_BK_DMY_RD_RK0_BK GENMASK(2, 0) + #define RK0_DUMMY_RD_BK_DUMMY_RD_1_CNT0 BIT(4) + #define RK0_DUMMY_RD_BK_DUMMY_RD_1_CNT1 BIT(5) + #define RK0_DUMMY_RD_BK_DUMMY_RD_1_CNT2 BIT(6) + #define RK0_DUMMY_RD_BK_DUMMY_RD_1_CNT3 BIT(7) + #define RK0_DUMMY_RD_BK_DUMMY_RD_1_CNT4 BIT(8) + #define RK0_DUMMY_RD_BK_DUMMY_RD_1_CNT5 BIT(9) + #define RK0_DUMMY_RD_BK_DUMMY_RD_1_CNT6 BIT(10) + #define RK0_DUMMY_RD_BK_DUMMY_RD_1_CNT7 BIT(11) +#define RK0_PRE_TDQSCK1 0x00000330 + #define RK0_PRE_TDQSCK1_TDQSCK_UIFREQ1_B0R0 GENMASK(5, 0) + #define RK0_PRE_TDQSCK1_TDQSCK_PIFREQ1_B0R0 GENMASK(12, 6) + #define RK0_PRE_TDQSCK1_TDQSCK_UIFREQ2_B0R0 GENMASK(18, 13) + #define RK0_PRE_TDQSCK1_TDQSCK_PIFREQ2_B0R0 GENMASK(25, 19) +#define RK0_PRE_TDQSCK2 0x00000334 + #define RK0_PRE_TDQSCK2_TDQSCK_UIFREQ3_B0R0 GENMASK(5, 0) + #define RK0_PRE_TDQSCK2_TDQSCK_PIFREQ3_B0R0 GENMASK(12, 6) + #define RK0_PRE_TDQSCK2_TDQSCK_UIFREQ4_B0R0 GENMASK(18, 13) + #define RK0_PRE_TDQSCK2_TDQSCK_PIFREQ4_B0R0 GENMASK(25, 19) +#define RK0_PRE_TDQSCK3 0x00000338 + #define RK0_PRE_TDQSCK3_TDQSCK_UIFREQ1_P1_B0R0 GENMASK(5, 0) + #define RK0_PRE_TDQSCK3_TDQSCK_UIFREQ2_P1_B0R0 GENMASK(11, 6) + #define RK0_PRE_TDQSCK3_TDQSCK_UIFREQ3_P1_B0R0 GENMASK(17, 12) + #define RK0_PRE_TDQSCK3_TDQSCK_UIFREQ4_P1_B0R0 GENMASK(23, 18) +#define RK0_PRE_TDQSCK4 0x0000033c + #define RK0_PRE_TDQSCK4_TDQSCK_UIFREQ1_B1R0 GENMASK(5, 0) + #define RK0_PRE_TDQSCK4_TDQSCK_PIFREQ1_B1R0 GENMASK(12, 6) + #define RK0_PRE_TDQSCK4_TDQSCK_UIFREQ2_B1R0 GENMASK(18, 13) + #define RK0_PRE_TDQSCK4_TDQSCK_PIFREQ2_B1R0 GENMASK(25, 19) +#define RK0_PRE_TDQSCK5 0x00000340 + #define RK0_PRE_TDQSCK5_TDQSCK_UIFREQ3_B1R0 GENMASK(5, 0) + #define RK0_PRE_TDQSCK5_TDQSCK_PIFREQ3_B1R0 GENMASK(12, 6) + #define RK0_PRE_TDQSCK5_TDQSCK_UIFREQ4_B1R0 GENMASK(18, 13) + #define RK0_PRE_TDQSCK5_TDQSCK_PIFREQ4_B1R0 GENMASK(25, 19) +#define RK0_PRE_TDQSCK6 0x00000344 + #define RK0_PRE_TDQSCK6_TDQSCK_UIFREQ1_P1_B1R0 GENMASK(5, 0) + #define RK0_PRE_TDQSCK6_TDQSCK_UIFREQ2_P1_B1R0 GENMASK(11, 6) + #define RK0_PRE_TDQSCK6_TDQSCK_UIFREQ3_P1_B1R0 GENMASK(17, 12) + #define RK0_PRE_TDQSCK6_TDQSCK_UIFREQ4_P1_B1R0 GENMASK(23, 18) +#define RK0_PRE_TDQSCK7 0x00000348 + #define RK0_PRE_TDQSCK7_TDQSCK_UIFREQ1_B2R0 GENMASK(5, 0) + #define RK0_PRE_TDQSCK7_TDQSCK_PIFREQ1_B2R0 GENMASK(12, 6) + #define RK0_PRE_TDQSCK7_TDQSCK_UIFREQ2_B2R0 GENMASK(18, 13) + #define RK0_PRE_TDQSCK7_TDQSCK_PIFREQ2_B2R0 GENMASK(25, 19) +#define RK0_PRE_TDQSCK8 0x0000034c + #define RK0_PRE_TDQSCK8_TDQSCK_UIFREQ3_B2R0 GENMASK(5, 0) + #define RK0_PRE_TDQSCK8_TDQSCK_PIFREQ3_B2R0 GENMASK(12, 6) + #define RK0_PRE_TDQSCK8_TDQSCK_UIFREQ4_B2R0 GENMASK(18, 13) + #define RK0_PRE_TDQSCK8_TDQSCK_PIFREQ4_B2R0 GENMASK(25, 19) +#define RK0_PRE_TDQSCK9 0x00000350 + #define RK0_PRE_TDQSCK9_TDQSCK_UIFREQ1_P1_B2R0 GENMASK(5, 0) + #define RK0_PRE_TDQSCK9_TDQSCK_UIFREQ2_P1_B2R0 GENMASK(11, 6) + #define RK0_PRE_TDQSCK9_TDQSCK_UIFREQ3_P1_B2R0 GENMASK(17, 12) + #define RK0_PRE_TDQSCK9_TDQSCK_UIFREQ4_P1_B2R0 GENMASK(23, 18) +#define RK0_PRE_TDQSCK10 0x00000354 + #define RK0_PRE_TDQSCK10_TDQSCK_UIFREQ1_B3R0 GENMASK(5, 0) + #define RK0_PRE_TDQSCK10_TDQSCK_PIFREQ1_B3R0 GENMASK(12, 6) + #define RK0_PRE_TDQSCK10_TDQSCK_UIFREQ2_B3R0 GENMASK(18, 13) + #define RK0_PRE_TDQSCK10_TDQSCK_PIFREQ2_B3R0 GENMASK(25, 19) +#define RK0_PRE_TDQSCK11 0x00000358 + #define RK0_PRE_TDQSCK11_TDQSCK_UIFREQ3_B3R0 GENMASK(5, 0) + #define RK0_PRE_TDQSCK11_TDQSCK_PIFREQ3_B3R0 GENMASK(12, 6) + #define RK0_PRE_TDQSCK11_TDQSCK_UIFREQ4_B3R0 GENMASK(18, 13) + #define RK0_PRE_TDQSCK11_TDQSCK_PIFREQ4_B3R0 GENMASK(25, 19) +#define RK0_PRE_TDQSCK12 0x0000035c + #define RK0_PRE_TDQSCK12_TDQSCK_UIFREQ1_P1_B3R0 GENMASK(5, 0) + #define RK0_PRE_TDQSCK12_TDQSCK_UIFREQ2_P1_B3R0 GENMASK(11, 6) + #define RK0_PRE_TDQSCK12_TDQSCK_UIFREQ3_P1_B3R0 GENMASK(17, 12) + #define RK0_PRE_TDQSCK12_TDQSCK_UIFREQ4_P1_B3R0 GENMASK(23, 18) +#define RK1_DQSOSC 0x00000400 + #define RK1_DQSOSC_DQSOSCR_RK1EN BIT(30) + #define RK1_DQSOSC_DQSOSC_RK1INTCLR BIT(31) +#define RK1_DUMMY_RD_WDATA0 0x00000418 + #define RK1_DUMMY_RD_WDATA0_DMY_RD_RK1_WDATA0 GENMASK(31, 0) +#define RK1_DUMMY_RD_WDATA1 0x0000041c + #define RK1_DUMMY_RD_WDATA1_DMY_RD_RK1_WDATA1 GENMASK(31, 0) +#define RK1_DUMMY_RD_WDATA2 0x00000420 + #define RK1_DUMMY_RD_WDATA2_DMY_RD_RK1_WDATA2 GENMASK(31, 0) +#define RK1_DUMMY_RD_WDATA3 0x00000424 + #define RK1_DUMMY_RD_WDATA3_DMY_RD_RK1_WDATA3 GENMASK(31, 0) +#define RK1_DUMMY_RD_ADR 0x00000428 + #define RK1_DUMMY_RD_ADR_DMY_RD_RK1_ROW_ADR GENMASK(16, 0) + #define RK1_DUMMY_RD_ADR_DMY_RD_RK1_COL_ADR GENMASK(27, 17) + #define RK1_DUMMY_RD_ADR_DMY_RD_RK1_LEN GENMASK(31, 28) +#define RK1_DUMMY_RD_BK 0x0000042c + #define RK1_DUMMY_RD_BK_DMY_RD_RK1_BK GENMASK(2, 0) +#define RK1_PRE_TDQSCK1 0x00000430 + #define RK1_PRE_TDQSCK1_TDQSCK_UIFREQ1_B0R1 GENMASK(5, 0) + #define RK1_PRE_TDQSCK1_TDQSCK_PIFREQ1_B0R1 GENMASK(12, 6) + #define RK1_PRE_TDQSCK1_TDQSCK_UIFREQ2_B0R1 GENMASK(18, 13) + #define RK1_PRE_TDQSCK1_TDQSCK_PIFREQ2_B0R1 GENMASK(25, 19) +#define RK1_PRE_TDQSCK2 0x00000434 + #define RK1_PRE_TDQSCK2_TDQSCK_UIFREQ3_B0R1 GENMASK(5, 0) + #define RK1_PRE_TDQSCK2_TDQSCK_PIFREQ3_B0R1 GENMASK(12, 6) + #define RK1_PRE_TDQSCK2_TDQSCK_UIFREQ4_B0R1 GENMASK(18, 13) + #define RK1_PRE_TDQSCK2_TDQSCK_PIFREQ4_B0R1 GENMASK(25, 19) +#define RK1_PRE_TDQSCK3 0x00000438 + #define RK1_PRE_TDQSCK3_TDQSCK_UIFREQ1_P1_B0R1 GENMASK(5, 0) + #define RK1_PRE_TDQSCK3_TDQSCK_UIFREQ2_P1_B0R1 GENMASK(11, 6) + #define RK1_PRE_TDQSCK3_TDQSCK_UIFREQ3_P1_B0R1 GENMASK(17, 12) + #define RK1_PRE_TDQSCK3_TDQSCK_UIFREQ4_P1_B0R1 GENMASK(23, 18) +#define RK1_PRE_TDQSCK4 0x0000043c + #define RK1_PRE_TDQSCK4_TDQSCK_UIFREQ1_B1R1 GENMASK(5, 0) + #define RK1_PRE_TDQSCK4_TDQSCK_PIFREQ1_B1R1 GENMASK(12, 6) + #define RK1_PRE_TDQSCK4_TDQSCK_UIFREQ2_B1R1 GENMASK(18, 13) + #define RK1_PRE_TDQSCK4_TDQSCK_PIFREQ2_B1R1 GENMASK(25, 19) +#define RK1_PRE_TDQSCK5 0x00000440 + #define RK1_PRE_TDQSCK5_TDQSCK_UIFREQ3_B1R1 GENMASK(5, 0) + #define RK1_PRE_TDQSCK5_TDQSCK_PIFREQ3_B1R1 GENMASK(12, 6) + #define RK1_PRE_TDQSCK5_TDQSCK_UIFREQ4_B1R1 GENMASK(18, 13) + #define RK1_PRE_TDQSCK5_TDQSCK_PIFREQ4_B1R1 GENMASK(25, 19) +#define RK1_PRE_TDQSCK6 0x00000444 + #define RK1_PRE_TDQSCK6_TDQSCK_UIFREQ1_P1_B1R1 GENMASK(5, 0) + #define RK1_PRE_TDQSCK6_TDQSCK_UIFREQ2_P1_B1R1 GENMASK(11, 6) + #define RK1_PRE_TDQSCK6_TDQSCK_UIFREQ3_P1_B1R1 GENMASK(17, 12) + #define RK1_PRE_TDQSCK6_TDQSCK_UIFREQ4_P1_B1R1 GENMASK(23, 18) +#define RK1_PRE_TDQSCK7 0x00000448 + #define RK1_PRE_TDQSCK7_TDQSCK_UIFREQ1_B2R1 GENMASK(5, 0) + #define RK1_PRE_TDQSCK7_TDQSCK_PIFREQ1_B2R1 GENMASK(12, 6) + #define RK1_PRE_TDQSCK7_TDQSCK_UIFREQ2_B2R1 GENMASK(18, 13) + #define RK1_PRE_TDQSCK7_TDQSCK_PIFREQ2_B2R1 GENMASK(25, 19) +#define RK1_PRE_TDQSCK8 0x0000044c + #define RK1_PRE_TDQSCK8_TDQSCK_UIFREQ3_B2R1 GENMASK(5, 0) + #define RK1_PRE_TDQSCK8_TDQSCK_PIFREQ3_B2R1 GENMASK(12, 6) + #define RK1_PRE_TDQSCK8_TDQSCK_UIFREQ4_B2R1 GENMASK(18, 13) + #define RK1_PRE_TDQSCK8_TDQSCK_PIFREQ4_B2R1 GENMASK(25, 19) +#define RK1_PRE_TDQSCK9 0x00000450 + #define RK1_PRE_TDQSCK9_TDQSCK_UIFREQ1_P1_B2R1 GENMASK(5, 0) + #define RK1_PRE_TDQSCK9_TDQSCK_UIFREQ2_P1_B2R1 GENMASK(11, 6) + #define RK1_PRE_TDQSCK9_TDQSCK_UIFREQ3_P1_B2R1 GENMASK(17, 12) + #define RK1_PRE_TDQSCK9_TDQSCK_UIFREQ4_P1_B2R1 GENMASK(23, 18) +#define RK1_PRE_TDQSCK10 0x00000454 + #define RK1_PRE_TDQSCK10_TDQSCK_UIFREQ1_B3R1 GENMASK(5, 0) + #define RK1_PRE_TDQSCK10_TDQSCK_PIFREQ1_B3R1 GENMASK(12, 6) + #define RK1_PRE_TDQSCK10_TDQSCK_UIFREQ2_B3R1 GENMASK(18, 13) + #define RK1_PRE_TDQSCK10_TDQSCK_PIFREQ2_B3R1 GENMASK(25, 19) +#define RK1_PRE_TDQSCK11 0x00000458 + #define RK1_PRE_TDQSCK11_TDQSCK_UIFREQ3_B3R1 GENMASK(5, 0) + #define RK1_PRE_TDQSCK11_TDQSCK_PIFREQ3_B3R1 GENMASK(12, 6) + #define RK1_PRE_TDQSCK11_TDQSCK_UIFREQ4_B3R1 GENMASK(18, 13) + #define RK1_PRE_TDQSCK11_TDQSCK_PIFREQ4_B3R1 GENMASK(25, 19) +#define RK1_PRE_TDQSCK12 0x0000045c + #define RK1_PRE_TDQSCK12_TDQSCK_UIFREQ1_P1_B3R1 GENMASK(5, 0) + #define RK1_PRE_TDQSCK12_TDQSCK_UIFREQ2_P1_B3R1 GENMASK(11, 6) + #define RK1_PRE_TDQSCK12_TDQSCK_UIFREQ3_P1_B3R1 GENMASK(17, 12) + #define RK1_PRE_TDQSCK12_TDQSCK_UIFREQ4_P1_B3R1 GENMASK(23, 18) +#define RK2_DQSOSC 0x00000500 + #define RK2_DQSOSC_FREQ_RATIO_TX_0 GENMASK(4, 0) + #define RK2_DQSOSC_FREQ_RATIO_TX_1 GENMASK(9, 5) + #define RK2_DQSOSC_FREQ_RATIO_TX_2 GENMASK(14, 10) + #define RK2_DQSOSC_FREQ_RATIO_TX_3 GENMASK(19, 15) + #define RK2_DQSOSC_FREQ_RATIO_TX_4 GENMASK(24, 20) + #define RK2_DQSOSC_FREQ_RATIO_TX_5 GENMASK(29, 25) + #define RK2_DQSOSC_DQSOSCR_RK2EN BIT(30) + #define RK2_DQSOSC_DQSOSC_RK2INTCLR BIT(31) +#define RK2_DUMMY_RD_WDATA0 0x00000518 + #define RK2_DUMMY_RD_WDATA0_DMY_RD_RK2_WDATA0 GENMASK(31, 0) +#define RK2_DUMMY_RD_WDATA1 0x0000051c + #define RK2_DUMMY_RD_WDATA1_DMY_RD_RK2_WDATA1 GENMASK(31, 0) +#define RK2_DUMMY_RD_WDATA2 0x00000520 + #define RK2_DUMMY_RD_WDATA2_DMY_RD_RK2_WDATA2 GENMASK(31, 0) +#define RK2_DUMMY_RD_WDATA3 0x00000524 + #define RK2_DUMMY_RD_WDATA3_DMY_RD_RK2_WDATA3 GENMASK(31, 0) +#define RK2_DUMMY_RD_ADR 0x00000528 + #define RK2_DUMMY_RD_ADR_DMY_RD_RK2_ROW_ADR GENMASK(16, 0) + #define RK2_DUMMY_RD_ADR_DMY_RD_RK2_COL_ADR GENMASK(27, 17) + #define RK2_DUMMY_RD_ADR_DMY_RD_RK2_LEN GENMASK(31, 28) +#define RK2_DUMMY_RD_BK 0x0000052c + #define RK2_DUMMY_RD_BK_DMY_RD_RK2_BK GENMASK(2, 0) + #define RK2_DUMMY_RD_BK_FREQ_RATIO_TX_6 GENMASK(7, 3) + #define RK2_DUMMY_RD_BK_FREQ_RATIO_TX_7 GENMASK(12, 8) + #define RK2_DUMMY_RD_BK_FREQ_RATIO_TX_8 GENMASK(17, 13) +#define RK2_PRE_TDQSCK1 0x00000530 + #define RK2_PRE_TDQSCK1_TDQSCK_UIFREQ1_B0R2 GENMASK(5, 0) + #define RK2_PRE_TDQSCK1_TDQSCK_PIFREQ1_B0R2 GENMASK(12, 6) + #define RK2_PRE_TDQSCK1_TDQSCK_UIFREQ2_B0R2 GENMASK(18, 13) + #define RK2_PRE_TDQSCK1_TDQSCK_PIFREQ2_B0R2 GENMASK(25, 19) +#define RK2_PRE_TDQSCK2 0x00000534 + #define RK2_PRE_TDQSCK2_TDQSCK_UIFREQ3_B0R2 GENMASK(5, 0) + #define RK2_PRE_TDQSCK2_TDQSCK_PIFREQ3_B0R2 GENMASK(12, 6) + #define RK2_PRE_TDQSCK2_TDQSCK_UIFREQ4_B0R2 GENMASK(18, 13) + #define RK2_PRE_TDQSCK2_TDQSCK_PIFREQ4_B0R2 GENMASK(25, 19) +#define RK2_PRE_TDQSCK3 0x00000538 + #define RK2_PRE_TDQSCK3_TDQSCK_UIFREQ1_P1_B0R2 GENMASK(5, 0) + #define RK2_PRE_TDQSCK3_TDQSCK_UIFREQ2_P1_B0R2 GENMASK(11, 6) + #define RK2_PRE_TDQSCK3_TDQSCK_UIFREQ3_P1_B0R2 GENMASK(17, 12) + #define RK2_PRE_TDQSCK3_TDQSCK_UIFREQ4_P1_B0R2 GENMASK(23, 18) +#define RK2_PRE_TDQSCK4 0x0000053c + #define RK2_PRE_TDQSCK4_TDQSCK_UIFREQ1_B1R2 GENMASK(5, 0) + #define RK2_PRE_TDQSCK4_TDQSCK_PIFREQ1_B1R2 GENMASK(12, 6) + #define RK2_PRE_TDQSCK4_TDQSCK_UIFREQ2_B1R2 GENMASK(18, 13) + #define RK2_PRE_TDQSCK4_TDQSCK_PIFREQ2_B1R2 GENMASK(25, 19) +#define RK2_PRE_TDQSCK5 0x00000540 + #define RK2_PRE_TDQSCK5_TDQSCK_UIFREQ3_B1R2 GENMASK(5, 0) + #define RK2_PRE_TDQSCK5_TDQSCK_PIFREQ3_B1R2 GENMASK(12, 6) + #define RK2_PRE_TDQSCK5_TDQSCK_UIFREQ4_B1R2 GENMASK(18, 13) + #define RK2_PRE_TDQSCK5_TDQSCK_PIFREQ4_B1R2 GENMASK(25, 19) +#define RK2_PRE_TDQSCK6 0x00000544 + #define RK2_PRE_TDQSCK6_TDQSCK_UIFREQ1_P1_B1R2 GENMASK(5, 0) + #define RK2_PRE_TDQSCK6_TDQSCK_UIFREQ2_P1_B1R2 GENMASK(11, 6) + #define RK2_PRE_TDQSCK6_TDQSCK_UIFREQ3_P1_B1R2 GENMASK(17, 12) + #define RK2_PRE_TDQSCK6_TDQSCK_UIFREQ4_P1_B1R2 GENMASK(23, 18) +#define RK2_PRE_TDQSCK7 0x00000548 + #define RK2_PRE_TDQSCK7_TDQSCK_UIFREQ1_B2R2 GENMASK(5, 0) + #define RK2_PRE_TDQSCK7_TDQSCK_PIFREQ1_B2R2 GENMASK(12, 6) + #define RK2_PRE_TDQSCK7_TDQSCK_UIFREQ2_B2R2 GENMASK(18, 13) + #define RK2_PRE_TDQSCK7_TDQSCK_PIFREQ2_B2R2 GENMASK(25, 19) +#define RK2_PRE_TDQSCK8 0x0000054c + #define RK2_PRE_TDQSCK8_TDQSCK_UIFREQ3_B2R2 GENMASK(5, 0) + #define RK2_PRE_TDQSCK8_TDQSCK_PIFREQ3_B2R2 GENMASK(12, 6) + #define RK2_PRE_TDQSCK8_TDQSCK_UIFREQ4_B2R2 GENMASK(18, 13) + #define RK2_PRE_TDQSCK8_TDQSCK_PIFREQ4_B2R2 GENMASK(25, 19) +#define RK2_PRE_TDQSCK9 0x00000550 + #define RK2_PRE_TDQSCK9_TDQSCK_UIFREQ1_P1_B2R2 GENMASK(5, 0) + #define RK2_PRE_TDQSCK9_TDQSCK_UIFREQ2_P1_B2R2 GENMASK(11, 6) + #define RK2_PRE_TDQSCK9_TDQSCK_UIFREQ3_P1_B2R2 GENMASK(17, 12) + #define RK2_PRE_TDQSCK9_TDQSCK_UIFREQ4_P1_B2R2 GENMASK(23, 18) +#define RK2_PRE_TDQSCK10 0x00000554 + #define RK2_PRE_TDQSCK10_TDQSCK_UIFREQ1_B3R2 GENMASK(5, 0) + #define RK2_PRE_TDQSCK10_TDQSCK_PIFREQ1_B3R2 GENMASK(12, 6) + #define RK2_PRE_TDQSCK10_TDQSCK_UIFREQ2_B3R2 GENMASK(18, 13) + #define RK2_PRE_TDQSCK10_TDQSCK_PIFREQ2_B3R2 GENMASK(25, 19) +#define RK2_PRE_TDQSCK11 0x00000558 + #define RK2_PRE_TDQSCK11_TDQSCK_UIFREQ3_B3R2 GENMASK(5, 0) + #define RK2_PRE_TDQSCK11_TDQSCK_PIFREQ3_B3R2 GENMASK(12, 6) + #define RK2_PRE_TDQSCK11_TDQSCK_UIFREQ4_B3R2 GENMASK(18, 13) + #define RK2_PRE_TDQSCK11_TDQSCK_PIFREQ4_B3R2 GENMASK(25, 19) +#define RK2_PRE_TDQSCK12 0x0000055c + #define RK2_PRE_TDQSCK12_TDQSCK_UIFREQ1_P1_B3R2 GENMASK(5, 0) + #define RK2_PRE_TDQSCK12_TDQSCK_UIFREQ2_P1_B3R2 GENMASK(11, 6) + #define RK2_PRE_TDQSCK12_TDQSCK_UIFREQ3_P1_B3R2 GENMASK(17, 12) + #define RK2_PRE_TDQSCK12_TDQSCK_UIFREQ4_P1_B3R2 GENMASK(23, 18) +#define SHU_ACTIM0 0x00000800 + #define SHU_ACTIM0_TWTR GENMASK(3, 0) + #define SHU_ACTIM0_TWR GENMASK(12, 8) + #define SHU_ACTIM0_TRRD GENMASK(18, 16) + #define SHU_ACTIM0_TRCD GENMASK(27, 24) +#define SHU_ACTIM1 0x00000804 + #define SHU_ACTIM1_TRPAB GENMASK(2, 0) + #define SHU_ACTIM1_TRP GENMASK(11, 8) + #define SHU_ACTIM1_TRAS GENMASK(19, 16) + #define SHU_ACTIM1_TRC GENMASK(28, 24) +#define SHU_ACTIM2 0x00000808 + #define SHU_ACTIM2_TXP GENMASK(2, 0) + #define SHU_ACTIM2_TRTP GENMASK(10, 8) + #define SHU_ACTIM2_TR2W GENMASK(19, 16) + #define SHU_ACTIM2_TFAW GENMASK(28, 24) +#define SHU_ACTIM3 0x0000080c + #define SHU_ACTIM3_TRFCPB GENMASK(7, 0) + #define SHU_ACTIM3_TRFC GENMASK(23, 16) + #define SHU_ACTIM3_REFCNT GENMASK(31, 24) +#define SHU_ACTIM4 0x00000810 + #define SHU_ACTIM4_TXREFCNT GENMASK(9, 0) + #define SHU_ACTIM4_REFCNT_FR_CLK GENMASK(23, 16) + #define SHU_ACTIM4_TZQCS GENMASK(31, 24) +#define SHU_ACTIM5 0x00000814 + #define SHU_ACTIM5_TR2PD GENMASK(4, 0) + #define SHU_ACTIM5_TWTPD GENMASK(12, 8) + #define SHU_ACTIM5_TMRR2W GENMASK(27, 24) +#define SHU_ACTIM6 0x00000818 + #define SHU_ACTIM6_BGTCCD GENMASK(1, 0) + #define SHU_ACTIM6_BGTWTR GENMASK(7, 4) + #define SHU_ACTIM6_TWRMPR GENMASK(11, 8) + #define SHU_ACTIM6_BGTRRD GENMASK(14, 12) +#define SHU_ACTIM_XRT 0x0000081c + #define SHU_ACTIM_XRT_XRTR2R GENMASK(4, 0) + #define SHU_ACTIM_XRT_XRTR2W GENMASK(11, 8) + #define SHU_ACTIM_XRT_XRTW2R GENMASK(18, 16) + #define SHU_ACTIM_XRT_XRTW2W GENMASK(27, 24) +#define SHU_AC_TIME_05T 0x00000820 + #define SHU_AC_TIME_05T_TRC_05T BIT(0) + #define SHU_AC_TIME_05T_TRFCPB_05T BIT(1) + #define SHU_AC_TIME_05T_TRFC_05T BIT(2) + #define SHU_AC_TIME_05T_TXP_05T BIT(4) + #define SHU_AC_TIME_05T_TRTP_05T BIT(5) + #define SHU_AC_TIME_05T_TRCD_05T BIT(6) + #define SHU_AC_TIME_05T_TRP_05T BIT(7) + #define SHU_AC_TIME_05T_TRPAB_05T BIT(8) + #define SHU_AC_TIME_05T_TRAS_05T BIT(9) + #define SHU_AC_TIME_05T_TWR_M05T BIT(10) + #define SHU_AC_TIME_05T_TRRD_05T BIT(12) + #define SHU_AC_TIME_05T_TFAW_05T BIT(13) + #define SHU_AC_TIME_05T_TR2PD_05T BIT(15) + #define SHU_AC_TIME_05T_TWTPD_M05T BIT(16) + #define SHU_AC_TIME_05T_BGTRRD_05T BIT(21) + #define SHU_AC_TIME_05T_BGTCCD_05T BIT(22) + #define SHU_AC_TIME_05T_BGTWTR_05T BIT(23) + #define SHU_AC_TIME_05T_TR2W_05T BIT(24) + #define SHU_AC_TIME_05T_TWTR_M05T BIT(25) + #define SHU_AC_TIME_05T_XRTR2W_05T BIT(26) + #define SHU_AC_TIME_05T_XRTW2R_M05T BIT(27) +#define SHU_AC_DERATING0 0x00000824 + #define SHU_AC_DERATING0_ACDERATEEN BIT(0) + #define SHU_AC_DERATING0_TRRD_DERATE GENMASK(18, 16) + #define SHU_AC_DERATING0_TRCD_DERATE GENMASK(27, 24) +#define SHU_AC_DERATING1 0x00000828 + #define SHU_AC_DERATING1_TRPAB_DERATE GENMASK(2, 0) + #define SHU_AC_DERATING1_TRP_DERATE GENMASK(11, 8) + #define SHU_AC_DERATING1_TRAS_DERATE GENMASK(19, 16) + #define SHU_AC_DERATING1_TRC_DERATE GENMASK(28, 24) +#define SHU_AC_DERATING_05T 0x00000830 + #define SHU_AC_DERATING_05T_TRC_05T_DERATE BIT(0) + #define SHU_AC_DERATING_05T_TRCD_05T_DERATE BIT(6) + #define SHU_AC_DERATING_05T_TRP_05T_DERATE BIT(7) + #define SHU_AC_DERATING_05T_TRPAB_05T_DERATE BIT(8) + #define SHU_AC_DERATING_05T_TRAS_05T_DERATE BIT(9) + #define SHU_AC_DERATING_05T_TRRD_05T_DERATE BIT(12) +#define SHU_CONF0 0x00000840 + #define SHU_CONF0_DMPGTIM GENMASK(5, 0) + #define SHU_CONF0_ADVREFEN BIT(6) + #define SHU_CONF0_ADVPREEN BIT(7) + #define SHU_CONF0_TRFCPBIG BIT(9) + #define SHU_CONF0_REFTHD GENMASK(15, 12) + #define SHU_CONF0_REQQUE_DEPTH GENMASK(19, 16) + #define SHU_CONF0_FREQDIV4 BIT(24) + #define SHU_CONF0_FDIV2 BIT(25) + #define SHU_CONF0_CL2 BIT(27) + #define SHU_CONF0_BL2 BIT(28) + #define SHU_CONF0_BL4 BIT(29) + #define SHU_CONF0_MATYPE GENMASK(31, 30) +#define SHU_CONF1 0x00000844 + #define SHU_CONF1_DATLAT GENMASK(4, 0) + #define SHU_CONF1_DATLAT_DSEL GENMASK(12, 8) + #define SHU_CONF1_REFBW_FR GENMASK(25, 16) + #define SHU_CONF1_DATLAT_DSEL_PHY GENMASK(30, 26) + #define SHU_CONF1_TREFBWIG BIT(31) +#define SHU_CONF2 0x00000848 + #define SHU_CONF2_TCMDO1LAT GENMASK(7, 0) + #define SHU_CONF2_FSPCHG_PRDCNT GENMASK(15, 8) + #define SHU_CONF2_DCMDLYREF GENMASK(18, 16) + #define SHU_CONF2_DQCMD BIT(25) + #define SHU_CONF2_DQ16COM1 BIT(26) + #define SHU_CONF2_RA15TOCS1 BIT(27) + #define SHU_CONF2_WPRE2T BIT(28) + #define SHU_CONF2_FASTWAKE2 BIT(29) + #define SHU_CONF2_DAREFEN BIT(30) + #define SHU_CONF2_FASTWAKE BIT(31) +#define SHU_CONF3 0x0000084c + #define SHU_CONF3_ZQCSCNT GENMASK(15, 0) + #define SHU_CONF3_REFRCNT GENMASK(24, 16) +#define SHU_STBCAL 0x00000850 + #define SHU_STBCAL_DMSTBLAT GENMASK(1, 0) + #define SHU_STBCAL_PICGLAT GENMASK(6, 4) + #define SHU_STBCAL_DQSG_MODE BIT(8) +#define SHU_DQSOSCTHRD 0x00000854 + #define SHU_DQSOSCTHRD_DQSOSCTHRD_INC_RK0 GENMASK(11, 0) + #define SHU_DQSOSCTHRD_DQSOSCTHRD_DEC_RK0 GENMASK(23, 12) + #define SHU_DQSOSCTHRD_DQSOSCTHRD_INC_RK1_7TO0 GENMASK(31, 24) +#define SHU_RANKCTL 0x00000858 + #define SHU_RANKCTL_RANKINCTL_RXDLY GENMASK(3, 0) + #define SHU_RANKCTL_TXRANKINCTL_TXDLY GENMASK(11, 8) + #define SHU_RANKCTL_TXRANKINCTL GENMASK(15, 12) + #define SHU_RANKCTL_TXRANKINCTL_ROOT GENMASK(19, 16) + #define SHU_RANKCTL_RANKINCTL GENMASK(23, 20) + #define SHU_RANKCTL_RANKINCTL_ROOT1 GENMASK(27, 24) + #define SHU_RANKCTL_RANKINCTL_PHY GENMASK(31, 28) +#define SHU_CKECTRL 0x0000085c + #define SHU_CKECTRL_CMDCKE GENMASK(18, 16) + #define SHU_CKECTRL_CKEPRD GENMASK(22, 20) + #define SHU_CKECTRL_TCKESRX GENMASK(25, 24) + #define SHU_CKECTRL_SREF_CK_DLY GENMASK(29, 28) +#define SHU_ODTCTRL 0x00000860 + #define SHU_ODTCTRL_ROEN BIT(0) + #define SHU_ODTCTRL_WOEN BIT(1) + #define SHU_ODTCTRL_RODTEN_SELPH_CG_IG BIT(2) + #define SHU_ODTCTRL_RODTENSTB_SELPH_CG_IG BIT(3) + #define SHU_ODTCTRL_RODT GENMASK(7, 4) + #define SHU_ODTCTRL_TWODT GENMASK(22, 16) + #define SHU_ODTCTRL_FIXRODT BIT(27) + #define SHU_ODTCTRL_RODTE2 BIT(30) + #define SHU_ODTCTRL_RODTE BIT(31) +#define SHU_IMPCAL1 0x00000864 + #define SHU_IMPCAL1_IMPCAL_CHKCYCLE GENMASK(2, 0) + #define SHU_IMPCAL1_IMPDRVP GENMASK(8, 4) + #define SHU_IMPCAL1_IMPDRVN GENMASK(15, 11) + #define SHU_IMPCAL1_IMPCAL_CALEN_CYCLE GENMASK(19, 17) + #define SHU_IMPCAL1_IMPCALCNT GENMASK(27, 20) + #define SHU_IMPCAL1_IMPCAL_CALICNT GENMASK(31, 28) +#define SHU1_DQSOSC_PRD 0x00000868 + #define SHU1_DQSOSC_PRD_DQSOSC_PRDCNT GENMASK(9, 0) + #define SHU1_DQSOSC_PRD_DQSOSCTHRD_INC_RK1_11TO8 GENMASK(19, 16) + #define SHU1_DQSOSC_PRD_DQSOSCTHRD_DEC_RK1 GENMASK(31, 20) +#define SHU_DQSOSCR 0x0000086c + #define SHU_DQSOSCR_DQSOSCRCNT GENMASK(7, 0) + #define SHU_DQSOSCR_DQSOSC_DELTA GENMASK(31, 16) +#define SHU_DQSOSCR2 0x00000870 + #define SHU_DQSOSCR2_DQSOSCENCNT GENMASK(15, 0) + #define SHU_DQSOSCR2_DQSOSC_ADV_SEL GENMASK(17, 16) + #define SHU_DQSOSCR2_DQSOSC_DRS_ADV_SEL GENMASK(19, 18) +#define SHU_RODTENSTB 0x00000874 + #define SHU_RODTENSTB_RODTEN_MCK_MODESEL BIT(0) + #define SHU_RODTENSTB_RODTEN_P1_ENABLE BIT(1) + #define SHU_RODTENSTB_RODTENSTB_OFFSET GENMASK(7, 2) + #define SHU_RODTENSTB_RODTENSTB_EXT GENMASK(23, 8) + #define SHU_RODTENSTB_RODTENSTB_4BYTE_EN BIT(31) +#define SHU_PIPE 0x00000878 + #define SHU_PIPE_PHYRXPIPE1 BIT(0) + #define SHU_PIPE_PHYRXPIPE2 BIT(1) + #define SHU_PIPE_PHYRXPIPE3 BIT(2) + #define SHU_PIPE_PHYRXRDSLPIPE1 BIT(4) + #define SHU_PIPE_PHYRXRDSLPIPE2 BIT(5) + #define SHU_PIPE_PHYRXRDSLPIPE3 BIT(6) + #define SHU_PIPE_PHYPIPE1EN BIT(8) + #define SHU_PIPE_PHYPIPE2EN BIT(9) + #define SHU_PIPE_PHYPIPE3EN BIT(10) + #define SHU_PIPE_DLE_LAST_EXTEND3 BIT(26) + #define SHU_PIPE_READ_START_EXTEND3 BIT(27) + #define SHU_PIPE_DLE_LAST_EXTEND2 BIT(28) + #define SHU_PIPE_READ_START_EXTEND2 BIT(29) + #define SHU_PIPE_DLE_LAST_EXTEND1 BIT(30) + #define SHU_PIPE_READ_START_EXTEND1 BIT(31) +#define SHU_TEST1 0x0000087c + #define SHU_TEST1_LATNORMPOP GENMASK(12, 8) + #define SHU_TEST1_DQSICALBLCOK_CNT GENMASK(22, 20) + #define SHU_TEST1_DQSICALI_NEW BIT(23) +#define SHU_SELPH_CA1 0x00000880 + #define SHU_SELPH_CA1_TXDLY_CS GENMASK(2, 0) + #define SHU_SELPH_CA1_TXDLY_CKE GENMASK(6, 4) + #define SHU_SELPH_CA1_TXDLY_ODT GENMASK(10, 8) + #define SHU_SELPH_CA1_TXDLY_RESET GENMASK(14, 12) + #define SHU_SELPH_CA1_TXDLY_WE GENMASK(18, 16) + #define SHU_SELPH_CA1_TXDLY_CAS GENMASK(22, 20) + #define SHU_SELPH_CA1_TXDLY_RAS GENMASK(26, 24) + #define SHU_SELPH_CA1_TXDLY_CS1 GENMASK(30, 28) +#define SHU_SELPH_CA2 0x00000884 + #define SHU_SELPH_CA2_TXDLY_BA0 GENMASK(2, 0) + #define SHU_SELPH_CA2_TXDLY_BA1 GENMASK(6, 4) + #define SHU_SELPH_CA2_TXDLY_BA2 GENMASK(10, 8) + #define SHU_SELPH_CA2_TXDLY_CMD GENMASK(20, 16) + #define SHU_SELPH_CA2_TXDLY_CKE1 GENMASK(26, 24) +#define SHU_SELPH_CA3 0x00000888 + #define SHU_SELPH_CA3_TXDLY_RA0 GENMASK(2, 0) + #define SHU_SELPH_CA3_TXDLY_RA1 GENMASK(6, 4) + #define SHU_SELPH_CA3_TXDLY_RA2 GENMASK(10, 8) + #define SHU_SELPH_CA3_TXDLY_RA3 GENMASK(14, 12) + #define SHU_SELPH_CA3_TXDLY_RA4 GENMASK(18, 16) + #define SHU_SELPH_CA3_TXDLY_RA5 GENMASK(22, 20) + #define SHU_SELPH_CA3_TXDLY_RA6 GENMASK(26, 24) + #define SHU_SELPH_CA3_TXDLY_RA7 GENMASK(30, 28) +#define SHU_SELPH_CA4 0x0000088c + #define SHU_SELPH_CA4_TXDLY_RA8 GENMASK(2, 0) + #define SHU_SELPH_CA4_TXDLY_RA9 GENMASK(6, 4) + #define SHU_SELPH_CA4_TXDLY_RA10 GENMASK(10, 8) + #define SHU_SELPH_CA4_TXDLY_RA11 GENMASK(14, 12) + #define SHU_SELPH_CA4_TXDLY_RA12 GENMASK(18, 16) + #define SHU_SELPH_CA4_TXDLY_RA13 GENMASK(22, 20) + #define SHU_SELPH_CA4_TXDLY_RA14 GENMASK(26, 24) + #define SHU_SELPH_CA4_TXDLY_RA15 GENMASK(30, 28) +#define SHU_SELPH_CA5 0x00000890 + #define SHU_SELPH_CA5_DLY_CS GENMASK(2, 0) + #define SHU_SELPH_CA5_DLY_CKE GENMASK(6, 4) + #define SHU_SELPH_CA5_DLY_ODT GENMASK(10, 8) + #define SHU_SELPH_CA5_DLY_RESET GENMASK(14, 12) + #define SHU_SELPH_CA5_DLY_WE GENMASK(18, 16) + #define SHU_SELPH_CA5_DLY_CAS GENMASK(22, 20) + #define SHU_SELPH_CA5_DLY_RAS GENMASK(26, 24) + #define SHU_SELPH_CA5_DLY_CS1 GENMASK(30, 28) +#define SHU_SELPH_CA6 0x00000894 + #define SHU_SELPH_CA6_DLY_BA0 GENMASK(2, 0) + #define SHU_SELPH_CA6_DLY_BA1 GENMASK(6, 4) + #define SHU_SELPH_CA6_DLY_BA2 GENMASK(10, 8) + #define SHU_SELPH_CA6_DLY_CKE1 GENMASK(26, 24) +#define SHU_SELPH_CA7 0x00000898 + #define SHU_SELPH_CA7_DLY_RA0 GENMASK(2, 0) + #define SHU_SELPH_CA7_DLY_RA1 GENMASK(6, 4) + #define SHU_SELPH_CA7_DLY_RA2 GENMASK(10, 8) + #define SHU_SELPH_CA7_DLY_RA3 GENMASK(14, 12) + #define SHU_SELPH_CA7_DLY_RA4 GENMASK(18, 16) + #define SHU_SELPH_CA7_DLY_RA5 GENMASK(22, 20) + #define SHU_SELPH_CA7_DLY_RA6 GENMASK(26, 24) + #define SHU_SELPH_CA7_DLY_RA7 GENMASK(30, 28) +#define SHU_SELPH_CA8 0x0000089c + #define SHU_SELPH_CA8_DLY_RA8 GENMASK(2, 0) + #define SHU_SELPH_CA8_DLY_RA9 GENMASK(6, 4) + #define SHU_SELPH_CA8_DLY_RA10 GENMASK(10, 8) + #define SHU_SELPH_CA8_DLY_RA11 GENMASK(14, 12) + #define SHU_SELPH_CA8_DLY_RA12 GENMASK(18, 16) + #define SHU_SELPH_CA8_DLY_RA13 GENMASK(22, 20) + #define SHU_SELPH_CA8_DLY_RA14 GENMASK(26, 24) + #define SHU_SELPH_CA8_DLY_RA15 GENMASK(30, 28) +#define SHU_SELPH_DQS0 0x000008a0 + #define SHU_SELPH_DQS0_TXDLY_DQS0 GENMASK(2, 0) + #define SHU_SELPH_DQS0_TXDLY_DQS1 GENMASK(6, 4) + #define SHU_SELPH_DQS0_TXDLY_DQS2 GENMASK(10, 8) + #define SHU_SELPH_DQS0_TXDLY_DQS3 GENMASK(14, 12) + #define SHU_SELPH_DQS0_TXDLY_OEN_DQS0 GENMASK(18, 16) + #define SHU_SELPH_DQS0_TXDLY_OEN_DQS1 GENMASK(22, 20) + #define SHU_SELPH_DQS0_TXDLY_OEN_DQS2 GENMASK(26, 24) + #define SHU_SELPH_DQS0_TXDLY_OEN_DQS3 GENMASK(30, 28) +#define SHU_SELPH_DQS1 0x000008a4 + #define SHU_SELPH_DQS1_DLY_DQS0 GENMASK(2, 0) + #define SHU_SELPH_DQS1_DLY_DQS1 GENMASK(6, 4) + #define SHU_SELPH_DQS1_DLY_DQS2 GENMASK(10, 8) + #define SHU_SELPH_DQS1_DLY_DQS3 GENMASK(14, 12) + #define SHU_SELPH_DQS1_DLY_OEN_DQS0 GENMASK(18, 16) + #define SHU_SELPH_DQS1_DLY_OEN_DQS1 GENMASK(22, 20) + #define SHU_SELPH_DQS1_DLY_OEN_DQS2 GENMASK(26, 24) + #define SHU_SELPH_DQS1_DLY_OEN_DQS3 GENMASK(30, 28) +#define SHU1_DRVING1 0x000008a8 + #define SHU1_DRVING1_DQDRVN2 GENMASK(4, 0) + #define SHU1_DRVING1_DQDRVP2 GENMASK(9, 5) + #define SHU1_DRVING1_DQSDRVN1 GENMASK(14, 10) + #define SHU1_DRVING1_DQSDRVP1 GENMASK(19, 15) + #define SHU1_DRVING1_DQSDRVN2 GENMASK(24, 20) + #define SHU1_DRVING1_DQSDRVP2 GENMASK(29, 25) + #define SHU1_DRVING1_DIS_IMP_ODTN_TRACK BIT(30) + #define SHU1_DRVING1_DIS_IMPCAL_HW BIT(31) +#define SHU1_DRVING2 0x000008ac + #define SHU1_DRVING2_CMDDRVN1 GENMASK(4, 0) + #define SHU1_DRVING2_CMDDRVP1 GENMASK(9, 5) + #define SHU1_DRVING2_CMDDRVN2 GENMASK(14, 10) + #define SHU1_DRVING2_CMDDRVP2 GENMASK(19, 15) + #define SHU1_DRVING2_DQDRVN1 GENMASK(24, 20) + #define SHU1_DRVING2_DQDRVP1 GENMASK(29, 25) + #define SHU1_DRVING2_DIS_IMPCAL_ODT_EN BIT(31) +#define SHU1_DRVING3 0x000008b0 + #define SHU1_DRVING3_DQODTN2 GENMASK(4, 0) + #define SHU1_DRVING3_DQODTP2 GENMASK(9, 5) + #define SHU1_DRVING3_DQSODTN GENMASK(14, 10) + #define SHU1_DRVING3_DQSODTP GENMASK(19, 15) + #define SHU1_DRVING3_DQSODTN2 GENMASK(24, 20) + #define SHU1_DRVING3_DQSODTP2 GENMASK(29, 25) +#define SHU1_DRVING4 0x000008b4 + #define SHU1_DRVING4_CMDODTN1 GENMASK(4, 0) + #define SHU1_DRVING4_CMDODTP1 GENMASK(9, 5) + #define SHU1_DRVING4_CMDODTN2 GENMASK(14, 10) + #define SHU1_DRVING4_CMDODTP2 GENMASK(19, 15) + #define SHU1_DRVING4_DQODTN1 GENMASK(24, 20) + #define SHU1_DRVING4_DQODTP1 GENMASK(29, 25) +#define SHU1_DRVING5 0x000008b8 + #define SHU1_DRVING5_DQCODTN2 GENMASK(4, 0) + #define SHU1_DRVING5_DQCODTP2 GENMASK(9, 5) + #define SHU1_DRVING5_DQCDRVN1 GENMASK(14, 10) + #define SHU1_DRVING5_DQCDRVP1 GENMASK(19, 15) + #define SHU1_DRVING5_DQCDRVN2 GENMASK(24, 20) + #define SHU1_DRVING5_DQCDRVP2 GENMASK(29, 25) +#define SHU1_DRVING6 0x000008bc + #define SHU1_DRVING6_DQCODTN1 GENMASK(24, 20) + #define SHU1_DRVING6_DQCODTP1 GENMASK(29, 25) +#define SHU1_WODT 0x000008c0 + #define SHU1_WODT_DISWODT GENMASK(2, 0) + #define SHU1_WODT_WODTFIX BIT(3) + #define SHU1_WODT_WODTFIXOFF BIT(4) + #define SHU1_WODT_DISWODTE BIT(5) + #define SHU1_WODT_DISWODTE2 BIT(6) + #define SHU1_WODT_WODTPDEN BIT(7) + #define SHU1_WODT_DQOE_CNT GENMASK(10, 8) + #define SHU1_WODT_DQOE_OPT BIT(11) + #define SHU1_WODT_TXUPD_SEL GENMASK(13, 12) + #define SHU1_WODT_TXUPD_W2R_SEL GENMASK(16, 14) + #define SHU1_WODT_DBIWR BIT(29) + #define SHU1_WODT_TWPSTEXT BIT(30) + #define SHU1_WODT_WPST2T BIT(31) +#define SHU1_DQSG 0x000008c4 + #define SHU1_DQSG_DLLFRZRFCOPT GENMASK(1, 0) + #define SHU1_DQSG_DLLFRZWROPT GENMASK(5, 4) + #define SHU1_DQSG_R_RSTBCNT_LATCH_OPT GENMASK(10, 8) + #define SHU1_DQSG_STB_UPDMASK_EN BIT(11) + #define SHU1_DQSG_STB_UPDMASKCYC GENMASK(15, 12) + #define SHU1_DQSG_DQSINCTL_PRE_SEL BIT(16) + #define SHU1_DQSG_SCINTV GENMASK(25, 20) +#define SHU_SCINTV 0x000008c8 + #define SHU_SCINTV_ODTREN BIT(0) + #define SHU_SCINTV_TZQLAT GENMASK(5, 1) + #define SHU_SCINTV_TZQLAT2 GENMASK(10, 6) + #define SHU_SCINTV_RDDQC_INTV GENMASK(12, 11) + #define SHU_SCINTV_MRW_INTV GENMASK(17, 13) + #define SHU_SCINTV_DQS2DQ_SHU_PITHRD GENMASK(23, 18) + #define SHU_SCINTV_DQS2DQ_FILT_PITHRD GENMASK(29, 24) + #define SHU_SCINTV_DQSOSCENDIS BIT(30) +#define SHU_MISC 0x000008cc + #define SHU_MISC_REQQUE_MAXCNT GENMASK(3, 0) + #define SHU_MISC_CKEHCMD GENMASK(5, 4) + #define SHU_MISC_NORMPOP_LEN GENMASK(10, 8) + #define SHU_MISC_PREA_INTV GENMASK(16, 12) +#define SHU_DQS2DQ_TX 0x000008d0 + #define SHU_DQS2DQ_TX_OE2DQ_OFFSET GENMASK(4, 0) +#define SHU_HWSET_MR2 0x000008d4 + #define SHU_HWSET_MR2_HWSET_MR2_MRSMA GENMASK(12, 0) + #define SHU_HWSET_MR2_HWSET_MR2_OP GENMASK(23, 16) +#define SHU_HWSET_MR13 0x000008d8 + #define SHU_HWSET_MR13_HWSET_MR13_MRSMA GENMASK(12, 0) + #define SHU_HWSET_MR13_HWSET_MR13_OP GENMASK(23, 16) +#define SHU_HWSET_VRCG 0x000008dc + #define SHU_HWSET_VRCG_HWSET_VRCG_MRSMA GENMASK(12, 0) + #define SHU_HWSET_VRCG_HWSET_VRCG_OP GENMASK(23, 16) +#define SHU_APHY_TX_PICG_CTRL 0x000008e4 + #define SHU_APHY_TX_PICG_CTRL_APHYPI_CG_CK_SEL GENMASK(23, 20) + #define SHU_APHY_TX_PICG_CTRL_APHYPI_CG_CK_OPT BIT(24) + #define SHU_APHY_TX_PICG_CTRL_DDRPHY_CLK_DYN_GATING_SEL GENMASK(30, 27) + #define SHU_APHY_TX_PICG_CTRL_DDRPHY_CLK_EN_OPT BIT(31) +#define SHURK0_DQSCTL 0x00000a00 + #define SHURK0_DQSCTL_DQSINCTL GENMASK(3, 0) +#define SHURK0_DQSIEN 0x00000a04 + #define SHURK0_DQSIEN_R0DQS0IEN GENMASK(6, 0) + #define SHURK0_DQSIEN_R0DQS1IEN GENMASK(14, 8) + #define SHURK0_DQSIEN_R0DQS2IEN GENMASK(22, 16) + #define SHURK0_DQSIEN_R0DQS3IEN GENMASK(30, 24) +#define SHURK0_DQSCAL 0x00000a08 + #define SHURK0_DQSCAL_R0DQSIENLLMT GENMASK(6, 0) + #define SHURK0_DQSCAL_R0DQSIENLLMTEN BIT(7) + #define SHURK0_DQSCAL_R0DQSIENHLMT GENMASK(14, 8) + #define SHURK0_DQSCAL_R0DQSIENHLMTEN BIT(15) +#define SHU1RK0_PI 0x00000a0c + #define SHU1RK0_PI_RK0_ARPI_DQ_B1 GENMASK(5, 0) + #define SHU1RK0_PI_RK0_ARPI_DQ_B0 GENMASK(13, 8) + #define SHU1RK0_PI_RK0_ARPI_DQM_B1 GENMASK(21, 16) + #define SHU1RK0_PI_RK0_ARPI_DQM_B0 GENMASK(29, 24) +#define SHU1RK0_DQSOSC 0x00000a10 + #define SHU1RK0_DQSOSC_DQSOSC_BASE_RK0 GENMASK(15, 0) + #define SHU1RK0_DQSOSC_DQSOSC_BASE_RK0_B1 GENMASK(31, 16) +#define SHURK0_SELPH_ODTEN0 0x00000a1c + #define SHURK0_SELPH_ODTEN0_TXDLY_B0_RODTEN GENMASK(2, 0) + #define SHURK0_SELPH_ODTEN0_TXDLY_B0_RODTEN_P1 GENMASK(6, 4) + #define SHURK0_SELPH_ODTEN0_TXDLY_B1_RODTEN GENMASK(10, 8) + #define SHURK0_SELPH_ODTEN0_TXDLY_B1_RODTEN_P1 GENMASK(14, 12) + #define SHURK0_SELPH_ODTEN0_TXDLY_B2_RODTEN GENMASK(18, 16) + #define SHURK0_SELPH_ODTEN0_TXDLY_B2_RODTEN_P1 GENMASK(22, 20) + #define SHURK0_SELPH_ODTEN0_TXDLY_B3_RODTEN GENMASK(26, 24) + #define SHURK0_SELPH_ODTEN0_TXDLY_B3_RODTEN_P1 GENMASK(30, 28) +#define SHURK0_SELPH_ODTEN1 0x00000a20 + #define SHURK0_SELPH_ODTEN1_DLY_B0_RODTEN GENMASK(2, 0) + #define SHURK0_SELPH_ODTEN1_DLY_B0_RODTEN_P1 GENMASK(6, 4) + #define SHURK0_SELPH_ODTEN1_DLY_B1_RODTEN GENMASK(10, 8) + #define SHURK0_SELPH_ODTEN1_DLY_B1_RODTEN_P1 GENMASK(14, 12) + #define SHURK0_SELPH_ODTEN1_DLY_B2_RODTEN GENMASK(18, 16) + #define SHURK0_SELPH_ODTEN1_DLY_B2_RODTEN_P1 GENMASK(22, 20) + #define SHURK0_SELPH_ODTEN1_DLY_B3_RODTEN GENMASK(26, 24) + #define SHURK0_SELPH_ODTEN1_DLY_B3_RODTEN_P1 GENMASK(30, 28) +#define SHURK0_SELPH_DQSG0 0x00000a24 + #define SHURK0_SELPH_DQSG0_TX_DLY_DQS0_GATED GENMASK(2, 0) + #define SHURK0_SELPH_DQSG0_TX_DLY_DQS0_GATED_P1 GENMASK(6, 4) + #define SHURK0_SELPH_DQSG0_TX_DLY_DQS1_GATED GENMASK(10, 8) + #define SHURK0_SELPH_DQSG0_TX_DLY_DQS1_GATED_P1 GENMASK(14, 12) + #define SHURK0_SELPH_DQSG0_TX_DLY_DQS2_GATED GENMASK(18, 16) + #define SHURK0_SELPH_DQSG0_TX_DLY_DQS2_GATED_P1 GENMASK(22, 20) + #define SHURK0_SELPH_DQSG0_TX_DLY_DQS3_GATED GENMASK(26, 24) + #define SHURK0_SELPH_DQSG0_TX_DLY_DQS3_GATED_P1 GENMASK(30, 28) +#define SHURK0_SELPH_DQSG1 0x00000a28 + #define SHURK0_SELPH_DQSG1_REG_DLY_DQS0_GATED GENMASK(2, 0) + #define SHURK0_SELPH_DQSG1_REG_DLY_DQS0_GATED_P1 GENMASK(6, 4) + #define SHURK0_SELPH_DQSG1_REG_DLY_DQS1_GATED GENMASK(10, 8) + #define SHURK0_SELPH_DQSG1_REG_DLY_DQS1_GATED_P1 GENMASK(14, 12) + #define SHURK0_SELPH_DQSG1_REG_DLY_DQS2_GATED GENMASK(18, 16) + #define SHURK0_SELPH_DQSG1_REG_DLY_DQS2_GATED_P1 GENMASK(22, 20) + #define SHURK0_SELPH_DQSG1_REG_DLY_DQS3_GATED GENMASK(26, 24) + #define SHURK0_SELPH_DQSG1_REG_DLY_DQS3_GATED_P1 GENMASK(30, 28) +#define SHURK0_SELPH_DQ0 0x00000a2c + #define SHURK0_SELPH_DQ0_TXDLY_DQ0 GENMASK(2, 0) + #define SHURK0_SELPH_DQ0_TXDLY_DQ1 GENMASK(6, 4) + #define SHURK0_SELPH_DQ0_TXDLY_DQ2 GENMASK(10, 8) + #define SHURK0_SELPH_DQ0_TXDLY_DQ3 GENMASK(14, 12) + #define SHURK0_SELPH_DQ0_TXDLY_OEN_DQ0 GENMASK(18, 16) + #define SHURK0_SELPH_DQ0_TXDLY_OEN_DQ1 GENMASK(22, 20) + #define SHURK0_SELPH_DQ0_TXDLY_OEN_DQ2 GENMASK(26, 24) + #define SHURK0_SELPH_DQ0_TXDLY_OEN_DQ3 GENMASK(30, 28) +#define SHURK0_SELPH_DQ1 0x00000a30 + #define SHURK0_SELPH_DQ1_TXDLY_DQM0 GENMASK(2, 0) + #define SHURK0_SELPH_DQ1_TXDLY_DQM1 GENMASK(6, 4) + #define SHURK0_SELPH_DQ1_TXDLY_DQM2 GENMASK(10, 8) + #define SHURK0_SELPH_DQ1_TXDLY_DQM3 GENMASK(14, 12) + #define SHURK0_SELPH_DQ1_TXDLY_OEN_DQM0 GENMASK(18, 16) + #define SHURK0_SELPH_DQ1_TXDLY_OEN_DQM1 GENMASK(22, 20) + #define SHURK0_SELPH_DQ1_TXDLY_OEN_DQM2 GENMASK(26, 24) + #define SHURK0_SELPH_DQ1_TXDLY_OEN_DQM3 GENMASK(30, 28) +#define SHURK0_SELPH_DQ2 0x00000a34 + #define SHURK0_SELPH_DQ2_DLY_DQ0 GENMASK(2, 0) + #define SHURK0_SELPH_DQ2_DLY_DQ1 GENMASK(6, 4) + #define SHURK0_SELPH_DQ2_DLY_DQ2 GENMASK(10, 8) + #define SHURK0_SELPH_DQ2_DLY_DQ3 GENMASK(14, 12) + #define SHURK0_SELPH_DQ2_DLY_OEN_DQ0 GENMASK(18, 16) + #define SHURK0_SELPH_DQ2_DLY_OEN_DQ1 GENMASK(22, 20) + #define SHURK0_SELPH_DQ2_DLY_OEN_DQ2 GENMASK(26, 24) + #define SHURK0_SELPH_DQ2_DLY_OEN_DQ3 GENMASK(30, 28) +#define SHURK0_SELPH_DQ3 0x00000a38 + #define SHURK0_SELPH_DQ3_DLY_DQM0 GENMASK(2, 0) + #define SHURK0_SELPH_DQ3_DLY_DQM1 GENMASK(6, 4) + #define SHURK0_SELPH_DQ3_DLY_DQM2 GENMASK(10, 8) + #define SHURK0_SELPH_DQ3_DLY_DQM3 GENMASK(14, 12) + #define SHURK0_SELPH_DQ3_DLY_OEN_DQM0 GENMASK(18, 16) + #define SHURK0_SELPH_DQ3_DLY_OEN_DQM1 GENMASK(22, 20) + #define SHURK0_SELPH_DQ3_DLY_OEN_DQM2 GENMASK(26, 24) + #define SHURK0_SELPH_DQ3_DLY_OEN_DQM3 GENMASK(30, 28) +#define SHU1RK0_DQS2DQ_CAL1 0x00000a40 + #define SHU1RK0_DQS2DQ_CAL1_BOOT_ORIG_UI_RK0_DQ0 GENMASK(10, 0) + #define SHU1RK0_DQS2DQ_CAL1_BOOT_ORIG_UI_RK0_DQ1 GENMASK(26, 16) +#define SHU1RK0_DQS2DQ_CAL2 0x00000a44 + #define SHU1RK0_DQS2DQ_CAL2_BOOT_TARG_UI_RK0_DQ0 GENMASK(10, 0) + #define SHU1RK0_DQS2DQ_CAL2_BOOT_TARG_UI_RK0_DQ1 GENMASK(26, 16) +#define SHU1RK0_DQS2DQ_CAL3 0x00000a48 + #define SHU1RK0_DQS2DQ_CAL3_BOOT_TARG_UI_RK0_OEN_DQ0 GENMASK(5, 0) + #define SHU1RK0_DQS2DQ_CAL3_BOOT_TARG_UI_RK0_OEN_DQ1 GENMASK(11, 6) + #define SHU1RK0_DQS2DQ_CAL3_BOOT_TARG_UI_RK0_OEN_DQ0_B4TO0 GENMASK(16, 12) + #define SHU1RK0_DQS2DQ_CAL3_BOOT_TARG_UI_RK0_OEN_DQ1_B4TO0 GENMASK(21, 17) +#define SHU1RK0_DQS2DQ_CAL4 0x00000a4c + #define SHU1RK0_DQS2DQ_CAL4_BOOT_TARG_UI_RK0_OEN_DQM0 GENMASK(5, 0) + #define SHU1RK0_DQS2DQ_CAL4_BOOT_TARG_UI_RK0_OEN_DQM1 GENMASK(11, 6) + #define SHU1RK0_DQS2DQ_CAL4_BOOT_TARG_UI_RK0_OEN_DQM0_B4TO0 GENMASK(16, 12) + #define SHU1RK0_DQS2DQ_CAL4_BOOT_TARG_UI_RK0_OEN_DQM1_B4TO0 GENMASK(21, 17) +#define SHU1RK0_DQS2DQ_CAL5 0x00000a50 + #define SHU1RK0_DQS2DQ_CAL5_BOOT_TARG_UI_RK0_DQM0 GENMASK(10, 0) + #define SHU1RK0_DQS2DQ_CAL5_BOOT_TARG_UI_RK0_DQM1 GENMASK(26, 16) +#define SHURK1_DQSCTL 0x00000b00 + #define SHURK1_DQSCTL_R1DQSINCTL GENMASK(3, 0) +#define SHURK1_DQSIEN 0x00000b04 + #define SHURK1_DQSIEN_R1DQS0IEN GENMASK(6, 0) + #define SHURK1_DQSIEN_R1DQS1IEN GENMASK(14, 8) + #define SHURK1_DQSIEN_R1DQS2IEN GENMASK(22, 16) + #define SHURK1_DQSIEN_R1DQS3IEN GENMASK(30, 24) +#define SHURK1_DQSCAL 0x00000b08 + #define SHURK1_DQSCAL_R1DQSIENLLMT GENMASK(6, 0) + #define SHURK1_DQSCAL_R1DQSIENLLMTEN BIT(7) + #define SHURK1_DQSCAL_R1DQSIENHLMT GENMASK(14, 8) + #define SHURK1_DQSCAL_R1DQSIENHLMTEN BIT(15) +#define SHU1RK1_PI 0x00000b0c + #define SHU1RK1_PI_RK1_ARPI_DQ_B1 GENMASK(5, 0) + #define SHU1RK1_PI_RK1_ARPI_DQ_B0 GENMASK(13, 8) + #define SHU1RK1_PI_RK1_ARPI_DQM_B1 GENMASK(21, 16) + #define SHU1RK1_PI_RK1_ARPI_DQM_B0 GENMASK(29, 24) +#define SHU1RK1_DQSOSC 0x00000b10 + #define SHU1RK1_DQSOSC_DQSOSC_BASE_RK1 GENMASK(15, 0) + #define SHU1RK1_DQSOSC_DQSOSC_BASE_RK1_B1 GENMASK(31, 16) +#define SHURK1_SELPH_ODTEN0 0x00000b1c + #define SHURK1_SELPH_ODTEN0_TXDLY_B0_R1RODTEN GENMASK(2, 0) + #define SHURK1_SELPH_ODTEN0_TXDLY_B0_R1RODTEN_P1 GENMASK(6, 4) + #define SHURK1_SELPH_ODTEN0_TXDLY_B1_R1RODTEN GENMASK(10, 8) + #define SHURK1_SELPH_ODTEN0_TXDLY_B1_R1RODTEN_P1 GENMASK(14, 12) + #define SHURK1_SELPH_ODTEN0_TXDLY_B2_R1RODTEN GENMASK(18, 16) + #define SHURK1_SELPH_ODTEN0_TXDLY_B2_R1RODTEN_P1 GENMASK(22, 20) + #define SHURK1_SELPH_ODTEN0_TXDLY_B3_R1RODTEN GENMASK(26, 24) + #define SHURK1_SELPH_ODTEN0_TXDLY_B3_R1RODTEN_P1 GENMASK(30, 28) +#define SHURK1_SELPH_ODTEN1 0x00000b20 + #define SHURK1_SELPH_ODTEN1_DLY_B0_R1RODTEN GENMASK(2, 0) + #define SHURK1_SELPH_ODTEN1_DLY_B0_R1RODTEN_P1 GENMASK(6, 4) + #define SHURK1_SELPH_ODTEN1_DLY_B1_R1RODTEN GENMASK(10, 8) + #define SHURK1_SELPH_ODTEN1_DLY_B1_R1RODTEN_P1 GENMASK(14, 12) + #define SHURK1_SELPH_ODTEN1_DLY_B2_R1RODTEN GENMASK(18, 16) + #define SHURK1_SELPH_ODTEN1_DLY_B2_R1RODTEN_P1 GENMASK(22, 20) + #define SHURK1_SELPH_ODTEN1_DLY_B3_R1RODTEN GENMASK(26, 24) + #define SHURK1_SELPH_ODTEN1_DLY_B3_R1RODTEN_P1 GENMASK(30, 28) +#define SHURK1_SELPH_DQSG0 0x00000b24 + #define SHURK1_SELPH_DQSG0_TX_DLY_R1DQS0_GATED GENMASK(2, 0) + #define SHURK1_SELPH_DQSG0_TX_DLY_R1DQS0_GATED_P1 GENMASK(6, 4) + #define SHURK1_SELPH_DQSG0_TX_DLY_R1DQS1_GATED GENMASK(10, 8) + #define SHURK1_SELPH_DQSG0_TX_DLY_R1DQS1_GATED_P1 GENMASK(14, 12) + #define SHURK1_SELPH_DQSG0_TX_DLY_R1DQS2_GATED GENMASK(18, 16) + #define SHURK1_SELPH_DQSG0_TX_DLY_R1DQS2_GATED_P1 GENMASK(22, 20) + #define SHURK1_SELPH_DQSG0_TX_DLY_R1DQS3_GATED GENMASK(26, 24) + #define SHURK1_SELPH_DQSG0_TX_DLY_R1DQS3_GATED_P1 GENMASK(30, 28) +#define SHURK1_SELPH_DQSG1 0x00000b28 + #define SHURK1_SELPH_DQSG1_REG_DLY_R1DQS0_GATED GENMASK(2, 0) + #define SHURK1_SELPH_DQSG1_REG_DLY_R1DQS0_GATED_P1 GENMASK(6, 4) + #define SHURK1_SELPH_DQSG1_REG_DLY_R1DQS1_GATED GENMASK(10, 8) + #define SHURK1_SELPH_DQSG1_REG_DLY_R1DQS1_GATED_P1 GENMASK(14, 12) + #define SHURK1_SELPH_DQSG1_REG_DLY_R1DQS2_GATED GENMASK(18, 16) + #define SHURK1_SELPH_DQSG1_REG_DLY_R1DQS2_GATED_P1 GENMASK(22, 20) + #define SHURK1_SELPH_DQSG1_REG_DLY_R1DQS3_GATED GENMASK(26, 24) + #define SHURK1_SELPH_DQSG1_REG_DLY_R1DQS3_GATED_P1 GENMASK(30, 28) +#define SHURK1_SELPH_DQ0 0x00000b2c + #define SHURK1_SELPH_DQ0_TX_DLY_R1DQ0 GENMASK(2, 0) + #define SHURK1_SELPH_DQ0_TX_DLY_R1DQ1 GENMASK(6, 4) + #define SHURK1_SELPH_DQ0_TX_DLY_R1DQ2 GENMASK(10, 8) + #define SHURK1_SELPH_DQ0_TX_DLY_R1DQ3 GENMASK(14, 12) + #define SHURK1_SELPH_DQ0_TX_DLY_R1OEN_DQ0 GENMASK(18, 16) + #define SHURK1_SELPH_DQ0_TX_DLY_R1OEN_DQ1 GENMASK(22, 20) + #define SHURK1_SELPH_DQ0_TX_DLY_R1OEN_DQ2 GENMASK(26, 24) + #define SHURK1_SELPH_DQ0_TX_DLY_R1OEN_DQ3 GENMASK(30, 28) +#define SHURK1_SELPH_DQ1 0x00000b30 + #define SHURK1_SELPH_DQ1_TX_DLY_R1DQM0 GENMASK(2, 0) + #define SHURK1_SELPH_DQ1_TX_DLY_R1DQM1 GENMASK(6, 4) + #define SHURK1_SELPH_DQ1_TX_DLY_R1DQM2 GENMASK(10, 8) + #define SHURK1_SELPH_DQ1_TX_DLY_R1DQM3 GENMASK(14, 12) + #define SHURK1_SELPH_DQ1_TX_DLY_R1OEN_DQM0 GENMASK(18, 16) + #define SHURK1_SELPH_DQ1_TX_DLY_R1OEN_DQM1 GENMASK(22, 20) + #define SHURK1_SELPH_DQ1_TX_DLY_R1OEN_DQM2 GENMASK(26, 24) + #define SHURK1_SELPH_DQ1_TX_DLY_R1OEN_DQM3 GENMASK(30, 28) +#define SHURK1_SELPH_DQ2 0x00000b34 + #define SHURK1_SELPH_DQ2_DLY_R1DQ0 GENMASK(2, 0) + #define SHURK1_SELPH_DQ2_DLY_R1DQ1 GENMASK(6, 4) + #define SHURK1_SELPH_DQ2_DLY_R1DQ2 GENMASK(10, 8) + #define SHURK1_SELPH_DQ2_DLY_R1DQ3 GENMASK(14, 12) + #define SHURK1_SELPH_DQ2_DLY_R1OEN_DQ0 GENMASK(18, 16) + #define SHURK1_SELPH_DQ2_DLY_R1OEN_DQ1 GENMASK(22, 20) + #define SHURK1_SELPH_DQ2_DLY_R1OEN_DQ2 GENMASK(26, 24) + #define SHURK1_SELPH_DQ2_DLY_R1OEN_DQ3 GENMASK(30, 28) +#define SHURK1_SELPH_DQ3 0x00000b38 + #define SHURK1_SELPH_DQ3_DLY_R1DQM0 GENMASK(2, 0) + #define SHURK1_SELPH_DQ3_DLY_R1DQM1 GENMASK(6, 4) + #define SHURK1_SELPH_DQ3_DLY_R1DQM2 GENMASK(10, 8) + #define SHURK1_SELPH_DQ3_DLY_R1DQM3 GENMASK(14, 12) + #define SHURK1_SELPH_DQ3_DLY_R1OEN_DQM0 GENMASK(18, 16) + #define SHURK1_SELPH_DQ3_DLY_R1OEN_DQM1 GENMASK(22, 20) + #define SHURK1_SELPH_DQ3_DLY_R1OEN_DQM2 GENMASK(26, 24) + #define SHURK1_SELPH_DQ3_DLY_R1OEN_DQM3 GENMASK(30, 28) +#define SHU1RK1_DQS2DQ_CAL1 0x00000b40 + #define SHU1RK1_DQS2DQ_CAL1_BOOT_ORIG_UI_RK1_DQ0 GENMASK(10, 0) + #define SHU1RK1_DQS2DQ_CAL1_BOOT_ORIG_UI_RK1_DQ1 GENMASK(26, 16) +#define SHU1RK1_DQS2DQ_CAL2 0x00000b44 + #define SHU1RK1_DQS2DQ_CAL2_BOOT_TARG_UI_RK1_DQ0 GENMASK(10, 0) + #define SHU1RK1_DQS2DQ_CAL2_BOOT_TARG_UI_RK1_DQ1 GENMASK(26, 16) +#define SHU1RK1_DQS2DQ_CAL3 0x00000b48 + #define SHU1RK1_DQS2DQ_CAL3_BOOT_TARG_UI_RK1_OEN_DQ0 GENMASK(5, 0) + #define SHU1RK1_DQS2DQ_CAL3_BOOT_TARG_UI_RK1_OEN_DQ1 GENMASK(11, 6) + #define SHU1RK1_DQS2DQ_CAL3_BOOT_TARG_UI_RK1_OEN_DQ0_B4TO0 GENMASK(16, 12) + #define SHU1RK1_DQS2DQ_CAL3_BOOT_TARG_UI_RK1_OEN_DQ1_B4TO0 GENMASK(21, 17) +#define SHU1RK1_DQS2DQ_CAL4 0x00000b4c + #define SHU1RK1_DQS2DQ_CAL4_BOOT_TARG_UI_RK1_OEN_DQM0 GENMASK(5, 0) + #define SHU1RK1_DQS2DQ_CAL4_BOOT_TARG_UI_RK1_OEN_DQM1 GENMASK(11, 6) + #define SHU1RK1_DQS2DQ_CAL4_BOOT_TARG_UI_RK1_OEN_DQM0_B4TO0 GENMASK(16, 12) + #define SHU1RK1_DQS2DQ_CAL4_BOOT_TARG_UI_RK1_OEN_DQM1_B4TO0 GENMASK(21, 17) +#define SHU1RK1_DQS2DQ_CAL5 0x00000b50 + #define SHU1RK1_DQS2DQ_CAL5_BOOT_TARG_UI_RK1_DQM0 GENMASK(10, 0) + #define SHU1RK1_DQS2DQ_CAL5_BOOT_TARG_UI_RK1_DQM1 GENMASK(26, 16) +#define SHURK2_DQSCTL 0x00000c00 + #define SHURK2_DQSCTL_R2DQSINCTL GENMASK(3, 0) +#define SHURK2_DQSIEN 0x00000c04 + #define SHURK2_DQSIEN_R2DQS0IEN GENMASK(6, 0) + #define SHURK2_DQSIEN_R2DQS1IEN GENMASK(14, 8) + #define SHURK2_DQSIEN_R2DQS2IEN GENMASK(22, 16) + #define SHURK2_DQSIEN_R2DQS3IEN GENMASK(30, 24) +#define SHURK2_DQSCAL 0x00000c08 + #define SHURK2_DQSCAL_R2DQSIENLLMT GENMASK(6, 0) + #define SHURK2_DQSCAL_R2DQSIENLLMTEN BIT(7) + #define SHURK2_DQSCAL_R2DQSIENHLMT GENMASK(14, 8) + #define SHURK2_DQSCAL_R2DQSIENHLMTEN BIT(15) +#define SHU1RK2_PI 0x00000c0c + #define SHU1RK2_PI_RK2_ARPI_DQ_B1 GENMASK(5, 0) + #define SHU1RK2_PI_RK2_ARPI_DQ_B0 GENMASK(13, 8) + #define SHU1RK2_PI_RK2_ARPI_DQM_B1 GENMASK(21, 16) + #define SHU1RK2_PI_RK2_ARPI_DQM_B0 GENMASK(29, 24) +#define SHU1RK2_DQSOSC 0x00000c10 + #define SHU1RK2_DQSOSC_DQSOSC_BASE_RK2 GENMASK(15, 0) + #define SHU1RK2_DQSOSC_DQSOSC_BASE_RK2_B1 GENMASK(31, 16) +#define SHURK2_SELPH_ODTEN0 0x00000c1c + #define SHURK2_SELPH_ODTEN0_TXDLY_B0_R2RODTEN GENMASK(2, 0) + #define SHURK2_SELPH_ODTEN0_TXDLY_B0_R2RODTEN_P1 GENMASK(6, 4) + #define SHURK2_SELPH_ODTEN0_TXDLY_B1_R2RODTEN GENMASK(10, 8) + #define SHURK2_SELPH_ODTEN0_TXDLY_B1_R2RODTEN_P1 GENMASK(14, 12) + #define SHURK2_SELPH_ODTEN0_TXDLY_B2_R2RODTEN GENMASK(18, 16) + #define SHURK2_SELPH_ODTEN0_TXDLY_B2_R2RODTEN_P1 GENMASK(22, 20) + #define SHURK2_SELPH_ODTEN0_TXDLY_B3_R2RODTEN GENMASK(26, 24) + #define SHURK2_SELPH_ODTEN0_TXDLY_B3_R2RODTEN_P1 GENMASK(30, 28) +#define SHURK2_SELPH_ODTEN1 0x00000c20 + #define SHURK2_SELPH_ODTEN1_DLY_B0_R2RODTEN GENMASK(2, 0) + #define SHURK2_SELPH_ODTEN1_DLY_B0_R2RODTEN_P1 GENMASK(6, 4) + #define SHURK2_SELPH_ODTEN1_DLY_B1_R2RODTEN GENMASK(10, 8) + #define SHURK2_SELPH_ODTEN1_DLY_B1_R2RODTEN_P1 GENMASK(14, 12) + #define SHURK2_SELPH_ODTEN1_DLY_B2_R2RODTEN GENMASK(18, 16) + #define SHURK2_SELPH_ODTEN1_DLY_B2_R2RODTEN_P1 GENMASK(22, 20) + #define SHURK2_SELPH_ODTEN1_DLY_B3_R2RODTEN GENMASK(26, 24) + #define SHURK2_SELPH_ODTEN1_DLY_B3_R2RODTEN_P1 GENMASK(30, 28) +#define SHURK2_SELPH_DQSG0 0x00000c24 + #define SHURK2_SELPH_DQSG0_TX_DLY_R2DQS0_GATED GENMASK(2, 0) + #define SHURK2_SELPH_DQSG0_TX_DLY_R2DQS0_GATED_P1 GENMASK(6, 4) + #define SHURK2_SELPH_DQSG0_TX_DLY_R2DQS1_GATED GENMASK(10, 8) + #define SHURK2_SELPH_DQSG0_TX_DLY_R2DQS1_GATED_P1 GENMASK(14, 12) + #define SHURK2_SELPH_DQSG0_TX_DLY_R2DQS2_GATED GENMASK(18, 16) + #define SHURK2_SELPH_DQSG0_TX_DLY_R2DQS2_GATED_P1 GENMASK(22, 20) + #define SHURK2_SELPH_DQSG0_TX_DLY_R2DQS3_GATED GENMASK(26, 24) + #define SHURK2_SELPH_DQSG0_TX_DLY_R2DQS3_GATED_P1 GENMASK(30, 28) +#define SHURK2_SELPH_DQSG1 0x00000c28 + #define SHURK2_SELPH_DQSG1_REG_DLY_R2DQS0_GATED GENMASK(2, 0) + #define SHURK2_SELPH_DQSG1_REG_DLY_R2DQS0_GATED_P1 GENMASK(6, 4) + #define SHURK2_SELPH_DQSG1_REG_DLY_R2DQS1_GATED GENMASK(10, 8) + #define SHURK2_SELPH_DQSG1_REG_DLY_R2DQS1_GATED_P1 GENMASK(14, 12) + #define SHURK2_SELPH_DQSG1_REG_DLY_R2DQS2_GATED GENMASK(18, 16) + #define SHURK2_SELPH_DQSG1_REG_DLY_R2DQS2_GATED_P1 GENMASK(22, 20) + #define SHURK2_SELPH_DQSG1_REG_DLY_R2DQS3_GATED GENMASK(26, 24) + #define SHURK2_SELPH_DQSG1_REG_DLY_R2DQS3_GATED_P1 GENMASK(30, 28) +#define SHURK2_SELPH_DQ0 0x00000c2c + #define SHURK2_SELPH_DQ0_TX_DLY_R2DQ0 GENMASK(2, 0) + #define SHURK2_SELPH_DQ0_TX_DLY_R2DQ1 GENMASK(6, 4) + #define SHURK2_SELPH_DQ0_TX_DLY_R2DQ2 GENMASK(10, 8) + #define SHURK2_SELPH_DQ0_TX_DLY_R2DQ3 GENMASK(14, 12) + #define SHURK2_SELPH_DQ0_TX_DLY_R2OEN_DQ0 GENMASK(18, 16) + #define SHURK2_SELPH_DQ0_TX_DLY_R2OEN_DQ1 GENMASK(22, 20) + #define SHURK2_SELPH_DQ0_TX_DLY_R2OEN_DQ2 GENMASK(26, 24) + #define SHURK2_SELPH_DQ0_TX_DLY_R2OEN_DQ3 GENMASK(30, 28) +#define SHURK2_SELPH_DQ1 0x00000c30 + #define SHURK2_SELPH_DQ1_TX_DLY_R2DQM0 GENMASK(2, 0) + #define SHURK2_SELPH_DQ1_TX_DLY_R2DQM1 GENMASK(6, 4) + #define SHURK2_SELPH_DQ1_TX_DLY_R2DQM2 GENMASK(10, 8) + #define SHURK2_SELPH_DQ1_TX_DLY_R2DQM3 GENMASK(14, 12) + #define SHURK2_SELPH_DQ1_TX_DLY_R2OEN_DQM0 GENMASK(18, 16) + #define SHURK2_SELPH_DQ1_TX_DLY_R2OEN_DQM1 GENMASK(22, 20) + #define SHURK2_SELPH_DQ1_TX_DLY_R2OEN_DQM2 GENMASK(26, 24) + #define SHURK2_SELPH_DQ1_TX_DLY_R2OEN_DQM3 GENMASK(30, 28) +#define SHURK2_SELPH_DQ2 0x00000c34 + #define SHURK2_SELPH_DQ2_DLY_R2DQ0 GENMASK(2, 0) + #define SHURK2_SELPH_DQ2_DLY_R2DQ1 GENMASK(6, 4) + #define SHURK2_SELPH_DQ2_DLY_R2DQ2 GENMASK(10, 8) + #define SHURK2_SELPH_DQ2_DLY_R2DQ3 GENMASK(14, 12) + #define SHURK2_SELPH_DQ2_DLY_R2OEN_DQ0 GENMASK(18, 16) + #define SHURK2_SELPH_DQ2_DLY_R2OEN_DQ1 GENMASK(22, 20) + #define SHURK2_SELPH_DQ2_DLY_R2OEN_DQ2 GENMASK(26, 24) + #define SHURK2_SELPH_DQ2_DLY_R2OEN_DQ3 GENMASK(30, 28) +#define SHURK2_SELPH_DQ3 0x00000c38 + #define SHURK2_SELPH_DQ3_DLY_R2DQM0 GENMASK(2, 0) + #define SHURK2_SELPH_DQ3_DLY_R2DQM1 GENMASK(6, 4) + #define SHURK2_SELPH_DQ3_DLY_R2DQM2 GENMASK(10, 8) + #define SHURK2_SELPH_DQ3_DLY_R2DQM3 GENMASK(14, 12) + #define SHURK2_SELPH_DQ3_DLY_R2OEN_DQM0 GENMASK(18, 16) + #define SHURK2_SELPH_DQ3_DLY_R2OEN_DQM1 GENMASK(22, 20) + #define SHURK2_SELPH_DQ3_DLY_R2OEN_DQM2 GENMASK(26, 24) + #define SHURK2_SELPH_DQ3_DLY_R2OEN_DQM3 GENMASK(30, 28) +#define SHU1RK2_DQS2DQ_CAL1 0x00000c40 + #define SHU1RK2_DQS2DQ_CAL1_BOOT_ORIG_UI_RK2_DQ0 GENMASK(10, 0) + #define SHU1RK2_DQS2DQ_CAL1_BOOT_ORIG_UI_RK2_DQ1 GENMASK(26, 16) +#define SHU1RK2_DQS2DQ_CAL2 0x00000c44 + #define SHU1RK2_DQS2DQ_CAL2_BOOT_TARG_UI_RK2_DQ0 GENMASK(10, 0) + #define SHU1RK2_DQS2DQ_CAL2_BOOT_TARG_UI_RK2_DQ1 GENMASK(26, 16) +#define SHU1RK2_DQS2DQ_CAL3 0x00000c48 + #define SHU1RK2_DQS2DQ_CAL3_BOOT_TARG_UI_RK2_OEN_DQ0 GENMASK(5, 0) + #define SHU1RK2_DQS2DQ_CAL3_BOOT_TARG_UI_RK2_OEN_DQ1 GENMASK(11, 6) +#define SHU1RK2_DQS2DQ_CAL4 0x00000c4c + #define SHU1RK2_DQS2DQ_CAL4_BOOT_TARG_UI_RK2_OEN_DQM0 GENMASK(5, 0) + #define SHU1RK2_DQS2DQ_CAL4_BOOT_TARG_UI_RK2_OEN_DQM1 GENMASK(11, 6) +#define SHU1RK2_DQS2DQ_CAL5 0x00000c50 + #define SHU1RK2_DQS2DQ_CAL5_BOOT_TARG_UI_RK2_DQM0 GENMASK(10, 0) + #define SHU1RK2_DQS2DQ_CAL5_BOOT_TARG_UI_RK2_DQM1 GENMASK(26, 16) +#define SHU_DQSG_RETRY 0x00000c54 + #define SHU_DQSG_RETRY_R_DQSGRETRY_SW_RESET BIT(0) + #define SHU_DQSG_RETRY_R_DQSG_RETRY_SW_EN BIT(1) + #define SHU_DQSG_RETRY_R_DDR1866_PLUS BIT(2) + #define SHU_DQSG_RETRY_R_RETRY_ONCE BIT(3) + #define SHU_DQSG_RETRY_R_RETRY_3TIMES BIT(4) + #define SHU_DQSG_RETRY_R_RETRY_1RANK BIT(5) + #define SHU_DQSG_RETRY_R_RETRY_SAV_MSK BIT(6) + #define SHU_DQSG_RETRY_R_DM4BYTE BIT(7) + #define SHU_DQSG_RETRY_R_DQSIENLAT GENMASK(11, 8) + #define SHU_DQSG_RETRY_R_STBENCMP_ALLBYTE BIT(12) + #define SHU_DQSG_RETRY_R_XSR_DQSG_RETRY_EN BIT(13) + #define SHU_DQSG_RETRY_R_XSR_RETRY_SPM_MODE BIT(14) + #define SHU_DQSG_RETRY_R_RETRY_CMP_DATA BIT(15) + #define SHU_DQSG_RETRY_R_RETRY_ALE_BLOCK_MASK BIT(20) + #define SHU_DQSG_RETRY_R_RDY_SEL_DLE BIT(21) + #define SHU_DQSG_RETRY_R_RETRY_ROUND_NUM GENMASK(25, 24) + #define SHU_DQSG_RETRY_R_RETRY_RANKSEL_FROM_PHY BIT(28) + #define SHU_DQSG_RETRY_R_RETRY_PA_DSIABLE BIT(29) + #define SHU_DQSG_RETRY_R_RETRY_STBEN_RESET_MSK BIT(30) + #define SHU_DQSG_RETRY_R_RETRY_USE_BURST_MDOE BIT(31) +#define SHU2_ACTIM0 0x00000e00 + #define SHU2_ACTIM0_TWTR GENMASK(3, 0) + #define SHU2_ACTIM0_TWR GENMASK(12, 8) + #define SHU2_ACTIM0_TRRD GENMASK(18, 16) + #define SHU2_ACTIM0_TRCD GENMASK(27, 24) +#define SHU2_ACTIM1 0x00000e04 + #define SHU2_ACTIM1_TRPAB GENMASK(2, 0) + #define SHU2_ACTIM1_TRP GENMASK(11, 8) + #define SHU2_ACTIM1_TRAS GENMASK(19, 16) + #define SHU2_ACTIM1_TRC GENMASK(28, 24) +#define SHU2_ACTIM2 0x00000e08 + #define SHU2_ACTIM2_TXP GENMASK(2, 0) + #define SHU2_ACTIM2_TRTP GENMASK(10, 8) + #define SHU2_ACTIM2_TR2W GENMASK(19, 16) + #define SHU2_ACTIM2_TFAW GENMASK(28, 24) +#define SHU2_ACTIM3 0x00000e0c + #define SHU2_ACTIM3_TRFCPB GENMASK(7, 0) + #define SHU2_ACTIM3_TRFC GENMASK(23, 16) + #define SHU2_ACTIM3_REFCNT GENMASK(31, 24) +#define SHU2_ACTIM4 0x00000e10 + #define SHU2_ACTIM4_TXREFCNT GENMASK(9, 0) + #define SHU2_ACTIM4_REFCNT_FR_CLK GENMASK(23, 16) + #define SHU2_ACTIM4_TZQCS GENMASK(31, 24) +#define SHU2_ACTIM5 0x00000e14 + #define SHU2_ACTIM5_TR2PD GENMASK(4, 0) + #define SHU2_ACTIM5_TWTPD GENMASK(12, 8) + #define SHU2_ACTIM5_TMRR2W GENMASK(27, 24) +#define SHU2_ACTIM6 0x00000e18 + #define SHU2_ACTIM6_BGTCCD GENMASK(1, 0) + #define SHU2_ACTIM6_BGTWTR GENMASK(7, 4) + #define SHU2_ACTIM6_TWRMPR GENMASK(11, 8) + #define SHU2_ACTIM6_BGTRRD GENMASK(14, 12) +#define SHU2_ACTIM_XRT 0x00000e1c + #define SHU2_ACTIM_XRT_XRTR2R GENMASK(4, 0) + #define SHU2_ACTIM_XRT_XRTR2W GENMASK(11, 8) + #define SHU2_ACTIM_XRT_XRTW2R GENMASK(18, 16) + #define SHU2_ACTIM_XRT_XRTW2W GENMASK(27, 24) +#define SHU2_AC_TIME_05T 0x00000e20 + #define SHU2_AC_TIME_05T_TRC_05T BIT(0) + #define SHU2_AC_TIME_05T_TRFCPB_05T BIT(1) + #define SHU2_AC_TIME_05T_TRFC_05T BIT(2) + #define SHU2_AC_TIME_05T_TXP_05T BIT(4) + #define SHU2_AC_TIME_05T_TRTP_05T BIT(5) + #define SHU2_AC_TIME_05T_TRCD_05T BIT(6) + #define SHU2_AC_TIME_05T_TRP_05T BIT(7) + #define SHU2_AC_TIME_05T_TRPAB_05T BIT(8) + #define SHU2_AC_TIME_05T_TRAS_05T BIT(9) + #define SHU2_AC_TIME_05T_TWR_M05T BIT(10) + #define SHU2_AC_TIME_05T_TRRD_05T BIT(12) + #define SHU2_AC_TIME_05T_TFAW_05T BIT(13) + #define SHU2_AC_TIME_05T_TR2PD_05T BIT(15) + #define SHU2_AC_TIME_05T_TWTPD_M05T BIT(16) + #define SHU2_AC_TIME_05T_BGTRRD_05T BIT(21) + #define SHU2_AC_TIME_05T_BGTCCD_05T BIT(22) + #define SHU2_AC_TIME_05T_BGTWTR_05T BIT(23) + #define SHU2_AC_TIME_05T_TR2W_05T BIT(24) + #define SHU2_AC_TIME_05T_TWTR_M05T BIT(25) + #define SHU2_AC_TIME_05T_XRTR2W_05T BIT(26) + #define SHU2_AC_TIME_05T_XRTW2R_M05T BIT(27) +#define SHU2_AC_DERATING0 0x00000e24 + #define SHU2_AC_DERATING0_ACDERATEEN BIT(0) + #define SHU2_AC_DERATING0_TRRD_DERATE GENMASK(18, 16) + #define SHU2_AC_DERATING0_TRCD_DERATE GENMASK(27, 24) +#define SHU2_AC_DERATING1 0x00000e28 + #define SHU2_AC_DERATING1_TRPAB_DERATE GENMASK(2, 0) + #define SHU2_AC_DERATING1_TRP_DERATE GENMASK(11, 8) + #define SHU2_AC_DERATING1_TRAS_DERATE GENMASK(19, 16) + #define SHU2_AC_DERATING1_TRC_DERATE GENMASK(28, 24) +#define SHU2_AC_DERATING_05T 0x00000e30 + #define SHU2_AC_DERATING_05T_TRC_05T_DERATE BIT(0) + #define SHU2_AC_DERATING_05T_TRCD_05T_DERATE BIT(6) + #define SHU2_AC_DERATING_05T_TRP_05T_DERATE BIT(7) + #define SHU2_AC_DERATING_05T_TRPAB_05T_DERATE BIT(8) + #define SHU2_AC_DERATING_05T_TRAS_05T_DERATE BIT(9) + #define SHU2_AC_DERATING_05T_TRRD_05T_DERATE BIT(12) +#define SHU2_CONF0 0x00000e40 + #define SHU2_CONF0_DMPGTIM GENMASK(5, 0) + #define SHU2_CONF0_ADVREFEN BIT(6) + #define SHU2_CONF0_ADVPREEN BIT(7) + #define SHU2_CONF0_TRFCPBIG BIT(9) + #define SHU2_CONF0_REFTHD GENMASK(15, 12) + #define SHU2_CONF0_REQQUE_DEPTH GENMASK(19, 16) + #define SHU2_CONF0_FREQDIV4 BIT(24) + #define SHU2_CONF0_FDIV2 BIT(25) + #define SHU2_CONF0_CL2 BIT(27) + #define SHU2_CONF0_BL2 BIT(28) + #define SHU2_CONF0_BL4 BIT(29) + #define SHU2_CONF0_MATYPE GENMASK(31, 30) +#define SHU2_CONF1 0x00000e44 + #define SHU2_CONF1_DATLAT GENMASK(4, 0) + #define SHU2_CONF1_DATLAT_DSEL GENMASK(12, 8) + #define SHU2_CONF1_REFBW_FR GENMASK(25, 16) + #define SHU2_CONF1_DATLAT_DSEL_PHY GENMASK(30, 26) + #define SHU2_CONF1_TREFBWIG BIT(31) +#define SHU2_CONF2 0x00000e48 + #define SHU2_CONF2_TCMDO1LAT GENMASK(7, 0) + #define SHU2_CONF2_FSPCHG_PRDCNT GENMASK(15, 8) + #define SHU2_CONF2_DCMDLYREF GENMASK(18, 16) + #define SHU2_CONF2_DQCMD BIT(25) + #define SHU2_CONF2_DQ16COM1 BIT(26) + #define SHU2_CONF2_RA15TOCS1 BIT(27) + #define SHU2_CONF2_WPRE2T BIT(28) + #define SHU2_CONF2_FASTWAKE2 BIT(29) + #define SHU2_CONF2_DAREFEN BIT(30) + #define SHU2_CONF2_FASTWAKE BIT(31) +#define SHU2_CONF3 0x00000e4c + #define SHU2_CONF3_ZQCSCNT GENMASK(15, 0) + #define SHU2_CONF3_REFRCNT GENMASK(24, 16) +#define SHU2_STBCAL 0x00000e50 + #define SHU2_STBCAL_DMSTBLAT GENMASK(1, 0) + #define SHU2_STBCAL_PICGLAT GENMASK(6, 4) + #define SHU2_STBCAL_DQSG_MODE BIT(8) +#define SHU2_DQSOSCTHRD 0x00000e54 + #define SHU2_DQSOSCTHRD_DQSOSCTHRD_INC_RK0 GENMASK(11, 0) + #define SHU2_DQSOSCTHRD_DQSOSCTHRD_DEC_RK0 GENMASK(23, 12) + #define SHU2_DQSOSCTHRD_DQSOSCTHRD_INC_RK1_7TO0 GENMASK(31, 24) +#define SHU2_RANKCTL 0x00000e58 + #define SHU2_RANKCTL_RANKINCTL_RXDLY GENMASK(3, 0) + #define SHU2_RANKCTL_TXRANKINCTL_TXDLY GENMASK(11, 8) + #define SHU2_RANKCTL_TXRANKINCTL GENMASK(15, 12) + #define SHU2_RANKCTL_TXRANKINCTL_ROOT GENMASK(19, 16) + #define SHU2_RANKCTL_RANKINCTL GENMASK(23, 20) + #define SHU2_RANKCTL_RANKINCTL_ROOT1 GENMASK(27, 24) + #define SHU2_RANKCTL_RANKINCTL_PHY GENMASK(31, 28) +#define SHU2_CKECTRL 0x00000e5c + #define SHU2_CKECTRL_CMDCKE GENMASK(18, 16) + #define SHU2_CKECTRL_CKEPRD GENMASK(22, 20) + #define SHU2_CKECTRL_TCKESRX GENMASK(25, 24) + #define SHU2_CKECTRL_SREF_CK_DLY GENMASK(29, 28) +#define SHU2_ODTCTRL 0x00000e60 + #define SHU2_ODTCTRL_ROEN BIT(0) + #define SHU2_ODTCTRL_WOEN BIT(1) + #define SHU2_ODTCTRL_RODTEN_SELPH_CG_IG BIT(2) + #define SHU2_ODTCTRL_RODTENSTB_SELPH_CG_IG BIT(3) + #define SHU2_ODTCTRL_RODT GENMASK(7, 4) + #define SHU2_ODTCTRL_TWODT GENMASK(22, 16) + #define SHU2_ODTCTRL_FIXRODT BIT(27) + #define SHU2_ODTCTRL_RODTE2 BIT(30) + #define SHU2_ODTCTRL_RODTE BIT(31) +#define SHU2_IMPCAL1 0x00000e64 + #define SHU2_IMPCAL1_IMPCAL_CHKCYCLE GENMASK(2, 0) + #define SHU2_IMPCAL1_IMPDRVP GENMASK(8, 4) + #define SHU2_IMPCAL1_IMPDRVN GENMASK(15, 11) + #define SHU2_IMPCAL1_IMPCAL_CALEN_CYCLE GENMASK(19, 17) + #define SHU2_IMPCAL1_IMPCALCNT GENMASK(27, 20) + #define SHU2_IMPCAL1_IMPCAL_CALICNT GENMASK(31, 28) +#define SHU2_DQSOSC_PRD 0x00000e68 + #define SHU2_DQSOSC_PRD_DQSOSC_PRDCNT GENMASK(9, 0) + #define SHU2_DQSOSC_PRD_DQSOSCTHRD_INC_RK1_11TO8 GENMASK(19, 16) + #define SHU2_DQSOSC_PRD_DQSOSCTHRD_DEC_RK1 GENMASK(31, 20) +#define SHU2_DQSOSCR 0x00000e6c + #define SHU2_DQSOSCR_DQSOSCRCNT GENMASK(7, 0) + #define SHU2_DQSOSCR_DQSOSC_DELTA GENMASK(31, 16) +#define SHU2_DQSOSCR2 0x00000e70 + #define SHU2_DQSOSCR2_DQSOSCENCNT GENMASK(15, 0) + #define SHU2_DQSOSCR2_DQSOSC_ADV_SEL GENMASK(17, 16) + #define SHU2_DQSOSCR2_DQSOSC_DRS_ADV_SEL GENMASK(19, 18) +#define SHU2_RODTENSTB 0x00000e74 + #define SHU2_RODTENSTB_RODTEN_MCK_MODESEL BIT(0) + #define SHU2_RODTENSTB_RODTEN_P1_ENABLE BIT(1) + #define SHU2_RODTENSTB_RODTENSTB_OFFSET GENMASK(7, 2) + #define SHU2_RODTENSTB_RODTENSTB_EXT GENMASK(23, 8) + #define SHU2_RODTENSTB_RODTENSTB_4BYTE_EN BIT(31) +#define SHU2_PIPE 0x00000e78 + #define SHU2_PIPE_PHYRXPIPE1 BIT(0) + #define SHU2_PIPE_PHYRXPIPE2 BIT(1) + #define SHU2_PIPE_PHYRXPIPE3 BIT(2) + #define SHU2_PIPE_PHYRXRDSLPIPE1 BIT(4) + #define SHU2_PIPE_PHYRXRDSLPIPE2 BIT(5) + #define SHU2_PIPE_PHYRXRDSLPIPE3 BIT(6) + #define SHU2_PIPE_PHYPIPE1EN BIT(8) + #define SHU2_PIPE_PHYPIPE2EN BIT(9) + #define SHU2_PIPE_PHYPIPE3EN BIT(10) + #define SHU2_PIPE_DLE_LAST_EXTEND3 BIT(26) + #define SHU2_PIPE_READ_START_EXTEND3 BIT(27) + #define SHU2_PIPE_DLE_LAST_EXTEND2 BIT(28) + #define SHU2_PIPE_READ_START_EXTEND2 BIT(29) + #define SHU2_PIPE_DLE_LAST_EXTEND1 BIT(30) + #define SHU2_PIPE_READ_START_EXTEND1 BIT(31) +#define SHU2_TEST1 0x00000e7c + #define SHU2_TEST1_LATNORMPOP GENMASK(12, 8) + #define SHU2_TEST1_DQSICALBLCOK_CNT GENMASK(22, 20) + #define SHU2_TEST1_DQSICALI_NEW BIT(23) +#define SHU2_SELPH_CA1 0x00000e80 + #define SHU2_SELPH_CA1_TXDLY_CS GENMASK(2, 0) + #define SHU2_SELPH_CA1_TXDLY_CKE GENMASK(6, 4) + #define SHU2_SELPH_CA1_TXDLY_ODT GENMASK(10, 8) + #define SHU2_SELPH_CA1_TXDLY_RESET GENMASK(14, 12) + #define SHU2_SELPH_CA1_TXDLY_WE GENMASK(18, 16) + #define SHU2_SELPH_CA1_TXDLY_CAS GENMASK(22, 20) + #define SHU2_SELPH_CA1_TXDLY_RAS GENMASK(26, 24) + #define SHU2_SELPH_CA1_TXDLY_CS1 GENMASK(30, 28) +#define SHU2_SELPH_CA2 0x00000e84 + #define SHU2_SELPH_CA2_TXDLY_BA0 GENMASK(2, 0) + #define SHU2_SELPH_CA2_TXDLY_BA1 GENMASK(6, 4) + #define SHU2_SELPH_CA2_TXDLY_BA2 GENMASK(10, 8) + #define SHU2_SELPH_CA2_TXDLY_CMD GENMASK(20, 16) + #define SHU2_SELPH_CA2_TXDLY_CKE1 GENMASK(26, 24) +#define SHU2_SELPH_CA3 0x00000e88 + #define SHU2_SELPH_CA3_TXDLY_RA0 GENMASK(2, 0) + #define SHU2_SELPH_CA3_TXDLY_RA1 GENMASK(6, 4) + #define SHU2_SELPH_CA3_TXDLY_RA2 GENMASK(10, 8) + #define SHU2_SELPH_CA3_TXDLY_RA3 GENMASK(14, 12) + #define SHU2_SELPH_CA3_TXDLY_RA4 GENMASK(18, 16) + #define SHU2_SELPH_CA3_TXDLY_RA5 GENMASK(22, 20) + #define SHU2_SELPH_CA3_TXDLY_RA6 GENMASK(26, 24) + #define SHU2_SELPH_CA3_TXDLY_RA7 GENMASK(30, 28) +#define SHU2_SELPH_CA4 0x00000e8c + #define SHU2_SELPH_CA4_TXDLY_RA8 GENMASK(2, 0) + #define SHU2_SELPH_CA4_TXDLY_RA9 GENMASK(6, 4) + #define SHU2_SELPH_CA4_TXDLY_RA10 GENMASK(10, 8) + #define SHU2_SELPH_CA4_TXDLY_RA11 GENMASK(14, 12) + #define SHU2_SELPH_CA4_TXDLY_RA12 GENMASK(18, 16) + #define SHU2_SELPH_CA4_TXDLY_RA13 GENMASK(22, 20) + #define SHU2_SELPH_CA4_TXDLY_RA14 GENMASK(26, 24) + #define SHU2_SELPH_CA4_TXDLY_RA15 GENMASK(30, 28) +#define SHU2_SELPH_CA5 0x00000e90 + #define SHU2_SELPH_CA5_DLY_CS GENMASK(2, 0) + #define SHU2_SELPH_CA5_DLY_CKE GENMASK(6, 4) + #define SHU2_SELPH_CA5_DLY_ODT GENMASK(10, 8) + #define SHU2_SELPH_CA5_DLY_RESET GENMASK(14, 12) + #define SHU2_SELPH_CA5_DLY_WE GENMASK(18, 16) + #define SHU2_SELPH_CA5_DLY_CAS GENMASK(22, 20) + #define SHU2_SELPH_CA5_DLY_RAS GENMASK(26, 24) + #define SHU2_SELPH_CA5_DLY_CS1 GENMASK(30, 28) +#define SHU2_SELPH_CA6 0x00000e94 + #define SHU2_SELPH_CA6_DLY_BA0 GENMASK(2, 0) + #define SHU2_SELPH_CA6_DLY_BA1 GENMASK(6, 4) + #define SHU2_SELPH_CA6_DLY_BA2 GENMASK(10, 8) + #define SHU2_SELPH_CA6_DLY_CKE1 GENMASK(26, 24) +#define SHU2_SELPH_CA7 0x00000e98 + #define SHU2_SELPH_CA7_DLY_RA0 GENMASK(2, 0) + #define SHU2_SELPH_CA7_DLY_RA1 GENMASK(6, 4) + #define SHU2_SELPH_CA7_DLY_RA2 GENMASK(10, 8) + #define SHU2_SELPH_CA7_DLY_RA3 GENMASK(14, 12) + #define SHU2_SELPH_CA7_DLY_RA4 GENMASK(18, 16) + #define SHU2_SELPH_CA7_DLY_RA5 GENMASK(22, 20) + #define SHU2_SELPH_CA7_DLY_RA6 GENMASK(26, 24) + #define SHU2_SELPH_CA7_DLY_RA7 GENMASK(30, 28) +#define SHU2_SELPH_CA8 0x00000e9c + #define SHU2_SELPH_CA8_DLY_RA8 GENMASK(2, 0) + #define SHU2_SELPH_CA8_DLY_RA9 GENMASK(6, 4) + #define SHU2_SELPH_CA8_DLY_RA10 GENMASK(10, 8) + #define SHU2_SELPH_CA8_DLY_RA11 GENMASK(14, 12) + #define SHU2_SELPH_CA8_DLY_RA12 GENMASK(18, 16) + #define SHU2_SELPH_CA8_DLY_RA13 GENMASK(22, 20) + #define SHU2_SELPH_CA8_DLY_RA14 GENMASK(26, 24) + #define SHU2_SELPH_CA8_DLY_RA15 GENMASK(30, 28) +#define SHU2_SELPH_DQS0 0x00000ea0 + #define SHU2_SELPH_DQS0_TXDLY_DQS0 GENMASK(2, 0) + #define SHU2_SELPH_DQS0_TXDLY_DQS1 GENMASK(6, 4) + #define SHU2_SELPH_DQS0_TXDLY_DQS2 GENMASK(10, 8) + #define SHU2_SELPH_DQS0_TXDLY_DQS3 GENMASK(14, 12) + #define SHU2_SELPH_DQS0_TXDLY_OEN_DQS0 GENMASK(18, 16) + #define SHU2_SELPH_DQS0_TXDLY_OEN_DQS1 GENMASK(22, 20) + #define SHU2_SELPH_DQS0_TXDLY_OEN_DQS2 GENMASK(26, 24) + #define SHU2_SELPH_DQS0_TXDLY_OEN_DQS3 GENMASK(30, 28) +#define SHU2_SELPH_DQS1 0x00000ea4 + #define SHU2_SELPH_DQS1_DLY_DQS0 GENMASK(2, 0) + #define SHU2_SELPH_DQS1_DLY_DQS1 GENMASK(6, 4) + #define SHU2_SELPH_DQS1_DLY_DQS2 GENMASK(10, 8) + #define SHU2_SELPH_DQS1_DLY_DQS3 GENMASK(14, 12) + #define SHU2_SELPH_DQS1_DLY_OEN_DQS0 GENMASK(18, 16) + #define SHU2_SELPH_DQS1_DLY_OEN_DQS1 GENMASK(22, 20) + #define SHU2_SELPH_DQS1_DLY_OEN_DQS2 GENMASK(26, 24) + #define SHU2_SELPH_DQS1_DLY_OEN_DQS3 GENMASK(30, 28) +#define SHU2_DRVING1 0x00000ea8 + #define SHU2_DRVING1_DQDRVN2 GENMASK(4, 0) + #define SHU2_DRVING1_DQDRVP2 GENMASK(9, 5) + #define SHU2_DRVING1_DQSDRVN1 GENMASK(14, 10) + #define SHU2_DRVING1_DQSDRVP1 GENMASK(19, 15) + #define SHU2_DRVING1_DQSDRVN2 GENMASK(24, 20) + #define SHU2_DRVING1_DQSDRVP2 GENMASK(29, 25) + #define SHU2_DRVING1_DIS_IMP_ODTN_TRACK BIT(30) + #define SHU2_DRVING1_DIS_IMPCAL_HW BIT(31) +#define SHU2_DRVING2 0x00000eac + #define SHU2_DRVING2_CMDDRVN1 GENMASK(4, 0) + #define SHU2_DRVING2_CMDDRVP1 GENMASK(9, 5) + #define SHU2_DRVING2_CMDDRVN2 GENMASK(14, 10) + #define SHU2_DRVING2_CMDDRVP2 GENMASK(19, 15) + #define SHU2_DRVING2_DQDRVN1 GENMASK(24, 20) + #define SHU2_DRVING2_DQDRVP1 GENMASK(29, 25) + #define SHU2_DRVING2_DIS_IMPCAL_ODT_EN BIT(31) +#define SHU2_DRVING3 0x00000eb0 + #define SHU2_DRVING3_DQODTN2 GENMASK(4, 0) + #define SHU2_DRVING3_DQODTP2 GENMASK(9, 5) + #define SHU2_DRVING3_DQSODTN GENMASK(14, 10) + #define SHU2_DRVING3_DQSODTP GENMASK(19, 15) + #define SHU2_DRVING3_DQSODTN2 GENMASK(24, 20) + #define SHU2_DRVING3_DQSODTP2 GENMASK(29, 25) +#define SHU2_DRVING4 0x00000eb4 + #define SHU2_DRVING4_CMDODTN1 GENMASK(4, 0) + #define SHU2_DRVING4_CMDODTP1 GENMASK(9, 5) + #define SHU2_DRVING4_CMDODTN2 GENMASK(14, 10) + #define SHU2_DRVING4_CMDODTP2 GENMASK(19, 15) + #define SHU2_DRVING4_DQODTN1 GENMASK(24, 20) + #define SHU2_DRVING4_DQODTP1 GENMASK(29, 25) +#define SHU2_DRVING5 0x00000eb8 + #define SHU2_DRVING5_DQCODTN2 GENMASK(4, 0) + #define SHU2_DRVING5_DQCODTP2 GENMASK(9, 5) + #define SHU2_DRVING5_DQCDRVN1 GENMASK(14, 10) + #define SHU2_DRVING5_DQCDRVP1 GENMASK(19, 15) + #define SHU2_DRVING5_DQCDRVN2 GENMASK(24, 20) + #define SHU2_DRVING5_DQCDRVP2 GENMASK(29, 25) +#define SHU2_DRVING6 0x00000ebc + #define SHU2_DRVING6_DQCODTN1 GENMASK(24, 20) + #define SHU2_DRVING6_DQCODTP1 GENMASK(29, 25) +#define SHU2_WODT 0x00000ec0 + #define SHU2_WODT_DISWODT GENMASK(2, 0) + #define SHU2_WODT_WODTFIX BIT(3) + #define SHU2_WODT_WODTFIXOFF BIT(4) + #define SHU2_WODT_DISWODTE BIT(5) + #define SHU2_WODT_DISWODTE2 BIT(6) + #define SHU2_WODT_WODTPDEN BIT(7) + #define SHU2_WODT_DQOE_CNT GENMASK(10, 8) + #define SHU2_WODT_DQOE_OPT BIT(11) + #define SHU2_WODT_TXUPD_SEL GENMASK(13, 12) + #define SHU2_WODT_TXUPD_W2R_SEL GENMASK(16, 14) + #define SHU2_WODT_DBIWR BIT(29) + #define SHU2_WODT_TWPSTEXT BIT(30) + #define SHU2_WODT_WPST2T BIT(31) +#define SHU2_DQSG 0x00000ec4 + #define SHU2_DQSG_DLLFRZRFCOPT GENMASK(1, 0) + #define SHU2_DQSG_DLLFRZWROPT GENMASK(5, 4) + #define SHU2_DQSG_R_RSTBCNT_LATCH_OPT GENMASK(10, 8) + #define SHU2_DQSG_STB_UPDMASK_EN BIT(11) + #define SHU2_DQSG_STB_UPDMASKCYC GENMASK(15, 12) + #define SHU2_DQSG_DQSINCTL_PRE_SEL BIT(16) + #define SHU2_DQSG_SCINTV GENMASK(25, 20) +#define SHU2_SCINTV 0x00000ec8 + #define SHU2_SCINTV_ODTREN BIT(0) + #define SHU2_SCINTV_TZQLAT GENMASK(5, 1) + #define SHU2_SCINTV_TZQLAT2 GENMASK(10, 6) + #define SHU2_SCINTV_RDDQC_INTV GENMASK(12, 11) + #define SHU2_SCINTV_MRW_INTV GENMASK(17, 13) + #define SHU2_SCINTV_DQS2DQ_SHU_PITHRD GENMASK(23, 18) + #define SHU2_SCINTV_DQS2DQ_FILT_PITHRD GENMASK(29, 24) + #define SHU2_SCINTV_DQSOSCENDIS BIT(30) +#define SHU2_MISC 0x00000ecc + #define SHU2_MISC_REQQUE_MAXCNT GENMASK(3, 0) + #define SHU2_MISC_CKEHCMD GENMASK(5, 4) + #define SHU2_MISC_NORMPOP_LEN GENMASK(10, 8) + #define SHU2_MISC_PREA_INTV GENMASK(16, 12) +#define SHU2_DQS2DQ_TX 0x00000ed0 + #define SHU2_DQS2DQ_TX_OE2DQ_OFFSET GENMASK(4, 0) +#define SHU2_HWSET_MR2 0x00000ed4 + #define SHU2_HWSET_MR2_HWSET_MR2_MRSMA GENMASK(12, 0) + #define SHU2_HWSET_MR2_HWSET_MR2_OP GENMASK(23, 16) +#define SHU2_HWSET_MR13 0x00000ed8 + #define SHU2_HWSET_MR13_HWSET_MR13_MRSMA GENMASK(12, 0) + #define SHU2_HWSET_MR13_HWSET_MR13_OP GENMASK(23, 16) +#define SHU2_HWSET_VRCG 0x00000edc + #define SHU2_HWSET_VRCG_HWSET_VRCG_MRSMA GENMASK(12, 0) + #define SHU2_HWSET_VRCG_HWSET_VRCG_OP GENMASK(23, 16) +#define SHU2_APHY_TX_PICG_CTRL 0x00000ee4 + #define SHU2_APHY_TX_PICG_CTRL_APHYPI_CG_CK_SEL GENMASK(23, 20) + #define SHU2_APHY_TX_PICG_CTRL_APHYPI_CG_CK_OPT BIT(24) + #define SHU2_APHY_TX_PICG_CTRL_DDRPHY_CLK_DYN_GATING_SEL GENMASK(30, 27) + #define SHU2_APHY_TX_PICG_CTRL_DDRPHY_CLK_EN_OPT BIT(31) +#define SHU2RK0_DQSCTL 0x00001000 + #define SHU2RK0_DQSCTL_DQSINCTL GENMASK(3, 0) +#define SHU2RK0_DQSIEN 0x00001004 + #define SHU2RK0_DQSIEN_R0DQS0IEN GENMASK(6, 0) + #define SHU2RK0_DQSIEN_R0DQS1IEN GENMASK(14, 8) + #define SHU2RK0_DQSIEN_R0DQS2IEN GENMASK(22, 16) + #define SHU2RK0_DQSIEN_R0DQS3IEN GENMASK(30, 24) +#define SHU2RK0_DQSCAL 0x00001008 + #define SHU2RK0_DQSCAL_R0DQSIENLLMT GENMASK(6, 0) + #define SHU2RK0_DQSCAL_R0DQSIENLLMTEN BIT(7) + #define SHU2RK0_DQSCAL_R0DQSIENHLMT GENMASK(14, 8) + #define SHU2RK0_DQSCAL_R0DQSIENHLMTEN BIT(15) +#define SHU2RK0_PI 0x0000100c + #define SHU2RK0_PI_RK0_ARPI_DQ_B1 GENMASK(5, 0) + #define SHU2RK0_PI_RK0_ARPI_DQ_B0 GENMASK(13, 8) + #define SHU2RK0_PI_RK0_ARPI_DQM_B1 GENMASK(21, 16) + #define SHU2RK0_PI_RK0_ARPI_DQM_B0 GENMASK(29, 24) +#define SHU2RK0_DQSOSC 0x00001010 + #define SHU2RK0_DQSOSC_DQSOSC_BASE_RK0 GENMASK(15, 0) + #define SHU2RK0_DQSOSC_DQSOSC_BASE_RK0_B1 GENMASK(31, 16) +#define SHU2RK0_SELPH_ODTEN0 0x0000101c + #define SHU2RK0_SELPH_ODTEN0_TXDLY_B0_RODTEN GENMASK(2, 0) + #define SHU2RK0_SELPH_ODTEN0_TXDLY_B0_RODTEN_P1 GENMASK(6, 4) + #define SHU2RK0_SELPH_ODTEN0_TXDLY_B1_RODTEN GENMASK(10, 8) + #define SHU2RK0_SELPH_ODTEN0_TXDLY_B1_RODTEN_P1 GENMASK(14, 12) + #define SHU2RK0_SELPH_ODTEN0_TXDLY_B2_RODTEN GENMASK(18, 16) + #define SHU2RK0_SELPH_ODTEN0_TXDLY_B2_RODTEN_P1 GENMASK(22, 20) + #define SHU2RK0_SELPH_ODTEN0_TXDLY_B3_RODTEN GENMASK(26, 24) + #define SHU2RK0_SELPH_ODTEN0_TXDLY_B3_RODTEN_P1 GENMASK(30, 28) +#define SHU2RK0_SELPH_ODTEN1 0x00001020 + #define SHU2RK0_SELPH_ODTEN1_DLY_B0_RODTEN GENMASK(2, 0) + #define SHU2RK0_SELPH_ODTEN1_DLY_B0_RODTEN_P1 GENMASK(6, 4) + #define SHU2RK0_SELPH_ODTEN1_DLY_B1_RODTEN GENMASK(10, 8) + #define SHU2RK0_SELPH_ODTEN1_DLY_B1_RODTEN_P1 GENMASK(14, 12) + #define SHU2RK0_SELPH_ODTEN1_DLY_B2_RODTEN GENMASK(18, 16) + #define SHU2RK0_SELPH_ODTEN1_DLY_B2_RODTEN_P1 GENMASK(22, 20) + #define SHU2RK0_SELPH_ODTEN1_DLY_B3_RODTEN GENMASK(26, 24) + #define SHU2RK0_SELPH_ODTEN1_DLY_B3_RODTEN_P1 GENMASK(30, 28) +#define SHU2RK0_SELPH_DQSG0 0x00001024 + #define SHU2RK0_SELPH_DQSG0_TX_DLY_DQS0_GATED GENMASK(2, 0) + #define SHU2RK0_SELPH_DQSG0_TX_DLY_DQS0_GATED_P1 GENMASK(6, 4) + #define SHU2RK0_SELPH_DQSG0_TX_DLY_DQS1_GATED GENMASK(10, 8) + #define SHU2RK0_SELPH_DQSG0_TX_DLY_DQS1_GATED_P1 GENMASK(14, 12) + #define SHU2RK0_SELPH_DQSG0_TX_DLY_DQS2_GATED GENMASK(18, 16) + #define SHU2RK0_SELPH_DQSG0_TX_DLY_DQS2_GATED_P1 GENMASK(22, 20) + #define SHU2RK0_SELPH_DQSG0_TX_DLY_DQS3_GATED GENMASK(26, 24) + #define SHU2RK0_SELPH_DQSG0_TX_DLY_DQS3_GATED_P1 GENMASK(30, 28) +#define SHU2RK0_SELPH_DQSG1 0x00001028 + #define SHU2RK0_SELPH_DQSG1_REG_DLY_DQS0_GATED GENMASK(2, 0) + #define SHU2RK0_SELPH_DQSG1_REG_DLY_DQS0_GATED_P1 GENMASK(6, 4) + #define SHU2RK0_SELPH_DQSG1_REG_DLY_DQS1_GATED GENMASK(10, 8) + #define SHU2RK0_SELPH_DQSG1_REG_DLY_DQS1_GATED_P1 GENMASK(14, 12) + #define SHU2RK0_SELPH_DQSG1_REG_DLY_DQS2_GATED GENMASK(18, 16) + #define SHU2RK0_SELPH_DQSG1_REG_DLY_DQS2_GATED_P1 GENMASK(22, 20) + #define SHU2RK0_SELPH_DQSG1_REG_DLY_DQS3_GATED GENMASK(26, 24) + #define SHU2RK0_SELPH_DQSG1_REG_DLY_DQS3_GATED_P1 GENMASK(30, 28) +#define SHU2RK0_SELPH_DQ0 0x0000102c + #define SHU2RK0_SELPH_DQ0_TXDLY_DQ0 GENMASK(2, 0) + #define SHU2RK0_SELPH_DQ0_TXDLY_DQ1 GENMASK(6, 4) + #define SHU2RK0_SELPH_DQ0_TXDLY_DQ2 GENMASK(10, 8) + #define SHU2RK0_SELPH_DQ0_TXDLY_DQ3 GENMASK(14, 12) + #define SHU2RK0_SELPH_DQ0_TXDLY_OEN_DQ0 GENMASK(18, 16) + #define SHU2RK0_SELPH_DQ0_TXDLY_OEN_DQ1 GENMASK(22, 20) + #define SHU2RK0_SELPH_DQ0_TXDLY_OEN_DQ2 GENMASK(26, 24) + #define SHU2RK0_SELPH_DQ0_TXDLY_OEN_DQ3 GENMASK(30, 28) +#define SHU2RK0_SELPH_DQ1 0x00001030 + #define SHU2RK0_SELPH_DQ1_TXDLY_DQM0 GENMASK(2, 0) + #define SHU2RK0_SELPH_DQ1_TXDLY_DQM1 GENMASK(6, 4) + #define SHU2RK0_SELPH_DQ1_TXDLY_DQM2 GENMASK(10, 8) + #define SHU2RK0_SELPH_DQ1_TXDLY_DQM3 GENMASK(14, 12) + #define SHU2RK0_SELPH_DQ1_TXDLY_OEN_DQM0 GENMASK(18, 16) + #define SHU2RK0_SELPH_DQ1_TXDLY_OEN_DQM1 GENMASK(22, 20) + #define SHU2RK0_SELPH_DQ1_TXDLY_OEN_DQM2 GENMASK(26, 24) + #define SHU2RK0_SELPH_DQ1_TXDLY_OEN_DQM3 GENMASK(30, 28) +#define SHU2RK0_SELPH_DQ2 0x00001034 + #define SHU2RK0_SELPH_DQ2_DLY_DQ0 GENMASK(2, 0) + #define SHU2RK0_SELPH_DQ2_DLY_DQ1 GENMASK(6, 4) + #define SHU2RK0_SELPH_DQ2_DLY_DQ2 GENMASK(10, 8) + #define SHU2RK0_SELPH_DQ2_DLY_DQ3 GENMASK(14, 12) + #define SHU2RK0_SELPH_DQ2_DLY_OEN_DQ0 GENMASK(18, 16) + #define SHU2RK0_SELPH_DQ2_DLY_OEN_DQ1 GENMASK(22, 20) + #define SHU2RK0_SELPH_DQ2_DLY_OEN_DQ2 GENMASK(26, 24) + #define SHU2RK0_SELPH_DQ2_DLY_OEN_DQ3 GENMASK(30, 28) +#define SHU2RK0_SELPH_DQ3 0x00001038 + #define SHU2RK0_SELPH_DQ3_DLY_DQM0 GENMASK(2, 0) + #define SHU2RK0_SELPH_DQ3_DLY_DQM1 GENMASK(6, 4) + #define SHU2RK0_SELPH_DQ3_DLY_DQM2 GENMASK(10, 8) + #define SHU2RK0_SELPH_DQ3_DLY_DQM3 GENMASK(14, 12) + #define SHU2RK0_SELPH_DQ3_DLY_OEN_DQM0 GENMASK(18, 16) + #define SHU2RK0_SELPH_DQ3_DLY_OEN_DQM1 GENMASK(22, 20) + #define SHU2RK0_SELPH_DQ3_DLY_OEN_DQM2 GENMASK(26, 24) + #define SHU2RK0_SELPH_DQ3_DLY_OEN_DQM3 GENMASK(30, 28) +#define SHU2RK0_DQS2DQ_CAL1 0x00001040 + #define SHU2RK0_DQS2DQ_CAL1_BOOT_ORIG_UI_RK0_DQ0 GENMASK(10, 0) + #define SHU2RK0_DQS2DQ_CAL1_BOOT_ORIG_UI_RK0_DQ1 GENMASK(26, 16) +#define SHU2RK0_DQS2DQ_CAL2 0x00001044 + #define SHU2RK0_DQS2DQ_CAL2_BOOT_TARG_UI_RK0_DQ0 GENMASK(10, 0) + #define SHU2RK0_DQS2DQ_CAL2_BOOT_TARG_UI_RK0_DQ1 GENMASK(26, 16) +#define SHU2RK0_DQS2DQ_CAL3 0x00001048 + #define SHU2RK0_DQS2DQ_CAL3_BOOT_TARG_UI_RK0_OEN_DQ0 GENMASK(5, 0) + #define SHU2RK0_DQS2DQ_CAL3_BOOT_TARG_UI_RK0_OEN_DQ1 GENMASK(11, 6) + #define SHU2RK0_DQS2DQ_CAL3_BOOT_TARG_UI_RK0_OEN_DQ0_B4TO0 GENMASK(16, 12) + #define SHU2RK0_DQS2DQ_CAL3_BOOT_TARG_UI_RK0_OEN_DQ1_B4TO0 GENMASK(21, 17) +#define SHU2RK0_DQS2DQ_CAL4 0x0000104c + #define SHU2RK0_DQS2DQ_CAL4_BOOT_TARG_UI_RK0_OEN_DQM0 GENMASK(5, 0) + #define SHU2RK0_DQS2DQ_CAL4_BOOT_TARG_UI_RK0_OEN_DQM1 GENMASK(11, 6) + #define SHU2RK0_DQS2DQ_CAL4_BOOT_TARG_UI_RK0_OEN_DQM0_B4TO0 GENMASK(16, 12) + #define SHU2RK0_DQS2DQ_CAL4_BOOT_TARG_UI_RK0_OEN_DQM1_B4TO0 GENMASK(21, 17) +#define SHU2RK0_DQS2DQ_CAL5 0x00001050 + #define SHU2RK0_DQS2DQ_CAL5_BOOT_TARG_UI_RK0_DQM0 GENMASK(10, 0) + #define SHU2RK0_DQS2DQ_CAL5_BOOT_TARG_UI_RK0_DQM1 GENMASK(26, 16) +#define SHU2RK1_DQSCTL 0x00001100 + #define SHU2RK1_DQSCTL_R1DQSINCTL GENMASK(3, 0) +#define SHU2RK1_DQSIEN 0x00001104 + #define SHU2RK1_DQSIEN_R1DQS0IEN GENMASK(6, 0) + #define SHU2RK1_DQSIEN_R1DQS1IEN GENMASK(14, 8) + #define SHU2RK1_DQSIEN_R1DQS2IEN GENMASK(22, 16) + #define SHU2RK1_DQSIEN_R1DQS3IEN GENMASK(30, 24) +#define SHU2RK1_DQSCAL 0x00001108 + #define SHU2RK1_DQSCAL_R1DQSIENLLMT GENMASK(6, 0) + #define SHU2RK1_DQSCAL_R1DQSIENLLMTEN BIT(7) + #define SHU2RK1_DQSCAL_R1DQSIENHLMT GENMASK(14, 8) + #define SHU2RK1_DQSCAL_R1DQSIENHLMTEN BIT(15) +#define SHU2RK1_PI 0x0000110c + #define SHU2RK1_PI_RK1_ARPI_DQ_B1 GENMASK(5, 0) + #define SHU2RK1_PI_RK1_ARPI_DQ_B0 GENMASK(13, 8) + #define SHU2RK1_PI_RK1_ARPI_DQM_B1 GENMASK(21, 16) + #define SHU2RK1_PI_RK1_ARPI_DQM_B0 GENMASK(29, 24) +#define SHU2RK1_DQSOSC 0x00001110 + #define SHU2RK1_DQSOSC_DQSOSC_BASE_RK1 GENMASK(15, 0) + #define SHU2RK1_DQSOSC_DQSOSC_BASE_RK1_B1 GENMASK(31, 16) +#define SHU2RK1_SELPH_ODTEN0 0x0000111c + #define SHU2RK1_SELPH_ODTEN0_TXDLY_B0_R1RODTEN GENMASK(2, 0) + #define SHU2RK1_SELPH_ODTEN0_TXDLY_B0_R1RODTEN_P1 GENMASK(6, 4) + #define SHU2RK1_SELPH_ODTEN0_TXDLY_B1_R1RODTEN GENMASK(10, 8) + #define SHU2RK1_SELPH_ODTEN0_TXDLY_B1_R1RODTEN_P1 GENMASK(14, 12) + #define SHU2RK1_SELPH_ODTEN0_TXDLY_B2_R1RODTEN GENMASK(18, 16) + #define SHU2RK1_SELPH_ODTEN0_TXDLY_B2_R1RODTEN_P1 GENMASK(22, 20) + #define SHU2RK1_SELPH_ODTEN0_TXDLY_B3_R1RODTEN GENMASK(26, 24) + #define SHU2RK1_SELPH_ODTEN0_TXDLY_B3_R1RODTEN_P1 GENMASK(30, 28) +#define SHU2RK1_SELPH_ODTEN1 0x00001120 + #define SHU2RK1_SELPH_ODTEN1_DLY_B0_R1RODTEN GENMASK(2, 0) + #define SHU2RK1_SELPH_ODTEN1_DLY_B0_R1RODTEN_P1 GENMASK(6, 4) + #define SHU2RK1_SELPH_ODTEN1_DLY_B1_R1RODTEN GENMASK(10, 8) + #define SHU2RK1_SELPH_ODTEN1_DLY_B1_R1RODTEN_P1 GENMASK(14, 12) + #define SHU2RK1_SELPH_ODTEN1_DLY_B2_R1RODTEN GENMASK(18, 16) + #define SHU2RK1_SELPH_ODTEN1_DLY_B2_R1RODTEN_P1 GENMASK(22, 20) + #define SHU2RK1_SELPH_ODTEN1_DLY_B3_R1RODTEN GENMASK(26, 24) + #define SHU2RK1_SELPH_ODTEN1_DLY_B3_R1RODTEN_P1 GENMASK(30, 28) +#define SHU2RK1_SELPH_DQSG0 0x00001124 + #define SHU2RK1_SELPH_DQSG0_TX_DLY_R1DQS0_GATED GENMASK(2, 0) + #define SHU2RK1_SELPH_DQSG0_TX_DLY_R1DQS0_GATED_P1 GENMASK(6, 4) + #define SHU2RK1_SELPH_DQSG0_TX_DLY_R1DQS1_GATED GENMASK(10, 8) + #define SHU2RK1_SELPH_DQSG0_TX_DLY_R1DQS1_GATED_P1 GENMASK(14, 12) + #define SHU2RK1_SELPH_DQSG0_TX_DLY_R1DQS2_GATED GENMASK(18, 16) + #define SHU2RK1_SELPH_DQSG0_TX_DLY_R1DQS2_GATED_P1 GENMASK(22, 20) + #define SHU2RK1_SELPH_DQSG0_TX_DLY_R1DQS3_GATED GENMASK(26, 24) + #define SHU2RK1_SELPH_DQSG0_TX_DLY_R1DQS3_GATED_P1 GENMASK(30, 28) +#define SHU2RK1_SELPH_DQSG1 0x00001128 + #define SHU2RK1_SELPH_DQSG1_REG_DLY_R1DQS0_GATED GENMASK(2, 0) + #define SHU2RK1_SELPH_DQSG1_REG_DLY_R1DQS0_GATED_P1 GENMASK(6, 4) + #define SHU2RK1_SELPH_DQSG1_REG_DLY_R1DQS1_GATED GENMASK(10, 8) + #define SHU2RK1_SELPH_DQSG1_REG_DLY_R1DQS1_GATED_P1 GENMASK(14, 12) + #define SHU2RK1_SELPH_DQSG1_REG_DLY_R1DQS2_GATED GENMASK(18, 16) + #define SHU2RK1_SELPH_DQSG1_REG_DLY_R1DQS2_GATED_P1 GENMASK(22, 20) + #define SHU2RK1_SELPH_DQSG1_REG_DLY_R1DQS3_GATED GENMASK(26, 24) + #define SHU2RK1_SELPH_DQSG1_REG_DLY_R1DQS3_GATED_P1 GENMASK(30, 28) +#define SHU2RK1_SELPH_DQ0 0x0000112c + #define SHU2RK1_SELPH_DQ0_TX_DLY_R1DQ0 GENMASK(2, 0) + #define SHU2RK1_SELPH_DQ0_TX_DLY_R1DQ1 GENMASK(6, 4) + #define SHU2RK1_SELPH_DQ0_TX_DLY_R1DQ2 GENMASK(10, 8) + #define SHU2RK1_SELPH_DQ0_TX_DLY_R1DQ3 GENMASK(14, 12) + #define SHU2RK1_SELPH_DQ0_TX_DLY_R1OEN_DQ0 GENMASK(18, 16) + #define SHU2RK1_SELPH_DQ0_TX_DLY_R1OEN_DQ1 GENMASK(22, 20) + #define SHU2RK1_SELPH_DQ0_TX_DLY_R1OEN_DQ2 GENMASK(26, 24) + #define SHU2RK1_SELPH_DQ0_TX_DLY_R1OEN_DQ3 GENMASK(30, 28) +#define SHU2RK1_SELPH_DQ1 0x00001130 + #define SHU2RK1_SELPH_DQ1_TX_DLY_R1DQM0 GENMASK(2, 0) + #define SHU2RK1_SELPH_DQ1_TX_DLY_R1DQM1 GENMASK(6, 4) + #define SHU2RK1_SELPH_DQ1_TX_DLY_R1DQM2 GENMASK(10, 8) + #define SHU2RK1_SELPH_DQ1_TX_DLY_R1DQM3 GENMASK(14, 12) + #define SHU2RK1_SELPH_DQ1_TX_DLY_R1OEN_DQM0 GENMASK(18, 16) + #define SHU2RK1_SELPH_DQ1_TX_DLY_R1OEN_DQM1 GENMASK(22, 20) + #define SHU2RK1_SELPH_DQ1_TX_DLY_R1OEN_DQM2 GENMASK(26, 24) + #define SHU2RK1_SELPH_DQ1_TX_DLY_R1OEN_DQM3 GENMASK(30, 28) +#define SHU2RK1_SELPH_DQ2 0x00001134 + #define SHU2RK1_SELPH_DQ2_DLY_R1DQ0 GENMASK(2, 0) + #define SHU2RK1_SELPH_DQ2_DLY_R1DQ1 GENMASK(6, 4) + #define SHU2RK1_SELPH_DQ2_DLY_R1DQ2 GENMASK(10, 8) + #define SHU2RK1_SELPH_DQ2_DLY_R1DQ3 GENMASK(14, 12) + #define SHU2RK1_SELPH_DQ2_DLY_R1OEN_DQ0 GENMASK(18, 16) + #define SHU2RK1_SELPH_DQ2_DLY_R1OEN_DQ1 GENMASK(22, 20) + #define SHU2RK1_SELPH_DQ2_DLY_R1OEN_DQ2 GENMASK(26, 24) + #define SHU2RK1_SELPH_DQ2_DLY_R1OEN_DQ3 GENMASK(30, 28) +#define SHU2RK1_SELPH_DQ3 0x00001138 + #define SHU2RK1_SELPH_DQ3_DLY_R1DQM0 GENMASK(2, 0) + #define SHU2RK1_SELPH_DQ3_DLY_R1DQM1 GENMASK(6, 4) + #define SHU2RK1_SELPH_DQ3_DLY_R1DQM2 GENMASK(10, 8) + #define SHU2RK1_SELPH_DQ3_DLY_R1DQM3 GENMASK(14, 12) + #define SHU2RK1_SELPH_DQ3_DLY_R1OEN_DQM0 GENMASK(18, 16) + #define SHU2RK1_SELPH_DQ3_DLY_R1OEN_DQM1 GENMASK(22, 20) + #define SHU2RK1_SELPH_DQ3_DLY_R1OEN_DQM2 GENMASK(26, 24) + #define SHU2RK1_SELPH_DQ3_DLY_R1OEN_DQM3 GENMASK(30, 28) +#define SHU2RK1_DQS2DQ_CAL1 0x00001140 + #define SHU2RK1_DQS2DQ_CAL1_BOOT_ORIG_UI_RK1_DQ0 GENMASK(10, 0) + #define SHU2RK1_DQS2DQ_CAL1_BOOT_ORIG_UI_RK1_DQ1 GENMASK(26, 16) +#define SHU2RK1_DQS2DQ_CAL2 0x00001144 + #define SHU2RK1_DQS2DQ_CAL2_BOOT_TARG_UI_RK1_DQ0 GENMASK(10, 0) + #define SHU2RK1_DQS2DQ_CAL2_BOOT_TARG_UI_RK1_DQ1 GENMASK(26, 16) +#define SHU2RK1_DQS2DQ_CAL3 0x00001148 + #define SHU2RK1_DQS2DQ_CAL3_BOOT_TARG_UI_RK1_OEN_DQ0 GENMASK(5, 0) + #define SHU2RK1_DQS2DQ_CAL3_BOOT_TARG_UI_RK1_OEN_DQ1 GENMASK(11, 6) + #define SHU2RK1_DQS2DQ_CAL3_BOOT_TARG_UI_RK1_OEN_DQ0_B4TO0 GENMASK(16, 12) + #define SHU2RK1_DQS2DQ_CAL3_BOOT_TARG_UI_RK1_OEN_DQ1_B4TO0 GENMASK(21, 17) +#define SHU2RK1_DQS2DQ_CAL4 0x0000114c + #define SHU2RK1_DQS2DQ_CAL4_BOOT_TARG_UI_RK1_OEN_DQM0 GENMASK(5, 0) + #define SHU2RK1_DQS2DQ_CAL4_BOOT_TARG_UI_RK1_OEN_DQM1 GENMASK(11, 6) + #define SHU2RK1_DQS2DQ_CAL4_BOOT_TARG_UI_RK1_OEN_DQM0_B4TO0 GENMASK(16, 12) + #define SHU2RK1_DQS2DQ_CAL4_BOOT_TARG_UI_RK1_OEN_DQM1_B4TO0 GENMASK(21, 17) +#define SHU2RK1_DQS2DQ_CAL5 0x00001150 + #define SHU2RK1_DQS2DQ_CAL5_BOOT_TARG_UI_RK1_DQM0 GENMASK(10, 0) + #define SHU2RK1_DQS2DQ_CAL5_BOOT_TARG_UI_RK1_DQM1 GENMASK(26, 16) +#define SHU2RK2_DQSCTL 0x00001200 + #define SHU2RK2_DQSCTL_R2DQSINCTL GENMASK(3, 0) +#define SHU2RK2_DQSIEN 0x00001204 + #define SHU2RK2_DQSIEN_R2DQS0IEN GENMASK(6, 0) + #define SHU2RK2_DQSIEN_R2DQS1IEN GENMASK(14, 8) + #define SHU2RK2_DQSIEN_R2DQS2IEN GENMASK(22, 16) + #define SHU2RK2_DQSIEN_R2DQS3IEN GENMASK(30, 24) +#define SHU2RK2_DQSCAL 0x00001208 + #define SHU2RK2_DQSCAL_R2DQSIENLLMT GENMASK(6, 0) + #define SHU2RK2_DQSCAL_R2DQSIENLLMTEN BIT(7) + #define SHU2RK2_DQSCAL_R2DQSIENHLMT GENMASK(14, 8) + #define SHU2RK2_DQSCAL_R2DQSIENHLMTEN BIT(15) +#define SHU2RK2_PI 0x0000120c + #define SHU2RK2_PI_RK2_ARPI_DQ_B1 GENMASK(5, 0) + #define SHU2RK2_PI_RK2_ARPI_DQ_B0 GENMASK(13, 8) + #define SHU2RK2_PI_RK2_ARPI_DQM_B1 GENMASK(21, 16) + #define SHU2RK2_PI_RK2_ARPI_DQM_B0 GENMASK(29, 24) +#define SHU2RK2_DQSOSC 0x00001210 + #define SHU2RK2_DQSOSC_DQSOSC_BASE_RK2 GENMASK(15, 0) + #define SHU2RK2_DQSOSC_DQSOSC_BASE_RK2_B1 GENMASK(31, 16) +#define SHU2RK2_SELPH_ODTEN0 0x0000121c + #define SHU2RK2_SELPH_ODTEN0_TXDLY_B0_R2RODTEN GENMASK(2, 0) + #define SHU2RK2_SELPH_ODTEN0_TXDLY_B0_R2RODTEN_P1 GENMASK(6, 4) + #define SHU2RK2_SELPH_ODTEN0_TXDLY_B1_R2RODTEN GENMASK(10, 8) + #define SHU2RK2_SELPH_ODTEN0_TXDLY_B1_R2RODTEN_P1 GENMASK(14, 12) + #define SHU2RK2_SELPH_ODTEN0_TXDLY_B2_R2RODTEN GENMASK(18, 16) + #define SHU2RK2_SELPH_ODTEN0_TXDLY_B2_R2RODTEN_P1 GENMASK(22, 20) + #define SHU2RK2_SELPH_ODTEN0_TXDLY_B3_R2RODTEN GENMASK(26, 24) + #define SHU2RK2_SELPH_ODTEN0_TXDLY_B3_R2RODTEN_P1 GENMASK(30, 28) +#define SHU2RK2_SELPH_ODTEN1 0x00001220 + #define SHU2RK2_SELPH_ODTEN1_DLY_B0_R2RODTEN GENMASK(2, 0) + #define SHU2RK2_SELPH_ODTEN1_DLY_B0_R2RODTEN_P1 GENMASK(6, 4) + #define SHU2RK2_SELPH_ODTEN1_DLY_B1_R2RODTEN GENMASK(10, 8) + #define SHU2RK2_SELPH_ODTEN1_DLY_B1_R2RODTEN_P1 GENMASK(14, 12) + #define SHU2RK2_SELPH_ODTEN1_DLY_B2_R2RODTEN GENMASK(18, 16) + #define SHU2RK2_SELPH_ODTEN1_DLY_B2_R2RODTEN_P1 GENMASK(22, 20) + #define SHU2RK2_SELPH_ODTEN1_DLY_B3_R2RODTEN GENMASK(26, 24) + #define SHU2RK2_SELPH_ODTEN1_DLY_B3_R2RODTEN_P1 GENMASK(30, 28) +#define SHU2RK2_SELPH_DQSG0 0x00001224 + #define SHU2RK2_SELPH_DQSG0_TX_DLY_R2DQS0_GATED GENMASK(2, 0) + #define SHU2RK2_SELPH_DQSG0_TX_DLY_R2DQS0_GATED_P1 GENMASK(6, 4) + #define SHU2RK2_SELPH_DQSG0_TX_DLY_R2DQS1_GATED GENMASK(10, 8) + #define SHU2RK2_SELPH_DQSG0_TX_DLY_R2DQS1_GATED_P1 GENMASK(14, 12) + #define SHU2RK2_SELPH_DQSG0_TX_DLY_R2DQS2_GATED GENMASK(18, 16) + #define SHU2RK2_SELPH_DQSG0_TX_DLY_R2DQS2_GATED_P1 GENMASK(22, 20) + #define SHU2RK2_SELPH_DQSG0_TX_DLY_R2DQS3_GATED GENMASK(26, 24) + #define SHU2RK2_SELPH_DQSG0_TX_DLY_R2DQS3_GATED_P1 GENMASK(30, 28) +#define SHU2RK2_SELPH_DQSG1 0x00001228 + #define SHU2RK2_SELPH_DQSG1_REG_DLY_R2DQS0_GATED GENMASK(2, 0) + #define SHU2RK2_SELPH_DQSG1_REG_DLY_R2DQS0_GATED_P1 GENMASK(6, 4) + #define SHU2RK2_SELPH_DQSG1_REG_DLY_R2DQS1_GATED GENMASK(10, 8) + #define SHU2RK2_SELPH_DQSG1_REG_DLY_R2DQS1_GATED_P1 GENMASK(14, 12) + #define SHU2RK2_SELPH_DQSG1_REG_DLY_R2DQS2_GATED GENMASK(18, 16) + #define SHU2RK2_SELPH_DQSG1_REG_DLY_R2DQS2_GATED_P1 GENMASK(22, 20) + #define SHU2RK2_SELPH_DQSG1_REG_DLY_R2DQS3_GATED GENMASK(26, 24) + #define SHU2RK2_SELPH_DQSG1_REG_DLY_R2DQS3_GATED_P1 GENMASK(30, 28) +#define SHU2RK2_SELPH_DQ0 0x0000122c + #define SHU2RK2_SELPH_DQ0_TX_DLY_R2DQ0 GENMASK(2, 0) + #define SHU2RK2_SELPH_DQ0_TX_DLY_R2DQ1 GENMASK(6, 4) + #define SHU2RK2_SELPH_DQ0_TX_DLY_R2DQ2 GENMASK(10, 8) + #define SHU2RK2_SELPH_DQ0_TX_DLY_R2DQ3 GENMASK(14, 12) + #define SHU2RK2_SELPH_DQ0_TX_DLY_R2OEN_DQ0 GENMASK(18, 16) + #define SHU2RK2_SELPH_DQ0_TX_DLY_R2OEN_DQ1 GENMASK(22, 20) + #define SHU2RK2_SELPH_DQ0_TX_DLY_R2OEN_DQ2 GENMASK(26, 24) + #define SHU2RK2_SELPH_DQ0_TX_DLY_R2OEN_DQ3 GENMASK(30, 28) +#define SHU2RK2_SELPH_DQ1 0x00001230 + #define SHU2RK2_SELPH_DQ1_TX_DLY_R2DQM0 GENMASK(2, 0) + #define SHU2RK2_SELPH_DQ1_TX_DLY_R2DQM1 GENMASK(6, 4) + #define SHU2RK2_SELPH_DQ1_TX_DLY_R2DQM2 GENMASK(10, 8) + #define SHU2RK2_SELPH_DQ1_TX_DLY_R2DQM3 GENMASK(14, 12) + #define SHU2RK2_SELPH_DQ1_TX_DLY_R2OEN_DQM0 GENMASK(18, 16) + #define SHU2RK2_SELPH_DQ1_TX_DLY_R2OEN_DQM1 GENMASK(22, 20) + #define SHU2RK2_SELPH_DQ1_TX_DLY_R2OEN_DQM2 GENMASK(26, 24) + #define SHU2RK2_SELPH_DQ1_TX_DLY_R2OEN_DQM3 GENMASK(30, 28) +#define SHU2RK2_SELPH_DQ2 0x00001234 + #define SHU2RK2_SELPH_DQ2_DLY_R2DQ0 GENMASK(2, 0) + #define SHU2RK2_SELPH_DQ2_DLY_R2DQ1 GENMASK(6, 4) + #define SHU2RK2_SELPH_DQ2_DLY_R2DQ2 GENMASK(10, 8) + #define SHU2RK2_SELPH_DQ2_DLY_R2DQ3 GENMASK(14, 12) + #define SHU2RK2_SELPH_DQ2_DLY_R2OEN_DQ0 GENMASK(18, 16) + #define SHU2RK2_SELPH_DQ2_DLY_R2OEN_DQ1 GENMASK(22, 20) + #define SHU2RK2_SELPH_DQ2_DLY_R2OEN_DQ2 GENMASK(26, 24) + #define SHU2RK2_SELPH_DQ2_DLY_R2OEN_DQ3 GENMASK(30, 28) +#define SHU2RK2_SELPH_DQ3 0x00001238 + #define SHU2RK2_SELPH_DQ3_DLY_R2DQM0 GENMASK(2, 0) + #define SHU2RK2_SELPH_DQ3_DLY_R2DQM1 GENMASK(6, 4) + #define SHU2RK2_SELPH_DQ3_DLY_R2DQM2 GENMASK(10, 8) + #define SHU2RK2_SELPH_DQ3_DLY_R2DQM3 GENMASK(14, 12) + #define SHU2RK2_SELPH_DQ3_DLY_R2OEN_DQM0 GENMASK(18, 16) + #define SHU2RK2_SELPH_DQ3_DLY_R2OEN_DQM1 GENMASK(22, 20) + #define SHU2RK2_SELPH_DQ3_DLY_R2OEN_DQM2 GENMASK(26, 24) + #define SHU2RK2_SELPH_DQ3_DLY_R2OEN_DQM3 GENMASK(30, 28) +#define SHU2RK2_DQS2DQ_CAL1 0x00001240 + #define SHU2RK2_DQS2DQ_CAL1_BOOT_ORIG_UI_RK2_DQ0 GENMASK(10, 0) + #define SHU2RK2_DQS2DQ_CAL1_BOOT_ORIG_UI_RK2_DQ1 GENMASK(26, 16) +#define SHU2RK2_DQS2DQ_CAL2 0x00001244 + #define SHU2RK2_DQS2DQ_CAL2_BOOT_TARG_UI_RK2_DQ0 GENMASK(10, 0) + #define SHU2RK2_DQS2DQ_CAL2_BOOT_TARG_UI_RK2_DQ1 GENMASK(26, 16) +#define SHU2RK2_DQS2DQ_CAL3 0x00001248 + #define SHU2RK2_DQS2DQ_CAL3_BOOT_TARG_UI_RK2_OEN_DQ0 GENMASK(5, 0) + #define SHU2RK2_DQS2DQ_CAL3_BOOT_TARG_UI_RK2_OEN_DQ1 GENMASK(11, 6) +#define SHU2RK2_DQS2DQ_CAL4 0x0000124c + #define SHU2RK2_DQS2DQ_CAL4_BOOT_TARG_UI_RK2_OEN_DQM0 GENMASK(5, 0) + #define SHU2RK2_DQS2DQ_CAL4_BOOT_TARG_UI_RK2_OEN_DQM1 GENMASK(11, 6) +#define SHU2RK2_DQS2DQ_CAL5 0x00001250 + #define SHU2RK2_DQS2DQ_CAL5_BOOT_TARG_UI_RK2_DQM0 GENMASK(10, 0) + #define SHU2RK2_DQS2DQ_CAL5_BOOT_TARG_UI_RK2_DQM1 GENMASK(26, 16) +#define SHU2_DQSG_RETRY 0x00001254 + #define SHU2_DQSG_RETRY_R_DQSGRETRY_SW_RESET BIT(0) + #define SHU2_DQSG_RETRY_R_DQSG_RETRY_SW_EN BIT(1) + #define SHU2_DQSG_RETRY_R_DDR1866_PLUS BIT(2) + #define SHU2_DQSG_RETRY_R_RETRY_ONCE BIT(3) + #define SHU2_DQSG_RETRY_R_RETRY_3TIMES BIT(4) + #define SHU2_DQSG_RETRY_R_RETRY_1RANK BIT(5) + #define SHU2_DQSG_RETRY_R_RETRY_SAV_MSK BIT(6) + #define SHU2_DQSG_RETRY_R_DM4BYTE BIT(7) + #define SHU2_DQSG_RETRY_R_DQSIENLAT GENMASK(11, 8) + #define SHU2_DQSG_RETRY_R_STBENCMP_ALLBYTE BIT(12) + #define SHU2_DQSG_RETRY_R_XSR_DQSG_RETRY_EN BIT(13) + #define SHU2_DQSG_RETRY_R_XSR_RETRY_SPM_MODE BIT(14) + #define SHU2_DQSG_RETRY_R_RETRY_CMP_DATA BIT(15) + #define SHU2_DQSG_RETRY_R_RETRY_ALE_BLOCK_MASK BIT(20) + #define SHU2_DQSG_RETRY_R_RDY_SEL_DLE BIT(21) + #define SHU2_DQSG_RETRY_R_RETRY_ROUND_NUM GENMASK(25, 24) + #define SHU2_DQSG_RETRY_R_RETRY_RANKSEL_FROM_PHY BIT(28) + #define SHU2_DQSG_RETRY_R_RETRY_PA_DSIABLE BIT(29) + #define SHU2_DQSG_RETRY_R_RETRY_STBEN_RESET_MSK BIT(30) + #define SHU2_DQSG_RETRY_R_RETRY_USE_BURST_MDOE BIT(31) +#define SHU3_ACTIM0 0x00001400 + #define SHU3_ACTIM0_TWTR GENMASK(3, 0) + #define SHU3_ACTIM0_TWR GENMASK(12, 8) + #define SHU3_ACTIM0_TRRD GENMASK(18, 16) + #define SHU3_ACTIM0_TRCD GENMASK(27, 24) +#define SHU3_ACTIM1 0x00001404 + #define SHU3_ACTIM1_TRPAB GENMASK(2, 0) + #define SHU3_ACTIM1_TRP GENMASK(11, 8) + #define SHU3_ACTIM1_TRAS GENMASK(19, 16) + #define SHU3_ACTIM1_TRC GENMASK(28, 24) +#define SHU3_ACTIM2 0x00001408 + #define SHU3_ACTIM2_TXP GENMASK(2, 0) + #define SHU3_ACTIM2_TRTP GENMASK(10, 8) + #define SHU3_ACTIM2_TR2W GENMASK(19, 16) + #define SHU3_ACTIM2_TFAW GENMASK(28, 24) +#define SHU3_ACTIM3 0x0000140c + #define SHU3_ACTIM3_TRFCPB GENMASK(7, 0) + #define SHU3_ACTIM3_TRFC GENMASK(23, 16) + #define SHU3_ACTIM3_REFCNT GENMASK(31, 24) +#define SHU3_ACTIM4 0x00001410 + #define SHU3_ACTIM4_TXREFCNT GENMASK(9, 0) + #define SHU3_ACTIM4_REFCNT_FR_CLK GENMASK(23, 16) + #define SHU3_ACTIM4_TZQCS GENMASK(31, 24) +#define SHU3_ACTIM5 0x00001414 + #define SHU3_ACTIM5_TR2PD GENMASK(4, 0) + #define SHU3_ACTIM5_TWTPD GENMASK(12, 8) + #define SHU3_ACTIM5_TMRR2W GENMASK(27, 24) +#define SHU3_ACTIM6 0x00001418 + #define SHU3_ACTIM6_BGTCCD GENMASK(1, 0) + #define SHU3_ACTIM6_BGTWTR GENMASK(7, 4) + #define SHU3_ACTIM6_TWRMPR GENMASK(11, 8) + #define SHU3_ACTIM6_BGTRRD GENMASK(14, 12) +#define SHU3_ACTIM_XRT 0x0000141c + #define SHU3_ACTIM_XRT_XRTR2R GENMASK(4, 0) + #define SHU3_ACTIM_XRT_XRTR2W GENMASK(11, 8) + #define SHU3_ACTIM_XRT_XRTW2R GENMASK(18, 16) + #define SHU3_ACTIM_XRT_XRTW2W GENMASK(27, 24) +#define SHU3_AC_TIME_05T 0x00001420 + #define SHU3_AC_TIME_05T_TRC_05T BIT(0) + #define SHU3_AC_TIME_05T_TRFCPB_05T BIT(1) + #define SHU3_AC_TIME_05T_TRFC_05T BIT(2) + #define SHU3_AC_TIME_05T_TXP_05T BIT(4) + #define SHU3_AC_TIME_05T_TRTP_05T BIT(5) + #define SHU3_AC_TIME_05T_TRCD_05T BIT(6) + #define SHU3_AC_TIME_05T_TRP_05T BIT(7) + #define SHU3_AC_TIME_05T_TRPAB_05T BIT(8) + #define SHU3_AC_TIME_05T_TRAS_05T BIT(9) + #define SHU3_AC_TIME_05T_TWR_M05T BIT(10) + #define SHU3_AC_TIME_05T_TRRD_05T BIT(12) + #define SHU3_AC_TIME_05T_TFAW_05T BIT(13) + #define SHU3_AC_TIME_05T_TR2PD_05T BIT(15) + #define SHU3_AC_TIME_05T_TWTPD_M05T BIT(16) + #define SHU3_AC_TIME_05T_BGTRRD_05T BIT(21) + #define SHU3_AC_TIME_05T_BGTCCD_05T BIT(22) + #define SHU3_AC_TIME_05T_BGTWTR_05T BIT(23) + #define SHU3_AC_TIME_05T_TR2W_05T BIT(24) + #define SHU3_AC_TIME_05T_TWTR_M05T BIT(25) + #define SHU3_AC_TIME_05T_XRTR2W_05T BIT(26) + #define SHU3_AC_TIME_05T_XRTW2R_M05T BIT(27) +#define SHU3_AC_DERATING0 0x00001424 + #define SHU3_AC_DERATING0_ACDERATEEN BIT(0) + #define SHU3_AC_DERATING0_TRRD_DERATE GENMASK(18, 16) + #define SHU3_AC_DERATING0_TRCD_DERATE GENMASK(27, 24) +#define SHU3_AC_DERATING1 0x00001428 + #define SHU3_AC_DERATING1_TRPAB_DERATE GENMASK(2, 0) + #define SHU3_AC_DERATING1_TRP_DERATE GENMASK(11, 8) + #define SHU3_AC_DERATING1_TRAS_DERATE GENMASK(19, 16) + #define SHU3_AC_DERATING1_TRC_DERATE GENMASK(28, 24) +#define SHU3_AC_DERATING_05T 0x00001430 + #define SHU3_AC_DERATING_05T_TRC_05T_DERATE BIT(0) + #define SHU3_AC_DERATING_05T_TRCD_05T_DERATE BIT(6) + #define SHU3_AC_DERATING_05T_TRP_05T_DERATE BIT(7) + #define SHU3_AC_DERATING_05T_TRPAB_05T_DERATE BIT(8) + #define SHU3_AC_DERATING_05T_TRAS_05T_DERATE BIT(9) + #define SHU3_AC_DERATING_05T_TRRD_05T_DERATE BIT(12) +#define SHU3_CONF0 0x00001440 + #define SHU3_CONF0_DMPGTIM GENMASK(5, 0) + #define SHU3_CONF0_ADVREFEN BIT(6) + #define SHU3_CONF0_ADVPREEN BIT(7) + #define SHU3_CONF0_TRFCPBIG BIT(9) + #define SHU3_CONF0_REFTHD GENMASK(15, 12) + #define SHU3_CONF0_REQQUE_DEPTH GENMASK(19, 16) + #define SHU3_CONF0_FREQDIV4 BIT(24) + #define SHU3_CONF0_FDIV2 BIT(25) + #define SHU3_CONF0_CL2 BIT(27) + #define SHU3_CONF0_BL2 BIT(28) + #define SHU3_CONF0_BL4 BIT(29) + #define SHU3_CONF0_MATYPE GENMASK(31, 30) +#define SHU3_CONF1 0x00001444 + #define SHU3_CONF1_DATLAT GENMASK(4, 0) + #define SHU3_CONF1_DATLAT_DSEL GENMASK(12, 8) + #define SHU3_CONF1_REFBW_FR GENMASK(25, 16) + #define SHU3_CONF1_DATLAT_DSEL_PHY GENMASK(30, 26) + #define SHU3_CONF1_TREFBWIG BIT(31) +#define SHU3_CONF2 0x00001448 + #define SHU3_CONF2_TCMDO1LAT GENMASK(7, 0) + #define SHU3_CONF2_FSPCHG_PRDCNT GENMASK(15, 8) + #define SHU3_CONF2_DCMDLYREF GENMASK(18, 16) + #define SHU3_CONF2_DQCMD BIT(25) + #define SHU3_CONF2_DQ16COM1 BIT(26) + #define SHU3_CONF2_RA15TOCS1 BIT(27) + #define SHU3_CONF2_WPRE2T BIT(28) + #define SHU3_CONF2_FASTWAKE2 BIT(29) + #define SHU3_CONF2_DAREFEN BIT(30) + #define SHU3_CONF2_FASTWAKE BIT(31) +#define SHU3_CONF3 0x0000144c + #define SHU3_CONF3_ZQCSCNT GENMASK(15, 0) + #define SHU3_CONF3_REFRCNT GENMASK(24, 16) +#define SHU3_STBCAL 0x00001450 + #define SHU3_STBCAL_DMSTBLAT GENMASK(1, 0) + #define SHU3_STBCAL_PICGLAT GENMASK(6, 4) + #define SHU3_STBCAL_DQSG_MODE BIT(8) +#define SHU3_DQSOSCTHRD 0x00001454 + #define SHU3_DQSOSCTHRD_DQSOSCTHRD_INC_RK0 GENMASK(11, 0) + #define SHU3_DQSOSCTHRD_DQSOSCTHRD_DEC_RK0 GENMASK(23, 12) + #define SHU3_DQSOSCTHRD_DQSOSCTHRD_INC_RK1_7TO0 GENMASK(31, 24) +#define SHU3_RANKCTL 0x00001458 + #define SHU3_RANKCTL_RANKINCTL_RXDLY GENMASK(3, 0) + #define SHU3_RANKCTL_TXRANKINCTL_TXDLY GENMASK(11, 8) + #define SHU3_RANKCTL_TXRANKINCTL GENMASK(15, 12) + #define SHU3_RANKCTL_TXRANKINCTL_ROOT GENMASK(19, 16) + #define SHU3_RANKCTL_RANKINCTL GENMASK(23, 20) + #define SHU3_RANKCTL_RANKINCTL_ROOT1 GENMASK(27, 24) + #define SHU3_RANKCTL_RANKINCTL_PHY GENMASK(31, 28) +#define SHU3_CKECTRL 0x0000145c + #define SHU3_CKECTRL_CMDCKE GENMASK(18, 16) + #define SHU3_CKECTRL_CKEPRD GENMASK(22, 20) + #define SHU3_CKECTRL_TCKESRX GENMASK(25, 24) + #define SHU3_CKECTRL_SREF_CK_DLY GENMASK(29, 28) +#define SHU3_ODTCTRL 0x00001460 + #define SHU3_ODTCTRL_ROEN BIT(0) + #define SHU3_ODTCTRL_WOEN BIT(1) + #define SHU3_ODTCTRL_RODTEN_SELPH_CG_IG BIT(2) + #define SHU3_ODTCTRL_RODTENSTB_SELPH_CG_IG BIT(3) + #define SHU3_ODTCTRL_RODT GENMASK(7, 4) + #define SHU3_ODTCTRL_TWODT GENMASK(22, 16) + #define SHU3_ODTCTRL_FIXRODT BIT(27) + #define SHU3_ODTCTRL_RODTE2 BIT(30) + #define SHU3_ODTCTRL_RODTE BIT(31) +#define SHU3_IMPCAL1 0x00001464 + #define SHU3_IMPCAL1_IMPCAL_CHKCYCLE GENMASK(2, 0) + #define SHU3_IMPCAL1_IMPDRVP GENMASK(8, 4) + #define SHU3_IMPCAL1_IMPDRVN GENMASK(15, 11) + #define SHU3_IMPCAL1_IMPCAL_CALEN_CYCLE GENMASK(19, 17) + #define SHU3_IMPCAL1_IMPCALCNT GENMASK(27, 20) + #define SHU3_IMPCAL1_IMPCAL_CALICNT GENMASK(31, 28) +#define SHU3_DQSOSC_PRD 0x00001468 + #define SHU3_DQSOSC_PRD_DQSOSC_PRDCNT GENMASK(9, 0) + #define SHU3_DQSOSC_PRD_DQSOSCTHRD_INC_RK1_11TO8 GENMASK(19, 16) + #define SHU3_DQSOSC_PRD_DQSOSCTHRD_DEC_RK1 GENMASK(31, 20) +#define SHU3_DQSOSCR 0x0000146c + #define SHU3_DQSOSCR_DQSOSCRCNT GENMASK(7, 0) + #define SHU3_DQSOSCR_DQSOSC_DELTA GENMASK(31, 16) +#define SHU3_DQSOSCR2 0x00001470 + #define SHU3_DQSOSCR2_DQSOSCENCNT GENMASK(15, 0) + #define SHU3_DQSOSCR2_DQSOSC_ADV_SEL GENMASK(17, 16) + #define SHU3_DQSOSCR2_DQSOSC_DRS_ADV_SEL GENMASK(19, 18) +#define SHU3_RODTENSTB 0x00001474 + #define SHU3_RODTENSTB_RODTEN_MCK_MODESEL BIT(0) + #define SHU3_RODTENSTB_RODTEN_P1_ENABLE BIT(1) + #define SHU3_RODTENSTB_RODTENSTB_OFFSET GENMASK(7, 2) + #define SHU3_RODTENSTB_RODTENSTB_EXT GENMASK(23, 8) + #define SHU3_RODTENSTB_RODTENSTB_4BYTE_EN BIT(31) +#define SHU3_PIPE 0x00001478 + #define SHU3_PIPE_PHYRXPIPE1 BIT(0) + #define SHU3_PIPE_PHYRXPIPE2 BIT(1) + #define SHU3_PIPE_PHYRXPIPE3 BIT(2) + #define SHU3_PIPE_PHYRXRDSLPIPE1 BIT(4) + #define SHU3_PIPE_PHYRXRDSLPIPE2 BIT(5) + #define SHU3_PIPE_PHYRXRDSLPIPE3 BIT(6) + #define SHU3_PIPE_PHYPIPE1EN BIT(8) + #define SHU3_PIPE_PHYPIPE2EN BIT(9) + #define SHU3_PIPE_PHYPIPE3EN BIT(10) + #define SHU3_PIPE_DLE_LAST_EXTEND3 BIT(26) + #define SHU3_PIPE_READ_START_EXTEND3 BIT(27) + #define SHU3_PIPE_DLE_LAST_EXTEND2 BIT(28) + #define SHU3_PIPE_READ_START_EXTEND2 BIT(29) + #define SHU3_PIPE_DLE_LAST_EXTEND1 BIT(30) + #define SHU3_PIPE_READ_START_EXTEND1 BIT(31) +#define SHU3_TEST1 0x0000147c + #define SHU3_TEST1_LATNORMPOP GENMASK(12, 8) + #define SHU3_TEST1_DQSICALBLCOK_CNT GENMASK(22, 20) + #define SHU3_TEST1_DQSICALI_NEW BIT(23) +#define SHU3_SELPH_CA1 0x00001480 + #define SHU3_SELPH_CA1_TXDLY_CS GENMASK(2, 0) + #define SHU3_SELPH_CA1_TXDLY_CKE GENMASK(6, 4) + #define SHU3_SELPH_CA1_TXDLY_ODT GENMASK(10, 8) + #define SHU3_SELPH_CA1_TXDLY_RESET GENMASK(14, 12) + #define SHU3_SELPH_CA1_TXDLY_WE GENMASK(18, 16) + #define SHU3_SELPH_CA1_TXDLY_CAS GENMASK(22, 20) + #define SHU3_SELPH_CA1_TXDLY_RAS GENMASK(26, 24) + #define SHU3_SELPH_CA1_TXDLY_CS1 GENMASK(30, 28) +#define SHU3_SELPH_CA2 0x00001484 + #define SHU3_SELPH_CA2_TXDLY_BA0 GENMASK(2, 0) + #define SHU3_SELPH_CA2_TXDLY_BA1 GENMASK(6, 4) + #define SHU3_SELPH_CA2_TXDLY_BA2 GENMASK(10, 8) + #define SHU3_SELPH_CA2_TXDLY_CMD GENMASK(20, 16) + #define SHU3_SELPH_CA2_TXDLY_CKE1 GENMASK(26, 24) +#define SHU3_SELPH_CA3 0x00001488 + #define SHU3_SELPH_CA3_TXDLY_RA0 GENMASK(2, 0) + #define SHU3_SELPH_CA3_TXDLY_RA1 GENMASK(6, 4) + #define SHU3_SELPH_CA3_TXDLY_RA2 GENMASK(10, 8) + #define SHU3_SELPH_CA3_TXDLY_RA3 GENMASK(14, 12) + #define SHU3_SELPH_CA3_TXDLY_RA4 GENMASK(18, 16) + #define SHU3_SELPH_CA3_TXDLY_RA5 GENMASK(22, 20) + #define SHU3_SELPH_CA3_TXDLY_RA6 GENMASK(26, 24) + #define SHU3_SELPH_CA3_TXDLY_RA7 GENMASK(30, 28) +#define SHU3_SELPH_CA4 0x0000148c + #define SHU3_SELPH_CA4_TXDLY_RA8 GENMASK(2, 0) + #define SHU3_SELPH_CA4_TXDLY_RA9 GENMASK(6, 4) + #define SHU3_SELPH_CA4_TXDLY_RA10 GENMASK(10, 8) + #define SHU3_SELPH_CA4_TXDLY_RA11 GENMASK(14, 12) + #define SHU3_SELPH_CA4_TXDLY_RA12 GENMASK(18, 16) + #define SHU3_SELPH_CA4_TXDLY_RA13 GENMASK(22, 20) + #define SHU3_SELPH_CA4_TXDLY_RA14 GENMASK(26, 24) + #define SHU3_SELPH_CA4_TXDLY_RA15 GENMASK(30, 28) +#define SHU3_SELPH_CA5 0x00001490 + #define SHU3_SELPH_CA5_DLY_CS GENMASK(2, 0) + #define SHU3_SELPH_CA5_DLY_CKE GENMASK(6, 4) + #define SHU3_SELPH_CA5_DLY_ODT GENMASK(10, 8) + #define SHU3_SELPH_CA5_DLY_RESET GENMASK(14, 12) + #define SHU3_SELPH_CA5_DLY_WE GENMASK(18, 16) + #define SHU3_SELPH_CA5_DLY_CAS GENMASK(22, 20) + #define SHU3_SELPH_CA5_DLY_RAS GENMASK(26, 24) + #define SHU3_SELPH_CA5_DLY_CS1 GENMASK(30, 28) +#define SHU3_SELPH_CA6 0x00001494 + #define SHU3_SELPH_CA6_DLY_BA0 GENMASK(2, 0) + #define SHU3_SELPH_CA6_DLY_BA1 GENMASK(6, 4) + #define SHU3_SELPH_CA6_DLY_BA2 GENMASK(10, 8) + #define SHU3_SELPH_CA6_DLY_CKE1 GENMASK(26, 24) +#define SHU3_SELPH_CA7 0x00001498 + #define SHU3_SELPH_CA7_DLY_RA0 GENMASK(2, 0) + #define SHU3_SELPH_CA7_DLY_RA1 GENMASK(6, 4) + #define SHU3_SELPH_CA7_DLY_RA2 GENMASK(10, 8) + #define SHU3_SELPH_CA7_DLY_RA3 GENMASK(14, 12) + #define SHU3_SELPH_CA7_DLY_RA4 GENMASK(18, 16) + #define SHU3_SELPH_CA7_DLY_RA5 GENMASK(22, 20) + #define SHU3_SELPH_CA7_DLY_RA6 GENMASK(26, 24) + #define SHU3_SELPH_CA7_DLY_RA7 GENMASK(30, 28) +#define SHU3_SELPH_CA8 0x0000149c + #define SHU3_SELPH_CA8_DLY_RA8 GENMASK(2, 0) + #define SHU3_SELPH_CA8_DLY_RA9 GENMASK(6, 4) + #define SHU3_SELPH_CA8_DLY_RA10 GENMASK(10, 8) + #define SHU3_SELPH_CA8_DLY_RA11 GENMASK(14, 12) + #define SHU3_SELPH_CA8_DLY_RA12 GENMASK(18, 16) + #define SHU3_SELPH_CA8_DLY_RA13 GENMASK(22, 20) + #define SHU3_SELPH_CA8_DLY_RA14 GENMASK(26, 24) + #define SHU3_SELPH_CA8_DLY_RA15 GENMASK(30, 28) +#define SHU3_SELPH_DQS0 0x000014a0 + #define SHU3_SELPH_DQS0_TXDLY_DQS0 GENMASK(2, 0) + #define SHU3_SELPH_DQS0_TXDLY_DQS1 GENMASK(6, 4) + #define SHU3_SELPH_DQS0_TXDLY_DQS2 GENMASK(10, 8) + #define SHU3_SELPH_DQS0_TXDLY_DQS3 GENMASK(14, 12) + #define SHU3_SELPH_DQS0_TXDLY_OEN_DQS0 GENMASK(18, 16) + #define SHU3_SELPH_DQS0_TXDLY_OEN_DQS1 GENMASK(22, 20) + #define SHU3_SELPH_DQS0_TXDLY_OEN_DQS2 GENMASK(26, 24) + #define SHU3_SELPH_DQS0_TXDLY_OEN_DQS3 GENMASK(30, 28) +#define SHU3_SELPH_DQS1 0x000014a4 + #define SHU3_SELPH_DQS1_DLY_DQS0 GENMASK(2, 0) + #define SHU3_SELPH_DQS1_DLY_DQS1 GENMASK(6, 4) + #define SHU3_SELPH_DQS1_DLY_DQS2 GENMASK(10, 8) + #define SHU3_SELPH_DQS1_DLY_DQS3 GENMASK(14, 12) + #define SHU3_SELPH_DQS1_DLY_OEN_DQS0 GENMASK(18, 16) + #define SHU3_SELPH_DQS1_DLY_OEN_DQS1 GENMASK(22, 20) + #define SHU3_SELPH_DQS1_DLY_OEN_DQS2 GENMASK(26, 24) + #define SHU3_SELPH_DQS1_DLY_OEN_DQS3 GENMASK(30, 28) +#define SHU3_DRVING1 0x000014a8 + #define SHU3_DRVING1_DQDRVN2 GENMASK(4, 0) + #define SHU3_DRVING1_DQDRVP2 GENMASK(9, 5) + #define SHU3_DRVING1_DQSDRVN1 GENMASK(14, 10) + #define SHU3_DRVING1_DQSDRVP1 GENMASK(19, 15) + #define SHU3_DRVING1_DQSDRVN2 GENMASK(24, 20) + #define SHU3_DRVING1_DQSDRVP2 GENMASK(29, 25) + #define SHU3_DRVING1_DIS_IMP_ODTN_TRACK BIT(30) + #define SHU3_DRVING1_DIS_IMPCAL_HW BIT(31) +#define SHU3_DRVING2 0x000014ac + #define SHU3_DRVING2_CMDDRVN1 GENMASK(4, 0) + #define SHU3_DRVING2_CMDDRVP1 GENMASK(9, 5) + #define SHU3_DRVING2_CMDDRVN2 GENMASK(14, 10) + #define SHU3_DRVING2_CMDDRVP2 GENMASK(19, 15) + #define SHU3_DRVING2_DQDRVN1 GENMASK(24, 20) + #define SHU3_DRVING2_DQDRVP1 GENMASK(29, 25) + #define SHU3_DRVING2_DIS_IMPCAL_ODT_EN BIT(31) +#define SHU3_DRVING3 0x000014b0 + #define SHU3_DRVING3_DQODTN2 GENMASK(4, 0) + #define SHU3_DRVING3_DQODTP2 GENMASK(9, 5) + #define SHU3_DRVING3_DQSODTN GENMASK(14, 10) + #define SHU3_DRVING3_DQSODTP GENMASK(19, 15) + #define SHU3_DRVING3_DQSODTN2 GENMASK(24, 20) + #define SHU3_DRVING3_DQSODTP2 GENMASK(29, 25) +#define SHU3_DRVING4 0x000014b4 + #define SHU3_DRVING4_CMDODTN1 GENMASK(4, 0) + #define SHU3_DRVING4_CMDODTP1 GENMASK(9, 5) + #define SHU3_DRVING4_CMDODTN2 GENMASK(14, 10) + #define SHU3_DRVING4_CMDODTP2 GENMASK(19, 15) + #define SHU3_DRVING4_DQODTN1 GENMASK(24, 20) + #define SHU3_DRVING4_DQODTP1 GENMASK(29, 25) +#define SHU3_DRVING5 0x000014b8 + #define SHU3_DRVING5_DQCODTN2 GENMASK(4, 0) + #define SHU3_DRVING5_DQCODTP2 GENMASK(9, 5) + #define SHU3_DRVING5_DQCDRVN1 GENMASK(14, 10) + #define SHU3_DRVING5_DQCDRVP1 GENMASK(19, 15) + #define SHU3_DRVING5_DQCDRVN2 GENMASK(24, 20) + #define SHU3_DRVING5_DQCDRVP2 GENMASK(29, 25) +#define SHU3_DRVING6 0x000014bc + #define SHU3_DRVING6_DQCODTN1 GENMASK(24, 20) + #define SHU3_DRVING6_DQCODTP1 GENMASK(29, 25) +#define SHU3_WODT 0x000014c0 + #define SHU3_WODT_DISWODT GENMASK(2, 0) + #define SHU3_WODT_WODTFIX BIT(3) + #define SHU3_WODT_WODTFIXOFF BIT(4) + #define SHU3_WODT_DISWODTE BIT(5) + #define SHU3_WODT_DISWODTE2 BIT(6) + #define SHU3_WODT_WODTPDEN BIT(7) + #define SHU3_WODT_DQOE_CNT GENMASK(10, 8) + #define SHU3_WODT_DQOE_OPT BIT(11) + #define SHU3_WODT_TXUPD_SEL GENMASK(13, 12) + #define SHU3_WODT_TXUPD_W2R_SEL GENMASK(16, 14) + #define SHU3_WODT_DBIWR BIT(29) + #define SHU3_WODT_TWPSTEXT BIT(30) + #define SHU3_WODT_WPST2T BIT(31) +#define SHU3_DQSG 0x000014c4 + #define SHU3_DQSG_DLLFRZRFCOPT GENMASK(1, 0) + #define SHU3_DQSG_DLLFRZWROPT GENMASK(5, 4) + #define SHU3_DQSG_R_RSTBCNT_LATCH_OPT GENMASK(10, 8) + #define SHU3_DQSG_STB_UPDMASK_EN BIT(11) + #define SHU3_DQSG_STB_UPDMASKCYC GENMASK(15, 12) + #define SHU3_DQSG_DQSINCTL_PRE_SEL BIT(16) + #define SHU3_DQSG_SCINTV GENMASK(25, 20) +#define SHU3_SCINTV 0x000014c8 + #define SHU3_SCINTV_ODTREN BIT(0) + #define SHU3_SCINTV_TZQLAT GENMASK(5, 1) + #define SHU3_SCINTV_TZQLAT2 GENMASK(10, 6) + #define SHU3_SCINTV_RDDQC_INTV GENMASK(12, 11) + #define SHU3_SCINTV_MRW_INTV GENMASK(17, 13) + #define SHU3_SCINTV_DQS2DQ_SHU_PITHRD GENMASK(23, 18) + #define SHU3_SCINTV_DQS2DQ_FILT_PITHRD GENMASK(29, 24) + #define SHU3_SCINTV_DQSOSCENDIS BIT(30) +#define SHU3_MISC 0x000014cc + #define SHU3_MISC_REQQUE_MAXCNT GENMASK(3, 0) + #define SHU3_MISC_CKEHCMD GENMASK(5, 4) + #define SHU3_MISC_NORMPOP_LEN GENMASK(10, 8) + #define SHU3_MISC_PREA_INTV GENMASK(16, 12) +#define SHU3_DQS2DQ_TX 0x000014d0 + #define SHU3_DQS2DQ_TX_OE2DQ_OFFSET GENMASK(4, 0) +#define SHU3_HWSET_MR2 0x000014d4 + #define SHU3_HWSET_MR2_HWSET_MR2_MRSMA GENMASK(12, 0) + #define SHU3_HWSET_MR2_HWSET_MR2_OP GENMASK(23, 16) +#define SHU3_HWSET_MR13 0x000014d8 + #define SHU3_HWSET_MR13_HWSET_MR13_MRSMA GENMASK(12, 0) + #define SHU3_HWSET_MR13_HWSET_MR13_OP GENMASK(23, 16) +#define SHU3_HWSET_VRCG 0x000014dc + #define SHU3_HWSET_VRCG_HWSET_VRCG_MRSMA GENMASK(12, 0) + #define SHU3_HWSET_VRCG_HWSET_VRCG_OP GENMASK(23, 16) +#define SHU3_APHY_TX_PICG_CTRL 0x000014e4 + #define SHU3_APHY_TX_PICG_CTRL_APHYPI_CG_CK_SEL GENMASK(23, 20) + #define SHU3_APHY_TX_PICG_CTRL_APHYPI_CG_CK_OPT BIT(24) + #define SHU3_APHY_TX_PICG_CTRL_DDRPHY_CLK_DYN_GATING_SEL GENMASK(30, 27) + #define SHU3_APHY_TX_PICG_CTRL_DDRPHY_CLK_EN_OPT BIT(31) +#define SHU3RK0_DQSCTL 0x00001600 + #define SHU3RK0_DQSCTL_DQSINCTL GENMASK(3, 0) +#define SHU3RK0_DQSIEN 0x00001604 + #define SHU3RK0_DQSIEN_R0DQS0IEN GENMASK(6, 0) + #define SHU3RK0_DQSIEN_R0DQS1IEN GENMASK(14, 8) + #define SHU3RK0_DQSIEN_R0DQS2IEN GENMASK(22, 16) + #define SHU3RK0_DQSIEN_R0DQS3IEN GENMASK(30, 24) +#define SHU3RK0_DQSCAL 0x00001608 + #define SHU3RK0_DQSCAL_R0DQSIENLLMT GENMASK(6, 0) + #define SHU3RK0_DQSCAL_R0DQSIENLLMTEN BIT(7) + #define SHU3RK0_DQSCAL_R0DQSIENHLMT GENMASK(14, 8) + #define SHU3RK0_DQSCAL_R0DQSIENHLMTEN BIT(15) +#define SHU3RK0_PI 0x0000160c + #define SHU3RK0_PI_RK0_ARPI_DQ_B1 GENMASK(5, 0) + #define SHU3RK0_PI_RK0_ARPI_DQ_B0 GENMASK(13, 8) + #define SHU3RK0_PI_RK0_ARPI_DQM_B1 GENMASK(21, 16) + #define SHU3RK0_PI_RK0_ARPI_DQM_B0 GENMASK(29, 24) +#define SHU3RK0_DQSOSC 0x00001610 + #define SHU3RK0_DQSOSC_DQSOSC_BASE_RK0 GENMASK(15, 0) + #define SHU3RK0_DQSOSC_DQSOSC_BASE_RK0_B1 GENMASK(31, 16) +#define SHU3RK0_SELPH_ODTEN0 0x0000161c + #define SHU3RK0_SELPH_ODTEN0_TXDLY_B0_RODTEN GENMASK(2, 0) + #define SHU3RK0_SELPH_ODTEN0_TXDLY_B0_RODTEN_P1 GENMASK(6, 4) + #define SHU3RK0_SELPH_ODTEN0_TXDLY_B1_RODTEN GENMASK(10, 8) + #define SHU3RK0_SELPH_ODTEN0_TXDLY_B1_RODTEN_P1 GENMASK(14, 12) + #define SHU3RK0_SELPH_ODTEN0_TXDLY_B2_RODTEN GENMASK(18, 16) + #define SHU3RK0_SELPH_ODTEN0_TXDLY_B2_RODTEN_P1 GENMASK(22, 20) + #define SHU3RK0_SELPH_ODTEN0_TXDLY_B3_RODTEN GENMASK(26, 24) + #define SHU3RK0_SELPH_ODTEN0_TXDLY_B3_RODTEN_P1 GENMASK(30, 28) +#define SHU3RK0_SELPH_ODTEN1 0x00001620 + #define SHU3RK0_SELPH_ODTEN1_DLY_B0_RODTEN GENMASK(2, 0) + #define SHU3RK0_SELPH_ODTEN1_DLY_B0_RODTEN_P1 GENMASK(6, 4) + #define SHU3RK0_SELPH_ODTEN1_DLY_B1_RODTEN GENMASK(10, 8) + #define SHU3RK0_SELPH_ODTEN1_DLY_B1_RODTEN_P1 GENMASK(14, 12) + #define SHU3RK0_SELPH_ODTEN1_DLY_B2_RODTEN GENMASK(18, 16) + #define SHU3RK0_SELPH_ODTEN1_DLY_B2_RODTEN_P1 GENMASK(22, 20) + #define SHU3RK0_SELPH_ODTEN1_DLY_B3_RODTEN GENMASK(26, 24) + #define SHU3RK0_SELPH_ODTEN1_DLY_B3_RODTEN_P1 GENMASK(30, 28) +#define SHU3RK0_SELPH_DQSG0 0x00001624 + #define SHU3RK0_SELPH_DQSG0_TX_DLY_DQS0_GATED GENMASK(2, 0) + #define SHU3RK0_SELPH_DQSG0_TX_DLY_DQS0_GATED_P1 GENMASK(6, 4) + #define SHU3RK0_SELPH_DQSG0_TX_DLY_DQS1_GATED GENMASK(10, 8) + #define SHU3RK0_SELPH_DQSG0_TX_DLY_DQS1_GATED_P1 GENMASK(14, 12) + #define SHU3RK0_SELPH_DQSG0_TX_DLY_DQS2_GATED GENMASK(18, 16) + #define SHU3RK0_SELPH_DQSG0_TX_DLY_DQS2_GATED_P1 GENMASK(22, 20) + #define SHU3RK0_SELPH_DQSG0_TX_DLY_DQS3_GATED GENMASK(26, 24) + #define SHU3RK0_SELPH_DQSG0_TX_DLY_DQS3_GATED_P1 GENMASK(30, 28) +#define SHU3RK0_SELPH_DQSG1 0x00001628 + #define SHU3RK0_SELPH_DQSG1_REG_DLY_DQS0_GATED GENMASK(2, 0) + #define SHU3RK0_SELPH_DQSG1_REG_DLY_DQS0_GATED_P1 GENMASK(6, 4) + #define SHU3RK0_SELPH_DQSG1_REG_DLY_DQS1_GATED GENMASK(10, 8) + #define SHU3RK0_SELPH_DQSG1_REG_DLY_DQS1_GATED_P1 GENMASK(14, 12) + #define SHU3RK0_SELPH_DQSG1_REG_DLY_DQS2_GATED GENMASK(18, 16) + #define SHU3RK0_SELPH_DQSG1_REG_DLY_DQS2_GATED_P1 GENMASK(22, 20) + #define SHU3RK0_SELPH_DQSG1_REG_DLY_DQS3_GATED GENMASK(26, 24) + #define SHU3RK0_SELPH_DQSG1_REG_DLY_DQS3_GATED_P1 GENMASK(30, 28) +#define SHU3RK0_SELPH_DQ0 0x0000162c + #define SHU3RK0_SELPH_DQ0_TXDLY_DQ0 GENMASK(2, 0) + #define SHU3RK0_SELPH_DQ0_TXDLY_DQ1 GENMASK(6, 4) + #define SHU3RK0_SELPH_DQ0_TXDLY_DQ2 GENMASK(10, 8) + #define SHU3RK0_SELPH_DQ0_TXDLY_DQ3 GENMASK(14, 12) + #define SHU3RK0_SELPH_DQ0_TXDLY_OEN_DQ0 GENMASK(18, 16) + #define SHU3RK0_SELPH_DQ0_TXDLY_OEN_DQ1 GENMASK(22, 20) + #define SHU3RK0_SELPH_DQ0_TXDLY_OEN_DQ2 GENMASK(26, 24) + #define SHU3RK0_SELPH_DQ0_TXDLY_OEN_DQ3 GENMASK(30, 28) +#define SHU3RK0_SELPH_DQ1 0x00001630 + #define SHU3RK0_SELPH_DQ1_TXDLY_DQM0 GENMASK(2, 0) + #define SHU3RK0_SELPH_DQ1_TXDLY_DQM1 GENMASK(6, 4) + #define SHU3RK0_SELPH_DQ1_TXDLY_DQM2 GENMASK(10, 8) + #define SHU3RK0_SELPH_DQ1_TXDLY_DQM3 GENMASK(14, 12) + #define SHU3RK0_SELPH_DQ1_TXDLY_OEN_DQM0 GENMASK(18, 16) + #define SHU3RK0_SELPH_DQ1_TXDLY_OEN_DQM1 GENMASK(22, 20) + #define SHU3RK0_SELPH_DQ1_TXDLY_OEN_DQM2 GENMASK(26, 24) + #define SHU3RK0_SELPH_DQ1_TXDLY_OEN_DQM3 GENMASK(30, 28) +#define SHU3RK0_SELPH_DQ2 0x00001634 + #define SHU3RK0_SELPH_DQ2_DLY_DQ0 GENMASK(2, 0) + #define SHU3RK0_SELPH_DQ2_DLY_DQ1 GENMASK(6, 4) + #define SHU3RK0_SELPH_DQ2_DLY_DQ2 GENMASK(10, 8) + #define SHU3RK0_SELPH_DQ2_DLY_DQ3 GENMASK(14, 12) + #define SHU3RK0_SELPH_DQ2_DLY_OEN_DQ0 GENMASK(18, 16) + #define SHU3RK0_SELPH_DQ2_DLY_OEN_DQ1 GENMASK(22, 20) + #define SHU3RK0_SELPH_DQ2_DLY_OEN_DQ2 GENMASK(26, 24) + #define SHU3RK0_SELPH_DQ2_DLY_OEN_DQ3 GENMASK(30, 28) +#define SHU3RK0_SELPH_DQ3 0x00001638 + #define SHU3RK0_SELPH_DQ3_DLY_DQM0 GENMASK(2, 0) + #define SHU3RK0_SELPH_DQ3_DLY_DQM1 GENMASK(6, 4) + #define SHU3RK0_SELPH_DQ3_DLY_DQM2 GENMASK(10, 8) + #define SHU3RK0_SELPH_DQ3_DLY_DQM3 GENMASK(14, 12) + #define SHU3RK0_SELPH_DQ3_DLY_OEN_DQM0 GENMASK(18, 16) + #define SHU3RK0_SELPH_DQ3_DLY_OEN_DQM1 GENMASK(22, 20) + #define SHU3RK0_SELPH_DQ3_DLY_OEN_DQM2 GENMASK(26, 24) + #define SHU3RK0_SELPH_DQ3_DLY_OEN_DQM3 GENMASK(30, 28) +#define SHU3RK0_DQS2DQ_CAL1 0x00001640 + #define SHU3RK0_DQS2DQ_CAL1_BOOT_ORIG_UI_RK0_DQ0 GENMASK(10, 0) + #define SHU3RK0_DQS2DQ_CAL1_BOOT_ORIG_UI_RK0_DQ1 GENMASK(26, 16) +#define SHU3RK0_DQS2DQ_CAL2 0x00001644 + #define SHU3RK0_DQS2DQ_CAL2_BOOT_TARG_UI_RK0_DQ0 GENMASK(10, 0) + #define SHU3RK0_DQS2DQ_CAL2_BOOT_TARG_UI_RK0_DQ1 GENMASK(26, 16) +#define SHU3RK0_DQS2DQ_CAL3 0x00001648 + #define SHU3RK0_DQS2DQ_CAL3_BOOT_TARG_UI_RK0_OEN_DQ0 GENMASK(5, 0) + #define SHU3RK0_DQS2DQ_CAL3_BOOT_TARG_UI_RK0_OEN_DQ1 GENMASK(11, 6) + #define SHU3RK0_DQS2DQ_CAL3_BOOT_TARG_UI_RK0_OEN_DQ0_B4TO0 GENMASK(16, 12) + #define SHU3RK0_DQS2DQ_CAL3_BOOT_TARG_UI_RK0_OEN_DQ1_B4TO0 GENMASK(21, 17) +#define SHU3RK0_DQS2DQ_CAL4 0x0000164c + #define SHU3RK0_DQS2DQ_CAL4_BOOT_TARG_UI_RK0_OEN_DQM0 GENMASK(5, 0) + #define SHU3RK0_DQS2DQ_CAL4_BOOT_TARG_UI_RK0_OEN_DQM1 GENMASK(11, 6) + #define SHU3RK0_DQS2DQ_CAL4_BOOT_TARG_UI_RK0_OEN_DQM0_B4TO0 GENMASK(16, 12) + #define SHU3RK0_DQS2DQ_CAL4_BOOT_TARG_UI_RK0_OEN_DQM1_B4TO0 GENMASK(21, 17) +#define SHU3RK0_DQS2DQ_CAL5 0x00001650 + #define SHU3RK0_DQS2DQ_CAL5_BOOT_TARG_UI_RK0_DQM0 GENMASK(10, 0) + #define SHU3RK0_DQS2DQ_CAL5_BOOT_TARG_UI_RK0_DQM1 GENMASK(26, 16) +#define SHU3RK1_DQSCTL 0x00001700 + #define SHU3RK1_DQSCTL_R1DQSINCTL GENMASK(3, 0) +#define SHU3RK1_DQSIEN 0x00001704 + #define SHU3RK1_DQSIEN_R1DQS0IEN GENMASK(6, 0) + #define SHU3RK1_DQSIEN_R1DQS1IEN GENMASK(14, 8) + #define SHU3RK1_DQSIEN_R1DQS2IEN GENMASK(22, 16) + #define SHU3RK1_DQSIEN_R1DQS3IEN GENMASK(30, 24) +#define SHU3RK1_DQSCAL 0x00001708 + #define SHU3RK1_DQSCAL_R1DQSIENLLMT GENMASK(6, 0) + #define SHU3RK1_DQSCAL_R1DQSIENLLMTEN BIT(7) + #define SHU3RK1_DQSCAL_R1DQSIENHLMT GENMASK(14, 8) + #define SHU3RK1_DQSCAL_R1DQSIENHLMTEN BIT(15) +#define SHU3RK1_PI 0x0000170c + #define SHU3RK1_PI_RK1_ARPI_DQ_B1 GENMASK(5, 0) + #define SHU3RK1_PI_RK1_ARPI_DQ_B0 GENMASK(13, 8) + #define SHU3RK1_PI_RK1_ARPI_DQM_B1 GENMASK(21, 16) + #define SHU3RK1_PI_RK1_ARPI_DQM_B0 GENMASK(29, 24) +#define SHU3RK1_DQSOSC 0x00001710 + #define SHU3RK1_DQSOSC_DQSOSC_BASE_RK1 GENMASK(15, 0) + #define SHU3RK1_DQSOSC_DQSOSC_BASE_RK1_B1 GENMASK(31, 16) +#define SHU3RK1_SELPH_ODTEN0 0x0000171c + #define SHU3RK1_SELPH_ODTEN0_TXDLY_B0_R1RODTEN GENMASK(2, 0) + #define SHU3RK1_SELPH_ODTEN0_TXDLY_B0_R1RODTEN_P1 GENMASK(6, 4) + #define SHU3RK1_SELPH_ODTEN0_TXDLY_B1_R1RODTEN GENMASK(10, 8) + #define SHU3RK1_SELPH_ODTEN0_TXDLY_B1_R1RODTEN_P1 GENMASK(14, 12) + #define SHU3RK1_SELPH_ODTEN0_TXDLY_B2_R1RODTEN GENMASK(18, 16) + #define SHU3RK1_SELPH_ODTEN0_TXDLY_B2_R1RODTEN_P1 GENMASK(22, 20) + #define SHU3RK1_SELPH_ODTEN0_TXDLY_B3_R1RODTEN GENMASK(26, 24) + #define SHU3RK1_SELPH_ODTEN0_TXDLY_B3_R1RODTEN_P1 GENMASK(30, 28) +#define SHU3RK1_SELPH_ODTEN1 0x00001720 + #define SHU3RK1_SELPH_ODTEN1_DLY_B0_R1RODTEN GENMASK(2, 0) + #define SHU3RK1_SELPH_ODTEN1_DLY_B0_R1RODTEN_P1 GENMASK(6, 4) + #define SHU3RK1_SELPH_ODTEN1_DLY_B1_R1RODTEN GENMASK(10, 8) + #define SHU3RK1_SELPH_ODTEN1_DLY_B1_R1RODTEN_P1 GENMASK(14, 12) + #define SHU3RK1_SELPH_ODTEN1_DLY_B2_R1RODTEN GENMASK(18, 16) + #define SHU3RK1_SELPH_ODTEN1_DLY_B2_R1RODTEN_P1 GENMASK(22, 20) + #define SHU3RK1_SELPH_ODTEN1_DLY_B3_R1RODTEN GENMASK(26, 24) + #define SHU3RK1_SELPH_ODTEN1_DLY_B3_R1RODTEN_P1 GENMASK(30, 28) +#define SHU3RK1_SELPH_DQSG0 0x00001724 + #define SHU3RK1_SELPH_DQSG0_TX_DLY_R1DQS0_GATED GENMASK(2, 0) + #define SHU3RK1_SELPH_DQSG0_TX_DLY_R1DQS0_GATED_P1 GENMASK(6, 4) + #define SHU3RK1_SELPH_DQSG0_TX_DLY_R1DQS1_GATED GENMASK(10, 8) + #define SHU3RK1_SELPH_DQSG0_TX_DLY_R1DQS1_GATED_P1 GENMASK(14, 12) + #define SHU3RK1_SELPH_DQSG0_TX_DLY_R1DQS2_GATED GENMASK(18, 16) + #define SHU3RK1_SELPH_DQSG0_TX_DLY_R1DQS2_GATED_P1 GENMASK(22, 20) + #define SHU3RK1_SELPH_DQSG0_TX_DLY_R1DQS3_GATED GENMASK(26, 24) + #define SHU3RK1_SELPH_DQSG0_TX_DLY_R1DQS3_GATED_P1 GENMASK(30, 28) +#define SHU3RK1_SELPH_DQSG1 0x00001728 + #define SHU3RK1_SELPH_DQSG1_REG_DLY_R1DQS0_GATED GENMASK(2, 0) + #define SHU3RK1_SELPH_DQSG1_REG_DLY_R1DQS0_GATED_P1 GENMASK(6, 4) + #define SHU3RK1_SELPH_DQSG1_REG_DLY_R1DQS1_GATED GENMASK(10, 8) + #define SHU3RK1_SELPH_DQSG1_REG_DLY_R1DQS1_GATED_P1 GENMASK(14, 12) + #define SHU3RK1_SELPH_DQSG1_REG_DLY_R1DQS2_GATED GENMASK(18, 16) + #define SHU3RK1_SELPH_DQSG1_REG_DLY_R1DQS2_GATED_P1 GENMASK(22, 20) + #define SHU3RK1_SELPH_DQSG1_REG_DLY_R1DQS3_GATED GENMASK(26, 24) + #define SHU3RK1_SELPH_DQSG1_REG_DLY_R1DQS3_GATED_P1 GENMASK(30, 28) +#define SHU3RK1_SELPH_DQ0 0x0000172c + #define SHU3RK1_SELPH_DQ0_TX_DLY_R1DQ0 GENMASK(2, 0) + #define SHU3RK1_SELPH_DQ0_TX_DLY_R1DQ1 GENMASK(6, 4) + #define SHU3RK1_SELPH_DQ0_TX_DLY_R1DQ2 GENMASK(10, 8) + #define SHU3RK1_SELPH_DQ0_TX_DLY_R1DQ3 GENMASK(14, 12) + #define SHU3RK1_SELPH_DQ0_TX_DLY_R1OEN_DQ0 GENMASK(18, 16) + #define SHU3RK1_SELPH_DQ0_TX_DLY_R1OEN_DQ1 GENMASK(22, 20) + #define SHU3RK1_SELPH_DQ0_TX_DLY_R1OEN_DQ2 GENMASK(26, 24) + #define SHU3RK1_SELPH_DQ0_TX_DLY_R1OEN_DQ3 GENMASK(30, 28) +#define SHU3RK1_SELPH_DQ1 0x00001730 + #define SHU3RK1_SELPH_DQ1_TX_DLY_R1DQM0 GENMASK(2, 0) + #define SHU3RK1_SELPH_DQ1_TX_DLY_R1DQM1 GENMASK(6, 4) + #define SHU3RK1_SELPH_DQ1_TX_DLY_R1DQM2 GENMASK(10, 8) + #define SHU3RK1_SELPH_DQ1_TX_DLY_R1DQM3 GENMASK(14, 12) + #define SHU3RK1_SELPH_DQ1_TX_DLY_R1OEN_DQM0 GENMASK(18, 16) + #define SHU3RK1_SELPH_DQ1_TX_DLY_R1OEN_DQM1 GENMASK(22, 20) + #define SHU3RK1_SELPH_DQ1_TX_DLY_R1OEN_DQM2 GENMASK(26, 24) + #define SHU3RK1_SELPH_DQ1_TX_DLY_R1OEN_DQM3 GENMASK(30, 28) +#define SHU3RK1_SELPH_DQ2 0x00001734 + #define SHU3RK1_SELPH_DQ2_DLY_R1DQ0 GENMASK(2, 0) + #define SHU3RK1_SELPH_DQ2_DLY_R1DQ1 GENMASK(6, 4) + #define SHU3RK1_SELPH_DQ2_DLY_R1DQ2 GENMASK(10, 8) + #define SHU3RK1_SELPH_DQ2_DLY_R1DQ3 GENMASK(14, 12) + #define SHU3RK1_SELPH_DQ2_DLY_R1OEN_DQ0 GENMASK(18, 16) + #define SHU3RK1_SELPH_DQ2_DLY_R1OEN_DQ1 GENMASK(22, 20) + #define SHU3RK1_SELPH_DQ2_DLY_R1OEN_DQ2 GENMASK(26, 24) + #define SHU3RK1_SELPH_DQ2_DLY_R1OEN_DQ3 GENMASK(30, 28) +#define SHU3RK1_SELPH_DQ3 0x00001738 + #define SHU3RK1_SELPH_DQ3_DLY_R1DQM0 GENMASK(2, 0) + #define SHU3RK1_SELPH_DQ3_DLY_R1DQM1 GENMASK(6, 4) + #define SHU3RK1_SELPH_DQ3_DLY_R1DQM2 GENMASK(10, 8) + #define SHU3RK1_SELPH_DQ3_DLY_R1DQM3 GENMASK(14, 12) + #define SHU3RK1_SELPH_DQ3_DLY_R1OEN_DQM0 GENMASK(18, 16) + #define SHU3RK1_SELPH_DQ3_DLY_R1OEN_DQM1 GENMASK(22, 20) + #define SHU3RK1_SELPH_DQ3_DLY_R1OEN_DQM2 GENMASK(26, 24) + #define SHU3RK1_SELPH_DQ3_DLY_R1OEN_DQM3 GENMASK(30, 28) +#define SHU3RK1_DQS2DQ_CAL1 0x00001740 + #define SHU3RK1_DQS2DQ_CAL1_BOOT_ORIG_UI_RK1_DQ0 GENMASK(10, 0) + #define SHU3RK1_DQS2DQ_CAL1_BOOT_ORIG_UI_RK1_DQ1 GENMASK(26, 16) +#define SHU3RK1_DQS2DQ_CAL2 0x00001744 + #define SHU3RK1_DQS2DQ_CAL2_BOOT_TARG_UI_RK1_DQ0 GENMASK(10, 0) + #define SHU3RK1_DQS2DQ_CAL2_BOOT_TARG_UI_RK1_DQ1 GENMASK(26, 16) +#define SHU3RK1_DQS2DQ_CAL3 0x00001748 + #define SHU3RK1_DQS2DQ_CAL3_BOOT_TARG_UI_RK1_OEN_DQ0 GENMASK(5, 0) + #define SHU3RK1_DQS2DQ_CAL3_BOOT_TARG_UI_RK1_OEN_DQ1 GENMASK(11, 6) + #define SHU3RK1_DQS2DQ_CAL3_BOOT_TARG_UI_RK1_OEN_DQ0_B4TO0 GENMASK(16, 12) + #define SHU3RK1_DQS2DQ_CAL3_BOOT_TARG_UI_RK1_OEN_DQ1_B4TO0 GENMASK(21, 17) +#define SHU3RK1_DQS2DQ_CAL4 0x0000174c + #define SHU3RK1_DQS2DQ_CAL4_BOOT_TARG_UI_RK1_OEN_DQM0 GENMASK(5, 0) + #define SHU3RK1_DQS2DQ_CAL4_BOOT_TARG_UI_RK1_OEN_DQM1 GENMASK(11, 6) + #define SHU3RK1_DQS2DQ_CAL4_BOOT_TARG_UI_RK1_OEN_DQM0_B4TO0 GENMASK(16, 12) + #define SHU3RK1_DQS2DQ_CAL4_BOOT_TARG_UI_RK1_OEN_DQM1_B4TO0 GENMASK(21, 17) +#define SHU3RK1_DQS2DQ_CAL5 0x00001750 + #define SHU3RK1_DQS2DQ_CAL5_BOOT_TARG_UI_RK1_DQM0 GENMASK(10, 0) + #define SHU3RK1_DQS2DQ_CAL5_BOOT_TARG_UI_RK1_DQM1 GENMASK(26, 16) +#define SHU3RK2_DQSCTL 0x00001800 + #define SHU3RK2_DQSCTL_R2DQSINCTL GENMASK(3, 0) +#define SHU3RK2_DQSIEN 0x00001804 + #define SHU3RK2_DQSIEN_R2DQS0IEN GENMASK(6, 0) + #define SHU3RK2_DQSIEN_R2DQS1IEN GENMASK(14, 8) + #define SHU3RK2_DQSIEN_R2DQS2IEN GENMASK(22, 16) + #define SHU3RK2_DQSIEN_R2DQS3IEN GENMASK(30, 24) +#define SHU3RK2_DQSCAL 0x00001808 + #define SHU3RK2_DQSCAL_R2DQSIENLLMT GENMASK(6, 0) + #define SHU3RK2_DQSCAL_R2DQSIENLLMTEN BIT(7) + #define SHU3RK2_DQSCAL_R2DQSIENHLMT GENMASK(14, 8) + #define SHU3RK2_DQSCAL_R2DQSIENHLMTEN BIT(15) +#define SHU3RK2_PI 0x0000180c + #define SHU3RK2_PI_RK2_ARPI_DQ_B1 GENMASK(5, 0) + #define SHU3RK2_PI_RK2_ARPI_DQ_B0 GENMASK(13, 8) + #define SHU3RK2_PI_RK2_ARPI_DQM_B1 GENMASK(21, 16) + #define SHU3RK2_PI_RK2_ARPI_DQM_B0 GENMASK(29, 24) +#define SHU3RK2_DQSOSC 0x00001810 + #define SHU3RK2_DQSOSC_DQSOSC_BASE_RK2 GENMASK(15, 0) + #define SHU3RK2_DQSOSC_DQSOSC_BASE_RK2_B1 GENMASK(31, 16) +#define SHU3RK2_SELPH_ODTEN0 0x0000181c + #define SHU3RK2_SELPH_ODTEN0_TXDLY_B0_R2RODTEN GENMASK(2, 0) + #define SHU3RK2_SELPH_ODTEN0_TXDLY_B0_R2RODTEN_P1 GENMASK(6, 4) + #define SHU3RK2_SELPH_ODTEN0_TXDLY_B1_R2RODTEN GENMASK(10, 8) + #define SHU3RK2_SELPH_ODTEN0_TXDLY_B1_R2RODTEN_P1 GENMASK(14, 12) + #define SHU3RK2_SELPH_ODTEN0_TXDLY_B2_R2RODTEN GENMASK(18, 16) + #define SHU3RK2_SELPH_ODTEN0_TXDLY_B2_R2RODTEN_P1 GENMASK(22, 20) + #define SHU3RK2_SELPH_ODTEN0_TXDLY_B3_R2RODTEN GENMASK(26, 24) + #define SHU3RK2_SELPH_ODTEN0_TXDLY_B3_R2RODTEN_P1 GENMASK(30, 28) +#define SHU3RK2_SELPH_ODTEN1 0x00001820 + #define SHU3RK2_SELPH_ODTEN1_DLY_B0_R2RODTEN GENMASK(2, 0) + #define SHU3RK2_SELPH_ODTEN1_DLY_B0_R2RODTEN_P1 GENMASK(6, 4) + #define SHU3RK2_SELPH_ODTEN1_DLY_B1_R2RODTEN GENMASK(10, 8) + #define SHU3RK2_SELPH_ODTEN1_DLY_B1_R2RODTEN_P1 GENMASK(14, 12) + #define SHU3RK2_SELPH_ODTEN1_DLY_B2_R2RODTEN GENMASK(18, 16) + #define SHU3RK2_SELPH_ODTEN1_DLY_B2_R2RODTEN_P1 GENMASK(22, 20) + #define SHU3RK2_SELPH_ODTEN1_DLY_B3_R2RODTEN GENMASK(26, 24) + #define SHU3RK2_SELPH_ODTEN1_DLY_B3_R2RODTEN_P1 GENMASK(30, 28) +#define SHU3RK2_SELPH_DQSG0 0x00001824 + #define SHU3RK2_SELPH_DQSG0_TX_DLY_R2DQS0_GATED GENMASK(2, 0) + #define SHU3RK2_SELPH_DQSG0_TX_DLY_R2DQS0_GATED_P1 GENMASK(6, 4) + #define SHU3RK2_SELPH_DQSG0_TX_DLY_R2DQS1_GATED GENMASK(10, 8) + #define SHU3RK2_SELPH_DQSG0_TX_DLY_R2DQS1_GATED_P1 GENMASK(14, 12) + #define SHU3RK2_SELPH_DQSG0_TX_DLY_R2DQS2_GATED GENMASK(18, 16) + #define SHU3RK2_SELPH_DQSG0_TX_DLY_R2DQS2_GATED_P1 GENMASK(22, 20) + #define SHU3RK2_SELPH_DQSG0_TX_DLY_R2DQS3_GATED GENMASK(26, 24) + #define SHU3RK2_SELPH_DQSG0_TX_DLY_R2DQS3_GATED_P1 GENMASK(30, 28) +#define SHU3RK2_SELPH_DQSG1 0x00001828 + #define SHU3RK2_SELPH_DQSG1_REG_DLY_R2DQS0_GATED GENMASK(2, 0) + #define SHU3RK2_SELPH_DQSG1_REG_DLY_R2DQS0_GATED_P1 GENMASK(6, 4) + #define SHU3RK2_SELPH_DQSG1_REG_DLY_R2DQS1_GATED GENMASK(10, 8) + #define SHU3RK2_SELPH_DQSG1_REG_DLY_R2DQS1_GATED_P1 GENMASK(14, 12) + #define SHU3RK2_SELPH_DQSG1_REG_DLY_R2DQS2_GATED GENMASK(18, 16) + #define SHU3RK2_SELPH_DQSG1_REG_DLY_R2DQS2_GATED_P1 GENMASK(22, 20) + #define SHU3RK2_SELPH_DQSG1_REG_DLY_R2DQS3_GATED GENMASK(26, 24) + #define SHU3RK2_SELPH_DQSG1_REG_DLY_R2DQS3_GATED_P1 GENMASK(30, 28) +#define SHU3RK2_SELPH_DQ0 0x0000182c + #define SHU3RK2_SELPH_DQ0_TX_DLY_R2DQ0 GENMASK(2, 0) + #define SHU3RK2_SELPH_DQ0_TX_DLY_R2DQ1 GENMASK(6, 4) + #define SHU3RK2_SELPH_DQ0_TX_DLY_R2DQ2 GENMASK(10, 8) + #define SHU3RK2_SELPH_DQ0_TX_DLY_R2DQ3 GENMASK(14, 12) + #define SHU3RK2_SELPH_DQ0_TX_DLY_R2OEN_DQ0 GENMASK(18, 16) + #define SHU3RK2_SELPH_DQ0_TX_DLY_R2OEN_DQ1 GENMASK(22, 20) + #define SHU3RK2_SELPH_DQ0_TX_DLY_R2OEN_DQ2 GENMASK(26, 24) + #define SHU3RK2_SELPH_DQ0_TX_DLY_R2OEN_DQ3 GENMASK(30, 28) +#define SHU3RK2_SELPH_DQ1 0x00001830 + #define SHU3RK2_SELPH_DQ1_TX_DLY_R2DQM0 GENMASK(2, 0) + #define SHU3RK2_SELPH_DQ1_TX_DLY_R2DQM1 GENMASK(6, 4) + #define SHU3RK2_SELPH_DQ1_TX_DLY_R2DQM2 GENMASK(10, 8) + #define SHU3RK2_SELPH_DQ1_TX_DLY_R2DQM3 GENMASK(14, 12) + #define SHU3RK2_SELPH_DQ1_TX_DLY_R2OEN_DQM0 GENMASK(18, 16) + #define SHU3RK2_SELPH_DQ1_TX_DLY_R2OEN_DQM1 GENMASK(22, 20) + #define SHU3RK2_SELPH_DQ1_TX_DLY_R2OEN_DQM2 GENMASK(26, 24) + #define SHU3RK2_SELPH_DQ1_TX_DLY_R2OEN_DQM3 GENMASK(30, 28) +#define SHU3RK2_SELPH_DQ2 0x00001834 + #define SHU3RK2_SELPH_DQ2_DLY_R2DQ0 GENMASK(2, 0) + #define SHU3RK2_SELPH_DQ2_DLY_R2DQ1 GENMASK(6, 4) + #define SHU3RK2_SELPH_DQ2_DLY_R2DQ2 GENMASK(10, 8) + #define SHU3RK2_SELPH_DQ2_DLY_R2DQ3 GENMASK(14, 12) + #define SHU3RK2_SELPH_DQ2_DLY_R2OEN_DQ0 GENMASK(18, 16) + #define SHU3RK2_SELPH_DQ2_DLY_R2OEN_DQ1 GENMASK(22, 20) + #define SHU3RK2_SELPH_DQ2_DLY_R2OEN_DQ2 GENMASK(26, 24) + #define SHU3RK2_SELPH_DQ2_DLY_R2OEN_DQ3 GENMASK(30, 28) +#define SHU3RK2_SELPH_DQ3 0x00001838 + #define SHU3RK2_SELPH_DQ3_DLY_R2DQM0 GENMASK(2, 0) + #define SHU3RK2_SELPH_DQ3_DLY_R2DQM1 GENMASK(6, 4) + #define SHU3RK2_SELPH_DQ3_DLY_R2DQM2 GENMASK(10, 8) + #define SHU3RK2_SELPH_DQ3_DLY_R2DQM3 GENMASK(14, 12) + #define SHU3RK2_SELPH_DQ3_DLY_R2OEN_DQM0 GENMASK(18, 16) + #define SHU3RK2_SELPH_DQ3_DLY_R2OEN_DQM1 GENMASK(22, 20) + #define SHU3RK2_SELPH_DQ3_DLY_R2OEN_DQM2 GENMASK(26, 24) + #define SHU3RK2_SELPH_DQ3_DLY_R2OEN_DQM3 GENMASK(30, 28) +#define SHU3RK2_DQS2DQ_CAL1 0x00001840 + #define SHU3RK2_DQS2DQ_CAL1_BOOT_ORIG_UI_RK2_DQ0 GENMASK(10, 0) + #define SHU3RK2_DQS2DQ_CAL1_BOOT_ORIG_UI_RK2_DQ1 GENMASK(26, 16) +#define SHU3RK2_DQS2DQ_CAL2 0x00001844 + #define SHU3RK2_DQS2DQ_CAL2_BOOT_TARG_UI_RK2_DQ0 GENMASK(10, 0) + #define SHU3RK2_DQS2DQ_CAL2_BOOT_TARG_UI_RK2_DQ1 GENMASK(26, 16) +#define SHU3RK2_DQS2DQ_CAL3 0x00001848 + #define SHU3RK2_DQS2DQ_CAL3_BOOT_TARG_UI_RK2_OEN_DQ0 GENMASK(5, 0) + #define SHU3RK2_DQS2DQ_CAL3_BOOT_TARG_UI_RK2_OEN_DQ1 GENMASK(11, 6) +#define SHU3RK2_DQS2DQ_CAL4 0x0000184c + #define SHU3RK2_DQS2DQ_CAL4_BOOT_TARG_UI_RK2_OEN_DQM0 GENMASK(5, 0) + #define SHU3RK2_DQS2DQ_CAL4_BOOT_TARG_UI_RK2_OEN_DQM1 GENMASK(11, 6) +#define SHU3RK2_DQS2DQ_CAL5 0x00001850 + #define SHU3RK2_DQS2DQ_CAL5_BOOT_TARG_UI_RK2_DQM0 GENMASK(10, 0) + #define SHU3RK2_DQS2DQ_CAL5_BOOT_TARG_UI_RK2_DQM1 GENMASK(26, 16) +#define SHU3_DQSG_RETRY 0x00001854 + #define SHU3_DQSG_RETRY_R_DQSGRETRY_SW_RESET BIT(0) + #define SHU3_DQSG_RETRY_R_DQSG_RETRY_SW_EN BIT(1) + #define SHU3_DQSG_RETRY_R_DDR1866_PLUS BIT(2) + #define SHU3_DQSG_RETRY_R_RETRY_ONCE BIT(3) + #define SHU3_DQSG_RETRY_R_RETRY_3TIMES BIT(4) + #define SHU3_DQSG_RETRY_R_RETRY_1RANK BIT(5) + #define SHU3_DQSG_RETRY_R_RETRY_SAV_MSK BIT(6) + #define SHU3_DQSG_RETRY_R_DM4BYTE BIT(7) + #define SHU3_DQSG_RETRY_R_DQSIENLAT GENMASK(11, 8) + #define SHU3_DQSG_RETRY_R_STBENCMP_ALLBYTE BIT(12) + #define SHU3_DQSG_RETRY_R_XSR_DQSG_RETRY_EN BIT(13) + #define SHU3_DQSG_RETRY_R_XSR_RETRY_SPM_MODE BIT(14) + #define SHU3_DQSG_RETRY_R_RETRY_CMP_DATA BIT(15) + #define SHU3_DQSG_RETRY_R_RETRY_ALE_BLOCK_MASK BIT(20) + #define SHU3_DQSG_RETRY_R_RDY_SEL_DLE BIT(21) + #define SHU3_DQSG_RETRY_R_RETRY_ROUND_NUM GENMASK(25, 24) + #define SHU3_DQSG_RETRY_R_RETRY_RANKSEL_FROM_PHY BIT(28) + #define SHU3_DQSG_RETRY_R_RETRY_PA_DSIABLE BIT(29) + #define SHU3_DQSG_RETRY_R_RETRY_STBEN_RESET_MSK BIT(30) + #define SHU3_DQSG_RETRY_R_RETRY_USE_BURST_MDOE BIT(31) +#define SHU4_ACTIM0 0x00001a00 + #define SHU4_ACTIM0_TWTR GENMASK(3, 0) + #define SHU4_ACTIM0_TWR GENMASK(12, 8) + #define SHU4_ACTIM0_TRRD GENMASK(18, 16) + #define SHU4_ACTIM0_TRCD GENMASK(27, 24) +#define SHU4_ACTIM1 0x00001a04 + #define SHU4_ACTIM1_TRPAB GENMASK(2, 0) + #define SHU4_ACTIM1_TRP GENMASK(11, 8) + #define SHU4_ACTIM1_TRAS GENMASK(19, 16) + #define SHU4_ACTIM1_TRC GENMASK(28, 24) +#define SHU4_ACTIM2 0x00001a08 + #define SHU4_ACTIM2_TXP GENMASK(2, 0) + #define SHU4_ACTIM2_TRTP GENMASK(10, 8) + #define SHU4_ACTIM2_TR2W GENMASK(19, 16) + #define SHU4_ACTIM2_TFAW GENMASK(28, 24) +#define SHU4_ACTIM3 0x00001a0c + #define SHU4_ACTIM3_TRFCPB GENMASK(7, 0) + #define SHU4_ACTIM3_TRFC GENMASK(23, 16) + #define SHU4_ACTIM3_REFCNT GENMASK(31, 24) +#define SHU4_ACTIM4 0x00001a10 + #define SHU4_ACTIM4_TXREFCNT GENMASK(9, 0) + #define SHU4_ACTIM4_REFCNT_FR_CLK GENMASK(23, 16) + #define SHU4_ACTIM4_TZQCS GENMASK(31, 24) +#define SHU4_ACTIM5 0x00001a14 + #define SHU4_ACTIM5_TR2PD GENMASK(4, 0) + #define SHU4_ACTIM5_TWTPD GENMASK(12, 8) + #define SHU4_ACTIM5_TMRR2W GENMASK(27, 24) +#define SHU4_ACTIM6 0x00001a18 + #define SHU4_ACTIM6_BGTCCD GENMASK(1, 0) + #define SHU4_ACTIM6_BGTWTR GENMASK(7, 4) + #define SHU4_ACTIM6_TWRMPR GENMASK(11, 8) + #define SHU4_ACTIM6_BGTRRD GENMASK(14, 12) +#define SHU4_ACTIM_XRT 0x00001a1c + #define SHU4_ACTIM_XRT_XRTR2R GENMASK(4, 0) + #define SHU4_ACTIM_XRT_XRTR2W GENMASK(11, 8) + #define SHU4_ACTIM_XRT_XRTW2R GENMASK(18, 16) + #define SHU4_ACTIM_XRT_XRTW2W GENMASK(27, 24) +#define SHU4_AC_TIME_05T 0x00001a20 + #define SHU4_AC_TIME_05T_TRC_05T BIT(0) + #define SHU4_AC_TIME_05T_TRFCPB_05T BIT(1) + #define SHU4_AC_TIME_05T_TRFC_05T BIT(2) + #define SHU4_AC_TIME_05T_TXP_05T BIT(4) + #define SHU4_AC_TIME_05T_TRTP_05T BIT(5) + #define SHU4_AC_TIME_05T_TRCD_05T BIT(6) + #define SHU4_AC_TIME_05T_TRP_05T BIT(7) + #define SHU4_AC_TIME_05T_TRPAB_05T BIT(8) + #define SHU4_AC_TIME_05T_TRAS_05T BIT(9) + #define SHU4_AC_TIME_05T_TWR_M05T BIT(10) + #define SHU4_AC_TIME_05T_TRRD_05T BIT(12) + #define SHU4_AC_TIME_05T_TFAW_05T BIT(13) + #define SHU4_AC_TIME_05T_TR2PD_05T BIT(15) + #define SHU4_AC_TIME_05T_TWTPD_M05T BIT(16) + #define SHU4_AC_TIME_05T_BGTRRD_05T BIT(21) + #define SHU4_AC_TIME_05T_BGTCCD_05T BIT(22) + #define SHU4_AC_TIME_05T_BGTWTR_05T BIT(23) + #define SHU4_AC_TIME_05T_TR2W_05T BIT(24) + #define SHU4_AC_TIME_05T_TWTR_M05T BIT(25) + #define SHU4_AC_TIME_05T_XRTR2W_05T BIT(26) + #define SHU4_AC_TIME_05T_XRTW2R_M05T BIT(27) +#define SHU4_AC_DERATING0 0x00001a24 + #define SHU4_AC_DERATING0_ACDERATEEN BIT(0) + #define SHU4_AC_DERATING0_TRRD_DERATE GENMASK(18, 16) + #define SHU4_AC_DERATING0_TRCD_DERATE GENMASK(27, 24) +#define SHU4_AC_DERATING1 0x00001a28 + #define SHU4_AC_DERATING1_TRPAB_DERATE GENMASK(2, 0) + #define SHU4_AC_DERATING1_TRP_DERATE GENMASK(11, 8) + #define SHU4_AC_DERATING1_TRAS_DERATE GENMASK(19, 16) + #define SHU4_AC_DERATING1_TRC_DERATE GENMASK(28, 24) +#define SHU4_AC_DERATING_05T 0x00001a30 + #define SHU4_AC_DERATING_05T_TRC_05T_DERATE BIT(0) + #define SHU4_AC_DERATING_05T_TRCD_05T_DERATE BIT(6) + #define SHU4_AC_DERATING_05T_TRP_05T_DERATE BIT(7) + #define SHU4_AC_DERATING_05T_TRPAB_05T_DERATE BIT(8) + #define SHU4_AC_DERATING_05T_TRAS_05T_DERATE BIT(9) + #define SHU4_AC_DERATING_05T_TRRD_05T_DERATE BIT(12) +#define SHU4_CONF0 0x00001a40 + #define SHU4_CONF0_DMPGTIM GENMASK(5, 0) + #define SHU4_CONF0_ADVREFEN BIT(6) + #define SHU4_CONF0_ADVPREEN BIT(7) + #define SHU4_CONF0_TRFCPBIG BIT(9) + #define SHU4_CONF0_REFTHD GENMASK(15, 12) + #define SHU4_CONF0_REQQUE_DEPTH GENMASK(19, 16) + #define SHU4_CONF0_FREQDIV4 BIT(24) + #define SHU4_CONF0_FDIV2 BIT(25) + #define SHU4_CONF0_CL2 BIT(27) + #define SHU4_CONF0_BL2 BIT(28) + #define SHU4_CONF0_BL4 BIT(29) + #define SHU4_CONF0_MATYPE GENMASK(31, 30) +#define SHU4_CONF1 0x00001a44 + #define SHU4_CONF1_DATLAT GENMASK(4, 0) + #define SHU4_CONF1_DATLAT_DSEL GENMASK(12, 8) + #define SHU4_CONF1_REFBW_FR GENMASK(25, 16) + #define SHU4_CONF1_DATLAT_DSEL_PHY GENMASK(30, 26) + #define SHU4_CONF1_TREFBWIG BIT(31) +#define SHU4_CONF2 0x00001a48 + #define SHU4_CONF2_TCMDO1LAT GENMASK(7, 0) + #define SHU4_CONF2_FSPCHG_PRDCNT GENMASK(15, 8) + #define SHU4_CONF2_DCMDLYREF GENMASK(18, 16) + #define SHU4_CONF2_DQCMD BIT(25) + #define SHU4_CONF2_DQ16COM1 BIT(26) + #define SHU4_CONF2_RA15TOCS1 BIT(27) + #define SHU4_CONF2_WPRE2T BIT(28) + #define SHU4_CONF2_FASTWAKE2 BIT(29) + #define SHU4_CONF2_DAREFEN BIT(30) + #define SHU4_CONF2_FASTWAKE BIT(31) +#define SHU4_CONF3 0x00001a4c + #define SHU4_CONF3_ZQCSCNT GENMASK(15, 0) + #define SHU4_CONF3_REFRCNT GENMASK(24, 16) +#define SHU4_STBCAL 0x00001a50 + #define SHU4_STBCAL_DMSTBLAT GENMASK(1, 0) + #define SHU4_STBCAL_PICGLAT GENMASK(6, 4) + #define SHU4_STBCAL_DQSG_MODE BIT(8) +#define SHU4_DQSOSCTHRD 0x00001a54 + #define SHU4_DQSOSCTHRD_DQSOSCTHRD_INC_RK0 GENMASK(11, 0) + #define SHU4_DQSOSCTHRD_DQSOSCTHRD_DEC_RK0 GENMASK(23, 12) + #define SHU4_DQSOSCTHRD_DQSOSCTHRD_INC_RK1_7TO0 GENMASK(31, 24) +#define SHU4_RANKCTL 0x00001a58 + #define SHU4_RANKCTL_RANKINCTL_RXDLY GENMASK(3, 0) + #define SHU4_RANKCTL_TXRANKINCTL_TXDLY GENMASK(11, 8) + #define SHU4_RANKCTL_TXRANKINCTL GENMASK(15, 12) + #define SHU4_RANKCTL_TXRANKINCTL_ROOT GENMASK(19, 16) + #define SHU4_RANKCTL_RANKINCTL GENMASK(23, 20) + #define SHU4_RANKCTL_RANKINCTL_ROOT1 GENMASK(27, 24) + #define SHU4_RANKCTL_RANKINCTL_PHY GENMASK(31, 28) +#define SHU4_CKECTRL 0x00001a5c + #define SHU4_CKECTRL_CMDCKE GENMASK(18, 16) + #define SHU4_CKECTRL_CKEPRD GENMASK(22, 20) + #define SHU4_CKECTRL_TCKESRX GENMASK(25, 24) + #define SHU4_CKECTRL_SREF_CK_DLY GENMASK(29, 28) +#define SHU4_ODTCTRL 0x00001a60 + #define SHU4_ODTCTRL_ROEN BIT(0) + #define SHU4_ODTCTRL_WOEN BIT(1) + #define SHU4_ODTCTRL_RODTEN_SELPH_CG_IG BIT(2) + #define SHU4_ODTCTRL_RODTENSTB_SELPH_CG_IG BIT(3) + #define SHU4_ODTCTRL_RODT GENMASK(7, 4) + #define SHU4_ODTCTRL_TWODT GENMASK(22, 16) + #define SHU4_ODTCTRL_FIXRODT BIT(27) + #define SHU4_ODTCTRL_RODTE2 BIT(30) + #define SHU4_ODTCTRL_RODTE BIT(31) +#define SHU4_IMPCAL1 0x00001a64 + #define SHU4_IMPCAL1_IMPCAL_CHKCYCLE GENMASK(2, 0) + #define SHU4_IMPCAL1_IMPDRVP GENMASK(8, 4) + #define SHU4_IMPCAL1_IMPDRVN GENMASK(15, 11) + #define SHU4_IMPCAL1_IMPCAL_CALEN_CYCLE GENMASK(19, 17) + #define SHU4_IMPCAL1_IMPCALCNT GENMASK(27, 20) + #define SHU4_IMPCAL1_IMPCAL_CALICNT GENMASK(31, 28) +#define SHU4_DQSOSC_PRD 0x00001a68 + #define SHU4_DQSOSC_PRD_DQSOSC_PRDCNT GENMASK(9, 0) + #define SHU4_DQSOSC_PRD_DQSOSCTHRD_INC_RK1_11TO8 GENMASK(19, 16) + #define SHU4_DQSOSC_PRD_DQSOSCTHRD_DEC_RK1 GENMASK(31, 20) +#define SHU4_DQSOSCR 0x00001a6c + #define SHU4_DQSOSCR_DQSOSCRCNT GENMASK(7, 0) + #define SHU4_DQSOSCR_DQSOSC_DELTA GENMASK(31, 16) +#define SHU4_DQSOSCR2 0x00001a70 + #define SHU4_DQSOSCR2_DQSOSCENCNT GENMASK(15, 0) + #define SHU4_DQSOSCR2_DQSOSC_ADV_SEL GENMASK(17, 16) + #define SHU4_DQSOSCR2_DQSOSC_DRS_ADV_SEL GENMASK(19, 18) +#define SHU4_RODTENSTB 0x00001a74 + #define SHU4_RODTENSTB_RODTEN_MCK_MODESEL BIT(0) + #define SHU4_RODTENSTB_RODTEN_P1_ENABLE BIT(1) + #define SHU4_RODTENSTB_RODTENSTB_OFFSET GENMASK(7, 2) + #define SHU4_RODTENSTB_RODTENSTB_EXT GENMASK(23, 8) + #define SHU4_RODTENSTB_RODTENSTB_4BYTE_EN BIT(31) +#define SHU4_PIPE 0x00001a78 + #define SHU4_PIPE_PHYRXPIPE1 BIT(0) + #define SHU4_PIPE_PHYRXPIPE2 BIT(1) + #define SHU4_PIPE_PHYRXPIPE3 BIT(2) + #define SHU4_PIPE_PHYRXRDSLPIPE1 BIT(4) + #define SHU4_PIPE_PHYRXRDSLPIPE2 BIT(5) + #define SHU4_PIPE_PHYRXRDSLPIPE3 BIT(6) + #define SHU4_PIPE_PHYPIPE1EN BIT(8) + #define SHU4_PIPE_PHYPIPE2EN BIT(9) + #define SHU4_PIPE_PHYPIPE3EN BIT(10) + #define SHU4_PIPE_DLE_LAST_EXTEND3 BIT(26) + #define SHU4_PIPE_READ_START_EXTEND3 BIT(27) + #define SHU4_PIPE_DLE_LAST_EXTEND2 BIT(28) + #define SHU4_PIPE_READ_START_EXTEND2 BIT(29) + #define SHU4_PIPE_DLE_LAST_EXTEND1 BIT(30) + #define SHU4_PIPE_READ_START_EXTEND1 BIT(31) +#define SHU4_TEST1 0x00001a7c + #define SHU4_TEST1_LATNORMPOP GENMASK(12, 8) + #define SHU4_TEST1_DQSICALBLCOK_CNT GENMASK(22, 20) + #define SHU4_TEST1_DQSICALI_NEW BIT(23) +#define SHU4_SELPH_CA1 0x00001a80 + #define SHU4_SELPH_CA1_TXDLY_CS GENMASK(2, 0) + #define SHU4_SELPH_CA1_TXDLY_CKE GENMASK(6, 4) + #define SHU4_SELPH_CA1_TXDLY_ODT GENMASK(10, 8) + #define SHU4_SELPH_CA1_TXDLY_RESET GENMASK(14, 12) + #define SHU4_SELPH_CA1_TXDLY_WE GENMASK(18, 16) + #define SHU4_SELPH_CA1_TXDLY_CAS GENMASK(22, 20) + #define SHU4_SELPH_CA1_TXDLY_RAS GENMASK(26, 24) + #define SHU4_SELPH_CA1_TXDLY_CS1 GENMASK(30, 28) +#define SHU4_SELPH_CA2 0x00001a84 + #define SHU4_SELPH_CA2_TXDLY_BA0 GENMASK(2, 0) + #define SHU4_SELPH_CA2_TXDLY_BA1 GENMASK(6, 4) + #define SHU4_SELPH_CA2_TXDLY_BA2 GENMASK(10, 8) + #define SHU4_SELPH_CA2_TXDLY_CMD GENMASK(20, 16) + #define SHU4_SELPH_CA2_TXDLY_CKE1 GENMASK(26, 24) +#define SHU4_SELPH_CA3 0x00001a88 + #define SHU4_SELPH_CA3_TXDLY_RA0 GENMASK(2, 0) + #define SHU4_SELPH_CA3_TXDLY_RA1 GENMASK(6, 4) + #define SHU4_SELPH_CA3_TXDLY_RA2 GENMASK(10, 8) + #define SHU4_SELPH_CA3_TXDLY_RA3 GENMASK(14, 12) + #define SHU4_SELPH_CA3_TXDLY_RA4 GENMASK(18, 16) + #define SHU4_SELPH_CA3_TXDLY_RA5 GENMASK(22, 20) + #define SHU4_SELPH_CA3_TXDLY_RA6 GENMASK(26, 24) + #define SHU4_SELPH_CA3_TXDLY_RA7 GENMASK(30, 28) +#define SHU4_SELPH_CA4 0x00001a8c + #define SHU4_SELPH_CA4_TXDLY_RA8 GENMASK(2, 0) + #define SHU4_SELPH_CA4_TXDLY_RA9 GENMASK(6, 4) + #define SHU4_SELPH_CA4_TXDLY_RA10 GENMASK(10, 8) + #define SHU4_SELPH_CA4_TXDLY_RA11 GENMASK(14, 12) + #define SHU4_SELPH_CA4_TXDLY_RA12 GENMASK(18, 16) + #define SHU4_SELPH_CA4_TXDLY_RA13 GENMASK(22, 20) + #define SHU4_SELPH_CA4_TXDLY_RA14 GENMASK(26, 24) + #define SHU4_SELPH_CA4_TXDLY_RA15 GENMASK(30, 28) +#define SHU4_SELPH_CA5 0x00001a90 + #define SHU4_SELPH_CA5_DLY_CS GENMASK(2, 0) + #define SHU4_SELPH_CA5_DLY_CKE GENMASK(6, 4) + #define SHU4_SELPH_CA5_DLY_ODT GENMASK(10, 8) + #define SHU4_SELPH_CA5_DLY_RESET GENMASK(14, 12) + #define SHU4_SELPH_CA5_DLY_WE GENMASK(18, 16) + #define SHU4_SELPH_CA5_DLY_CAS GENMASK(22, 20) + #define SHU4_SELPH_CA5_DLY_RAS GENMASK(26, 24) + #define SHU4_SELPH_CA5_DLY_CS1 GENMASK(30, 28) +#define SHU4_SELPH_CA6 0x00001a94 + #define SHU4_SELPH_CA6_DLY_BA0 GENMASK(2, 0) + #define SHU4_SELPH_CA6_DLY_BA1 GENMASK(6, 4) + #define SHU4_SELPH_CA6_DLY_BA2 GENMASK(10, 8) + #define SHU4_SELPH_CA6_DLY_CKE1 GENMASK(26, 24) +#define SHU4_SELPH_CA7 0x00001a98 + #define SHU4_SELPH_CA7_DLY_RA0 GENMASK(2, 0) + #define SHU4_SELPH_CA7_DLY_RA1 GENMASK(6, 4) + #define SHU4_SELPH_CA7_DLY_RA2 GENMASK(10, 8) + #define SHU4_SELPH_CA7_DLY_RA3 GENMASK(14, 12) + #define SHU4_SELPH_CA7_DLY_RA4 GENMASK(18, 16) + #define SHU4_SELPH_CA7_DLY_RA5 GENMASK(22, 20) + #define SHU4_SELPH_CA7_DLY_RA6 GENMASK(26, 24) + #define SHU4_SELPH_CA7_DLY_RA7 GENMASK(30, 28) +#define SHU4_SELPH_CA8 0x00001a9c + #define SHU4_SELPH_CA8_DLY_RA8 GENMASK(2, 0) + #define SHU4_SELPH_CA8_DLY_RA9 GENMASK(6, 4) + #define SHU4_SELPH_CA8_DLY_RA10 GENMASK(10, 8) + #define SHU4_SELPH_CA8_DLY_RA11 GENMASK(14, 12) + #define SHU4_SELPH_CA8_DLY_RA12 GENMASK(18, 16) + #define SHU4_SELPH_CA8_DLY_RA13 GENMASK(22, 20) + #define SHU4_SELPH_CA8_DLY_RA14 GENMASK(26, 24) + #define SHU4_SELPH_CA8_DLY_RA15 GENMASK(30, 28) +#define SHU4_SELPH_DQS0 0x00001aa0 + #define SHU4_SELPH_DQS0_TXDLY_DQS0 GENMASK(2, 0) + #define SHU4_SELPH_DQS0_TXDLY_DQS1 GENMASK(6, 4) + #define SHU4_SELPH_DQS0_TXDLY_DQS2 GENMASK(10, 8) + #define SHU4_SELPH_DQS0_TXDLY_DQS3 GENMASK(14, 12) + #define SHU4_SELPH_DQS0_TXDLY_OEN_DQS0 GENMASK(18, 16) + #define SHU4_SELPH_DQS0_TXDLY_OEN_DQS1 GENMASK(22, 20) + #define SHU4_SELPH_DQS0_TXDLY_OEN_DQS2 GENMASK(26, 24) + #define SHU4_SELPH_DQS0_TXDLY_OEN_DQS3 GENMASK(30, 28) +#define SHU4_SELPH_DQS1 0x00001aa4 + #define SHU4_SELPH_DQS1_DLY_DQS0 GENMASK(2, 0) + #define SHU4_SELPH_DQS1_DLY_DQS1 GENMASK(6, 4) + #define SHU4_SELPH_DQS1_DLY_DQS2 GENMASK(10, 8) + #define SHU4_SELPH_DQS1_DLY_DQS3 GENMASK(14, 12) + #define SHU4_SELPH_DQS1_DLY_OEN_DQS0 GENMASK(18, 16) + #define SHU4_SELPH_DQS1_DLY_OEN_DQS1 GENMASK(22, 20) + #define SHU4_SELPH_DQS1_DLY_OEN_DQS2 GENMASK(26, 24) + #define SHU4_SELPH_DQS1_DLY_OEN_DQS3 GENMASK(30, 28) +#define SHU4_DRVING1 0x00001aa8 + #define SHU4_DRVING1_DQDRVN2 GENMASK(4, 0) + #define SHU4_DRVING1_DQDRVP2 GENMASK(9, 5) + #define SHU4_DRVING1_DQSDRVN1 GENMASK(14, 10) + #define SHU4_DRVING1_DQSDRVP1 GENMASK(19, 15) + #define SHU4_DRVING1_DQSDRVN2 GENMASK(24, 20) + #define SHU4_DRVING1_DQSDRVP2 GENMASK(29, 25) + #define SHU4_DRVING1_DIS_IMP_ODTN_TRACK BIT(30) + #define SHU4_DRVING1_DIS_IMPCAL_HW BIT(31) +#define SHU4_DRVING2 0x00001aac + #define SHU4_DRVING2_CMDDRVN1 GENMASK(4, 0) + #define SHU4_DRVING2_CMDDRVP1 GENMASK(9, 5) + #define SHU4_DRVING2_CMDDRVN2 GENMASK(14, 10) + #define SHU4_DRVING2_CMDDRVP2 GENMASK(19, 15) + #define SHU4_DRVING2_DQDRVN1 GENMASK(24, 20) + #define SHU4_DRVING2_DQDRVP1 GENMASK(29, 25) + #define SHU4_DRVING2_DIS_IMPCAL_ODT_EN BIT(31) +#define SHU4_DRVING3 0x00001ab0 + #define SHU4_DRVING3_DQODTN2 GENMASK(4, 0) + #define SHU4_DRVING3_DQODTP2 GENMASK(9, 5) + #define SHU4_DRVING3_DQSODTN GENMASK(14, 10) + #define SHU4_DRVING3_DQSODTP GENMASK(19, 15) + #define SHU4_DRVING3_DQSODTN2 GENMASK(24, 20) + #define SHU4_DRVING3_DQSODTP2 GENMASK(29, 25) +#define SHU4_DRVING4 0x00001ab4 + #define SHU4_DRVING4_CMDODTN1 GENMASK(4, 0) + #define SHU4_DRVING4_CMDODTP1 GENMASK(9, 5) + #define SHU4_DRVING4_CMDODTN2 GENMASK(14, 10) + #define SHU4_DRVING4_CMDODTP2 GENMASK(19, 15) + #define SHU4_DRVING4_DQODTN1 GENMASK(24, 20) + #define SHU4_DRVING4_DQODTP1 GENMASK(29, 25) +#define SHU4_DRVING5 0x00001ab8 + #define SHU4_DRVING5_DQCODTN2 GENMASK(4, 0) + #define SHU4_DRVING5_DQCODTP2 GENMASK(9, 5) + #define SHU4_DRVING5_DQCDRVN1 GENMASK(14, 10) + #define SHU4_DRVING5_DQCDRVP1 GENMASK(19, 15) + #define SHU4_DRVING5_DQCDRVN2 GENMASK(24, 20) + #define SHU4_DRVING5_DQCDRVP2 GENMASK(29, 25) +#define SHU4_DRVING6 0x00001abc + #define SHU4_DRVING6_DQCODTN1 GENMASK(24, 20) + #define SHU4_DRVING6_DQCODTP1 GENMASK(29, 25) +#define SHU4_WODT 0x00001ac0 + #define SHU4_WODT_DISWODT GENMASK(2, 0) + #define SHU4_WODT_WODTFIX BIT(3) + #define SHU4_WODT_WODTFIXOFF BIT(4) + #define SHU4_WODT_DISWODTE BIT(5) + #define SHU4_WODT_DISWODTE2 BIT(6) + #define SHU4_WODT_WODTPDEN BIT(7) + #define SHU4_WODT_DQOE_CNT GENMASK(10, 8) + #define SHU4_WODT_DQOE_OPT BIT(11) + #define SHU4_WODT_TXUPD_SEL GENMASK(13, 12) + #define SHU4_WODT_TXUPD_W2R_SEL GENMASK(16, 14) + #define SHU4_WODT_DBIWR BIT(29) + #define SHU4_WODT_TWPSTEXT BIT(30) + #define SHU4_WODT_WPST2T BIT(31) +#define SHU4_DQSG 0x00001ac4 + #define SHU4_DQSG_DLLFRZRFCOPT GENMASK(1, 0) + #define SHU4_DQSG_DLLFRZWROPT GENMASK(5, 4) + #define SHU4_DQSG_R_RSTBCNT_LATCH_OPT GENMASK(10, 8) + #define SHU4_DQSG_STB_UPDMASK_EN BIT(11) + #define SHU4_DQSG_STB_UPDMASKCYC GENMASK(15, 12) + #define SHU4_DQSG_DQSINCTL_PRE_SEL BIT(16) + #define SHU4_DQSG_SCINTV GENMASK(25, 20) +#define SHU4_SCINTV 0x00001ac8 + #define SHU4_SCINTV_ODTREN BIT(0) + #define SHU4_SCINTV_TZQLAT GENMASK(5, 1) + #define SHU4_SCINTV_TZQLAT2 GENMASK(10, 6) + #define SHU4_SCINTV_RDDQC_INTV GENMASK(12, 11) + #define SHU4_SCINTV_MRW_INTV GENMASK(17, 13) + #define SHU4_SCINTV_DQS2DQ_SHU_PITHRD GENMASK(23, 18) + #define SHU4_SCINTV_DQS2DQ_FILT_PITHRD GENMASK(29, 24) + #define SHU4_SCINTV_DQSOSCENDIS BIT(30) +#define SHU4_MISC 0x00001acc + #define SHU4_MISC_REQQUE_MAXCNT GENMASK(3, 0) + #define SHU4_MISC_CKEHCMD GENMASK(5, 4) + #define SHU4_MISC_NORMPOP_LEN GENMASK(10, 8) + #define SHU4_MISC_PREA_INTV GENMASK(16, 12) +#define SHU4_DQS2DQ_TX 0x00001ad0 + #define SHU4_DQS2DQ_TX_OE2DQ_OFFSET GENMASK(4, 0) +#define SHU4_HWSET_MR2 0x00001ad4 + #define SHU4_HWSET_MR2_HWSET_MR2_MRSMA GENMASK(12, 0) + #define SHU4_HWSET_MR2_HWSET_MR2_OP GENMASK(23, 16) +#define SHU4_HWSET_MR13 0x00001ad8 + #define SHU4_HWSET_MR13_HWSET_MR13_MRSMA GENMASK(12, 0) + #define SHU4_HWSET_MR13_HWSET_MR13_OP GENMASK(23, 16) +#define SHU4_HWSET_VRCG 0x00001adc + #define SHU4_HWSET_VRCG_HWSET_VRCG_MRSMA GENMASK(12, 0) + #define SHU4_HWSET_VRCG_HWSET_VRCG_OP GENMASK(23, 16) +#define SHU4_APHY_TX_PICG_CTRL 0x00001ae4 + #define SHU4_APHY_TX_PICG_CTRL_APHYPI_CG_CK_SEL GENMASK(23, 20) + #define SHU4_APHY_TX_PICG_CTRL_APHYPI_CG_CK_OPT BIT(24) + #define SHU4_APHY_TX_PICG_CTRL_DDRPHY_CLK_DYN_GATING_SEL GENMASK(30, 27) + #define SHU4_APHY_TX_PICG_CTRL_DDRPHY_CLK_EN_OPT BIT(31) +#define SHU4RK0_DQSCTL 0x00001c00 + #define SHU4RK0_DQSCTL_DQSINCTL GENMASK(3, 0) +#define SHU4RK0_DQSIEN 0x00001c04 + #define SHU4RK0_DQSIEN_R0DQS0IEN GENMASK(6, 0) + #define SHU4RK0_DQSIEN_R0DQS1IEN GENMASK(14, 8) + #define SHU4RK0_DQSIEN_R0DQS2IEN GENMASK(22, 16) + #define SHU4RK0_DQSIEN_R0DQS3IEN GENMASK(30, 24) +#define SHU4RK0_DQSCAL 0x00001c08 + #define SHU4RK0_DQSCAL_R0DQSIENLLMT GENMASK(6, 0) + #define SHU4RK0_DQSCAL_R0DQSIENLLMTEN BIT(7) + #define SHU4RK0_DQSCAL_R0DQSIENHLMT GENMASK(14, 8) + #define SHU4RK0_DQSCAL_R0DQSIENHLMTEN BIT(15) +#define SHU4RK0_PI 0x00001c0c + #define SHU4RK0_PI_RK0_ARPI_DQ_B1 GENMASK(5, 0) + #define SHU4RK0_PI_RK0_ARPI_DQ_B0 GENMASK(13, 8) + #define SHU4RK0_PI_RK0_ARPI_DQM_B1 GENMASK(21, 16) + #define SHU4RK0_PI_RK0_ARPI_DQM_B0 GENMASK(29, 24) +#define SHU4RK0_DQSOSC 0x00001c10 + #define SHU4RK0_DQSOSC_DQSOSC_BASE_RK0 GENMASK(15, 0) + #define SHU4RK0_DQSOSC_DQSOSC_BASE_RK0_B1 GENMASK(31, 16) +#define SHU4RK0_SELPH_ODTEN0 0x00001c1c + #define SHU4RK0_SELPH_ODTEN0_TXDLY_B0_RODTEN GENMASK(2, 0) + #define SHU4RK0_SELPH_ODTEN0_TXDLY_B0_RODTEN_P1 GENMASK(6, 4) + #define SHU4RK0_SELPH_ODTEN0_TXDLY_B1_RODTEN GENMASK(10, 8) + #define SHU4RK0_SELPH_ODTEN0_TXDLY_B1_RODTEN_P1 GENMASK(14, 12) + #define SHU4RK0_SELPH_ODTEN0_TXDLY_B2_RODTEN GENMASK(18, 16) + #define SHU4RK0_SELPH_ODTEN0_TXDLY_B2_RODTEN_P1 GENMASK(22, 20) + #define SHU4RK0_SELPH_ODTEN0_TXDLY_B3_RODTEN GENMASK(26, 24) + #define SHU4RK0_SELPH_ODTEN0_TXDLY_B3_RODTEN_P1 GENMASK(30, 28) +#define SHU4RK0_SELPH_ODTEN1 0x00001c20 + #define SHU4RK0_SELPH_ODTEN1_DLY_B0_RODTEN GENMASK(2, 0) + #define SHU4RK0_SELPH_ODTEN1_DLY_B0_RODTEN_P1 GENMASK(6, 4) + #define SHU4RK0_SELPH_ODTEN1_DLY_B1_RODTEN GENMASK(10, 8) + #define SHU4RK0_SELPH_ODTEN1_DLY_B1_RODTEN_P1 GENMASK(14, 12) + #define SHU4RK0_SELPH_ODTEN1_DLY_B2_RODTEN GENMASK(18, 16) + #define SHU4RK0_SELPH_ODTEN1_DLY_B2_RODTEN_P1 GENMASK(22, 20) + #define SHU4RK0_SELPH_ODTEN1_DLY_B3_RODTEN GENMASK(26, 24) + #define SHU4RK0_SELPH_ODTEN1_DLY_B3_RODTEN_P1 GENMASK(30, 28) +#define SHU4RK0_SELPH_DQSG0 0x00001c24 + #define SHU4RK0_SELPH_DQSG0_TX_DLY_DQS0_GATED GENMASK(2, 0) + #define SHU4RK0_SELPH_DQSG0_TX_DLY_DQS0_GATED_P1 GENMASK(6, 4) + #define SHU4RK0_SELPH_DQSG0_TX_DLY_DQS1_GATED GENMASK(10, 8) + #define SHU4RK0_SELPH_DQSG0_TX_DLY_DQS1_GATED_P1 GENMASK(14, 12) + #define SHU4RK0_SELPH_DQSG0_TX_DLY_DQS2_GATED GENMASK(18, 16) + #define SHU4RK0_SELPH_DQSG0_TX_DLY_DQS2_GATED_P1 GENMASK(22, 20) + #define SHU4RK0_SELPH_DQSG0_TX_DLY_DQS3_GATED GENMASK(26, 24) + #define SHU4RK0_SELPH_DQSG0_TX_DLY_DQS3_GATED_P1 GENMASK(30, 28) +#define SHU4RK0_SELPH_DQSG1 0x00001c28 + #define SHU4RK0_SELPH_DQSG1_REG_DLY_DQS0_GATED GENMASK(2, 0) + #define SHU4RK0_SELPH_DQSG1_REG_DLY_DQS0_GATED_P1 GENMASK(6, 4) + #define SHU4RK0_SELPH_DQSG1_REG_DLY_DQS1_GATED GENMASK(10, 8) + #define SHU4RK0_SELPH_DQSG1_REG_DLY_DQS1_GATED_P1 GENMASK(14, 12) + #define SHU4RK0_SELPH_DQSG1_REG_DLY_DQS2_GATED GENMASK(18, 16) + #define SHU4RK0_SELPH_DQSG1_REG_DLY_DQS2_GATED_P1 GENMASK(22, 20) + #define SHU4RK0_SELPH_DQSG1_REG_DLY_DQS3_GATED GENMASK(26, 24) + #define SHU4RK0_SELPH_DQSG1_REG_DLY_DQS3_GATED_P1 GENMASK(30, 28) +#define SHU4RK0_SELPH_DQ0 0x00001c2c + #define SHU4RK0_SELPH_DQ0_TXDLY_DQ0 GENMASK(2, 0) + #define SHU4RK0_SELPH_DQ0_TXDLY_DQ1 GENMASK(6, 4) + #define SHU4RK0_SELPH_DQ0_TXDLY_DQ2 GENMASK(10, 8) + #define SHU4RK0_SELPH_DQ0_TXDLY_DQ3 GENMASK(14, 12) + #define SHU4RK0_SELPH_DQ0_TXDLY_OEN_DQ0 GENMASK(18, 16) + #define SHU4RK0_SELPH_DQ0_TXDLY_OEN_DQ1 GENMASK(22, 20) + #define SHU4RK0_SELPH_DQ0_TXDLY_OEN_DQ2 GENMASK(26, 24) + #define SHU4RK0_SELPH_DQ0_TXDLY_OEN_DQ3 GENMASK(30, 28) +#define SHU4RK0_SELPH_DQ1 0x00001c30 + #define SHU4RK0_SELPH_DQ1_TXDLY_DQM0 GENMASK(2, 0) + #define SHU4RK0_SELPH_DQ1_TXDLY_DQM1 GENMASK(6, 4) + #define SHU4RK0_SELPH_DQ1_TXDLY_DQM2 GENMASK(10, 8) + #define SHU4RK0_SELPH_DQ1_TXDLY_DQM3 GENMASK(14, 12) + #define SHU4RK0_SELPH_DQ1_TXDLY_OEN_DQM0 GENMASK(18, 16) + #define SHU4RK0_SELPH_DQ1_TXDLY_OEN_DQM1 GENMASK(22, 20) + #define SHU4RK0_SELPH_DQ1_TXDLY_OEN_DQM2 GENMASK(26, 24) + #define SHU4RK0_SELPH_DQ1_TXDLY_OEN_DQM3 GENMASK(30, 28) +#define SHU4RK0_SELPH_DQ2 0x00001c34 + #define SHU4RK0_SELPH_DQ2_DLY_DQ0 GENMASK(2, 0) + #define SHU4RK0_SELPH_DQ2_DLY_DQ1 GENMASK(6, 4) + #define SHU4RK0_SELPH_DQ2_DLY_DQ2 GENMASK(10, 8) + #define SHU4RK0_SELPH_DQ2_DLY_DQ3 GENMASK(14, 12) + #define SHU4RK0_SELPH_DQ2_DLY_OEN_DQ0 GENMASK(18, 16) + #define SHU4RK0_SELPH_DQ2_DLY_OEN_DQ1 GENMASK(22, 20) + #define SHU4RK0_SELPH_DQ2_DLY_OEN_DQ2 GENMASK(26, 24) + #define SHU4RK0_SELPH_DQ2_DLY_OEN_DQ3 GENMASK(30, 28) +#define SHU4RK0_SELPH_DQ3 0x00001c38 + #define SHU4RK0_SELPH_DQ3_DLY_DQM0 GENMASK(2, 0) + #define SHU4RK0_SELPH_DQ3_DLY_DQM1 GENMASK(6, 4) + #define SHU4RK0_SELPH_DQ3_DLY_DQM2 GENMASK(10, 8) + #define SHU4RK0_SELPH_DQ3_DLY_DQM3 GENMASK(14, 12) + #define SHU4RK0_SELPH_DQ3_DLY_OEN_DQM0 GENMASK(18, 16) + #define SHU4RK0_SELPH_DQ3_DLY_OEN_DQM1 GENMASK(22, 20) + #define SHU4RK0_SELPH_DQ3_DLY_OEN_DQM2 GENMASK(26, 24) + #define SHU4RK0_SELPH_DQ3_DLY_OEN_DQM3 GENMASK(30, 28) +#define SHU4RK0_DQS2DQ_CAL1 0x00001c40 + #define SHU4RK0_DQS2DQ_CAL1_BOOT_ORIG_UI_RK0_DQ0 GENMASK(10, 0) + #define SHU4RK0_DQS2DQ_CAL1_BOOT_ORIG_UI_RK0_DQ1 GENMASK(26, 16) +#define SHU4RK0_DQS2DQ_CAL2 0x00001c44 + #define SHU4RK0_DQS2DQ_CAL2_BOOT_TARG_UI_RK0_DQ0 GENMASK(10, 0) + #define SHU4RK0_DQS2DQ_CAL2_BOOT_TARG_UI_RK0_DQ1 GENMASK(26, 16) +#define SHU4RK0_DQS2DQ_CAL3 0x00001c48 + #define SHU4RK0_DQS2DQ_CAL3_BOOT_TARG_UI_RK0_OEN_DQ0 GENMASK(5, 0) + #define SHU4RK0_DQS2DQ_CAL3_BOOT_TARG_UI_RK0_OEN_DQ1 GENMASK(11, 6) + #define SHU4RK0_DQS2DQ_CAL3_BOOT_TARG_UI_RK0_OEN_DQ0_B4TO0 GENMASK(16, 12) + #define SHU4RK0_DQS2DQ_CAL3_BOOT_TARG_UI_RK0_OEN_DQ1_B4TO0 GENMASK(21, 17) +#define SHU4RK0_DQS2DQ_CAL4 0x00001c4c + #define SHU4RK0_DQS2DQ_CAL4_BOOT_TARG_UI_RK0_OEN_DQM0 GENMASK(5, 0) + #define SHU4RK0_DQS2DQ_CAL4_BOOT_TARG_UI_RK0_OEN_DQM1 GENMASK(11, 6) + #define SHU4RK0_DQS2DQ_CAL4_BOOT_TARG_UI_RK0_OEN_DQM0_B4TO0 GENMASK(16, 12) + #define SHU4RK0_DQS2DQ_CAL4_BOOT_TARG_UI_RK0_OEN_DQM1_B4TO0 GENMASK(21, 17) +#define SHU4RK0_DQS2DQ_CAL5 0x00001c50 + #define SHU4RK0_DQS2DQ_CAL5_BOOT_TARG_UI_RK0_DQM0 GENMASK(10, 0) + #define SHU4RK0_DQS2DQ_CAL5_BOOT_TARG_UI_RK0_DQM1 GENMASK(26, 16) +#define SHU4RK1_DQSCTL 0x00001d00 + #define SHU4RK1_DQSCTL_R1DQSINCTL GENMASK(3, 0) +#define SHU4RK1_DQSIEN 0x00001d04 + #define SHU4RK1_DQSIEN_R1DQS0IEN GENMASK(6, 0) + #define SHU4RK1_DQSIEN_R1DQS1IEN GENMASK(14, 8) + #define SHU4RK1_DQSIEN_R1DQS2IEN GENMASK(22, 16) + #define SHU4RK1_DQSIEN_R1DQS3IEN GENMASK(30, 24) +#define SHU4RK1_DQSCAL 0x00001d08 + #define SHU4RK1_DQSCAL_R1DQSIENLLMT GENMASK(6, 0) + #define SHU4RK1_DQSCAL_R1DQSIENLLMTEN BIT(7) + #define SHU4RK1_DQSCAL_R1DQSIENHLMT GENMASK(14, 8) + #define SHU4RK1_DQSCAL_R1DQSIENHLMTEN BIT(15) +#define SHU4RK1_PI 0x00001d0c + #define SHU4RK1_PI_RK1_ARPI_DQ_B1 GENMASK(5, 0) + #define SHU4RK1_PI_RK1_ARPI_DQ_B0 GENMASK(13, 8) + #define SHU4RK1_PI_RK1_ARPI_DQM_B1 GENMASK(21, 16) + #define SHU4RK1_PI_RK1_ARPI_DQM_B0 GENMASK(29, 24) +#define SHU4RK1_DQSOSC 0x00001d10 + #define SHU4RK1_DQSOSC_DQSOSC_BASE_RK1 GENMASK(15, 0) + #define SHU4RK1_DQSOSC_DQSOSC_BASE_RK1_B1 GENMASK(31, 16) +#define SHU4RK1_SELPH_ODTEN0 0x00001d1c + #define SHU4RK1_SELPH_ODTEN0_TXDLY_B0_R1RODTEN GENMASK(2, 0) + #define SHU4RK1_SELPH_ODTEN0_TXDLY_B0_R1RODTEN_P1 GENMASK(6, 4) + #define SHU4RK1_SELPH_ODTEN0_TXDLY_B1_R1RODTEN GENMASK(10, 8) + #define SHU4RK1_SELPH_ODTEN0_TXDLY_B1_R1RODTEN_P1 GENMASK(14, 12) + #define SHU4RK1_SELPH_ODTEN0_TXDLY_B2_R1RODTEN GENMASK(18, 16) + #define SHU4RK1_SELPH_ODTEN0_TXDLY_B2_R1RODTEN_P1 GENMASK(22, 20) + #define SHU4RK1_SELPH_ODTEN0_TXDLY_B3_R1RODTEN GENMASK(26, 24) + #define SHU4RK1_SELPH_ODTEN0_TXDLY_B3_R1RODTEN_P1 GENMASK(30, 28) +#define SHU4RK1_SELPH_ODTEN1 0x00001d20 + #define SHU4RK1_SELPH_ODTEN1_DLY_B0_R1RODTEN GENMASK(2, 0) + #define SHU4RK1_SELPH_ODTEN1_DLY_B0_R1RODTEN_P1 GENMASK(6, 4) + #define SHU4RK1_SELPH_ODTEN1_DLY_B1_R1RODTEN GENMASK(10, 8) + #define SHU4RK1_SELPH_ODTEN1_DLY_B1_R1RODTEN_P1 GENMASK(14, 12) + #define SHU4RK1_SELPH_ODTEN1_DLY_B2_R1RODTEN GENMASK(18, 16) + #define SHU4RK1_SELPH_ODTEN1_DLY_B2_R1RODTEN_P1 GENMASK(22, 20) + #define SHU4RK1_SELPH_ODTEN1_DLY_B3_R1RODTEN GENMASK(26, 24) + #define SHU4RK1_SELPH_ODTEN1_DLY_B3_R1RODTEN_P1 GENMASK(30, 28) +#define SHU4RK1_SELPH_DQSG0 0x00001d24 + #define SHU4RK1_SELPH_DQSG0_TX_DLY_R1DQS0_GATED GENMASK(2, 0) + #define SHU4RK1_SELPH_DQSG0_TX_DLY_R1DQS0_GATED_P1 GENMASK(6, 4) + #define SHU4RK1_SELPH_DQSG0_TX_DLY_R1DQS1_GATED GENMASK(10, 8) + #define SHU4RK1_SELPH_DQSG0_TX_DLY_R1DQS1_GATED_P1 GENMASK(14, 12) + #define SHU4RK1_SELPH_DQSG0_TX_DLY_R1DQS2_GATED GENMASK(18, 16) + #define SHU4RK1_SELPH_DQSG0_TX_DLY_R1DQS2_GATED_P1 GENMASK(22, 20) + #define SHU4RK1_SELPH_DQSG0_TX_DLY_R1DQS3_GATED GENMASK(26, 24) + #define SHU4RK1_SELPH_DQSG0_TX_DLY_R1DQS3_GATED_P1 GENMASK(30, 28) +#define SHU4RK1_SELPH_DQSG1 0x00001d28 + #define SHU4RK1_SELPH_DQSG1_REG_DLY_R1DQS0_GATED GENMASK(2, 0) + #define SHU4RK1_SELPH_DQSG1_REG_DLY_R1DQS0_GATED_P1 GENMASK(6, 4) + #define SHU4RK1_SELPH_DQSG1_REG_DLY_R1DQS1_GATED GENMASK(10, 8) + #define SHU4RK1_SELPH_DQSG1_REG_DLY_R1DQS1_GATED_P1 GENMASK(14, 12) + #define SHU4RK1_SELPH_DQSG1_REG_DLY_R1DQS2_GATED GENMASK(18, 16) + #define SHU4RK1_SELPH_DQSG1_REG_DLY_R1DQS2_GATED_P1 GENMASK(22, 20) + #define SHU4RK1_SELPH_DQSG1_REG_DLY_R1DQS3_GATED GENMASK(26, 24) + #define SHU4RK1_SELPH_DQSG1_REG_DLY_R1DQS3_GATED_P1 GENMASK(30, 28) +#define SHU4RK1_SELPH_DQ0 0x00001d2c + #define SHU4RK1_SELPH_DQ0_TX_DLY_R1DQ0 GENMASK(2, 0) + #define SHU4RK1_SELPH_DQ0_TX_DLY_R1DQ1 GENMASK(6, 4) + #define SHU4RK1_SELPH_DQ0_TX_DLY_R1DQ2 GENMASK(10, 8) + #define SHU4RK1_SELPH_DQ0_TX_DLY_R1DQ3 GENMASK(14, 12) + #define SHU4RK1_SELPH_DQ0_TX_DLY_R1OEN_DQ0 GENMASK(18, 16) + #define SHU4RK1_SELPH_DQ0_TX_DLY_R1OEN_DQ1 GENMASK(22, 20) + #define SHU4RK1_SELPH_DQ0_TX_DLY_R1OEN_DQ2 GENMASK(26, 24) + #define SHU4RK1_SELPH_DQ0_TX_DLY_R1OEN_DQ3 GENMASK(30, 28) +#define SHU4RK1_SELPH_DQ1 0x00001d30 + #define SHU4RK1_SELPH_DQ1_TX_DLY_R1DQM0 GENMASK(2, 0) + #define SHU4RK1_SELPH_DQ1_TX_DLY_R1DQM1 GENMASK(6, 4) + #define SHU4RK1_SELPH_DQ1_TX_DLY_R1DQM2 GENMASK(10, 8) + #define SHU4RK1_SELPH_DQ1_TX_DLY_R1DQM3 GENMASK(14, 12) + #define SHU4RK1_SELPH_DQ1_TX_DLY_R1OEN_DQM0 GENMASK(18, 16) + #define SHU4RK1_SELPH_DQ1_TX_DLY_R1OEN_DQM1 GENMASK(22, 20) + #define SHU4RK1_SELPH_DQ1_TX_DLY_R1OEN_DQM2 GENMASK(26, 24) + #define SHU4RK1_SELPH_DQ1_TX_DLY_R1OEN_DQM3 GENMASK(30, 28) +#define SHU4RK1_SELPH_DQ2 0x00001d34 + #define SHU4RK1_SELPH_DQ2_DLY_R1DQ0 GENMASK(2, 0) + #define SHU4RK1_SELPH_DQ2_DLY_R1DQ1 GENMASK(6, 4) + #define SHU4RK1_SELPH_DQ2_DLY_R1DQ2 GENMASK(10, 8) + #define SHU4RK1_SELPH_DQ2_DLY_R1DQ3 GENMASK(14, 12) + #define SHU4RK1_SELPH_DQ2_DLY_R1OEN_DQ0 GENMASK(18, 16) + #define SHU4RK1_SELPH_DQ2_DLY_R1OEN_DQ1 GENMASK(22, 20) + #define SHU4RK1_SELPH_DQ2_DLY_R1OEN_DQ2 GENMASK(26, 24) + #define SHU4RK1_SELPH_DQ2_DLY_R1OEN_DQ3 GENMASK(30, 28) +#define SHU4RK1_SELPH_DQ3 0x00001d38 + #define SHU4RK1_SELPH_DQ3_DLY_R1DQM0 GENMASK(2, 0) + #define SHU4RK1_SELPH_DQ3_DLY_R1DQM1 GENMASK(6, 4) + #define SHU4RK1_SELPH_DQ3_DLY_R1DQM2 GENMASK(10, 8) + #define SHU4RK1_SELPH_DQ3_DLY_R1DQM3 GENMASK(14, 12) + #define SHU4RK1_SELPH_DQ3_DLY_R1OEN_DQM0 GENMASK(18, 16) + #define SHU4RK1_SELPH_DQ3_DLY_R1OEN_DQM1 GENMASK(22, 20) + #define SHU4RK1_SELPH_DQ3_DLY_R1OEN_DQM2 GENMASK(26, 24) + #define SHU4RK1_SELPH_DQ3_DLY_R1OEN_DQM3 GENMASK(30, 28) +#define SHU4RK1_DQS2DQ_CAL1 0x00001d40 + #define SHU4RK1_DQS2DQ_CAL1_BOOT_ORIG_UI_RK1_DQ0 GENMASK(10, 0) + #define SHU4RK1_DQS2DQ_CAL1_BOOT_ORIG_UI_RK1_DQ1 GENMASK(26, 16) +#define SHU4RK1_DQS2DQ_CAL2 0x00001d44 + #define SHU4RK1_DQS2DQ_CAL2_BOOT_TARG_UI_RK1_DQ0 GENMASK(10, 0) + #define SHU4RK1_DQS2DQ_CAL2_BOOT_TARG_UI_RK1_DQ1 GENMASK(26, 16) +#define SHU4RK1_DQS2DQ_CAL3 0x00001d48 + #define SHU4RK1_DQS2DQ_CAL3_BOOT_TARG_UI_RK1_OEN_DQ0 GENMASK(5, 0) + #define SHU4RK1_DQS2DQ_CAL3_BOOT_TARG_UI_RK1_OEN_DQ1 GENMASK(11, 6) + #define SHU4RK1_DQS2DQ_CAL3_BOOT_TARG_UI_RK1_OEN_DQ0_B4TO0 GENMASK(16, 12) + #define SHU4RK1_DQS2DQ_CAL3_BOOT_TARG_UI_RK1_OEN_DQ1_B4TO0 GENMASK(21, 17) +#define SHU4RK1_DQS2DQ_CAL4 0x00001d4c + #define SHU4RK1_DQS2DQ_CAL4_BOOT_TARG_UI_RK1_OEN_DQM0 GENMASK(5, 0) + #define SHU4RK1_DQS2DQ_CAL4_BOOT_TARG_UI_RK1_OEN_DQM1 GENMASK(11, 6) + #define SHU4RK1_DQS2DQ_CAL4_BOOT_TARG_UI_RK1_OEN_DQM0_B4TO0 GENMASK(16, 12) + #define SHU4RK1_DQS2DQ_CAL4_BOOT_TARG_UI_RK1_OEN_DQM1_B4TO0 GENMASK(21, 17) +#define SHU4RK1_DQS2DQ_CAL5 0x00001d50 + #define SHU4RK1_DQS2DQ_CAL5_BOOT_TARG_UI_RK1_DQM0 GENMASK(10, 0) + #define SHU4RK1_DQS2DQ_CAL5_BOOT_TARG_UI_RK1_DQM1 GENMASK(26, 16) +#define SHU4RK2_DQSCTL 0x00001e00 + #define SHU4RK2_DQSCTL_R2DQSINCTL GENMASK(3, 0) +#define SHU4RK2_DQSIEN 0x00001e04 + #define SHU4RK2_DQSIEN_R2DQS0IEN GENMASK(6, 0) + #define SHU4RK2_DQSIEN_R2DQS1IEN GENMASK(14, 8) + #define SHU4RK2_DQSIEN_R2DQS2IEN GENMASK(22, 16) + #define SHU4RK2_DQSIEN_R2DQS3IEN GENMASK(30, 24) +#define SHU4RK2_DQSCAL 0x00001e08 + #define SHU4RK2_DQSCAL_R2DQSIENLLMT GENMASK(6, 0) + #define SHU4RK2_DQSCAL_R2DQSIENLLMTEN BIT(7) + #define SHU4RK2_DQSCAL_R2DQSIENHLMT GENMASK(14, 8) + #define SHU4RK2_DQSCAL_R2DQSIENHLMTEN BIT(15) +#define SHU4RK2_PI 0x00001e0c + #define SHU4RK2_PI_RK2_ARPI_DQ_B1 GENMASK(5, 0) + #define SHU4RK2_PI_RK2_ARPI_DQ_B0 GENMASK(13, 8) + #define SHU4RK2_PI_RK2_ARPI_DQM_B1 GENMASK(21, 16) + #define SHU4RK2_PI_RK2_ARPI_DQM_B0 GENMASK(29, 24) +#define SHU4RK2_DQSOSC 0x00001e10 + #define SHU4RK2_DQSOSC_DQSOSC_BASE_RK2 GENMASK(15, 0) + #define SHU4RK2_DQSOSC_DQSOSC_BASE_RK2_B1 GENMASK(31, 16) +#define SHU4RK2_SELPH_ODTEN0 0x00001e1c + #define SHU4RK2_SELPH_ODTEN0_TXDLY_B0_R2RODTEN GENMASK(2, 0) + #define SHU4RK2_SELPH_ODTEN0_TXDLY_B0_R2RODTEN_P1 GENMASK(6, 4) + #define SHU4RK2_SELPH_ODTEN0_TXDLY_B1_R2RODTEN GENMASK(10, 8) + #define SHU4RK2_SELPH_ODTEN0_TXDLY_B1_R2RODTEN_P1 GENMASK(14, 12) + #define SHU4RK2_SELPH_ODTEN0_TXDLY_B2_R2RODTEN GENMASK(18, 16) + #define SHU4RK2_SELPH_ODTEN0_TXDLY_B2_R2RODTEN_P1 GENMASK(22, 20) + #define SHU4RK2_SELPH_ODTEN0_TXDLY_B3_R2RODTEN GENMASK(26, 24) + #define SHU4RK2_SELPH_ODTEN0_TXDLY_B3_R2RODTEN_P1 GENMASK(30, 28) +#define SHU4RK2_SELPH_ODTEN1 0x00001e20 + #define SHU4RK2_SELPH_ODTEN1_DLY_B0_R2RODTEN GENMASK(2, 0) + #define SHU4RK2_SELPH_ODTEN1_DLY_B0_R2RODTEN_P1 GENMASK(6, 4) + #define SHU4RK2_SELPH_ODTEN1_DLY_B1_R2RODTEN GENMASK(10, 8) + #define SHU4RK2_SELPH_ODTEN1_DLY_B1_R2RODTEN_P1 GENMASK(14, 12) + #define SHU4RK2_SELPH_ODTEN1_DLY_B2_R2RODTEN GENMASK(18, 16) + #define SHU4RK2_SELPH_ODTEN1_DLY_B2_R2RODTEN_P1 GENMASK(22, 20) + #define SHU4RK2_SELPH_ODTEN1_DLY_B3_R2RODTEN GENMASK(26, 24) + #define SHU4RK2_SELPH_ODTEN1_DLY_B3_R2RODTEN_P1 GENMASK(30, 28) +#define SHU4RK2_SELPH_DQSG0 0x00001e24 + #define SHU4RK2_SELPH_DQSG0_TX_DLY_R2DQS0_GATED GENMASK(2, 0) + #define SHU4RK2_SELPH_DQSG0_TX_DLY_R2DQS0_GATED_P1 GENMASK(6, 4) + #define SHU4RK2_SELPH_DQSG0_TX_DLY_R2DQS1_GATED GENMASK(10, 8) + #define SHU4RK2_SELPH_DQSG0_TX_DLY_R2DQS1_GATED_P1 GENMASK(14, 12) + #define SHU4RK2_SELPH_DQSG0_TX_DLY_R2DQS2_GATED GENMASK(18, 16) + #define SHU4RK2_SELPH_DQSG0_TX_DLY_R2DQS2_GATED_P1 GENMASK(22, 20) + #define SHU4RK2_SELPH_DQSG0_TX_DLY_R2DQS3_GATED GENMASK(26, 24) + #define SHU4RK2_SELPH_DQSG0_TX_DLY_R2DQS3_GATED_P1 GENMASK(30, 28) +#define SHU4RK2_SELPH_DQSG1 0x00001e28 + #define SHU4RK2_SELPH_DQSG1_REG_DLY_R2DQS0_GATED GENMASK(2, 0) + #define SHU4RK2_SELPH_DQSG1_REG_DLY_R2DQS0_GATED_P1 GENMASK(6, 4) + #define SHU4RK2_SELPH_DQSG1_REG_DLY_R2DQS1_GATED GENMASK(10, 8) + #define SHU4RK2_SELPH_DQSG1_REG_DLY_R2DQS1_GATED_P1 GENMASK(14, 12) + #define SHU4RK2_SELPH_DQSG1_REG_DLY_R2DQS2_GATED GENMASK(18, 16) + #define SHU4RK2_SELPH_DQSG1_REG_DLY_R2DQS2_GATED_P1 GENMASK(22, 20) + #define SHU4RK2_SELPH_DQSG1_REG_DLY_R2DQS3_GATED GENMASK(26, 24) + #define SHU4RK2_SELPH_DQSG1_REG_DLY_R2DQS3_GATED_P1 GENMASK(30, 28) +#define SHU4RK2_SELPH_DQ0 0x00001e2c + #define SHU4RK2_SELPH_DQ0_TX_DLY_R2DQ0 GENMASK(2, 0) + #define SHU4RK2_SELPH_DQ0_TX_DLY_R2DQ1 GENMASK(6, 4) + #define SHU4RK2_SELPH_DQ0_TX_DLY_R2DQ2 GENMASK(10, 8) + #define SHU4RK2_SELPH_DQ0_TX_DLY_R2DQ3 GENMASK(14, 12) + #define SHU4RK2_SELPH_DQ0_TX_DLY_R2OEN_DQ0 GENMASK(18, 16) + #define SHU4RK2_SELPH_DQ0_TX_DLY_R2OEN_DQ1 GENMASK(22, 20) + #define SHU4RK2_SELPH_DQ0_TX_DLY_R2OEN_DQ2 GENMASK(26, 24) + #define SHU4RK2_SELPH_DQ0_TX_DLY_R2OEN_DQ3 GENMASK(30, 28) +#define SHU4RK2_SELPH_DQ1 0x00001e30 + #define SHU4RK2_SELPH_DQ1_TX_DLY_R2DQM0 GENMASK(2, 0) + #define SHU4RK2_SELPH_DQ1_TX_DLY_R2DQM1 GENMASK(6, 4) + #define SHU4RK2_SELPH_DQ1_TX_DLY_R2DQM2 GENMASK(10, 8) + #define SHU4RK2_SELPH_DQ1_TX_DLY_R2DQM3 GENMASK(14, 12) + #define SHU4RK2_SELPH_DQ1_TX_DLY_R2OEN_DQM0 GENMASK(18, 16) + #define SHU4RK2_SELPH_DQ1_TX_DLY_R2OEN_DQM1 GENMASK(22, 20) + #define SHU4RK2_SELPH_DQ1_TX_DLY_R2OEN_DQM2 GENMASK(26, 24) + #define SHU4RK2_SELPH_DQ1_TX_DLY_R2OEN_DQM3 GENMASK(30, 28) +#define SHU4RK2_SELPH_DQ2 0x00001e34 + #define SHU4RK2_SELPH_DQ2_DLY_R2DQ0 GENMASK(2, 0) + #define SHU4RK2_SELPH_DQ2_DLY_R2DQ1 GENMASK(6, 4) + #define SHU4RK2_SELPH_DQ2_DLY_R2DQ2 GENMASK(10, 8) + #define SHU4RK2_SELPH_DQ2_DLY_R2DQ3 GENMASK(14, 12) + #define SHU4RK2_SELPH_DQ2_DLY_R2OEN_DQ0 GENMASK(18, 16) + #define SHU4RK2_SELPH_DQ2_DLY_R2OEN_DQ1 GENMASK(22, 20) + #define SHU4RK2_SELPH_DQ2_DLY_R2OEN_DQ2 GENMASK(26, 24) + #define SHU4RK2_SELPH_DQ2_DLY_R2OEN_DQ3 GENMASK(30, 28) +#define SHU4RK2_SELPH_DQ3 0x00001e38 + #define SHU4RK2_SELPH_DQ3_DLY_R2DQM0 GENMASK(2, 0) + #define SHU4RK2_SELPH_DQ3_DLY_R2DQM1 GENMASK(6, 4) + #define SHU4RK2_SELPH_DQ3_DLY_R2DQM2 GENMASK(10, 8) + #define SHU4RK2_SELPH_DQ3_DLY_R2DQM3 GENMASK(14, 12) + #define SHU4RK2_SELPH_DQ3_DLY_R2OEN_DQM0 GENMASK(18, 16) + #define SHU4RK2_SELPH_DQ3_DLY_R2OEN_DQM1 GENMASK(22, 20) + #define SHU4RK2_SELPH_DQ3_DLY_R2OEN_DQM2 GENMASK(26, 24) + #define SHU4RK2_SELPH_DQ3_DLY_R2OEN_DQM3 GENMASK(30, 28) +#define SHU4RK2_DQS2DQ_CAL1 0x00001e40 + #define SHU4RK2_DQS2DQ_CAL1_BOOT_ORIG_UI_RK2_DQ0 GENMASK(10, 0) + #define SHU4RK2_DQS2DQ_CAL1_BOOT_ORIG_UI_RK2_DQ1 GENMASK(26, 16) +#define SHU4RK2_DQS2DQ_CAL2 0x00001e44 + #define SHU4RK2_DQS2DQ_CAL2_BOOT_TARG_UI_RK2_DQ0 GENMASK(10, 0) + #define SHU4RK2_DQS2DQ_CAL2_BOOT_TARG_UI_RK2_DQ1 GENMASK(26, 16) +#define SHU4RK2_DQS2DQ_CAL3 0x00001e48 + #define SHU4RK2_DQS2DQ_CAL3_BOOT_TARG_UI_RK2_OEN_DQ0 GENMASK(5, 0) + #define SHU4RK2_DQS2DQ_CAL3_BOOT_TARG_UI_RK2_OEN_DQ1 GENMASK(11, 6) +#define SHU4RK2_DQS2DQ_CAL4 0x00001e4c + #define SHU4RK2_DQS2DQ_CAL4_BOOT_TARG_UI_RK2_OEN_DQM0 GENMASK(5, 0) + #define SHU4RK2_DQS2DQ_CAL4_BOOT_TARG_UI_RK2_OEN_DQM1 GENMASK(11, 6) +#define SHU4RK2_DQS2DQ_CAL5 0x00001e50 + #define SHU4RK2_DQS2DQ_CAL5_BOOT_TARG_UI_RK2_DQM0 GENMASK(10, 0) + #define SHU4RK2_DQS2DQ_CAL5_BOOT_TARG_UI_RK2_DQM1 GENMASK(26, 16) +#define SHU4_DQSG_RETRY 0x00001e54 + #define SHU4_DQSG_RETRY_R_DQSGRETRY_SW_RESET BIT(0) + #define SHU4_DQSG_RETRY_R_DQSG_RETRY_SW_EN BIT(1) + #define SHU4_DQSG_RETRY_R_DDR1866_PLUS BIT(2) + #define SHU4_DQSG_RETRY_R_RETRY_ONCE BIT(3) + #define SHU4_DQSG_RETRY_R_RETRY_3TIMES BIT(4) + #define SHU4_DQSG_RETRY_R_RETRY_1RANK BIT(5) + #define SHU4_DQSG_RETRY_R_RETRY_SAV_MSK BIT(6) + #define SHU4_DQSG_RETRY_R_DM4BYTE BIT(7) + #define SHU4_DQSG_RETRY_R_DQSIENLAT GENMASK(11, 8) + #define SHU4_DQSG_RETRY_R_STBENCMP_ALLBYTE BIT(12) + #define SHU4_DQSG_RETRY_R_XSR_DQSG_RETRY_EN BIT(13) + #define SHU4_DQSG_RETRY_R_XSR_RETRY_SPM_MODE BIT(14) + #define SHU4_DQSG_RETRY_R_RETRY_CMP_DATA BIT(15) + #define SHU4_DQSG_RETRY_R_RETRY_ALE_BLOCK_MASK BIT(20) + #define SHU4_DQSG_RETRY_R_RDY_SEL_DLE BIT(21) + #define SHU4_DQSG_RETRY_R_RETRY_ROUND_NUM GENMASK(25, 24) + #define SHU4_DQSG_RETRY_R_RETRY_RANKSEL_FROM_PHY BIT(28) + #define SHU4_DQSG_RETRY_R_RETRY_PA_DSIABLE BIT(29) + #define SHU4_DQSG_RETRY_R_RETRY_STBEN_RESET_MSK BIT(30) + #define SHU4_DQSG_RETRY_R_RETRY_USE_BURST_MDOE BIT(31) + +#endif /*__DRAMC_CH0_REG_H__*/ diff --git a/src/vendorcode/mediatek/mt8192/include/dramc_common.h b/src/vendorcode/mediatek/mt8192/include/dramc_common.h new file mode 100644 index 000000000000..04d07a025c53 --- /dev/null +++ b/src/vendorcode/mediatek/mt8192/include/dramc_common.h @@ -0,0 +1,91 @@ +/* SPDX-License-Identifier: BSD-3-Clause */ + +#ifndef _DRAMC_COMMON_H_ +#define _DRAMC_COMMON_H_ + +#define __ETT__ 0 + +//#include <console/console.h> +#include <delay.h> +#include <device/mmio.h> +#include <stdint.h> +#include <types.h> +#include <reg.h> +#include <string.h> +#include <soc/dramc_common.h> +#include <timer.h> +#include <print.h> + +#include "dramc_register.h" +#include "dramc_pi_api.h" +#include "dramc_int_slt.h" + +#if FOR_DV_SIMULATION_USED == 1 +#include "dramc_dv_init.h" +#endif + +/***********************************************************************/ +/* Public Types */ +/***********************************************************************/ + +/*------------------------------------------------------------*/ +/* macros, defines, typedefs, enums */ +/*------------------------------------------------------------*/ +/************************** Common Macro *********************/ +#define dsb() asm volatile("dsb sy" : : : "memory") + +#define DRV_Reg32(x) read32((const void *)((u64)(x))) +#define DRV_WriteReg32(x, y) write32((void *)((u64)(x)), (y)) + +#define mcDELAY_US(x) udelay(x) +#define mcDELAY_MS(x) udelay(x*1000) +#define mcDELAY_XUS(x) udelay(x) +#define mcDELAY_XNS(x) udelay(1) + +/**********************************************/ +/* Priority of debug log */ +/*--------------------------------------------*/ +/* mcSHOW_DBG_MSG: High */ +/* mcSHOW_DBG_MSG2: Medium High */ +/* mcSHOW_DBG_MSG3: Medium Low */ +/* mcSHOW_DBG_MSG4: Low */ +/**********************************************/ + +#define CALIBRATION_LOG 1 + +#if CALIBRATION_LOG +#define mcSHOW_DBG_MSG(_x_) {print _x_;} +#define mcSHOW_DBG_MSG2(_x_) //{print _x_;} +#define mcSHOW_ERR_MSG(_x_) {print _x_;} +#else +#define mcSHOW_DBG_MSG(_x_) +#define mcSHOW_DBG_MSG2(_x_) +#define mcSHOW_ERR_MSG(_x_) +#endif + +#define mcSHOW_DBG_MSG3(_x_) // {print _x_;} +#define mcSHOW_DBG_MSG4(_x_) +#define mcSHOW_DBG_MSG5(_x_) +#define mcSHOW_JV_LOG_MSG(_x_) +#if EYESCAN_LOG +#define mcSHOW_EYESCAN_MSG(_x_) {print _x_;} +#else +#define mcSHOW_EYESCAN_MSG(_x_) //{print _x_;} +#endif +#define mcSHOW_DBG_MSG5(_x_) +#define mcSHOW_TIME_MSG(_x_) +#define mcDUMP_REG_MSG(_x_) +#define mcFPRINTF(_x_) + +#ifndef ARRAY_SIZE +#define ARRAY_SIZE(x) (sizeof (x) / sizeof (x[0])) +#endif + +#define enter_function() \ + ({mcSHOW_DBG_MSG(("enter %s\n", __FUNCTION__));}) + +#define exit_function() \ + ({mcSHOW_DBG_MSG(("exit %s\n", __FUNCTION__));}) + +extern int dump_log; +#endif // _DRAMC_COMMON_H_ diff --git a/src/vendorcode/mediatek/mt8192/include/dramc_dv_init.h b/src/vendorcode/mediatek/mt8192/include/dramc_dv_init.h new file mode 100644 index 000000000000..bbb9fb2e2dd8 --- /dev/null +++ b/src/vendorcode/mediatek/mt8192/include/dramc_dv_init.h @@ -0,0 +1,331 @@ +/* SPDX-License-Identifier: BSD-3-Clause */ + +#ifndef _DRAMC_DV_INIT_H_ +#define _DRAMC_DV_INIT_H_ + +#include "dramc_common.h" +#include "dramc_int_global.h" +#include "x_hal_io.h" +#include "sv_c_data_traffic.h" + +//========================================================= +//DRAM CONFIG ELEMENT COLLECTION +//========================================================= +typedef enum { DDR3, DDR4, LPDDR3, LPDDR4, LPDDR5, PSRAM } DRAM_TYPE_T; +typedef enum {BG4BK4, BK8, BK16, BKORG_RFU} e_BKORG; +typedef enum {DIS_both, EN_t, EN_both, EN_c} e_RDQSWCK;//MR20 + +#define SA_CONFIG_EN 1 +#define DV_CONFIG_EN 1 +//========================================================= +//Build Top configuration +//========================================================= +#define DFS_GROUP_NUM 10 +#define CH_NUM 2 +#define RK_NUM_PER_CH 2 +#define DONT_CARE_VALUE 0 +#define PULL_UP 1 +#define PULL_DOWN 1 + + + +typedef struct Gating_config +{ + U8 GAT_TRACK_EN ; + U8 RX_GATING_MODE ; + U8 RX_GATING_TRACK_MODE ; + U8 SELPH_MODE ; + U8 PICG_EARLY_EN ; + U8 VALID_LAT_VALUE ; +}Gating_confg_T; + + +//========================================================= +//DV configuration connection +//========================================================= +#if DV_CONFIG_EN==1 +typedef struct DRAMC_DVFS_GROUP_transfer +{ + U8 CKR ; //LPDDR5 CKR could be 4 and 2 other memory type should be 1 + U8 DQSIEN_MODE ; //ANA DQSG mode config LPDDR4 = 1, LPDDR5 with other modes + U8 DQ_P2S_RATIO; //16-1 8-1 4-1 LPDDR5 could support 16-1 mode + U8 RESERVED_8BIT; + U32 data_rate ; +}DRAMC_DVFS_GROUP_transfer_T; + +typedef struct DV_configuration +{ + U8 EX_ROW_EN_1 ; + U8 EX_ROW_EN_0 ; + U8 BYTE_MODE_1 ; + U8 BYTE_MODE_0 ; + U8 LP4Y_EN ; + U8 LP4_WR_PST ; + U8 LP4_OTF ; + U8 NEW_8X_MODE ; + U8 LP45_APHY_COMB_EN; + U8 DLL_IDLE_MODE ; + U8 NEW_RANK_MODE ; + U8 DLL_ASYNC_EN ; + U8 MD32_EN ; + U8 SRAM_EN ; + U8 GP_NUM ; +} DV_new_config_T; +#endif + + +//========================================================= +//LPDDR4 DRAM config +//========================================================= +typedef struct LP4_DRAM_CONFIG +{ + U8 BYTE_MODE[2]; //diff rank + U8 EX_ROW_EN[2]; //diff rank --density over 10G should 1 + U8 MR_WL ; + U8 MR_RL ; + U8 BL ; + U8 RPST ; + U8 RD_PRE ; + U8 WR_PRE ; + U8 WR_PST ; + U8 DBI_WR ; + U8 DBI_RD ; +// U8 DMI ; //No use default enable + U8 OTF ; + U8 LP4Y_EN ; + U8 WORK_FSP ; +} LP4_DRAM_CONFIG_T; + + + +//========================================================= +//LPDDR5 DRAM config +//========================================================= +typedef struct LP5_DRAM_CONFIG +{ + U8 BYTE_MODE[2] ; + U8 EX_ROW_EN[2] ; + U8 MR_WL ; + U8 MR_RL ; + U8 BL ; + U8 CK_Mode ; + U8 RPST ; + U8 RD_PRE ; + U8 WR_PRE ; + U8 WR_PST ; + U8 DBI_WR ; + U8 DBI_RD ; + U8 DMI ; + U8 OTF ; + U8 WCK_PST ; + U8 RDQS_PRE ; + U8 RDQS_PST ; + U8 CA_ODT ; + U8 DQ_ODT ; + U8 CKR ; + U8 WCK_ON ; + U8 WCK_FM ; + U8 WCK_ODT ; + U8 DVFSQ ; + U8 DVFSC ; + e_RDQSWCK RDQSmode[2] ; + U8 WCKmode[2] ; + U8 RECC ; + U8 WECC ; + e_BKORG BankMode ; + U8 WORK_FSP ; +} LP5_DRAM_CONFIG_T; + +//========================================================= +//Analog PHY config +//========================================================= +typedef struct ANA_top_function_config +{ + U8 DLL_ASYNC_EN ; + U8 ALL_SLAVE_EN ; + U8 NEW_RANK_MODE ; + U8 DLL_IDLE_MODE ; + U8 LP45_APHY_COMB_EN; + U8 TX_ODT_DIS ; + U8 NEW_8X_MODE ; +}ANA_top_config_T; + + +typedef struct ANA_DVFS_core_config +{ + U8 CKR; + U8 DQ_P2S_RATIO; + U8 LP5_1600_DQ_P2S_MODE; + U8 CA_P2S_RATIO; + U8 DQ_CA_OPEN; + U8 DQ_SEMI_OPEN; + U8 CA_SEMI_OPEN; + U8 CA_FULL_RATE; + U8 DQ_CKDIV4_EN; + U8 CA_CKDIV4_EN; + U8 CA_PREDIV_EN; + U8 PH8_DLY; + U8 SEMI_OPEN_CA_PICK_MCK_RATIO; + U8 DQ_AAMCK_DIV; + U8 CA_AAMCK_DIV; + U8 CA_ADMCK_DIV; + U8 DQ_TRACK_CA_EN; + U32 PLL_FREQ; + U8 DQ_UI_PI_RATIO; + U8 CA_UI_PI_RATIO; +} ANA_DVFS_CORE_T; + + +//========================================================= +//DVFS group configuration +//========================================================= +typedef struct DRAMC_DVFS_GROUP_CONFIG +{ + U32 data_rate ; + U8 DQSIEN_MODE ; //ANA DQSG mode config LPDDR4 = 1, LPDDR5 with other modes + U8 DQ_P2S_RATIO; //16-1 8-1 4-1 LPDDR5 could support 16-1 mode + U8 CKR ; //LPDDR5 CKR could be 4 and 2 other memory type should be 1 +}DRAMC_DVFS_GROUP_CONFIG_T; + +//========================================================= +//DRAMC Subsystem config +//========================================================= +typedef struct DRAMC_SUBSYS_CONFIG +{ + U8 GP_NUM ; + U8 SRAM_EN ; + U8 MD32_EN ; + ANA_top_config_T *a_cfg ; + ANA_DVFS_CORE_T *a_opt ; + LP4_DRAM_CONFIG_T *lp4_init ; + LP5_DRAM_CONFIG_T *lp5_init ; + DRAMC_DVFS_GROUP_CONFIG_T *DFS_GP[DFS_GROUP_NUM]; +}DRAMC_SUBSYS_CONFIG_T; + + +typedef struct DUT_shuf_config_T { + U8 CKE_DBE_CNT ; + U8 FASTWAKE2 ; + U8 DMPGTIM ; + U8 ADVPREEN ; + U8 DLE_256EN ; + U8 LECC ; + U8 WPST1P5T_OPT ; + U8 LP4YEN ; + U8 LP5_CAS_MODE ; + U8 LP5_SEP_ACT ; + U8 LP5_BGOTF ; + U8 LP5_BGEN ; + U8 LP5_RDQS_SE_EN ; + U8 CKR ; + U8 DQSIEN_MODE ; + U8 DQ_P2S_RATIO ; + U32 data_rate ; +}__attribute__((packed)) DUT_shuf_config_T; + + +typedef struct DUT_top_set_T { + U8 DVFSRTMRWEN ; + U8 NO_QUEUEFLUSH_EN ; + U8 RG_SPM_MODE ; + U8 MD32_EN ; + U8 SRAM_EN ; + U8 RX_PIPE_BYPASS_EN ; + U8 TX_PIPE_BYPASS_EN ; + U32 WAIT_DLE_EXT_DLY ; + U32 RX_DCM_EXT_DLY ; + U8 old_dcm_mode ; + U8 DPHY_DCM_MODE ; + U8 TX_OE_EXT_OPT ; + U8 TXP_WORKAROUND_OPT ; + U32 VALID_LAT_VALUE ; + U8 RXTRACK_PBYTE_OPT ; + U8 TRACK_UP_MODE ; + U8 TREFBWIG_IGNORE ; + U8 SELPH_MODE ; + U8 RANK_SWAP ; + U8 BGPIPE_EN ; + U8 PICG_MODE ; + U8 RTMRR_MODE ; + U8 TMRRI_MODE ; + U8 DQS_OSC_AT_TIMER ; + U8 WPST1P5T_OPT ; + U8 LP5_ZQ_OPT ; + U8 LP5WRAPEN ; + U8 LP4_SE_MODE ; + U8 LP4Y_EN ; + U8 LP4_WR_PST ; + U8 LP4_OTF ; + U8 PLL_MODE_OPTION ; + U8 NEW_8X_MODE ; + U8 LP45_APHY_COMB_EN ; + U8 DLL_IDLE_MODE ; + U8 NEW_RANK_MODE ; + U8 DLL_ASYNC_EN ; + U32 memory_type ; + U32 GP_NUM ; +}__attribute__((packed)) DUT_top_set_T; + + + +extern Gating_confg_T Gat_p; +extern DRAM_TYPE_T MEM_TYPE; +extern LP4_DRAM_CONFIG_T LP4_INIT; +extern LP5_DRAM_CONFIG_T LP5_INIT; +extern ANA_top_config_T ana_top_p; +extern ANA_DVFS_CORE_T ANA_option; +extern DRAMC_DVFS_GROUP_CONFIG_T DFS_TOP[DFS_GROUP_NUM]; +extern DRAMC_SUBSYS_CONFIG_T DV_p; +extern DRAMC_CTX_T *DramcConfig; +extern DUT_top_set_T DUTTopSetGlobal; +extern DUT_shuf_config_T DUTShufConfigGlobal[10]; + +#define A_T DV_p.a_cfg +#define A_D DV_p.a_opt +#define M_LP4 DV_p.lp4_init +#define DFS(i) DV_p.DFS_GP[i] +#define LPDDR5_EN_S ((MEM_TYPE==LPDDR5) ? 1 : 0) +#define LPDDR4_EN_S ((MEM_TYPE==LPDDR4) ? 1 : 0) + +#define DUT_p DUTTopSetGlobal +#define DUT_shu_p DUTShufConfigGlobal + + +#if FOR_DV_SIMULATION_USED==1 +EXTERN void register_write(int address, int data); +EXTERN void register_read(int address, int * data); +EXTERN void delay_us(u32 delta); +EXTERN void delay_ns(u32 delta); +EXTERN void timestamp_show(); +EXTERN void build_api_initial(); +EXTERN void register_write_c(u32 address, u32 data); +EXTERN u32 register_read_c(u32 address); +EXTERN void conf_to_sram_sudo(int ch_id , int group_id, int conf_id); +//================ added by Lingyun Wu 11.14 ===================== +EXTERN void broadcast_on(void); +EXTERN void broadcast_off(void); +//================ added by Lingyun Wu 11.14 ===================== +EXTERN void mygetscope(); +EXTERN void mysetscope(); +#endif + + +#if DV_CONFIG_EN +extern void get_dfs_configuration_from_DV_random(DRAMC_DVFS_GROUP_transfer_T * tr, int group_id); +extern void get_top_configuration_from_DV_random(DV_new_config_T * tr); +#endif +//DRAM LP4 initial configuration +extern U8 LP4_DRAM_INIT_RLWL_MRfield_config(U32 data_rate); + + + +extern void DPI_SW_main_LP4(DRAMC_CTX_T *p, cal_sv_rand_args_t *psra); +extern void DRAMC_SUBSYS_PRE_CONFIG(DRAMC_CTX_T *p, DRAMC_SUBSYS_CONFIG_T *tr); +extern void LP4_DRAM_config(U32 data_rate, LP4_DRAM_CONFIG_T *tr); +extern void LP5_DRAM_config(DRAMC_DVFS_GROUP_CONFIG_T *dfs_tr, LP5_DRAM_CONFIG_T *tr); +extern void ANA_TOP_FUNCTION_CFG(ANA_top_config_T *tr,U16 data_rate); +extern void ANA_CLK_DIV_config( ANA_DVFS_CORE_T *tr,DRAMC_DVFS_GROUP_CONFIG_T *dfs); +extern void ANA_sequence_shuffle_colletion(DRAMC_CTX_T *p,ANA_DVFS_CORE_T *tr); +extern void ANA_Config_shuffle(DRAMC_CTX_T *p,ANA_top_config_T *a_cfg,U8 group_id); + +#endif // _DRAMC_DV_INIT_H_ diff --git a/src/vendorcode/mediatek/mt8192/include/dramc_int_global.h b/src/vendorcode/mediatek/mt8192/include/dramc_int_global.h new file mode 100644 index 000000000000..ed153531ba83 --- /dev/null +++ b/src/vendorcode/mediatek/mt8192/include/dramc_int_global.h @@ -0,0 +1,652 @@ +/* SPDX-License-Identifier: BSD-3-Clause */ + +#ifndef _INT_GLOBAL_H +#define _INT_GLOBAL_H + +#include "dramc_pi_api.h" +#include "dramc_int_slt.h" + +/* + **************************************************************************************** + ** macro + **************************************************************************************** + */ +#define DVT_TEST_DUMMY_RD_SIDEBAND_FROM_SPM 0 +//#define DVT_TEST_DUMMY_READ_FOR_DQS_GATING_TRACKING +//#define DVT_TEST_RX_DLY_HW_TRACKING + + +/* + **************************************************************************************** + ** ANA_init_config.c + **************************************************************************************** + */ +EXTERN void ANA_init(DRAMC_CTX_T *p); +EXTERN void RESETB_PULL_DN(DRAMC_CTX_T *p); + + + +/* + **************************************************************************************** + ** DIG_NONSHUF_config.c + **************************************************************************************** + */ +EXTERN void DIG_STATIC_SETTING(DRAMC_CTX_T *p); + + +/* + **************************************************************************************** + * + ** DIG_SHUF_config.c + **************************************************************************************** + */ +EXTERN void DIG_CONFIG_SHUF(DRAMC_CTX_T *p,U32 ch_id, U32 group_id); + + +/* + **************************************************************************************** + * + ** dramc_debug.c + **************************************************************************************** + */ +EXTERN U8 gFinalCBTVrefDQ[CHANNEL_NUM][RANK_MAX]; +EXTERN U8 gFinalRXVrefDQ[CHANNEL_NUM][RANK_MAX][2]; +EXTERN U8 gFinalTXVrefDQ[CHANNEL_NUM][RANK_MAX]; + +#ifdef FOR_HQA_REPORT_USED +EXTERN U8 gHQALog_flag; +EXTERN U16 gHQALOG_RX_delay_cell_ps_075V; +EXTERN int hqa_vmddr_class; +EXTERN void HQA_Log_Message_for_Report(DRAMC_CTX_T *p, U8 u1ChannelIdx, U8 u1RankIdx, U32 who_am_I, U8 *main_str, U8 *main_str2, U8 byte_bit_idx, S32 value1, U8 *ans_str); +#endif + + +// --- Eye scan variables ----- + +EXTERN U8 gCBT_EYE_Scan_flag; +EXTERN U8 gRX_EYE_Scan_flag; +EXTERN U8 gTX_EYE_Scan_flag; +EXTERN U8 gEye_Scan_color_flag; +EXTERN U8 gCBT_EYE_Scan_only_higheset_freq_flag; +EXTERN U8 gRX_EYE_Scan_only_higheset_freq_flag; +EXTERN U8 gTX_EYE_Scan_only_higheset_freq_flag; +EXTERN U8 gEye_Scan_unterm_highest_flag; + +#if ENABLE_EYESCAN_GRAPH +#define VREF_TOTAL_NUM_WITH_RANGE (((51 + 30) + 1) / (EYESCAN_GRAPH_CATX_VREF_STEP < EYESCAN_GRAPH_RX_VREF_STEP ? EYESCAN_GRAPH_CATX_VREF_STEP : EYESCAN_GRAPH_RX_VREF_STEP)) //range0 0~50 + range1 21~50 +#define EYESCAN_BROKEN_NUM 3 +#define EYESCAN_DATA_INVALID 0x7f +EXTERN S16 gEyeScan_Min[VREF_VOLTAGE_TABLE_NUM_LP5][DQ_DATA_WIDTH_LP4][EYESCAN_BROKEN_NUM]; +EXTERN S16 gEyeScan_Max[VREF_VOLTAGE_TABLE_NUM_LP5][DQ_DATA_WIDTH_LP4][EYESCAN_BROKEN_NUM]; +EXTERN S16 gEyeScan_MinMax_store_delay[DQS_NUMBER]; +EXTERN U16 gEyeScan_CaliDelay[DQS_NUMBER]; +EXTERN U16 gEyeScan_WinSize[VREF_VOLTAGE_TABLE_NUM_LP5][DQ_DATA_WIDTH_LP4]; +EXTERN S16 gEyeScan_DelayCellPI[DQ_DATA_WIDTH_LP4]; +EXTERN U16 gEyeScan_ContinueVrefHeight[DQ_DATA_WIDTH_LP4]; +EXTERN U16 gEyeScan_TotalPassCount[DQ_DATA_WIDTH_LP4]; +EXTERN void Dramc_K_TX_EyeScan_Log(DRAMC_CTX_T *p); +EXTERN void print_EYESCAN_LOG_message(DRAMC_CTX_T *p, U8 print_type); +#endif +#if MRW_CHECK_ONLY || MRW_BACKUP +EXTERN U8 gFSPWR_Flag[RANK_MAX]; +#endif +#ifdef FOR_HQA_TEST_USED +EXTERN void HQA_measure_message_reset_all_data(DRAMC_CTX_T *p); +#endif +#if RUNTIME_SHMOO_RELEATED_FUNCTION && SUPPORT_SAVE_TIME_FOR_CALIBRATION +void DramcRunTimeShmooRG_BackupRestore(DRAMC_CTX_T *p); +#endif + + + +/* + **************************************************************************************** + ** dramc_dvfs.c + **************************************************************************************** + */ +EXTERN U8 get_shuffleIndex_by_Freq(DRAMC_CTX_T *p); +EXTERN void vInitMappingFreqArray(DRAMC_CTX_T *p); +EXTERN void vSetDFSTable(DRAMC_CTX_T *p, DRAM_DFS_FREQUENCY_TABLE_T *pFreqTable); +EXTERN DRAM_DFS_FREQUENCY_TABLE_T* get_FreqTbl_by_shuffleIndex(DRAMC_CTX_T *p, U8 index); +EXTERN void vSetDFSFreqSelByTable(DRAMC_CTX_T *p, DRAM_DFS_FREQUENCY_TABLE_T *pFreqTable); +EXTERN void DramcDFSDirectJump(DRAMC_CTX_T *p, U8 shu_level); +EXTERN void DramcSaveToShuffleSRAM(DRAMC_CTX_T *p, DRAM_DFS_SHUFFLE_TYPE_T srcRG, DRAM_DFS_SHUFFLE_TYPE_T dstRG); +EXTERN void LoadShuffleSRAMtoDramc(DRAMC_CTX_T *p, DRAM_DFS_SHUFFLE_TYPE_T srcRG, DRAM_DFS_SHUFFLE_TYPE_T dstRG); +EXTERN void DramcDFSDirectJump_RGMode(DRAMC_CTX_T *p, U8 shu_level); +EXTERN void DVFSSettings(DRAMC_CTX_T *p); +EXTERN void DPMEnableTracking(DRAMC_CTX_T *p, U32 u4Reg, U32 u4Field, U8 u1ShuIdx, U8 u1Enable); +EXTERN void DPMInit(DRAMC_CTX_T *p); +EXTERN void TransferPLLToSPMControl(DRAMC_CTX_T *p, U32 MD32Offset); +EXTERN void DramcCopyShu0toShu1(DRAMC_CTX_T *p, U32 u4StartAddr, U32 u4EndAddr); +EXTERN void DdrphyCopyShu0toShu1(DRAMC_CTX_T *p, U32 u4StartAddr, U32 u4EndAddr); +EXTERN void EnableDFSHwModeClk(DRAMC_CTX_T *p); +EXTERN void DPHYSaveToSRAMShuWA(DRAMC_CTX_T *p, U8 shu_level); +EXTERN void DPHYSRAMShuWAToSHU1(DRAMC_CTX_T *p); +EXTERN void SRAMShuRestoreToDPHYWA(DRAMC_CTX_T *p, U8 sram_shu_level, U8 pingpong_shu_level); + + +/* + **************************************************************************************** + ** dramc_dv_freq_related.c + **************************************************************************************** + */ +EXTERN void sv_algorithm_assistance_LP4_1600(DRAMC_CTX_T *p); +EXTERN void sv_algorithm_assistance_LP4_3733(DRAMC_CTX_T *p); +EXTERN void sv_algorithm_assistance_LP4_800(DRAMC_CTX_T *p); +EXTERN void CInit_golden_mini_freq_related_vseq_LP4_1600(DRAMC_CTX_T *p); +EXTERN void CInit_golden_mini_freq_related_vseq_LP4_4266(DRAMC_CTX_T *p); +EXTERN void CInit_golden_mini_freq_related_vseq_LP5_3200(DRAMC_CTX_T *p); +EXTERN void CInit_golden_mini_freq_related_vseq_LP5_3200_SHU1(DRAMC_CTX_T *p); +EXTERN void CInit_golden_mini_freq_related_vseq_LP5_4266(DRAMC_CTX_T *p); +EXTERN void CInit_golden_mini_freq_related_vseq_LP5_5500(DRAMC_CTX_T *p); + + +/* + **************************************************************************************** + ** dramc_dv_main.c + **************************************************************************************** + */ +#if (FOR_DV_SIMULATION_USED == 1) +EXTERN void DPI_DRAMC_init_entry(); +EXTERN void DPI_DRAM_INIT(); +#endif + + +/* + **************************************************************************************** + ** dramc_pi_basic.c + **************************************************************************************** + */ +EXTERN U8 u1PrintModeRegWrite; +EXTERN void vApplyConfigBeforeCalibration(DRAMC_CTX_T *p); +EXTERN DRAM_STATUS_T DramcInit(DRAMC_CTX_T *p); +EXTERN void SetCKE2RankIndependent(DRAMC_CTX_T *p); +EXTERN void DramcDQSPrecalculation_TrackingOff(DRAMC_CTX_T *p, U8 shu_level); +EXTERN void DramcDQSPrecalculation_TrackingOn(DRAMC_CTX_T *p, U8 shu_level); +EXTERN void DramcHWDQSGatingTracking_ModeSetting(DRAMC_CTX_T *p); +EXTERN void Set_MRR_Pinmux_Mapping(DRAMC_CTX_T *p); +EXTERN void Set_DQO1_Pinmux_Mapping(DRAMC_CTX_T *p); +#if CBT_MOVE_CA_INSTEAD_OF_CLK +EXTERN void DramcCmdUIDelaySetting(DRAMC_CTX_T *p, U8 value); +#endif +EXTERN void cbt_switch_freq(DRAMC_CTX_T *p, U8 freq); +EXTERN DRAM_STATUS_T DramcModeRegInit_LP4(DRAMC_CTX_T *p); +EXTERN DRAM_STATUS_T DramcModeRegInit_CATerm(DRAMC_CTX_T *p, U8 bWorkAround); +EXTERN void DramcPowerOnSequence(DRAMC_CTX_T *p); +EXTERN void Global_Option_Init(DRAMC_CTX_T *p); +EXTERN U16 u2DFSGetHighestFreq(DRAMC_CTX_T * p); +EXTERN void EnableDRAMModeRegWriteDBIAfterCalibration(DRAMC_CTX_T *p); +EXTERN void EnableDRAMModeRegReadDBIAfterCalibration(DRAMC_CTX_T *p); +EXTERN void ApplyWriteDBIPowerImprove(DRAMC_CTX_T *p, U8 onoff); +EXTERN void DramcHMR4_Presetting(DRAMC_CTX_T *p); +EXTERN void DramcEnablePerBankRefresh(DRAMC_CTX_T *p, bool en); +EXTERN void RXPICGSetting(DRAMC_CTX_T * p); +EXTERN void TXPICGNewModeEnable(DRAMC_CTX_T * p); +EXTERN unsigned int DDRPhyFreqMeter(void); +#ifndef DPM_CONTROL_AFTERK +EXTERN void dramc_exit_with_DFS_legacy_mode(DRAMC_CTX_T * p); +#endif + + + +/* + **************************************************************************************** + ** dramc_pi_calibration_api.c + **************************************************************************************** + */ +EXTERN U16 gu2MR0_Value[RANK_MAX]; //read only mode register +EXTERN U32 gDramcSwImpedanceResult[IMP_VREF_MAX][IMP_DRV_MAX]; //ODT_ON/OFF x DRVP/DRVN/ODTP/ODTN +EXTERN U16 u2g_num_dlycell_perT_all[DRAM_DFS_SHUFFLE_MAX][CHANNEL_NUM]; //TODO: to be removed by Francis +EXTERN U16 u2gdelay_cell_ps_all[DRAM_DFS_SHUFFLE_MAX][CHANNEL_NUM]; //TODO: to be removed by Francis +EXTERN U16 u2gdelay_cell_ps; +EXTERN U8 gCBT_VREF_RANGE_SEL; +EXTERN U32 u4gVcore[DRAM_DFS_SHUFFLE_MAX]; +EXTERN U8 uiLPDDR4_O1_Mapping_POP[CHANNEL_NUM][16]; +EXTERN const U8 uiLPDDR4_O1_DRAM_Pinmux[PINMUX_MAX][CHANNEL_NUM][16]; +EXTERN U8 uiLPDDR4_CA_Mapping_POP[CHANNEL_NUM][6]; +EXTERN const U8 uiLPDDR4_CA_DRAM_Pinmux[PINMUX_MAX][CHANNEL_NUM][6]; + +#if __ETT__ +EXTERN U8 gETT_WHILE_1_flag; +#endif + +#ifdef FOR_HQA_REPORT_USED +extern U8 gHQALog_flag; +extern U16 gHQALOG_RX_delay_cell_ps_075V; +#endif + +#ifdef FOR_HQA_TEST_USED +EXTERN U16 gFinalCBTVrefCA[CHANNEL_NUM][RANK_MAX]; +EXTERN U16 gFinalCBTCA[CHANNEL_NUM][RANK_MAX][10]; +EXTERN U16 gFinalRXPerbitWin[CHANNEL_NUM][RANK_MAX][DQ_DATA_WIDTH]; +EXTERN U16 gFinalTXPerbitWin[CHANNEL_NUM][RANK_MAX][DQ_DATA_WIDTH]; +EXTERN U16 gFinalTXPerbitWin_min_max[CHANNEL_NUM][RANK_MAX]; +EXTERN U16 gFinalTXPerbitWin_min_margin[CHANNEL_NUM][RANK_MAX]; +EXTERN U16 gFinalTXPerbitWin_min_margin_bit[CHANNEL_NUM][RANK_MAX]; +EXTERN S8 gFinalClkDuty[CHANNEL_NUM]; +EXTERN U32 gFinalClkDutyMinMax[CHANNEL_NUM][2]; +EXTERN S8 gFinalDQSDuty[CHANNEL_NUM][DQS_NUMBER]; +EXTERN U32 gFinalDQSDutyMinMax[CHANNEL_NUM][DQS_NUMBER][2]; +#endif +EXTERN U8 u1MR01Value[FSP_MAX]; +EXTERN U8 u1MR02Value[FSP_MAX]; +EXTERN U8 u1MR03Value[FSP_MAX]; +EXTERN U8 u1MR11Value[FSP_MAX]; +EXTERN U8 u1MR18Value[FSP_MAX]; +EXTERN U8 u1MR19Value[FSP_MAX]; +EXTERN U8 u1MR20Value[FSP_MAX]; +EXTERN U8 u1MR21Value[FSP_MAX]; +EXTERN U8 u1MR22Value[FSP_MAX]; +EXTERN U8 u1MR51Value[FSP_MAX]; +EXTERN U8 u1MR04Value[RANK_MAX]; +EXTERN U8 u1MR13Value[RANK_MAX]; +EXTERN U8 u1MR26Value[RANK_MAX]; +EXTERN U8 u1MR30Value[RANK_MAX]; +EXTERN U8 u1MR12Value[CHANNEL_NUM][RANK_MAX][FSP_MAX]; +EXTERN U8 u1MR14Value[CHANNEL_NUM][RANK_MAX][FSP_MAX]; +#if PINMUX_AUTO_TEST_PER_BIT_RX +EXTERN U8 gRX_check_per_bit_flag; +EXTERN S16 gFinalRXPerbitFirstPass[CHANNEL_NUM][DQ_DATA_WIDTH]; +#endif +#if PINMUX_AUTO_TEST_PER_BIT_TX +EXTERN U8 gTX_check_per_bit_flag; +EXTERN S16 gFinalTXPerbitFirstPass[CHANNEL_NUM][DQ_DATA_WIDTH]; +#endif +EXTERN U8 u1IsLP4Div4DDR800(DRAMC_CTX_T *p); +EXTERN DRAM_STATUS_T DramcTxWindowPerbitCal(DRAMC_CTX_T *p, DRAM_TX_PER_BIT_CALIBRATION_TYTE_T calType, U8 u1VrefScanEnable, u8 isAutoK); +EXTERN DRAM_STATUS_T DramcZQCalibration(DRAMC_CTX_T *p, U8 rank); +EXTERN DRAM_STATUS_T CmdBusTrainingLP45(DRAMC_CTX_T *p, int autok); +EXTERN DRAM_STATUS_T DramcWriteLeveling(DRAMC_CTX_T *p, u8 isAutoK, WLEV_DELAY_BASED_T stDelayBase); +EXTERN DRAM_STATUS_T dramc_rx_dqs_gating_cal(DRAMC_CTX_T *p, u8 autok, U8 use_enhanced_rdqs); +EXTERN DRAM_STATUS_T DramcRxWindowPerbitCal(DRAMC_CTX_T *p, RX_PATTERN_OPTION_T eRxPattern, + U8 *u1AssignedVref, u8 isAutoK); +EXTERN DRAM_STATUS_T DramcRxDVSWindowCal(DRAMC_CTX_T *p); +EXTERN DRAM_STATUS_T Dramc8PhaseCal(DRAMC_CTX_T *p); +EXTERN DRAM_STATUS_T DramcSwImpedanceCal(DRAMC_CTX_T *p, U8 u1Para, DRAMC_IMP_T freq_region); +EXTERN void DramcSwImpedanceSaveRegister(DRAMC_CTX_T *p, U8 ca_freq_option, U8 dq_freq_option, U8 save_to_where); +EXTERN void vBeforeCalibration(DRAMC_CTX_T *p); +EXTERN void vAfterCalibration(DRAMC_CTX_T *p); +EXTERN void DramcRunTimeConfig(DRAMC_CTX_T *p); +EXTERN DRAM_STATUS_T DramcMiockJmeter(DRAMC_CTX_T *p); +EXTERN DRAM_STATUS_T DramcDutyCycleMonitor(DRAMC_CTX_T *p); +EXTERN void DramcTxOECalibration(DRAMC_CTX_T *p); +EXTERN DRAM_STATUS_T DramcRxdatlatCal(DRAMC_CTX_T *p); +EXTERN void LP4_ShiftDQS_OENUI(DRAMC_CTX_T *p, S8 iShiftUI, BYTES_T eByteIdx); +EXTERN void ShiftDQ_OENUI_AllRK(DRAMC_CTX_T *p, S8 iShiftUI, BYTES_T eByteIdx); +EXTERN void DramcMiockJmeterHQA(DRAMC_CTX_T *p); +EXTERN U8 u1IsPhaseMode(DRAMC_CTX_T *p); +EXTERN void RODTSettings(DRAMC_CTX_T *p); +EXTERN void DQSSTBSettings(DRAMC_CTX_T *p); +EXTERN void DramcWriteShiftMCKForWriteDBI(DRAMC_CTX_T *p, S8 iShiftMCK); +EXTERN void DramPhyReset(DRAMC_CTX_T *p); +EXTERN U32 DramcRxWinRDDQCInit(DRAMC_CTX_T *p); +EXTERN U32 DramcRxWinRDDQCRun(DRAMC_CTX_T *p); +EXTERN U32 DramcRxWinRDDQCEnd(DRAMC_CTX_T *p); +#if BYPASS_CALIBRATION +EXTERN void dle_factor_handler(DRAMC_CTX_T *p, U8 curr_val); +EXTERN void ShiftDQSWCK_UI(DRAMC_CTX_T *p, S8 iShiftUI, BYTES_T eByteIdx); +EXTERN void ShiftDQUI_AllRK(DRAMC_CTX_T *p, S8 iShiftUI, BYTES_T eByteIdx); +EXTERN void TXSetDelayReg_DQ(DRAMC_CTX_T *p, U8 u1UpdateRegUI, U8 ucdqm_ui_large[], U8 ucdqm_oen_ui_large[], U8 ucdqm_ui_small[], U8 ucdqm_oen_ui_small[], U8 ucdqm_pi[]); +EXTERN void TXSetDelayReg_DQM(DRAMC_CTX_T *p, U8 u1UpdateRegUI, U8 ucdqm_ui_large[], U8 ucdqm_oen_ui_large[], U8 ucdqm_ui_small[], U8 ucdqm_oen_ui_small[], U8 ucdqm_pi[]); +EXTERN void TXUpdateTXTracking(DRAMC_CTX_T *p, DRAM_TX_PER_BIT_CALIBRATION_TYTE_T calType, U8 ucdq_pi[], U8 ucdqm_pi[]); +EXTERN void Apply_LP4_1600_Calibraton_Result(DRAMC_CTX_T *p); +EXTERN void Apply_LP4_4266_Calibraton_Result(DRAMC_CTX_T *p); +#endif +EXTERN void vInitGlobalVariablesByCondition(DRAMC_CTX_T *p); +EXTERN void DramcDramcRxDVSCalPostProcess(DRAMC_CTX_T *p); +EXTERN void CBTDelayCACLK(DRAMC_CTX_T *p, S32 iDelay); +#if __FLASH_TOOL_DA__ +EXTERN void vPrintPinInfoResult(DRAMC_CTX_T *p); +EXTERN DEBUG_PIN_INF_FOR_FLASHTOOL_T PINInfo_flashtool; +#endif + + +/* + **************************************************************************************** + ** dramc_pi_main.c + **************************************************************************************** + */ +EXTERN DRAMC_CTX_T gTimeProfilingDramCtx; +EXTERN U8 gHQA_Test_Freq_Vcore_Level; +#if (FOR_DV_SIMULATION_USED == 1) +EXTERN U8 gu1BroadcastIsLP4; +#endif +EXTERN bool gAndroid_DVFS_en; +EXTERN bool gUpdateHighestFreq; +EXTERN DRAM_DFS_FREQUENCY_TABLE_T gFreqTbl[DRAM_DFS_SHUFFLE_MAX]; +EXTERN void dump_dramc_ctx(DRAMC_CTX_T *p); +#ifdef ENABLE_MIOCK_JMETER +EXTERN void PRE_MIOCK_JMETER_HQA_USED(DRAMC_CTX_T *p); +#endif +EXTERN void vCalibration_Flow_For_MDL(DRAMC_CTX_T *p); +EXTERN void vDramCalibrationAllChannel(DRAMC_CTX_T *p); +EXTERN U32 vGetVoltage(DRAMC_CTX_T *p, U32 get_voltage_type); + + +/* + **************************************************************************************** + ** dramc_slt.c + **************************************************************************************** + */ +#if ENABLE_EMI_LPBK_TEST +EXTERN U8 gEmiLpbkTest; +#endif +EXTERN void SLT_DramcDFS(DRAMC_CTX_T *p, int iDoDMA); +EXTERN void SLT_DFSTestProgram(DRAMC_CTX_T *p, int iDoDMA); +EXTERN void SLT_Test_DFS_and_Memory_Test(DRAMC_CTX_T*p); + + + +/* + **************************************************************************************** + ** dramc_temp_function.c + **************************************************************************************** + */ +EXTERN DRAMC_CTX_T DramCtx_LPDDR4; + + +/* + **************************************************************************************** + ** dramc_tracking.c + **************************************************************************************** + */ +EXTERN U8 gu1MR23[CHANNEL_NUM][RANK_MAX]; +EXTERN void DramcHWGatingInit(DRAMC_CTX_T *p); +EXTERN void DramcHWGatingOnOff(DRAMC_CTX_T *p, U8 u1OnOff); +EXTERN void DramcHWGatingDebugOnOff(DRAMC_CTX_T *p, U8 u1OnOff); +EXTERN void DramcPrintHWGatingStatus(DRAMC_CTX_T *p, U8 u1Channel); +#if (ENABLE_TX_TRACKING || TDQSCK_PRECALCULATION_FOR_DVFS) +EXTERN void FreqJumpRatioCalculation(DRAMC_CTX_T *p); +#endif +#if TDQSCK_PRECALCULATION_FOR_DVFS +EXTERN void DramcDQSPrecalculation_preset(DRAMC_CTX_T *p); +EXTERN void DramcDQSPrecalculation_enable(DRAMC_CTX_T *p); +#endif +EXTERN void DramcDQSOSCInit(void); +EXTERN DRAM_STATUS_T DramcDQSOSCAuto(DRAMC_CTX_T *p); +#if ENABLE_TX_TRACKING +EXTERN DRAM_STATUS_T DramcDQSOSCMR23(DRAMC_CTX_T *p); +EXTERN DRAM_STATUS_T DramcDQSOSCSetMR18MR19(DRAMC_CTX_T *p); +EXTERN DRAM_STATUS_T DramcDQSOSCShuSettings(DRAMC_CTX_T *p); +EXTERN void DramcHwDQSOSC(DRAMC_CTX_T *p); +EXTERN void Enable_TX_Tracking(DRAMC_CTX_T *p, U32 u4DramcShuOffset); +#endif + +#if RDSEL_TRACKING_EN +EXTERN void Enable_RDSEL_Tracking(DRAMC_CTX_T *p, U32 u4DramcShuOffset); +EXTERN void RDSELRunTimeTracking_preset(DRAMC_CTX_T *p); +#endif +#ifdef HW_GATING +EXTERN void Enable_Gating_Tracking(DRAMC_CTX_T *p, U32 u4DramcShuOffset); +#endif +EXTERN void DramcImpedanceHWSaving(DRAMC_CTX_T *p); +EXTERN void DramcImpedanceTrackingEnable(DRAMC_CTX_T *p); +EXTERN void DramcRxInputDelayTrackingInit_Common(DRAMC_CTX_T *p); +EXTERN void DramcRxInputDelayTrackingHW(DRAMC_CTX_T *p); +EXTERN void DramcRxInputDelayTrackingInit_byFreq(DRAMC_CTX_T *p); + + +/* + **************************************************************************************** + ** dramc_utility.c + **************************************************************************************** + */ +EXTERN U16 gddrphyfmeter_value; +#if FOR_DV_SIMULATION_USED +EXTERN U8 u1BroadcastOnOff; +#endif +#if (fcFOR_CHIP_ID == fcA60868) +EXTERN U8 u1EnterRuntime; +#endif +EXTERN U8 u1MaType; +EXTERN void TA2_Test_Run_Time_HW_Set_Column_Num(DRAMC_CTX_T * p); +EXTERN void TA2_Test_Run_Time_HW_Presetting(DRAMC_CTX_T * p, U32 len, TA2_RKSEL_TYPE_T rksel_mode); +EXTERN void TA2_Test_Run_Time_Pat_Setting(DRAMC_CTX_T *p, U8 PatSwitch); +EXTERN void TA2_Test_Run_Time_HW_Write(DRAMC_CTX_T * p, U8 u1Enable); +EXTERN U32 TA2_Test_Run_Time_HW_Status(DRAMC_CTX_T * p); +EXTERN void TA2_Test_Run_Time_HW(DRAMC_CTX_T * p); +EXTERN void vAutoRefreshSwitch(DRAMC_CTX_T *p, U8 option); +EXTERN void vSetRank(DRAMC_CTX_T *p, U8 ucRank); +EXTERN void vSetPHY2ChannelMapping(DRAMC_CTX_T *p, U8 u1Channel); +EXTERN VREF_CALIBRATION_ENABLE_T Get_Vref_Calibration_OnOff(DRAMC_CTX_T *p); +EXTERN u8 lp5heff_save_disable(DRAMC_CTX_T *p); +EXTERN void lp5heff_restore(DRAMC_CTX_T *p); +EXTERN u8 is_lp5_family(DRAMC_CTX_T *p); +EXTERN U32 GetDramcBroadcast(void); +EXTERN void CKEFixOnOff(DRAMC_CTX_T *p, U8 u1RankIdx, CKE_FIX_OPTION option, + CKE_FIX_CHANNEL WriteChannelNUM); +EXTERN void DramcBackupRegisters(DRAMC_CTX_T *p, U32 *backup_addr, U32 backup_num); +EXTERN U8 u1GetRank(DRAMC_CTX_T *p); +EXTERN void vPrintCalibrationBasicInfo(DRAMC_CTX_T *p); +EXTERN void vPrintCalibrationBasicInfo_ForJV(DRAMC_CTX_T *p); +EXTERN U32 DramcEngine2Run(DRAMC_CTX_T *p, DRAM_TE_OP_T wr, U8 testaudpat); +EXTERN void DramcEngine2End(DRAMC_CTX_T *p); +EXTERN DRAM_STATUS_T DramcEngine2Init(DRAMC_CTX_T *p, U32 test2_1, U32 test2_2, U8 u1TestPat, U8 u1LoopCnt, U8 u1EnableUiShift); +EXTERN void DramcRestoreRegisters(DRAMC_CTX_T *p, U32 *restore_addr, U32 restore_num); +EXTERN DDR800_MODE_T vGet_DDR_Loop_Mode(DRAMC_CTX_T *p); +EXTERN u8 is_heff_mode(DRAMC_CTX_T *p); +EXTERN void DramcEngine2SetPat(DRAMC_CTX_T *p, U8 u1TestPat, U8 u1LoopCnt, U8 u1Len1Flag, U8 u1EnableUiShift); +EXTERN void DramcSetRankEngine2(DRAMC_CTX_T *p, U8 u1RankSel); +EXTERN U16 GetFreqBySel(DRAMC_CTX_T *p, DRAM_PLL_FREQ_SEL_T sel); +EXTERN U8 GetEyeScanEnable(DRAMC_CTX_T * p, U8 get_type); +EXTERN U8 vGetPHY2ChannelMapping(DRAMC_CTX_T *p); +EXTERN DUTY_CALIBRATION_T Get_Duty_Calibration_Mode(DRAMC_CTX_T *p); +EXTERN void DDRPhyFreqSel(DRAMC_CTX_T *p, DRAM_PLL_FREQ_SEL_T sel); +EXTERN DRAM_DFS_SRAM_SHU_T vGet_Current_ShuLevel(DRAMC_CTX_T *p); +EXTERN void vSetChannelNumber(DRAMC_CTX_T *p); +EXTERN void vSetRankNumber(DRAMC_CTX_T *p); +EXTERN void vSetFSPNumber(DRAMC_CTX_T *p); +EXTERN void vCKERankCtrl(DRAMC_CTX_T *p, CKE_CTRL_MODE_T CKECtrlMode); +EXTERN DRAM_PLL_FREQ_SEL_T vGet_PLL_FreqSel(DRAMC_CTX_T *p); +EXTERN void vSet_PLL_FreqSel(DRAMC_CTX_T *p, DRAM_PLL_FREQ_SEL_T sel); +EXTERN void Temp_TA2_Test_After_K(DRAMC_CTX_T * p); +EXTERN void DramcBroadcastOnOff(U32 bOnOff); +EXTERN DIV_MODE_T vGet_Div_Mode(DRAMC_CTX_T *p); +EXTERN void DramcMRWriteFldMsk(DRAMC_CTX_T *p, U8 mr_idx, U8 listValue, U8 msk, U8 UpdateMode); +EXTERN void DramcMRWriteFldAlign(DRAMC_CTX_T *p, U8 mr_idx, U8 value, U32 mr_fld, U8 UpdateMode); +EXTERN void DramcModeRegReadByRank(DRAMC_CTX_T *p, U8 u1Rank, U8 u1MRIdx, U16 *u2pValue); +EXTERN void DramcModeRegRead(DRAMC_CTX_T *p, U8 u1MRIdx, U16 *u1pValue); +EXTERN void DramcModeRegWriteByRank(DRAMC_CTX_T *p, U8 u1Rank, U8 u1MRIdx, U8 u1Value); +EXTERN void SetDramModeRegForWriteDBIOnOff(DRAMC_CTX_T *p, U8 u1fsp, U8 onoff); +EXTERN void SetDramModeRegForReadDBIOnOff(DRAMC_CTX_T *p, U8 u1fsp, U8 onoff); +#if MRW_CHECK_ONLY +EXTERN void vPrintFinalModeRegisterSetting(DRAMC_CTX_T *p); +#endif +#if MRW_BACKUP +EXTERN U8 DramcMRWriteBackup(DRAMC_CTX_T *p, U8 u1MRIdx, U8 u1Rank); +#endif +#if QT_GUI_Tool +EXTERN void TA2_Test_Run_Time_SW_Presetting(DRAMC_CTX_T *p, U32 test2_1, U32 test2_2, U8 testaudpat, U8 log2loopcount); +EXTERN U32 TestEngineCompare(DRAMC_CTX_T *p); +#endif +EXTERN void vSet_Div_Mode(DRAMC_CTX_T *p, DIV_MODE_T eMode); +EXTERN void vSet_Current_ShuLevel(DRAMC_CTX_T *p, DRAM_DFS_SRAM_SHU_T u1ShuIndex); +EXTERN void GetPhyPllFrequency(DRAMC_CTX_T *p); +EXTERN void DramcWriteDBIOnOff(DRAMC_CTX_T *p, U8 onoff); +EXTERN void DramcReadDBIOnOff(DRAMC_CTX_T *p, U8 onoff); +EXTERN void CheckDramcWBR(U32 u4address); +EXTERN void DramcModeRegWriteByRank_RTMRW(DRAMC_CTX_T *p, U8 *u1Rank, U8 *u1MRIdx, U8 *u1Value, U8 u1Len); +#if PRINT_CALIBRATION_SUMMARY +EXTERN void vPrintCalibrationResult(DRAMC_CTX_T *p); +#endif +EXTERN int dramc_complex_mem_test (unsigned int start, unsigned int len); +EXTERN U16 DDRPhyFMeter(void); +#ifdef DDR_INIT_TIME_PROFILING +void TimeProfileBegin(void); +UINT32 TimeProfileEnd(void); +#endif + + + +/* + **************************************************************************************** + ** Hal_IO.cpp + **************************************************************************************** + */ +#ifdef DUMP_INIT_RG_LOG_TO_DE +EXTERN U8 gDUMP_INIT_RG_LOG_TO_DE_RG_log_flag; +#endif + + + +/* + **************************************************************************************** + ** dramc_utility.cpp + **************************************************************************************** + */ +#if (QT_GUI_Tool == 1) +EXTERN MCK_TO_UI_SHIFT_T u1Lp5MCK2WCKUI_DivShift(DRAMC_CTX_T *p); +#endif + + +/* + **************************************************************************************** + ** dramc_debug.cpp + **************************************************************************************** + */ +extern void HQA_Log_Message_for_Report(DRAMC_CTX_T *p, U8 u1ChannelIdx, U8 u1RankIdx, U32 who_am_I, U8 *main_str, U8 *main_str2, U8 byte_bit_idx, S32 value1, U8 *ans_str); + + +/* + **************************************************************************************** + ** dramc_utility_QT.cpp + **************************************************************************************** + */ +#if (QT_GUI_Tool == 1) +EXTERN void QT_DRAMCTX_INIT(DRAMC_CTX_T *p); +EXTERN DRAM_STATUS_T DramcDDRPHYInit_FPGA_A60868(DRAMC_CTX_T *p); +EXTERN DRAM_STATUS_T DramcDDRPHYInit_LP5_FPGA_A60868(DRAMC_CTX_T *p); +EXTERN void TA2_Stress_Test(DRAMC_CTX_T *p); +EXTERN void TA2_Stress_Test_2(DRAMC_CTX_T *p); +EXTERN U32 QT_TestEngineCompare(DRAMC_CTX_T *p); +EXTERN void Write_Byte_Counter_Begin(DRAMC_CTX_T *p); +EXTERN U32 Write_Byte_Counter_End(DRAMC_CTX_T *p); +EXTERN void DDRPhyFMeter_Init(DRAMC_CTX_T *p); +EXTERN U32 DDRPhyFreqMeter(void); +#endif + + +/* + **************************************************************************************** + ** fake_engine.c + **************************************************************************************** + */ + + +/* + **************************************************************************************** + ** low_power_test.c + **************************************************************************************** + */ +EXTERN int global_which_test; +EXTERN void EnableDramcPhyDCMShuffle(DRAMC_CTX_T *p, bool bEn, U32 u4DramcShuOffset, U32 u4DDRPhyShuOffset); +EXTERN void Enter_Precharge_All(DRAMC_CTX_T *p); +EXTERN void EnableDramcPhyDCM(DRAMC_CTX_T *p, bool bEn); +EXTERN DRAM_STATUS_T CheckGoldenSetting(DRAMC_CTX_T *p); +EXTERN void Low_Power_Scenarios_Test(DRAMC_CTX_T *p); +#if ENABLE_DDR800_OPEN_LOOP_MODE_OPTION +void DDR800semiPowerSavingOn(DRAMC_CTX_T *p, U8 next_shu_level, U8 u1OnOff); +#endif + +#define LOW_POWER_SCENARIO_PRECHARGE_ALL 3 //idle(all bank refresh) +#define LOW_POWER_SCENARIO_S1 5 +#define LOW_POWER_SCENARIO_S0 6 +#define LOW_POWER_SCENARIO_PASR 7 +#define LOW_POWER_SCENARIO_ALL 8 +#define LOW_POWER_SCENARIO_FAKE_ENGINE_READ 9 +#define LOW_POWER_SCENARIO_FAKE_ENGINE_WRITE 10 +#define LOW_POWER_SCENARIO_ONLY_SELF_REFRESH 12 +#define LOW_POWER_SCENARIO_HW_AUTO_SAVE_S0 13 +#define LOW_POWER_SCENARIO_HW_AUTO_SAVE_S0_METHOD_2 14 +#define LOW_POWER_SCENARIO_PASR_1BANK 15 +#define LOW_POWER_SCENARIO_PASR_2BANK 16 +#define LOW_POWER_SCENARIO_PASR_4BANK 17 +#define LOW_POWER_SCENARIO_PASR_8BANK 18 +#define LOW_POWER_SCENARIO_FAKE_ENGINE_BW 19 +#define LOW_POWER_SCENARIO_FAKE_ENGINE_READ_WRITE 21 +#define AUTO_REFRESH_RESERVE_TEST 22 +/* + **************************************************************************************** + ** low_power_test.c + **************************************************************************************** + */ +EXTERN U8 u1StopMiniStress; +EXTERN void Ett_Mini_Strss_Test(DRAMC_CTX_T *p); + + +/* + **************************************************************************************** + ** LP4_dram_init.c + **************************************************************************************** + */ +EXTERN void CKE_FIX_ON(DRAMC_CTX_T *p, U8 EN, U8 rank); +EXTERN void LP4_UpdateInitialSettings(DRAMC_CTX_T *p); +EXTERN void LP4_DRAM_INIT(DRAMC_CTX_T *p); + + +/* + **************************************************************************************** + ** LP5_dram_init.c + **************************************************************************************** + */ +EXTERN void LP5_UpdateInitialSettings(DRAMC_CTX_T *p); +EXTERN void LP5_DRAM_INIT(DRAMC_CTX_T *p); + + +/* + **************************************************************************************** + ** system_init.c + **************************************************************************************** + */ +#if (fcFOR_CHIP_ID == fcA60868) +EXTERN void syspll_init(DRAMC_CTX_T *p); +#endif + + +/* + **************************************************************************************** + ** dramc_utility_QT.cpp + **************************************************************************************** + */ +#if (QT_GUI_Tool == 1) +EXTERN U8 ucDramRegRead_1(U32 reg_addr, U32 *reg_data); +EXTERN U8 ucDramRegWrite_1(U32 reg_addr, U32 reg_data); +#endif + + +/* + **************************************************************************************** + ** svsim_dummy.c + **************************************************************************************** + */ +#if (FOR_DV_SIMULATION_USED == 0) +#define delay_us(x) +#define delay_ns(x) +#define mysetscope() +#define broadcast_on() +#define broadcast_off() +#define timestamp_show() +#define build_api_initial() +#define conf_to_sram_sudo(...) +#endif + +/* + **************************************************************************************** + ** RS232.cpp + **************************************************************************************** + */ +#if (QT_GUI_Tool == 1) +EXTERN U8 ucDramSetReg_1(U32 address, U32 *data, U16 count); +EXTERN U8 ucDramGetReg_1(U32 address, U32 *data, U16 count); +#endif + + +/* + **************************************************************************************** + ** ett_test.c + **************************************************************************************** + */ +extern int hqa_vmddr_voltage, hqa_vmddr_class; + + +#endif //_INT_GLOBAL_H diff --git a/src/vendorcode/mediatek/mt8192/include/dramc_int_slt.h b/src/vendorcode/mediatek/mt8192/include/dramc_int_slt.h new file mode 100644 index 000000000000..356c8176c7da --- /dev/null +++ b/src/vendorcode/mediatek/mt8192/include/dramc_int_slt.h @@ -0,0 +1,106 @@ +/* SPDX-License-Identifier: BSD-3-Clause */ + +#ifndef _INT_SLT_H +#define _INT_SLT_H + + +//======================== EMI LPBK TEST Definition ===================================== + +#if defined(SLT) +#define ENABLE_EMI_LPBK_TEST 1 +#else +#define ENABLE_EMI_LPBK_TEST 0 +#endif + +#define EMI_LPBK_DRAM_USED !ENABLE_EMI_LPBK_TEST // 0: EMI LPBK test, 1: normal K, dram used + +#define EMI_LPBK_USE_THROUGH_IO 0 //test through IO +#define EMI_INT_LPBK_WL_DQS_RINGCNT 0 //DQS Ring cnt: through io @ 800,1600,2400,3200, emi intlpbk wo rx/tx K window +#define EMI_LPBK_ADDRESS_DEFECT 0 //test address defect, MUST use CPU WRITE mode + +#if ENABLE_EMI_LPBK_TEST +#define EMI_USE_TA2 0 // 0:CPU write, 1:TA2, DVsim/Dsim use TA2, but 1:4 mode must use cpu write(because TA2 not support 1:4 mode) +#else +#define EMI_USE_TA2 0 +#endif + +/**************************** +Summary: +1W1R: address offset : 0, 4, 8, c (1:8 mode only), no support 1:4 mode +8W1R: address offset 0x0 ~ 0xC (8W1R), 0x10 ~ 0x1C, (10W1R) (1:8 & 1:4 mode) +****************************/ +#define EMI_LPBK_1W1R 0 //CPU mode 0:8W1R, 1:1W1R + +#define EMI_LPBK_S1 0 + +#define FREQ_METER 1 +#define DQSG_COUNTER 1 + + +#define ADJUST_TXDLY_SCAN_RX_WIN 0 + +#define EMI_LPBK_K_TX 0 +#define ENABLE_PRE_POSTAMBLE !EMI_USE_TA2 //0: no pre/post-amble for TA2, 1: need pre/post-amble for cpu write + + +#define EMI_LPBK_DFS_32 0 //DFS 32<->32<->32 +#define EMI_LPBK_DFS_24 0 //DFS 24<->24<->24 +#define EMI_LPBK_DFS_16 0 //DFS 16<->16<->16 +#define EMI_LPBK_USE_LP3_PINMUX 0 +#define EMI_LPBK_8W1R 1 +#if EMI_LPBK_1W1R +#undef EMI_LPBK_8W1R +#define EMI_LPBK_8W1R 0 +#endif + +#if EMI_LPBK_USE_THROUGH_IO +#define EMI_LPBK_USE_DDR_800 1 +#else +#define EMI_LPBK_USE_DDR_800 0 +#endif +//#define K_TX_DQS_DLY 0 + +#define LP4_4266_freq_meter 533 // //shu0 533 +#define LP4_3733_freq_meter 464 // //shu0 464 +#define LP4_3200_freq_meter 386 // //shu8 386 //shu9 386 +#define LP4_2400_freq_meter 299 //shu6 299 shu5 299 +#define LP4_1600_freq_meter 191 //199 //shu4 383 shu3 191 +#define LP4_1200_freq_meter 299 //shu2 299 shu1 299 +#define LP4_800_freq_meter 199 //shu7 199 + + +#if ENABLE_EMI_LPBK_TEST //EMI_LPBK_DRAM_USED==0 +/* +#define SLT +#undef ENABLE_TMRRI_NEW_MODE +#define ENABLE_TMRRI_NEW_MODE 0 +#undef ENABLE_DUTY_SCAN_V2 +#define ENABLE_DUTY_SCAN_V2 0 +#undef ENABLE_RODT_TRACKING +#define ENABLE_RODT_TRACKING 0 +#undef TX_K_DQM_WITH_WDBI +#define TX_K_DQM_WITH_WDBI 0 +#undef ENABLE_WRITE_DBI +#define ENABLE_WRITE_DBI 0 +*/ + +#if EMI_INT_LPBK_WL_DQS_RINGCNT +#undef EMI_LPBK_USE_THROUGH_IO +#define EMI_LPBK_USE_THROUGH_IO 1 +#undef EMI_LPBK_USE_DDR_800 +#define EMI_LPBK_USE_DDR_800 0 +#endif + +#endif +//#if (EMI_LPBK_DRAM_USED) +//#undef ENABLE_MIOCK_JMETER +//#define ENABLE_MIOCK_JMETER // for TX_PER_BIT_DELAY_CELL +//#endif + + +//============================================================================= + + + + +#endif //_INT_GLOBAL_H diff --git a/src/vendorcode/mediatek/mt8192/include/dramc_pi_api.h b/src/vendorcode/mediatek/mt8192/include/dramc_pi_api.h new file mode 100644 index 000000000000..af6986b6c627 --- /dev/null +++ b/src/vendorcode/mediatek/mt8192/include/dramc_pi_api.h @@ -0,0 +1,1482 @@ +/* SPDX-License-Identifier: BSD-3-Clause */ + +#ifndef _PI_API_H +#define _PI_API_H + +#ifndef __ETT__ +#define __ETT__ 0 +#endif + +#define __FLASH_TOOL_DA__ 0 +#define CFG_DRAM_LOG_TO_STORAGE 0 + +#define FORCE_FASTK + +/***********************************************************************/ +/* Includes */ +/***********************************************************************/ + +/***********************************************************************/ +/* Constant Define */ +/***********************************************************************/ + +#define SW_CHANGE_FOR_SIMULATION 0 //calibration funciton for whole chip simulation. Code changed due to different compiler +#ifndef FOR_DV_SIMULATION_USED +#define FOR_DV_SIMULATION_USED (FALSE) ////calibration funciton for DV simulation. Code changed due to different compiler#define FT_DSIM_USED 0 +#endif +#define DV_SIMULATION_LP4 1 +#define BYPASS_CALIBRATION 0 +//Bring Up Selection : Do Not open it when normal operation +//#define SLT +//#define FIRST_BRING_UP +//#define DUMP_INIT_RG_LOG_TO_DE //dump init RG settings to DE + +#include "dramc_typedefs.h" +#include "dramc_reg_base_addr.h" +#include <soc/addressmap.h> +#include <soc/dramc_soc.h> +#include <soc/dramc_param.h> + +#define CPU_RW_TEST_AFTER_K 0 +#define TA2_RW_TEST_AFTER_K 0 + +#define ENABLE (1) +#define DISABLE (0) +#define ON (1) +#define OFF (0) +#define AUTOK_ON (1) +#define AUTOK_OFF (0) +#define DCM_ON (1) +#define DCM_OFF (0) + + +//Read Chip QT Tool +#ifndef QT_GUI_Tool +#define QT_GUI_Tool 0 //Setting 1 when using QT GUI Tool Compiler. +#define HAPS_FPFG_A60868 0 //Setting 1 when testing HAPS FPGA +#endif + +//DRAMC Chip +#define fcA60868 1 +#define fcPetrus 2 +#define fcIPM 3 +#define fcMargaux 4 +#define fcFOR_CHIP_ID fcMargaux + +#define __A60868_TO_BE_PORTING__ 0 +#define __Petrus_TO_BE_PORTING__ 0 + +#define VENDOR_SAMSUNG 1 +#define VENDOR_HYNIX 6 +#define REVISION_ID_MAGIC 0x9501 + + +#define __LP5_COMBO__ (FALSE) +#define FEATURE_RDDQC_K_DMI (FALSE) // This feature is not supported at A60868 test chip + + +#if __ETT__ +#define __FLASH_TOOL_DA__ 0 +#endif + +#if (FEATURE_RDDQC_K_DMI == TRUE) + #define RDDQC_ADD_DMI_NUM 2 +#else + #define RDDQC_ADD_DMI_NUM 0 +#endif + +#define CHANNEL_NUM 2 // single chhanel for A60868. 1 single channel, 2 dual channel, 4 channel +#define DPM_CH_NUM 2 // CH0/1 is Master, CH2/3 is Slave + +//ZQ calibration +#define ENABLE_LP4_ZQ_CAL 1 +#if ENABLE_LP4_ZQ_CAL //choose one mode to do ZQ calibration +#define ZQ_SWCMD_MODE 1 //suggested SW CMD mode +#define ZQ_RTSWCMD_MODE 0 //run time SW mode +#define ZQ_SCSM_MODE 0 //old mode +#endif + +#define CALIBRATION_SPEED_UP_DEBUG 0 +#define VENDER_JV_LOG 0 + +//SW option +#define DUAL_FREQ_K 0 //If enable, need to define DDR_xxxx the same as DUAL_FREQ_HIGH +#define ENABLE_EYESCAN_GRAPH 0 //__ETT__ //draw eye diagram after calibration, if enable, need to fix code size problem. +#define EYESCAN_GRAPH_CATX_VREF_STEP 1 // 1 (origin), 2 (div 2)(save 9K size), 5 for A60868 +#define EYESCAN_GRAPH_RX_VREF_STEP 2 +#define EYESCAN_RX_VREF_RANGE_END 128 //field is 6 bit, but can only use 0~63,7bit ->127 +#if (fcFOR_CHIP_ID == fcA60868) +#define ENABLE_EYESCAN_CBT 0 //TO DO:Forece to draw CBT eye diagram after calibration +#define ENABLE_EYESCAN_RX 0 //TO DO:Forece to draw RX eye diagram after calibration +#define ENABLE_EYESCAN_TX 0 //TO DO:Forece to draw TX eye diagram after calibration +#define ENABLE_VREFSCAN 0 //TO DO:Forece to Vref Scan for calibration +#endif + +#define CHECK_HQA_CRITERIA 0 +#define REDUCE_LOG_FOR_PRELOADER 1 +#define APPLY_LP4_POWER_INIT_SEQUENCE 1 +#define ENABLE_READ_DBI 0 +#define ENABLE_WRITE_DBI 1 +#define ENABLE_WRITE_DBI_Protect 0 +#define ENABLE_TX_WDQS 1 +#define ENABLE_WDQS_MODE_2 0 +#define ENABLE_DRS 0 +#define ENABLE_TX_TRACKING 1 +#define ENABLE_K_WITH_WORST_SI_UI_SHIFT 1 +#define ETT_MINI_STRESS_USE_TA2_LOOP_MODE 1 +#define DUMP_TA2_WINDOW_SIZE_RX_TX 0 +#if ENABLE_TX_TRACKING + #define ENABLE_SW_TX_TRACKING 0 //if SW_TX_TRACKING is 0, using HW_TX_TRACKING +#endif +#define ENABLE_PA_IMPRO_FOR_TX_TRACKING 1 +#define ENABLE_WRITE_POST_AMBLE_1_POINT_5_TCK 1 +#define ENABLE_RX_TRACKING 0 +#define ENABLE_RX_DCM_DPHY 1 //Set 0 will lead DCM on/off error +#define ENABLE_OPEN_LOOP_MODE_OPTION 1 +#define ENABLE_TMRRI_NEW_MODE 1 +#define ENABLE_8PHASE_CALIBRATION 1 +#define ENABLE_DUTY_SCAN_V2 1 +#define DUTY_SCAN_V2_ONLY_K_HIGHEST_FREQ 0 //0: K all Freq 1: K highest Freq +#define APPLY_DQDQM_DUTY_CALIBRATION 1 +#define IMPEDANCE_TRACKING_ENABLE //Impendence tracking +#define IMPEDANCE_HW_SAVING //mask because function fail, it lets clk swing change larger before DVFS occurs +#define ENABLE_MIOCK_JMETER +#define ENABLE_RUNTIME_MRW_FOR_LP5 1 +#define ENABLE_RODT_TRACKING 1 +#define GATING_ADJUST_TXDLY_FOR_TRACKING 1 +#define TDQSCK_PRECALCULATION_FOR_DVFS 1 +#define HW_GATING +#define ENABLE_RX_FIFO_MISMATCH_DEBUG 1 +#define VERIFY_CKE_PWR_DOWN_FLOW 0 //Lewis add for DVT +#define CBT_MOVE_CA_INSTEAD_OF_CLK 1 // need to check on LP5 +#define MRW_CHECK_ONLY 0 +#define MRW_BACKUP 0 +#define ENABLE_SAMSUNG_NT_ODT 0 +#define DRAMC_MODEREG_CHECK 0 +#define DVT_READ_LATENCY_MONITOR 0 + +#define PINMUX_AUTO_TEST_PER_BIT_CA 0 +#define PINMUX_AUTO_TEST_PER_BIT_RX 0 +#define PINMUX_AUTO_TEST_PER_BIT_TX 0 + +#define CA_PER_BIT_DELAY_CELL 1//LP4 +#if PINMUX_AUTO_TEST_PER_BIT_CA +#undef CA_PER_BIT_DELAY_CELL +#define CA_PER_BIT_DELAY_CELL 0 +#endif + +//Gating calibration +#define GATING_LEADLAG_LOW_LEVEL_CHECK 0 + +//#define ENABLE_POST_PACKAGE_REPAIR + +#define DPM_CONTROL_AFTERK +#if __ETT__ +#define ENABLE_DBG_2_0_IRQ +#endif + +//////////////////////////////////// FIXME start ///////////////////////// +#define CMD_CKE_WORKAROUND_FIX 0 +#define DQS_DUTY_SLT_CONDITION_TEST 0 +#define DV_SIMULATION_BEFORE_K 0 +#define DV_SIMULATION_DATLAT 0 +#define DV_SIMULATION_DBI_ON 0 +#define DV_SIMULATION_DFS 0 +#define DV_SIMULATION_GATING 0 +#define ENABLE_APB_MASK_WRITE 0 +#define ENABLE_DVFS_BYPASS_MR13_FSP 0 +#define ENABLE_RODT_TRACKING_SAVE_MCK 0 +#define ETT_NO_DRAM 0 +#define EYESCAN_LOG 0 +#define FSP1_CLKCA_TERM 1 +#define MR_CBT_SWITCH_FREQ !FOR_DV_SIMULATION_USED //@Darren, Wait DFS ready +#define FT_DSIM_USED 0 +#define GATING_ONLY_FOR_DEBUG 0 +#define MEASURE_DRAM_POWER_INDEX 0 +#define PA_IMPROVEMENT_FOR_DRAMC_ACTIVE_POWER 0 +#define REG_ACCESS_PORTING_DGB 0 +#define RX_PIPE_BYPASS_ENABLE 0 +#define SAMSUNG_TEST_MODE_MRS_FOR_PRELOADER 0 +#define SUPPORT_PICG_MONITOR 0 +#define SUPPORT_REQ_QUEUE_BLOCK_ALE 0 +#define SUPPORT_REQ_QUEUE_READ_LATERNCY_MONITOR 0 +#define REFRESH_OVERHEAD_REDUCTION 1 +#define TEST_LOW_POWER_WITH_1_SEC_DELAY 1 //Add 1 second dealy between suspend and resume to avoid APHY control PATH is not switched to SPM {SPM_CONTROL_AFTERK} +#define TEST_LOW_POWER_WITH_STRESS 0 +#if TEST_LOW_POWER_WITH_STRESS + #undef TEST_LOW_POWER_WITH_1_SEC_DELAY + #define TEST_LOW_POWER_WITH_1_SEC_DELAY 0 +#endif +#define XRTRTR_NEW_CROSS_RK_MODE 1 +#define XRTWTW_NEW_CROSS_RK_MODE 1 +#define APPLY_SIGNAL_WAVEFORM_SETTINGS_ADJUST 0 +#define SUPPORT_HYNIX_RX_DQS_WEAK_PULL 0 +#define RX_DLY_TRACK_ONLY_FOR_DEBUG 0 +//Run time config +#define TEMP_SENSOR_ENABLE // Enable rumtime HMR4 +#define ENABLE_REFRESH_RATE_DEBOUNCE 1 +#define ENABLE_PER_BANK_REFRESH 1 +#define PER_BANK_REFRESH_USE_MODE 1 // 0: original mode, 1: hybrid mode, 2: always pb mode +#define IMP_TRACKING_PB_TO_AB_REFRESH_WA 1 +#define DRAMC_MODIFIED_REFRESH_MODE 1 +#define DRAMC_CKE_DEBOUNCE 1 +#define XRTR2R_PERFORM_ENHANCE_DQSG_RX_DLY + +#define SAMSUNG_LP4_NWR_WORKAROUND 0 +#define AC_TIMING_DERATE_ENABLE 1 +#define ENABLE_EARLY_BG_CMD 0 // 0: Disable 1: Enable, Reduce the CMD latency by CTO_EBG request + +//////////////////////////////////// DVFS ////////////////////////////// +#define ENABLE_DVS 1 //DVS need tracking enable +#define DRAMC_DFS_MODE 1 // 0:Legacy, 1:MD32 RG, 2: PHY RG +#define ENABLE_SRAM_DMA_WA 0 // for Pexxxs/Maxxxx/xxx868 +#define ENABLE_ECO_SRAM_DMA_MISS_REG 1 // for Maxxxx +#define ENABLE_TX_REBASE_ODT_WA 0 // for Pexxxs/xxx868 +#if ENABLE_TX_WDQS +#define ENABLE_TX_REBASE_WDQS_DQS_PI_WA 0 +#endif +#define ENABLE_DFS_DEBUG_MODE 0 +#define DFS_NOQUEUE_FLUSH_WA 1 +#define DFS_NOQUEUE_FLUSH_LATENCY_CNT 0 +#define ENABLE_DFS_NOQUEUE_FLUSH_DBG 0 +#define ENABLE_CONFIG_MCK_4TO1_MUX 0 +#define ENABLE_TPBR2PBR_REFRESH_TIMING 1 +#define ENABLE_DFS_TIMING_ENLARGE 0 +#define ENABLE_DFS_208M_CLOCK 0 +#define ENABLE_DFS_HW_SAVE_MASK 0 +#define ENABLE_LP4Y_DFS 0 +#if ENABLE_LP4Y_DFS +#define ENABLE_LP4Y_WA 1 +#define ENABLE_DFS_RUNTIME_MRW 1 +#else +#define ENABLE_LP4Y_WA 0 +#define ENABLE_DFS_RUNTIME_MRW 0 // for LP4x +#endif +#define ENABLE_TIMING_TXSR_DFS_WA REFRESH_OVERHEAD_REDUCTION // Wait overhead refresh enable, @Darren, Entry SREF -> EXIT SREF -> PDE Command violates tXSR time +#define ENABLE_RANK_NUMBER_AUTO_DETECTION 0 +#define DDR_HW_AUTOK_POLLING_CNT 100000 + +//////////////////////////////////// FIXME end///////////////////////// + +#if (fcFOR_CHIP_ID == fcA60868) +#define WORKAROUND_LP5_HEFF 1 //High efficiency mode +#undef ENABLE_RUNTIME_MRW_FOR_LP5 +#define ENABLE_RUNTIME_MRW_FOR_LP5 0 // DV fail in 868, use RTSWCMD_MRW +#endif + +#if ENABLE_RODT_TRACKING +#define GATING_RODT_LATANCY_EN 0 +#else +#define GATING_RODT_LATANCY_EN 1 +#endif + +#define CHECK_GOLDEN_SETTING (FALSE) +#define APPLY_LOWPOWER_GOLDEN_SETTINGS 1 // 0: DCM Off, 1: DCM On +#define LP5_GOLDEN_SETTING_CHECKER (FALSE) // FALSE: enable LP4 checker + +#if APPLY_LOWPOWER_GOLDEN_SETTINGS +#define TX_PICG_NEW_MODE 1 +#define RX_PICG_NEW_MODE 1 +#else +#define TX_PICG_NEW_MODE 0 +#define RX_PICG_NEW_MODE 0 +#endif +#define CMD_PICG_NEW_MODE 0 + +#define DDR_RESERVE_NEW_MODE 1 //0: old mode 1: new mode +//============================================================================= +// for D Sim sumulation used +//============================================================================= +#if QT_GUI_Tool || !FOR_DV_SIMULATION_USED +#define DV_SIMULATION_INIT_C 1 +#define SIMULATION_LP4_ZQ 1 +#define SIMULATION_SW_IMPED 1 +#define SIMULATION_MIOCK_JMETER 0 +#define SIMULATION_8PHASE 0 +#define SIMULATION_RX_INPUT_BUF 0 +#define SIMUILATION_CBT 1 +#define SIMULATION_WRITE_LEVELING 1 +#define SIMULATION_DUTY_CYC_MONITOR 0 +#define SIMULATION_GATING 1 +#define SIMULATION_DATLAT 1 +#define SIMULATION_RX_RDDQC 1 +#define SIMULATION_RX_PERBIT 1 +#define SIMULATION_TX_PERBIT 1 // Please enable with write leveling +#define SIMULATION_RX_DVS 0 +#define SIMULATION_RUNTIME_CONFIG 0 +#else +#define DV_SIMULATION_INIT_C 1 +#define SIMULATION_LP4_ZQ 1 +#define SIMULATION_SW_IMPED 1 +#define SIMULATION_MIOCK_JMETER 0 +#define SIMULATION_8PHASE 0 +#define SIMULATION_RX_INPUT_BUF 0 +#define SIMUILATION_CBT 1 +#define SIMULATION_WRITE_LEVELING 1 +#define SIMULATION_DUTY_CYC_MONITOR 0 +#define SIMULATION_GATING 1 +#define SIMULATION_DATLAT 1 +#define SIMULATION_RX_RDDQC 1 +#define SIMULATION_RX_PERBIT 1 +#define SIMULATION_TX_PERBIT 1 // Please enable with write leveling +#define SIMULATION_RX_DVS 0 +#define SIMULATION_RUNTIME_CONFIG 1 // @Darren for DV sim +#endif +//Used to keep original VREF when doing Rx calibration for RX DVS +#define DVS_CAL_KEEP_VREF 0xf + +//#define DDR_INIT_TIME_PROFILING +#define DDR_INIT_TIME_PROFILING_TEST_CNT 1 +#ifdef DDR_INIT_TIME_PROFILING +extern U16 u2TimeProfileCnt; +#endif + +//============================================================================= +// common +#define DQS_NUMBER 4 +#define DQ_DATA_WIDTH 32 // define max support bus width in the system (to allocate array size) +#define TIME_OUT_CNT 100 //100us +#define HW_REG_SHUFFLE_MAX 4 + +typedef enum +{ + BYTE_0 = 0, + BYTE_1 = 1, + ALL_BYTES +} BYTES_T; + +//Should be removed after A60868 +#define LP5_DDR4266_RDBI_WORKAROUND 0 +#define CBT_O1_PINMUX_WORKAROUND 0 +#define WLEV_O1_PINMUX_WORKAROUND 0 +#define WCK_LEVELING_FM_WORKAROUND 0 + + +/* Gating window */ +#define DQS_GW_COARSE_STEP 1 +#define DQS_GW_FINE_START 0 +#define DQS_GW_FINE_END 32 +#define DQS_GW_FINE_STEP 4 + +#define DQS_GW_UI_PER_MCK 16 +#define DQS_GW_PI_PER_UI 32 + +// DATLAT +#define DATLAT_TAP_NUMBER 32 + +// RX DQ/DQS +#define MAX_RX_DQSDLY_TAPS 508 // 0x018, May set back to 64 if no need. +#define MAX_RX_DQDLY_TAPS 252 +#define RX_VREF_NOT_SPECIFY 0xff +#define RX_VREF_DUAL_RANK_K_FREQ 1866 // if freq >=RX_VREF_DUAL_RANK_K_FREQ, Rank1 rx vref K will be enable. +#define RX_VREF_RANGE_BEGIN 0 +#define RX_VREF_RANGE_BEGIN_ODT_OFF 32 +#define RX_VREF_RANGE_BEGIN_ODT_ON 24 +#define RX_VREF_RANGE_END 128 //field is 6 bit, but can only use 0~63 +#define RX_VREF_RANGE_STEP 1 +#define RX_PASS_WIN_CRITERIA 30 +#define RDDQC_PINMUX_WORKAROUND 1 + +// TX DQ/DQS +#define TX_AUTO_K_ENABLE 1 +#if TX_AUTO_K_ENABLE +#define TX_AUTO_K_DEBUG_ENABLE 0 +#define TX_AUTO_K_WORKAROUND 1 +#define ENABLE_PA_IMPRO_FOR_TX_AUTOK 1 +#endif +#define MAX_TX_DQDLY_TAPS 31 // max DQ TAP number +#define MAX_TX_DQSDLY_TAPS 31 // max DQS TAP number +#define TX_OE_EXTEND 0 +#define TX_DQ_OE_SHIFT_LP5 5 +#if TX_OE_EXTEND +#define TX_DQ_OE_SHIFT_LP4 4 +#else +#define TX_DQ_OE_SHIFT_LP4 3 +#endif +#define TX_DQ_OE_SHIFT_LP3 2 +#define TX_K_DQM_WITH_WDBI 1 +#define TX_OE_CALIBATION (!TX_OE_EXTEND) + +#define TX_RETRY_ENABLE 0 +#if TX_RETRY_ENABLE +#define TX_RETRY_CONTROL_BY_SPM 1 +#define SW_TX_RETRY_ENABLE 0 +#else +#define TX_RETRY_CONTROL_BY_SPM 0 +#endif + +// Sw work around options. +#define CA_TRAIN_RESULT_DO_NOT_MOVE_CLK 1 // work around for clock multi phase problem(cannot move clk or the clk will be bad) +#define DramcHWDQSGatingTracking_JADE_TRACKING_MODE 1 +#define DramcHWDQSGatingTracking_FIFO_MODE 1 +#define DONT_MOVE_CLK_DELAY // don't move clk delay +/* If defined for gFreqTbl and fastK + */ +#define LP4_SHU0_FREQ (1866) +#define LP4_SHU8_FREQ (1600) +#define LP4_SHU9_FREQ (1600) +#define LP4_SHU6_FREQ (1200) +#define LP4_SHU5_FREQ (1200) +#define LP4_SHU4_FREQ (800) +#define LP4_SHU3_FREQ (800) +#define LP4_SHU2_FREQ (600) +#define LP4_SHU1_FREQ (600) +#define LP4_SHU7_FREQ (400) +#define LP4_HIGHEST_FREQ LP4_SHU0_FREQ + +#define LP4_SHU0_FREQSEL (LP4_DDR3733) +#define LP4_SHU8_FREQSEL (LP4_DDR3200) +#define LP4_SHU9_FREQSEL (LP4_DDR3200) +#define LP4_SHU6_FREQSEL (LP4_DDR2400) +#define LP4_SHU5_FREQSEL (LP4_DDR2400) +#define LP4_SHU4_FREQSEL (LP4_DDR1600) +#define LP4_SHU3_FREQSEL (LP4_DDR1600) +#define LP4_SHU2_FREQSEL (LP4_DDR1200) +#define LP4_SHU1_FREQSEL (LP4_DDR1200) +#define LP4_SHU7_FREQSEL (LP4_DDR800) + +#if FOR_DV_SIMULATION_USED +#define DEFAULT_TEST2_1_CAL 0x55000000 // pattern0 and base address for test engine when we do calibration +#define DEFAULT_TEST2_2_CAL 0xaa000020 // pattern1 and offset address for test engine when we do calibraion +#else +#define DEFAULT_TEST2_1_CAL 0x55000000 // pattern0 and base address for test engine when we do calibration +#define DEFAULT_TEST2_2_CAL 0xaa000100 // pattern1 and offset address for test engine when we do calibraion +#endif + +//CBT/CA training +#define CATRAINING_NUM_LP4 6 +#define CATRAINING_NUM_LP5 7 +#define CATRAINING_NUM CATRAINING_NUM_LP5 +#define LP4_MRFSP_TERM_FREQ 1333 +#define LP5_MRFSP_TERM_FREQ 1866 + +//Calibration Summary +#define PRINT_CALIBRATION_SUMMARY (!SW_CHANGE_FOR_SIMULATION) +#define PRINT_CALIBRATION_SUMMARY_DETAIL 1 +#define PRINT_CALIBRATION_SUMMARY_FASTK_CHECK 0 + +#if 1 //(FOR_DV_SIMULATION_USED==0) +#define ETT_PRINT_FORMAT // Apply for both preloader and ETT +#endif + +//#define FOR_HQA_TEST_USED // HQA test used, to print result for easy report +//#define FOR_HQA_REPORT_USED +//Run Time Config +//#define DUMMY_READ_FOR_TRACKING +#define ZQCS_ENABLE_LP4 +#ifndef ZQCS_ENABLE_LP4 +#define ENABLE_SW_RUN_TIME_ZQ_WA +#endif + +//============================ For Future DVT Definition ================================= + +#define ENABLE_DVFS_CDC_SYNCHRONIZER_OPTION 1 +#define ENABLE_BLOCK_APHY_CLOCK_DFS_OPTION 1 +#define ENABLE_REMOVE_MCK8X_UNCERT_LOWPOWER_OPTION 1 +#define ENABLE_REMOVE_MCK8X_UNCERT_DFS_OPTION 1 +#define RDSEL_TRACKING_EN 0 // @Darren, for SHU0 only (DDR3733 or DDR4266) +#define ENABLE_DFS_SSC_WA 0 +#define ENABLE_DDR800_OPEN_LOOP_MODE_OPTION 1 + +//============================================================================= +//#define DDR_BASE 0x40000000ULL //for DV sim and ett_test.c +/***********************************************************************/ +/* Defines */ +/***********************************************************************/ +#define CBT_LOW_FREQ 0 +#define CBT_HIGH_FREQ 1 +#define CBT_UNKNOWN_FREQ 0xFF + + +#if !__ETT__ +// Preloader: using config CFG_DRAM_CALIB_OPTIMIZATION to identify +#if (FOR_DV_SIMULATION_USED==0) && !defined(SLT) +// Preloader: using config CFG_DRAM_CALIB_OPTIMIZATION to identify +#define SUPPORT_SAVE_TIME_FOR_CALIBRATION 1 + +#if defined(FORCE_FASTK) && !SUPPORT_SAVE_TIME_FOR_CALIBRATION +#error "FORCE_FASTK needs enable SUPPORT_SAVE_TIME_FOR_CALIBRATION!" +#endif + +#else +// DV simulation, use full calibration flow +#define SUPPORT_SAVE_TIME_FOR_CALIBRATION 0 +#endif +#define EMMC_READY 1 +#define BYPASS_VREF_CAL (SUPPORT_SAVE_TIME_FOR_CALIBRATION & EMMC_READY) +#define BYPASS_CBT (SUPPORT_SAVE_TIME_FOR_CALIBRATION & EMMC_READY) +#define BYPASS_DATLAT (SUPPORT_SAVE_TIME_FOR_CALIBRATION & EMMC_READY) +#define BYPASS_WRITELEVELING (SUPPORT_SAVE_TIME_FOR_CALIBRATION & EMMC_READY) +#define BYPASS_RDDQC (SUPPORT_SAVE_TIME_FOR_CALIBRATION & EMMC_READY) +#define BYPASS_RXWINDOW (SUPPORT_SAVE_TIME_FOR_CALIBRATION & EMMC_READY) +#define BYPASS_TXWINDOW (SUPPORT_SAVE_TIME_FOR_CALIBRATION & EMMC_READY) +#define BYPASS_TXOE (SUPPORT_SAVE_TIME_FOR_CALIBRATION & EMMC_READY) +#define BYPASS_GatingCal (SUPPORT_SAVE_TIME_FOR_CALIBRATION & EMMC_READY) +#define BYPASS_CA_PER_BIT_DELAY_CELL (SUPPORT_SAVE_TIME_FOR_CALIBRATION & EMMC_READY) +//#define BYPASS_TX_PER_BIT_DELAY_CELL (SUPPORT_SAVE_TIME_FOR_CALIBRATION & EMMC_READY) +#else +// ETT +#define SUPPORT_SAVE_TIME_FOR_CALIBRATION 0 +#define EMMC_READY 0 +#define BYPASS_VREF_CAL 1 +#define BYPASS_CBT 1 +#define BYPASS_DATLAT 1 +#define BYPASS_WRITELEVELING 1 +#define BYPASS_RDDQC 1 +#define BYPASS_RXWINDOW 1 +#define BYPASS_TXWINDOW 1 +#define BYPASS_TXOE 1 +#define BYPASS_GatingCal 1 +#define BYPASS_CA_PER_BIT_DELAY_CELL CA_PER_BIT_DELAY_CELL +//#define BYPASS_TX_PER_BIT_DELAY_CELL 0 +#endif + +#define ENABLE_PINMUX_FOR_RANK_SWAP 0 + +//======================== FIRST_BRING_UP Init Definition ===================== +#ifdef FIRST_BRING_UP + +//#define USE_CLK26M + +#undef TDQSCK_PRECALCULATION_FOR_DVFS +#define TDQSCK_PRECALCULATION_FOR_DVFS 0//DQS pre-calculation + +#undef CHANNEL_NUM +#define CHANNEL_NUM 2 + +#undef ENABLE_DUTY_SCAN_V2 +#define ENABLE_DUTY_SCAN_V2 0 + +#undef ENABLE_DRS +#define ENABLE_DRS 0 + +#undef ENABLE_CA_TRAINING +#define ENABLE_CA_TRAINING 1 +#undef ENABLE_WRITE_LEVELING +#define ENABLE_WRITE_LEVELING 1 +#undef ENABLE_PHY_RX_INPUT_OFFSET +#define ENABLE_PHY_RX_INPUT_OFFSET 0 + +//#undef REDUCE_LOG_FOR_PRELOADER +//#define REDUCE_LOG_FOR_PRELOADER 0 + +#undef REDUCE_CALIBRATION_OLYMPUS_ONLY +#define REDUCE_CALIBRATION_OLYMPUS_ONLY 0 + +#undef APPLY_LOWPOWER_GOLDEN_SETTINGS +#define APPLY_LOWPOWER_GOLDEN_SETTINGS 0 //Should open APPLY_LOWPOWER_GOLDEN_SETTINGS before SB + 3 + +//#undef SPM_CONTROL_AFTERK //Should open SPM_CONTROL_AFTERK before SB + 3 + +#undef TX_K_DQM_WITH_WDBI +#define TX_K_DQM_WITH_WDBI 0 + +#undef ENABLE_EYESCAN_GRAPH +#define ENABLE_EYESCAN_GRAPH 0 + +#undef PA_IMPROVEMENT_FOR_DRAMC_ACTIVE_POWER +#define PA_IMPROVEMENT_FOR_DRAMC_ACTIVE_POWER 0 + +#undef ENABLE_TX_TRACKING +#undef ENABLE_SW_TX_TRACKING +#define ENABLE_TX_TRACKING 0 +#define ENABLE_SW_TX_TRACKING 0 + +#undef ENABLE_RX_TRACKING +#define ENABLE_RX_TRACKING 0 + +#undef ENABLE_PER_BANK_REFRESH +#define ENABLE_PER_BANK_REFRESH 1 + +#undef CMD_PICG_NEW_MODE +#define CMD_PICG_NEW_MODE 0 + +#undef XRTWTW_NEW_CROSS_RK_MODE +#define XRTWTW_NEW_CROSS_RK_MODE 1 +#undef XRTRTR_NEW_CROSS_RK_MODE +#define XRTRTR_NEW_CROSS_RK_MODE 1 + +#undef ENABLE_DVFS_BYPASS_MR13_FSP +#define ENABLE_DVFS_BYPASS_MR13_FSP 0 + +#undef HW_GATING +#undef DUMMY_READ_FOR_TRACKING +#undef ZQCS_ENABLE_LP4 +//#define ZQCS_ENABLE_LP4 + +#undef TEMP_SENSOR_ENABLE +//#define TEMP_SENSOR_ENABLE +#undef IMPEDANCE_TRACKING_ENABLE +//#define IMPEDANCE_TRACKING_ENABLE +#undef ENABLE_SW_RUN_TIME_ZQ_WA + +//#undef XRTR2R_PERFORM_ENHANCE_DQSG_RX_DLY + +#undef APPLY_SIGNAL_WAVEFORM_SETTINGS_ADJUST +#define APPLY_SIGNAL_WAVEFORM_SETTINGS_ADJUST 0 + +#undef DFS_NOQUEUE_FLUSH_WA +#define DFS_NOQUEUE_FLUSH_WA 0 + + +#undef TX_PICG_NEW_MODE +#undef RX_PICG_NEW_MODE +#undef ENABLE_RX_DCM_DPHY +#define ENABLE_RX_DCM_DPHY 1 //Set 0 will lead DCM on/off error +#if APPLY_LOWPOWER_GOLDEN_SETTINGS +#define TX_PICG_NEW_MODE 1 +#define RX_PICG_NEW_MODE 1 +#else +#define TX_PICG_NEW_MODE 0 +#define RX_PICG_NEW_MODE 0 +#endif + + +#if 0 +#undef XRTW2W_PERFORM_ENHANCE_TX +#undef XRTR2R_PERFORM_ENHANCE_DQSG_RX_DLY +#ifdef XRTR2W_PERFORM_ENHANCE_RODTEN +#undef XRTR2W_PERFORM_ENHANCE_RODTEN //conflict with ENABLE_RODT_TRACKING, LP4 support only +#endif +#endif +#endif //FIRST_BRING_UP + +#define CFG_DRAM_SAVE_FOR_RUNTIME_SHMOO 0 +#define RUNTIME_SHMOO_RELEATED_FUNCTION CFG_DRAM_SAVE_FOR_RUNTIME_SHMOO +#define RUNTIME_SHMOO_RG_BACKUP_NUM (100) +#define RUNTIME_SHMOO_TX 0 //TX RX can't be opened simultaneously +#define RUNTIME_SHMOO_RX 0 +#if RUNTIME_SHMOO_RELEATED_FUNCTION //if enable rshmoo, close TX OE calibration +#undef TX_OE_EXTEND +#define TX_OE_EXTEND 1 +#undef TX_DQ_OE_SHIFT_LP4 +#define TX_DQ_OE_SHIFT_LP4 4 +#undef TX_OE_CALIBATION +#define TX_OE_CALIBATION (!TX_OE_EXTEND) +#undef ENABLE_RX_TRACKING_LP4 +#define ENABLE_RX_TRACKING_LP4 0 +#undef ENABLE_TX_TRACKING +#undef ENABLE_SW_TX_TRACKING +#define ENABLE_TX_TRACKING 0 +#define ENABLE_SW_TX_TRACKING 0 +#define RUNTIME_SHMOO_FAST_K 1 +#define RUNTIME_SHMOO_TEST_CHANNEL 0 // 0: CHA, 1: CHB +#define RUNTIME_SHMOO_TEST_RANK 0 // 0: RK0, 1: RK1 +#define RUNTIME_SHMOO_TEST_BYTE 0 // 0: Byte0, 1: Byte1 +#define RUNTIME_SHMOO_TEST_PI_DELAY_START 0 // 0~63 +#define RUNTIME_SHMOO_TEST_PI_DELAY_END 63 // 0~63 +#define RUNTIME_SHMOO_TEST_PI_DELAY_STEP 1 +#define RUNTIME_SHMOO_RX_VREF_RANGE_END 127 //La_fite: 63 +#define RUNTIME_SHMOO_RX_TEST_MARGIN 2 //for RX Delay (start:first_pass-margin, end:last_pass +margin) +#define RUNTIME_SHMOO_TEST_VREF_START 0 // 0~81 : 0~50 is range 0, 51~81 is range 1 +#define RUNTIME_SHMOO_TEST_VREF_END 81 // 0~81 : 0~50 is range 0, 51~81 is range 1 +#define RUNTIME_SHMOO_TEST_VREF_STEP 1 +#endif +typedef enum +{ + CLK_MUX_208M = 0, + CLK_MUX_104M, + CLK_MUX_52M, +} CLK_MUX_T; + +typedef enum +{ + BEF_DFS_MODE = 0, + AFT_DFS_MODE, + CHG_CLK_MODE, +} DFS_DBG_T; + +typedef enum +{ + SHUFFLE_HW_MODE = 0, + SPM_DEBUG_MODE, + RG_DEBUG_MODE, +} DFS_IP_CLOCK_T; + +typedef enum +{ + DutyScan_Calibration_K_CLK= 0, + DutyScan_Calibration_K_DQS, + DutyScan_Calibration_K_DQ, + DutyScan_Calibration_K_DQM, + DutyScan_Calibration_K_WCK +} DUTYSCAN_CALIBRATION_FLOW_K_T; + +typedef enum +{ + DQS_8PH_DEGREE_0 = 0, + DQS_8PH_DEGREE_180, + DQS_8PH_DEGREE_45, + DQS_8PH_DEGREE_MAX, +} DQS_8_PHASE_T; + +typedef enum +{ + DRVP = 0, + DRVN, + ODTP, + ODTN, + IMP_DRV_MAX +} DRAM_IMP_DRV_T; + +typedef enum +{ + IMP_LOW_FREQ = 0, + IMP_HIGH_FREQ, + IMP_NT_ODTN, // Samsung support only for LP4X + IMP_VREF_MAX +} DRAMC_IMP_T; + +typedef enum +{ + GET_MDL_USED = 0, + NORMAL_USED, + SLT_USED +} DRAM_INIT_USED_T; + +typedef enum +{ + PATTERN_RDDQC, + PATTERN_TEST_ENGINE, +} RX_PATTERN_OPTION_T; + +typedef enum +{ + DRAM_OK = 0, // OK + DRAM_FAIL, // FAIL + DRAM_FAST_K, + DRAM_NO_K, +} DRAM_STATUS_T; // DRAM status type + +typedef enum +{ + VREF_RANGE_0= 0, + VREF_RANGE_1, + VREF_RANGE_MAX +}DRAM_VREF_RANGE_T; +#define VREF_VOLTAGE_TABLE_NUM_LP4 51 +#define VREF_VOLTAGE_TABLE_NUM_LP5 128 + +typedef enum +{ + CKE_FIXOFF = 0, + CKE_FIXON, + CKE_DYNAMIC //After CKE FIX on/off, CKE should be returned to dynamic (control by HW) +} CKE_FIX_OPTION; + +typedef enum +{ + CKE_WRITE_TO_ONE_CHANNEL = 0, //just need to write CKE FIX register to current channel + CKE_WRITE_TO_ALL_CHANNEL, //need to write CKE FIX register to all channel + CKE_WRITE_TO_ALL_RANK +} CKE_FIX_CHANNEL; + +typedef enum +{ + LP5_DDR6400 = 0, + LP5_DDR6000, + LP5_DDR5500, + LP5_DDR4800, + LP5_DDR4266, + LP5_DDR3733, + LP5_DDR3200, + LP5_DDR2400, + LP5_DDR1600, + LP5_DDR1200, + LP5_DDR800, + + LP4_DDR4266, + LP4_DDR3733, + LP4_DDR3200, + LP4_DDR2667, + LP4_DDR2400, + LP4_DDR2280, + LP4_DDR1866, + LP4_DDR1600, + LP4_DDR1200, + LP4_DDR800, + LP4_DDR400, + + PLL_FREQ_SEL_MAX +} DRAM_PLL_FREQ_SEL_T; // DRAM DFS type + +typedef enum +{ + MCK_TO_4UI_SHIFT = 2, + MCK_TO_8UI_SHIFT = 3, + MCK_TO_16UI_SHIFT = 4 +} MCK_TO_UI_SHIFT_T; + +typedef enum +{ + AUTOK_CA, + AUTOK_CS, + AUTOK_DQS +} ATUOK_MODE_T; + +typedef enum +{ + AUTOK_RESPI_1 = 0, + AUTOK_RESPI_2 = 1, + AUTOK_RESPI_4 = 2, + AUTOK_RESPI_8 = 3 +} AUTOK_PI_RESOLUTION; + +typedef enum +{ + DRAM_DFS_REG_SHU0 = 0, + DRAM_DFS_REG_SHU1, + DRAM_DFS_REG_MAX +} DRAM_DFS_REG_SHU_T; + +typedef enum +{ + SRAM_SHU0 = 0, + SRAM_SHU1, + SRAM_SHU2, + SRAM_SHU3, + SRAM_SHU4, + SRAM_SHU5, + SRAM_SHU6, + DRAM_DFS_SRAM_MAX +} DRAM_DFS_SRAM_SHU_T; // DRAM SRAM RG type + +typedef enum +{ + SHUFFLE_RG = 0, + NONSHUFFLE_RG, + BOTH_SHU_NONSHU_RG, +} RG_SHU_TYPE_T; // RG SHUFFLE type +typedef enum +{ + DIV16_MODE = 0, + DIV8_MODE, + DIV4_MODE, + UNKNOWN_MODE, +} DIV_MODE_T; + +typedef enum +{ + DUTY_DEFAULT = 0, + DUTY_NEED_K, + DUTY_LAST_K +} DUTY_CALIBRATION_T; + + +typedef enum +{ + VREF_CALI_OFF = 0, + VREF_CALI_ON, +} VREF_CALIBRATION_ENABLE_T; + +typedef enum +{ + DDR800_CLOSE_LOOP = 0, + OPEN_LOOP_MODE, + SEMI_OPEN_LOOP_MODE, + CLOSE_LOOP_MODE, +} DDR800_MODE_T; + +typedef enum +{ + DRAM_CALIBRATION_SW_IMPEDANCE= 0, + DRAM_CALIBRATION_DUTY_SCAN, + DRAM_CALIBRATION_ZQ, + DRAM_CALIBRATION_JITTER_METER, + DRAM_CALIBRATION_CA_TRAIN , + DRAM_CALIBRATION_WRITE_LEVEL, + DRAM_CALIBRATION_GATING, + DRAM_CALIBRATION_RX_RDDQC, + DRAM_CALIBRATION_TX_PERBIT, + DRAM_CALIBRATION_DATLAT, + DRAM_CALIBRATION_RX_PERBIT, + DRAM_CALIBRATION_TX_OE, + DRAM_CALIBRATION_MAX +} DRAM_CALIBRATION_STATUS_T; + +typedef struct _DRAM_DFS_FREQUENCY_TABLE_T +{ + DRAM_PLL_FREQ_SEL_T freq_sel; + DIV_MODE_T divmode; + DRAM_DFS_SRAM_SHU_T shuffleIdx; + DUTY_CALIBRATION_T duty_calibration_mode; + VREF_CALIBRATION_ENABLE_T vref_calibartion_enable; // CBT/RX/TX vref calibration enable or not + DDR800_MODE_T ddr_loop_mode; +} DRAM_DFS_FREQUENCY_TABLE_T; + +typedef enum +{ + CHANNEL_SINGLE = 1, + CHANNEL_DUAL, +#if (CHANNEL_NUM > 2) + CHANNEL_THIRD, + CHANNEL_FOURTH +#endif +} DRAM_CHANNEL_NUMBER_T; + + +typedef enum +{ + RANK_SINGLE = 1, + RANK_DUAL +} DRAM_RANK_NUMBER_T; + + +typedef enum +{ + TYPE_DDR1 = 1, + TYPE_LPDDR2, + TYPE_LPDDR3, + TYPE_PCDDR3, + TYPE_LPDDR4, + TYPE_LPDDR4X, + TYPE_LPDDR4P, + TYPE_LPDDR5 +} DRAM_DRAM_TYPE_T; + +typedef enum +{ + PINMUX_DSC = 0, + PINMUX_LPBK, + PINMUX_EMCP, + PINMUX_MAX +} DRAM_PINMUX; + +/* For faster switching between term and un-term operation + * FSP_0: For un-terminated freq. + * FSP_1: For terminated freq. + */ +typedef enum +{ + FSP_0 = 0, + FSP_1, + FSP_2, + FSP_MAX +} DRAM_FAST_SWITH_POINT_T; + +typedef struct +{ + u8 pat_v[8]; + u8 pat_a[8]; + u8 pat_dmv; + u8 pat_dma; + u8 pat_cs0; + u8 pat_cs1; + u8 ca_golden_sel; + u8 invert_num; +} new_cbt_pat_cfg_t; + +typedef enum +{ + TRAINING_MODE1 = 0, + TRAINING_MODE2 +} lp5_training_mode_t; + +typedef enum +{ + CBT_PHASE_RISING = 0, + CBT_PHASE_FALLING +} lp5_cbt_phase_t; + +/* + * External CBT mode enum + * Due to MDL structure compatibility (single field for dram CBT mode), + * the below enum is used in preloader to differentiate between dram cbt modes + */ +typedef enum +{ + CBT_R0_R1_NORMAL = 0, // Normal mode + CBT_R0_R1_BYTE, // Byte mode + CBT_R0_NORMAL_R1_BYTE, // Mixed mode R0: Normal R1: Byte + CBT_R0_BYTE_R1_NORMAL // Mixed mode R0: Byte R1: Normal +} DRAM_CBT_MODE_EXTERN_T; + +typedef enum +{ + ODT_OFF = 0, + ODT_ON +} DRAM_ODT_MODE_T; + +typedef enum +{ + DBI_OFF = 0, + DBI_ON +} DRAM_DBI_MODE_T; + +typedef enum +{ + DATA_WIDTH_16BIT = 16, + DATA_WIDTH_32BIT = 32 +} DRAM_DATA_WIDTH_T; + +typedef enum +{ + TE_OP_WRITE_READ_CHECK = 0, + TE_OP_READ_CHECK +} DRAM_TE_OP_T; + +typedef enum +{ + TEST_ISI_PATTERN = 0, //don't change + TEST_AUDIO_PATTERN = 1, //don't change + TEST_XTALK_PATTERN = 2, //don't change + TEST_WORST_SI_PATTERN, + TEST_TA1_SIMPLE, + TEST_TESTPAT4, + TEST_TESTPAT4_3, + TEST_MIX_PATTERN, + TEST_DMA, + TEST_SSOXTALK_PATTERN, +} DRAM_TEST_PATTERN_T; + +typedef enum +{ + TE_NO_UI_SHIFT = 0, + TE_UI_SHIFT +} DRAM_TE_UI_SHIFT_T; + +typedef enum +{ + TX_DQ_DQS_MOVE_DQ_ONLY = 0, + TX_DQ_DQS_MOVE_DQM_ONLY, + TX_DQ_DQS_MOVE_DQ_DQM +} DRAM_TX_PER_BIT_CALIBRATION_TYTE_T; + +typedef enum +{ + TX_DQM_WINDOW_SPEC_IN = 0xfe, + TX_DQM_WINDOW_SPEC_OUT = 0xff +} DRAM_TX_PER_BIT_DQM_WINDOW_RESULT_TYPE_T; + +// enum for CKE toggle mode (toggle both ranks 1. at the same time (CKE_RANK_DEPENDENT) 2. individually (CKE_RANK_INDEPENDENT)) +typedef enum +{ + CKE_RANK_INDEPENDENT = 0, + CKE_RANK_DEPENDENT +} CKE_CTRL_MODE_T; + +typedef enum +{ + TA2_RKSEL_XRT = 3, + TA2_RKSEL_HW = 4, +} TA2_RKSEL_TYPE_T; + +typedef enum +{ + TA2_PAT_SWITCH_OFF = 0, + TA2_PAT_SWITCH_ON, +} TA2_PAT_SWITCH_TYPE_T; + +typedef enum +{ + PHYPLL_MODE = 0, + CLRPLL_MODE, +} PLL_MODE_T; + +typedef enum +{ + RUNTIME_SWCMD_CAS_FS = 0, + RUNTIME_SWCMD_CAS_OFF, + RUNTIME_SWCMD_WCK2DQI_START, + RUNTIME_SWCMD_WCK2DQO_START, + RUNTIME_SWCMD_MRW, + RUNTIME_SWCMD_ZQCAL_START, + RUNTIME_SWCMD_ZQCAL_LATCH +} RUNTIME_SWCMD_SEL_T; + +typedef enum +{ + PI_BASED, + DLY_BASED +} WLEV_DELAY_BASED_T; + +enum lpddr5_rpre_mode { + LPDDR5_RPRE_4S_0T = 0, + LPDDR5_RPRE_2S_2T, + LPDDR5_RPRE_0S_4T, + LPDDR5_RPRE_XS_4T, /* X = 2~4tWCK */ +}; + +enum rxdqs_autok_burst_len { + RXDQS_BURST_LEN_8 = 0, + RXDQS_BURST_LEN_16, + RXDQS_BURST_LEN_32, +}; + +typedef enum +{ + EYESCAN_FLAG_DISABLE= 0, + EYESCAN_FLAG_ENABLE, + EYESCAN_FLAG_ENABLE_BUT_NORMAL_K, +} EYESCAN_FLAG_TYPE_T; + +#ifdef FOR_HQA_REPORT_USED +typedef enum +{ + HQA_REPORT_FORMAT0 = 0, + HQA_REPORT_FORMAT0_1, + HQA_REPORT_FORMAT0_2, + HQA_REPORT_FORMAT1, + HQA_REPORT_FORMAT2, + HQA_REPORT_FORMAT2_1, + HQA_REPORT_FORMAT3, + HQA_REPORT_FORMAT4, + HQA_REPORT_FORMAT5, + HQA_REPORT_FORMAT6 +} HQA_REPORT_FORMAT_T; +#endif + +#if SUPPORT_SAVE_TIME_FOR_CALIBRATION +#if RUNTIME_SHMOO_RELEATED_FUNCTION +typedef struct _RUNTIME_SHMOO_SAVE_PARAMETER_T +{ + U8 flag; + U16 TX_PI_delay; + U16 TX_Original_PI_delay; + U16 TX_DQM_PI_delay; + U16 TX_Original_DQM_PI_delay; + S16 RX_delay[8]; + S16 RX_Original_delay; + U8 TX_Vref_Range; + U8 TX_Vref_Value; + U8 TX_Channel; + U8 TX_Rank; + U8 TX_Byte; + U8 Scan_Direction; +} RUNTIME_SHMOO_SAVE_PARAMETER_T; +#endif + +typedef struct _SAVE_TIME_FOR_CALIBRATION_T +{ + //U8 femmc_Ready; + + DRAM_RANK_NUMBER_T support_rank_num; + + U16 u2num_dlycell_perT; + U16 u2DelayCellTimex100; + + // CLK & DQS duty + S8 s1ClockDuty_clk_delay_cell[CHANNEL_NUM][RANK_MAX]; + S8 s1DQSDuty_clk_delay_cell[CHANNEL_NUM][DQS_NUMBER_LP4]; + S8 s1WCKDuty_clk_delay_cell[CHANNEL_NUM][DQS_NUMBER_LP4]; +#if APPLY_DQDQM_DUTY_CALIBRATION + S8 s1DQDuty_clk_delay_cell[CHANNEL_NUM][DQS_NUMBER_LP4]; + S8 s1DQMDuty_clk_delay_cell[CHANNEL_NUM][DQS_NUMBER_LP4]; +#endif + // CBT + U8 u1CBTVref_Save[CHANNEL_NUM][RANK_MAX]; + S8 s1CBTCmdDelay_Save[CHANNEL_NUM][RANK_MAX]; + U8 u1CBTCsDelay_Save[CHANNEL_NUM][RANK_MAX]; + #if CA_PER_BIT_DELAY_CELL + U8 u1CBTCA_PerBit_DelayLine_Save[CHANNEL_NUM][RANK_MAX][DQS_BIT_NUMBER]; + #endif + + // Write leveling + U8 u1WriteLeveling_bypass_Save[CHANNEL_NUM][RANK_MAX][DQS_NUMBER_LP4]; //for bypass writeleveling + + // Gating + U8 u1Gating_MCK_Save[CHANNEL_NUM][RANK_MAX][DQS_NUMBER_LP4]; + U8 u1Gating_UI_Save[CHANNEL_NUM][RANK_MAX][DQS_NUMBER_LP4]; + U8 u1Gating_PI_Save[CHANNEL_NUM][RANK_MAX][DQS_NUMBER_LP4]; + U8 u1Gating_pass_count_Save[CHANNEL_NUM][RANK_MAX][DQS_NUMBER_LP4]; + + // TX perbit + U8 u1TxWindowPerbitVref_Save[CHANNEL_NUM][RANK_MAX]; + U16 u1TxCenter_min_Save[CHANNEL_NUM][RANK_MAX][DQS_NUMBER_LP4]; + U16 u1TxCenter_max_Save[CHANNEL_NUM][RANK_MAX][DQS_NUMBER_LP4]; + U16 u1Txwin_center_Save[CHANNEL_NUM][RANK_MAX][DQ_DATA_WIDTH_LP4]; + + // Datlat + U8 u1RxDatlat_Save[CHANNEL_NUM][RANK_MAX]; + + // RX perbit + U8 u1RxWinPerbitVref_Save[CHANNEL_NUM][RANK_MAX][DQS_NUMBER_LP4]; + U16 u1RxWinPerbit_DQS[CHANNEL_NUM][RANK_MAX][DQS_NUMBER_LP4]; + U16 u1RxWinPerbit_DQM[CHANNEL_NUM][RANK_MAX][DQS_NUMBER_LP4]; + U16 u1RxWinPerbit_DQ[CHANNEL_NUM][RANK_MAX][DQ_DATA_WIDTH_LP4]; + + //TX OE + U8 u1TX_OE_DQ_MCK[CHANNEL_NUM][RANK_MAX][DQS_NUMBER_LP4]; + U8 u1TX_OE_DQ_UI[CHANNEL_NUM][RANK_MAX][DQS_NUMBER_LP4]; + + +#if RUNTIME_SHMOO_RELEATED_FUNCTION + S16 u1RxWinPerbitDQ_firsbypass_Save[CHANNEL_NUM][RANK_MAX][DQ_DATA_WIDTH_LP4]; //for bypass rxwindow + U8 u1RxWinPerbitDQ_lastbypass_Save[CHANNEL_NUM][RANK_MAX][DQ_DATA_WIDTH_LP4]; //for bypass rxwindow + U8 u1SwImpedanceResule[2][4]; + U32 u4RG_Backup[CHANNEL_NUM][RUNTIME_SHMOO_RG_BACKUP_NUM]; + + RUNTIME_SHMOO_SAVE_PARAMETER_T Runtime_Shmoo_para; +#endif +}SAVE_TIME_FOR_CALIBRATION_T; +#endif // SUPPORT_SAVE_TIME_FOR_CALIBRATION + +#if MRW_CHECK_ONLY +#define MR_NUM 64 +extern U16 u2MRRecord[CHANNEL_NUM][RANK_MAX][FSP_MAX][MR_NUM]; +#endif + +//////////////////////////// +typedef struct _DRAMC_CTX_T +{ + DRAM_CHANNEL_NUMBER_T support_channel_num; + DRAM_CHANNEL_T channel; + DRAM_RANK_NUMBER_T support_rank_num; + DRAM_RANK_T rank; + DRAM_PLL_FREQ_SEL_T freq_sel; + DRAM_DFS_SHUFFLE_TYPE_T shu_type; + DRAM_DRAM_TYPE_T dram_type; + DRAM_FAST_SWITH_POINT_T dram_fsp; // only for LP4, uesless in LP3 + DRAM_ODT_MODE_T odt_onoff;/// only for LP4, uesless in LP3 + DRAM_CBT_MODE_T dram_cbt_mode[RANK_MAX]; //only for LP4, useless in LP3 + DRAM_DBI_MODE_T DBI_R_onoff[FSP_MAX]; // only for LP4, uesless in LP3 + DRAM_DBI_MODE_T DBI_W_onoff[FSP_MAX]; // only for LP4, uesless in LP3 + DRAM_DATA_WIDTH_T data_width; + U32 test2_1; + U32 test2_2; + DRAM_TEST_PATTERN_T test_pattern; + U16 frequency; + U16 freqGroup; /* Used to support freq's that are not in ACTimingTable */ + U16 vendor_id; + U16 revision_id; + U16 density; + U64 ranksize[RANK_MAX]; + U16 u2num_dlycell_perT; + U16 u2DelayCellTimex100; + //U8 enable_cbt_scan_vref; + //U8 enable_rx_scan_vref; + //U8 enable_tx_scan_vref; + + #if PRINT_CALIBRATION_SUMMARY + U32 aru4CalResultFlag[CHANNEL_NUM][RANK_MAX];// record the calibration is fail or success, 0:success, 1: fail + U32 aru4CalExecuteFlag[CHANNEL_NUM][RANK_MAX]; // record the calibration is execute or not, 0:no operate, 1: done + U32 SWImpCalResult; + U32 SWImpCalExecute; + #if PRINT_CALIBRATION_SUMMARY_FASTK_CHECK + U32 FastKResultFlag[2][RANK_MAX];// record the calibration is fail or success, 0:success, 1: fail + U32 FastKExecuteFlag[2][RANK_MAX]; // record the calibration is execute or not, 0:no operate, 1: done + #endif + #endif + + bool isWLevInitShift[CHANNEL_NUM]; + + #if SUPPORT_SAVE_TIME_FOR_CALIBRATION + U8 femmc_Ready; + // Calibration or not + U8 Bypass_TXWINDOW; + U8 Bypass_RXWINDOW; + U8 Bypass_RDDQC; + SAVE_TIME_FOR_CALIBRATION_T *pSavetimeData; + #endif + DRAM_DFS_FREQUENCY_TABLE_T *pDFSTable; + DRAM_DFS_REG_SHU_T ShuRGAccessIdx; + lp5_training_mode_t lp5_training_mode; //only for LP5 + lp5_cbt_phase_t lp5_cbt_phase; //only for LP5 + u8 new_cbt_mode; + U8 u1PLLMode; + DRAM_DBI_MODE_T curDBIState; + DRAM_FAST_SWITH_POINT_T support_fsp_num; + DRAM_PINMUX DRAMPinmux; + U8 u110GBEn[RANK_MAX]; + bool isMaxFreq4266; +} DRAMC_CTX_T; + +typedef struct _DRAM_DVFS_TABLE_T +{ + DRAM_PLL_FREQ_SEL_T freq_sel; + DIV_MODE_T divmode; + DRAM_DFS_SRAM_SHU_T shuffleIdx; + U32 u4Vcore; +} DRAM_DVFS_TABLE_T; + +typedef struct _PASS_WIN_DATA_T +{ + S16 first_pass; + S16 last_pass; + S16 win_center; + U16 win_size; + U16 best_dqdly; +} PASS_WIN_DATA_T; + +typedef struct _FINAL_WIN_DATA_T { + unsigned char final_vref; + signed int final_ca_clk; + unsigned char final_range; +} FINAL_WIN_DATA_T; + +typedef struct _REG_TRANSFER +{ + U32 u4Addr; + U32 u4Fld; +} REG_TRANSFER_T; + +typedef struct _DRAM_INFO_BY_MRR_T +{ + U16 u2MR5VendorID; + U16 u2MR6RevisionID; + U64 u8MR8RankSize[RANK_MAX]; +} DRAM_INFO_BY_MRR_T; + +#if __FLASH_TOOL_DA__ +typedef struct _DEBUG_PIN_INF_FOR_FLASHTOOL_T +{ + U16 TOTAL_ERR;//DQ,CA + U16 IMP_ERR_FLAG; + U8 WL_ERR_FLAG;//DQS + U8 CA_ERR_FLAG[CHANNEL_MAX][RANK_MAX]; + U8 CA_WIN_SIZE[CHANNEL_MAX][RANK_MAX][CATRAINING_NUM_LP4]; + U8 DRAM_PIN_RX_ERR_FLAG[CHANNEL_MAX][RANK_MAX][DQS_NUMBER_LP4]; + U8 DRAM_PIN_TX_ERR_FLAG[CHANNEL_MAX][RANK_MAX][DQS_NUMBER_LP4]; + U8 DQ_RX_ERR_FLAG[CHANNEL_MAX][RANK_MAX][DQS_NUMBER_LP4]; + U8 DQ_TX_ERR_FLAG[CHANNEL_MAX][RANK_MAX][DQS_NUMBER_LP4]; + U16 DQ_RX_WIN_SIZE[CHANNEL_MAX][RANK_MAX][DQ_DATA_WIDTH_LP4]; + U8 DQ_TX_WIN_SIZE[CHANNEL_MAX][RANK_MAX][DQ_DATA_WIDTH_LP4]; +} DEBUG_PIN_INF_FOR_FLASHTOOL_T; +#endif +typedef struct _VCORE_DELAYCELL_T +{ + U32 u2Vcore; + U16 u2DelayCell; +} VCORE_DELAYCELL_T; + +typedef enum +{ + DMA_PREPARE_DATA_ONLY, + DMA_CHECK_DATA_ACCESS_ONLY_AND_NO_WAIT, + DMA_CHECK_COMAPRE_RESULT_ONLY, + DMA_CHECK_DATA_ACCESS_AND_COMPARE, +} DRAM_DMA_CHECK_RESULT_T; + + +//For new register access +#define SHIFT_TO_CHB_ADDR ((U32)CHANNEL_B << POS_BANK_NUM) +#if (CHANNEL_NUM > 2) +#define SHIFT_TO_CHC_ADDR ((U32)CHANNEL_C << POS_BANK_NUM) +#define SHIFT_TO_CHD_ADDR ((U32)CHANNEL_D << POS_BANK_NUM) +#endif +#define DRAMC_REG_ADDR(offset) ((p->channel << POS_BANK_NUM) + (offset)) +#define SYS_REG_ADDR(offset) (offset) + +// Different from Pi_calibration.c due to Base address +//#define mcSET_DRAMC_REG_ADDR(offset) (DRAMC_BASE_ADDRESS | (p->channel << POS_BANK_NUM) | (offset)) +#define mcSET_SYS_REG_ADDR(offset) (DRAMC_BASE_ADDRESS | (offset)) +#define mcSET_DRAMC_NAO_REG_ADDR(offset) (DRAMC_NAO_BASE_ADDRESS | (offset)) +#define mcSET_DRAMC_AO_REG_ADDR(offset) (DRAMC_AO_BASE_ADDRESS | (offset)) +//#define mcSET_DRAMC_AO_REG_ADDR_CHC(offset) ((DRAMC_AO_BASE_ADDRESS + ((U32)CHANNEL_C << POS_BANK_NUM)) | (offset)) +#define mcSET_DDRPHY_REG_ADDR(offset) (DDRPHY_BASE_ADDR | (offset)) +#define mcSET_DDRPHY_REG_ADDR_CHA(offset) ((DDRPHY_BASE_ADDR + ((U32) CHANNEL_A << POS_BANK_NUM)) | (offset)) +#define mcSET_DDRPHY_REG_ADDR_CHB(offset) ((DDRPHY_BASE_ADDR + SHIFT_TO_CHB_ADDR) | (offset)) +//#define mcSET_DDRPHY_REG_ADDR_CHC(offset) ((DDRPHY_BASE_ADDR + ((U32) CHANNEL_C << POS_BANK_NUM)) | (offset)) +//#define mcSET_DDRPHY_REG_ADDR_CHD(offset) ((DDRPHY_BASE_ADDR + ((U32) CHANNEL_D << POS_BANK_NUM)) | (offset)) + +//-------------------------------------------------------------------------- +// Dram Mode Registers Operation +//-------------------------------------------------------------------------- +#define MRWriteFldMulti(p, mr_idx, list, UpdateMode) \ +{ \ + UINT16 upk = 1; \ + U8 msk = (U8)(list); \ + { \ + upk = 0; \ + DramcMRWriteFldMsk(p, mr_idx, (U8)(list), msk, UpdateMode); \ + } \ +} + +#define JUST_TO_GLOBAL_VALUE (0) +#define TO_MR (1) + +// LP5 MR30 +#define MR30_DCAU (Fld(4, 4)) // DCA for upper byte +#define MR30_DCAL (Fld(4, 0)) // DCA for lower byte + +// LP5 MR26 +#define MR26_DCMU1 (Fld(1, 5)) +#define MR26_DCMU0 (Fld(1, 4)) +#define MR26_DCML1 (Fld(1, 3)) +#define MR26_DCML0 (Fld(1, 2)) +#define MR26_DCM_FLIP (Fld(1, 1)) +#define MR26_DCM_START_STOP (Fld(1, 0)) + +// LP4 MR13 +#define MR13_FSP_OP (Fld(1, 7)) +#define MR13_FSP_WR (Fld(1, 6)) +#define MR13_DMD (Fld(1, 5)) +#define MR13_PRO (Fld(1, 4)) +#define MR13_VRCG (Fld(1, 3)) +#define MR13_CBT (Fld(1, 0)) + +#define MR16_FSP_WR_SHIFT (0) +#define MR16_FSP_OP_SHIFT (2) +#define MR16_FSP_CBT (4) +#define MR16_VRCG (6) +#define MR16_CBT_PHASE (7) + +/***********************************************************************/ +/* External declarations */ +/***********************************************************************/ +EXTERN DRAMC_CTX_T *psCurrDramCtx; +#if QT_GUI_Tool +EXTERN FILE *fp_A60868; +EXTERN FILE *fp_A60868_RGDump; +#endif +/***********************************************************************/ +/* Public Functions */ +/***********************************************************************/ +// basic function +EXTERN U8 u1IsLP4Family(DRAM_DRAM_TYPE_T dram_type); +EXTERN int Init_DRAM(DRAM_DRAM_TYPE_T dram_type, DRAM_CBT_MODE_EXTERN_T dram_cbt_mode_extern, DRAM_INFO_BY_MRR_T *DramInfo, U8 get_mdl_used); +EXTERN void Dramc_DDR_Reserved_Mode_setting(void); +EXTERN void Dramc_DDR_Reserved_Mode_AfterSR(void); +EXTERN void Before_Init_DRAM_While_Reserve_Mode_fail(DRAM_DRAM_TYPE_T dram_type); +EXTERN void ShuffleDfsToFSP1(DRAMC_CTX_T *p); + +void vSetVcoreByFreq(DRAMC_CTX_T *p); +U32 Get_WL_by_MR_LP4(U8 Version, U8 MR_WL_field_value); +U8 u1MCK2UI_DivShift(DRAMC_CTX_T *p); +void DramcDFSDirectJump_SRAMShuRGMode(DRAMC_CTX_T *p, U8 shu_level); +void UpdateDFSTbltoDDR3200(DRAMC_CTX_T *p); +void DFSInitForCalibration(DRAMC_CTX_T *p); +void mdl_setting(DRAMC_CTX_T *p); +void MPLLInit(void); +void DramcCKEDebounce(DRAMC_CTX_T *p); +void DramcModifiedRefreshMode(DRAMC_CTX_T *p); +void XRTRTR_SHU_Setting(DRAMC_CTX_T * p); +void TXPICGSetting(DRAMC_CTX_T * p); +void XRTWTW_SHU_Setting(DRAMC_CTX_T * p); +DRAM_STATUS_T DramcDualRankRxdatlatCal(DRAMC_CTX_T *p); +void vSwitchWriteDBISettings(DRAMC_CTX_T *p, U8 u1OnOff); +void Get_RX_DelayCell(DRAMC_CTX_T *p); +void DramcRxdqsGatingPostProcess(DRAMC_CTX_T *p); +void EnableDFSNoQueueFlush(DRAMC_CTX_T *p); +void EnableDramcPhyDCMNonShuffle(DRAMC_CTX_T *p, bool bEn); +void Enable_TxWDQS(DRAMC_CTX_T *p, U32 u4DDRPhyShuOffset, U16 u2Freq); +void Enable_ClkTxRxLatchEn(DRAMC_CTX_T *p, U32 u4DDRPhyShuOffset); +void EnableRxDcmDPhy(DRAMC_CTX_T *p, U32 u4DDRPhyShuOffset, U16 u2Freq); +void DramcRxdqsGatingPreProcess(DRAMC_CTX_T *p); +void LP4_single_end_DRAMC_post_config(DRAMC_CTX_T *p, U8 LP4Y_EN); +void vResetDelayChainBeforeCalibration(DRAMC_CTX_T *p); + +unsigned int dramc_set_vcore_voltage(unsigned int vcore); +unsigned int dramc_get_vcore_voltage(void); +unsigned int dramc_set_vdram_voltage(unsigned int ddr_type, unsigned int vdram); +unsigned int dramc_get_vdram_voltage(unsigned int ddr_type); +unsigned int dramc_set_vddq_voltage(unsigned int ddr_type, unsigned int vddq); +unsigned int dramc_get_vddq_voltage(unsigned int ddr_type); +unsigned int dramc_set_vmddr_voltage(unsigned int vmddr); +unsigned int dramc_get_vmddr_voltage(void); +unsigned int dramc_set_vio18_voltage(unsigned int vio18); +unsigned int dramc_get_vio18_voltage(void); + +void sv_algorithm_assistance_LP4_4266(DRAMC_CTX_T *p); + +void DramcNewDutyCalibration(DRAMC_CTX_T *p); +unsigned int mt_get_dram_type_from_hw_trap(void); +U8 Get_MDL_Used_Flag(void); +void Set_MDL_Used_Flag(U8 value); +void SetMr13VrcgToNormalOperation(DRAMC_CTX_T *p); +void cbt_dfs_mr13_global(DRAMC_CTX_T *p, U8 freq); +void TX_Path_Algorithm(DRAMC_CTX_T *p); +DRAM_PLL_FREQ_SEL_T GetSelByFreq(DRAMC_CTX_T *p, U16 u2freq); +U32 Get_RL_by_MR_LP4(U8 BYTE_MODE_EN,U8 DBI_EN, U8 MR_RL_field_value); + +#endif // _PI_API_H diff --git a/src/vendorcode/mediatek/mt8192/include/dramc_reg_base_addr.h b/src/vendorcode/mediatek/mt8192/include/dramc_reg_base_addr.h new file mode 100644 index 000000000000..d29c47907611 --- /dev/null +++ b/src/vendorcode/mediatek/mt8192/include/dramc_reg_base_addr.h @@ -0,0 +1,42 @@ +/* SPDX-License-Identifier: BSD-3-Clause */ + +#ifndef __REG_BASE_ADDR__ +#define __REG_BASE_ADDR__ + +#include "soc/addressmap.h" +#include "emi_hw.h" + +#ifndef __ETT__ +#define __ETT__ 0 +#endif + +//#define DRAM_BASE 0x40000000ULL +//#define DDR_BASE DRAM_BASE +#define CQ_DMA_BASE (IO_PHYS + 0x212000) +//#define CKSYS_BASE IO_PHYS +//#define EMI_APB_BASE 0x10219000 +//#define EMI_BASE EMI_APB_BASE +//#define EMI_MPU_BASE 0x10226000 +#define CHN0_EMI_BASE (IO_PHYS + 0x235000) +#define CHN1_EMI_BASE (IO_PHYS + 0x245000) +#define INFRA_DRAMC_REG_CONFIG (INFRACFG_AO_BASE + 0xB4) +//#define INFRACFG_AO_BASE (IO_PHYS + 0x00001000) +//#define APMIXED_BASE (IO_PHYS + 0x0000C000) + +#define MPLL_CON0 (APMIXED_BASE + 0x390) +#define MPLL_CON1 (APMIXED_BASE + 0x394) +#define MPLL_CON3 (APMIXED_BASE + 0x39C) + +#define PLLON_CON0 (APMIXED_BASE + 0x050) +#define PLLON_CON1 (APMIXED_BASE + 0x054) +#define PLLON_CON2 (APMIXED_BASE + 0x058) +#define PLLON_CON3 (APMIXED_BASE + 0x05C) + +/* TOPCKGEN Register */ +#define CLK_MISC_CFG_0 (CKSYS_BASE + 0x104) +#define CLK_MISC_CFG_1 (CKSYS_BASE + 0x108) +#define CLK_DBG_CFG (CKSYS_BASE + 0x10C) +#define CLK26CALI_0 (CKSYS_BASE + 0x220) +#define CLK26CALI_1 (CKSYS_BASE + 0x224) + +#endif //__REG_BASE_ADDR__ diff --git a/src/vendorcode/mediatek/mt8192/include/dramc_register.h b/src/vendorcode/mediatek/mt8192/include/dramc_register.h new file mode 100644 index 000000000000..17cde4cdf335 --- /dev/null +++ b/src/vendorcode/mediatek/mt8192/include/dramc_register.h @@ -0,0 +1,248 @@ +/* SPDX-License-Identifier: BSD-3-Clause */ + +#ifndef _A60868_REGISTER_H_ +#define _A60868_REGISTER_H_ + +#include "dramc_pi_api.h" + +#define POS_BANK_NUM 16 // SW Virtual base address position + +#if (fcFOR_CHIP_ID == fcMargaux) +#include "Margaux_Register_DDRPHY_MD32.h" +#include "Margaux_Register_DDRPHY_NAO.h" +#include "Margaux_Register_DDRPHY_AO.h" +#include "Margaux_Register_DRAMC_AO.h" +#include "Margaux_Register_DRAMC_NAO.h" +#else +#include "Register_DDRPHY_MD32.h" +#include "Register_DDRPHY_NAO.h" +#include "Register_DDRPHY_AO.h" +#include "Register_DRAMC_AO.h" +#include "Register_DRAMC_NAO.h" +#include "Register_SYSTEM.h" +#endif + +// SW Virtual base address +#define Channel_A_DRAMC_NAO_BASE_VIRTUAL 0x40000 +#define Channel_B_DRAMC_NAO_BASE_VIRTUAL 0x50000 +#define Channel_A_DRAMC_AO_BASE_VIRTUAL 0x60000 +#define Channel_B_DRAMC_AO_BASE_VIRTUAL 0x70000 +#define Channel_A_DDRPHY_NAO_BASE_VIRTUAL 0x80000 +#define Channel_B_DDRPHY_NAO_BASE_VIRTUAL 0x90000 +#define Channel_A_DDRPHY_AO_BASE_VIRTUAL 0xa0000 +#define Channel_B_DDRPHY_AO_BASE_VIRTUAL 0xb0000 +#define Channel_A_DDRPHY_DPM_BASE_VIRTUAL 0xc0000 +#define MAX_BASE_VIRTUAL 0xd0000 + +#define DRAMC_WBR 0x100010B4 +#if (CHANNEL_NUM==4) +#define DRAMC_BROADCAST_ON 0x27f7f //4CH +#else +#define DRAMC_BROADCAST_ON 0x7f //2CH +#endif +#define DRAMC_BROADCAST_OFF 0x0 + +//Definitions indicating DRAMC, DDRPHY register shuffle offset +#define SHU_GRP_DRAMC_OFFSET 0x700 +#define SHU_GRP_DDRPHY_OFFSET 0x700 + +#define DRAMC_REG_AO_SHU_OFFSET (0x700) +#define DRAMC_REG_AO_RANK_OFFSET (0x200) +#define DRAMC_REG_AO_RANK0_WO_SHUFFLE_BASE_ADDR (DRAMC_REG_RK_TEST2_A1 - DRAMC_AO_BASE_ADDRESS) // 0x0500 +#define DRAMC_REG_AO_RANK0_WO_SHUFFLE_END_ADDR (DRAMC_REG_AO_RANK0_WO_SHUFFLE_BASE_ADDR + DRAMC_REG_AO_RANK_OFFSET) +#define DRAMC_REG_AO_RANK0_W_SHUFFLE0_BASE_ADDR (DRAMC_REG_SHURK_SELPH_DQ0 - DRAMC_AO_BASE_ADDRESS) // 0x1200 +#define DRAMC_REG_AO_RANK0_W_SHUFFLE0_END_ADDR (DRAMC_REG_AO_RANK0_W_SHUFFLE0_BASE_ADDR + DRAMC_REG_AO_RANK_OFFSET) +#define DRAMC_REG_AO_SHUFFLE0_BASE_ADDR (DRAMC_REG_SHURK_SELPH_DQ0 - DRAMC_AO_BASE_ADDRESS) // 0x1200 +#define DRAMC_REG_AO_SHUFFLE0_END_ADDR (DRAMC_REG_SHU_ACTIM7 - DRAMC_AO_BASE_ADDRESS) // 0x16E8 + +#define DDRPHY_AO_B0_B1_OFFSET (0x180) +#define DDRPHY_AO_SHU_OFFSET (0x700) +#define DDRPHY_AO_RANK_OFFSET (0x80) +#define DDRPHY_AO_RANK0_B0_NON_SHU_BASE_ADDR (DDRPHY_REG_RK_B0_RXDVS0 - DDRPHY_AO_BASE_ADDRESS) // 0x0060 +#define DDRPHY_AO_RANK0_B0_NON_SHU_END_ADDR (DDRPHY_AO_RANK0_B0_NON_SHU_BASE_ADDR + DDRPHY_AO_RANK_OFFSET) +#define DDRPHY_AO_RANK0_B1_NON_SHU_BASE_ADDR (DDRPHY_REG_RK_B1_RXDVS0 - DDRPHY_AO_BASE_ADDRESS) // 0x01E0 +#define DDRPHY_AO_RANK0_B1_NON_SHU_END_ADDR (DDRPHY_AO_RANK0_B1_NON_SHU_BASE_ADDR + DDRPHY_AO_RANK_OFFSET) +#define DDRPHY_AO_RANK0_CA_NON_SHU_BASE_ADDR (DDRPHY_REG_RK_CA_RXDVS0 - DDRPHY_AO_BASE_ADDRESS) // 0x0360 +#define DDRPHY_AO_RANK0_CA_NON_SHU_END_ADDR (DDRPHY_AO_RANK0_CA_NON_SHU_BASE_ADDR + DDRPHY_AO_RANK_OFFSET) +#define DDRPHY_AO_RANK0_B0_SHU0_BASE_ADDR (DDRPHY_REG_SHU_R0_B0_TXDLY0 - DDRPHY_AO_BASE_ADDRESS) // 0x0760 +#define DDRPHY_AO_RANK0_B0_SHU0_END_ADDR (DDRPHY_AO_RANK0_B0_SHU0_BASE_ADDR + DDRPHY_AO_RANK_OFFSET) +#define DDRPHY_AO_RANK0_B1_SHU0_BASE_ADDR (DDRPHY_REG_SHU_R0_B1_TXDLY0 - DDRPHY_AO_BASE_ADDRESS) // 0x08E0 +#define DDRPHY_AO_RANK0_B1_SHU0_END_ADDR (DDRPHY_AO_RANK0_B1_SHU0_BASE_ADDR + DDRPHY_AO_RANK_OFFSET) +#define DDRPHY_AO_RANK0_CA_SHU0_BASE_ADDR (DDRPHY_REG_SHU_R0_CA_TXDLY0 - DDRPHY_AO_BASE_ADDRESS) // 0x0A60 +#define DDRPHY_AO_RANK0_CA_SHU0_END_ADDR (DDRPHY_AO_RANK0_CA_SHU0_BASE_ADDR + DDRPHY_AO_RANK_OFFSET) +#define DDRPHY_AO_RANK0_MISC_SHU0_BASE_ADDR (DDRPHY_REG_MISC_SHU_RK_DQSCTL - DDRPHY_AO_BASE_ADDRESS) // 0x0BE0 +#define DDRPHY_AO_RANK0_MISC_SHU0_END_ADDR (DDRPHY_AO_RANK0_MISC_SHU0_BASE_ADDR + DDRPHY_AO_RANK_OFFSET) +#define DDRPHY_AO_SHUFFLE0_BASE_ADDR (DDRPHY_REG_SHU_PHYPLL0 - DDRPHY_AO_BASE_ADDRESS) // 0x700 +#define DDRPHY_AO_SHUFFLE0_END_ADDR (DDRPHY_REG_MISC_SHU_CG_CTRL0 - DDRPHY_AO_BASE_ADDRESS) // 0xDA4 + +#define DDRPHY_NAO_DQSIEN_AUTOK_STATUS_RK_OFFSET (0x20) +#define DDRPHY_NAO_GATING_STATUS_RK_OFFSET (0x10) +#define DDRPHY_NAO_RANK0_B0_DQSIEN_AUTOK_STATUS_START (DDRPHY_REG_DQSIEN_AUTOK_B0_RK0_STATUS0 - DDRPHY_NAO_BASE_ADDRESS) // 0x0600 +#define DDRPHY_NAO_RANK0_B0_DQSIEN_AUTOK_STATUS_END (DDRPHY_NAO_RANK0_B0_DQSIEN_AUTOK_STATUS_START + DDRPHY_NAO_DQSIEN_AUTOK_STATUS_RK_OFFSET) +#define DDRPHY_NAO_RANK0_B1_DQSIEN_AUTOK_STATUS_START (DDRPHY_REG_DQSIEN_AUTOK_B1_RK0_STATUS0 - DDRPHY_NAO_BASE_ADDRESS) // 0x0640 +#define DDRPHY_NAO_RANK0_B1_DQSIEN_AUTOK_STATUS_END (DDRPHY_NAO_RANK0_B1_DQSIEN_AUTOK_STATUS_START + DDRPHY_NAO_DQSIEN_AUTOK_STATUS_RK_OFFSET) +#define DDRPHY_NAO_RANK0_CA_DQSIEN_AUTOK_STATUS_START (DDRPHY_REG_DQSIEN_AUTOK_CA_RK0_STATUS0 - DDRPHY_NAO_BASE_ADDRESS) // 0x0680 +#define DDRPHY_NAO_RANK0_CA_DQSIEN_AUTOK_STATUS_END (DDRPHY_NAO_RANK0_CA_DQSIEN_AUTOK_STATUS_START + DDRPHY_NAO_DQSIEN_AUTOK_STATUS_RK_OFFSET) +#define DDRPHY_NAO_RANK0_GATING_STATUS_START (DDRPHY_REG_GATING_ERR_LATCH_DLY_B0_RK0 - DDRPHY_NAO_BASE_ADDRESS) // 0x0420 +#define DDRPHY_NAO_RANK0_GATING_STATUS_END (DDRPHY_NAO_RANK0_GATING_STATUS_START + DDRPHY_NAO_GATING_STATUS_RK_OFFSET) + +#define DRAMC_REG_NAO_RANK_OFFSET (0x200) +#define DRAMC_REG_NAO_RANK0_ROW_OFFSET_BASE_ADDR (DRAMC_REG_MR_BACKUP_00_RK0_FSP0 - DRAMC_NAO_BASE_ADDRESS) // 0x0900 +#define DRAMC_REG_NAO_RANK0_ROW_OFFSET_END_ADDR (DRAMC_REG_NAO_RANK0_ROW_OFFSET_BASE_ADDR + DRAMC_REG_NAO_RANK_OFFSET) + +// HW Physical base address +#if defined(__MD32__) +/* MD32 address */ +#undef Channel_A_DRAMC_AO_BASE_ADDRESS +#define Channel_A_DRAMC_AO_BASE_ADDRESS 0x300A2000 +#undef Channel_B_DRAMC_AO_BASE_ADDRESS +#define Channel_B_DRAMC_AO_BASE_ADDRESS 0x300B2000 +#undef Channel_C_DRAMC_AO_BASE_ADDRESS +#define Channel_C_DRAMC_AO_BASE_ADDRESS 0x0 +#undef Channel_D_DRAMC_AO_BASE_ADDRESS +#define Channel_D_DRAMC_AO_BASE_ADDRESS 0x0 +#undef Channel_A_DRAMC_NAO_BASE_ADDRESS +#define Channel_A_DRAMC_NAO_BASE_ADDRESS 0x300A8000 +#undef Channel_B_DRAMC_NAO_BASE_ADDRESS +#define Channel_B_DRAMC_NAO_BASE_ADDRESS 0x300B8000 +#undef Channel_C_DRAMC_NAO_BASE_ADDRESS +#define Channel_C_DRAMC_NAO_BASE_ADDRESS 0x0 +#undef Channel_D_DRAMC_NAO_BASE_ADDRESS +#define Channel_D_DRAMC_NAO_BASE_ADDRESS 0x0 +#undef Channel_A_DDRPHY_AO_BASE_ADDRESS +#define Channel_A_DDRPHY_AO_BASE_ADDRESS 0x300A6000 +#undef Channel_B_DDRPHY_AO_BASE_ADDRESS +#define Channel_B_DDRPHY_AO_BASE_ADDRESS 0x300B6000 +#undef Channel_C_DDRPHY_AO_BASE_ADDRESS +#define Channel_C_DDRPHY_AO_BASE_ADDRESS 0x0 +#undef Channel_D_DDRPHY_AO_BASE_ADDRESS +#define Channel_D_DDRPHY_AO_BASE_ADDRESS 0x0 +#undef Channel_A_DDRPHY_NAO_BASE_ADDRESS +#define Channel_A_DDRPHY_NAO_BASE_ADDRESS 0x300AA000 +#undef Channel_B_DDRPHY_NAO_BASE_ADDRESS +#define Channel_B_DDRPHY_NAO_BASE_ADDRESS 0x300BA000 +#undef Channel_C_DDRPHY_NAO_BASE_ADDRESS +#define Channel_C_DDRPHY_NAO_BASE_ADDRESS 0x0 +#undef Channel_D_DDRPHY_NAO_BASE_ADDRESS +#define Channel_D_DDRPHY_NAO_BASE_ADDRESS 0x0 +#undef Channel_A_DDRPHY_DPM_BASE_ADDRESS +#define Channel_A_DDRPHY_DPM_BASE_ADDRESS 0x30040000 +#elif (FOR_DV_SIMULATION_USED) +#undef Channel_A_DRAMC_AO_BASE_ADDRESS +#define Channel_A_DRAMC_AO_BASE_ADDRESS 0x10000 +#undef Channel_B_DRAMC_AO_BASE_ADDRESS +#define Channel_B_DRAMC_AO_BASE_ADDRESS 0x40000 +#undef Channel_C_DRAMC_AO_BASE_ADDRESS +#define Channel_C_DRAMC_AO_BASE_ADDRESS 0x0 +#undef Channel_D_DRAMC_AO_BASE_ADDRESS +#define Channel_D_DRAMC_AO_BASE_ADDRESS 0x0 + +#undef Channel_A_DRAMC_NAO_BASE_ADDRESS +#define Channel_A_DRAMC_NAO_BASE_ADDRESS 0x20000 +#undef Channel_B_DRAMC_NAO_BASE_ADDRESS +#define Channel_B_DRAMC_NAO_BASE_ADDRESS 0x50000 +#undef Channel_C_DRAMC_NAO_BASE_ADDRESS +#define Channel_C_DRAMC_NAO_BASE_ADDRESS 0x0 +#undef Channel_D_DRAMC_NAO_BASE_ADDRESS +#define Channel_D_DRAMC_NAO_BASE_ADDRESS 0x0 + +#undef Channel_A_DDRPHY_AO_BASE_ADDRESS +#define Channel_A_DDRPHY_AO_BASE_ADDRESS 0x30000 +#undef Channel_B_DDRPHY_AO_BASE_ADDRESS +#define Channel_B_DDRPHY_AO_BASE_ADDRESS 0x60000 +#undef Channel_C_DDRPHY_AO_BASE_ADDRESS +#define Channel_C_DDRPHY_AO_BASE_ADDRESS 0x0 +#undef Channel_D_DDRPHY_AO_BASE_ADDRESS +#define Channel_D_DDRPHY_AO_BASE_ADDRESS 0x0 + +#undef Channel_A_DDRPHY_NAO_BASE_ADDRESS +#define Channel_A_DDRPHY_NAO_BASE_ADDRESS 0x70000 +#undef Channel_B_DDRPHY_NAO_BASE_ADDRESS +#define Channel_B_DDRPHY_NAO_BASE_ADDRESS 0x80000 +#undef Channel_C_DDRPHY_NAO_BASE_ADDRESS +#define Channel_C_DDRPHY_NAO_BASE_ADDRESS 0x0 +#undef Channel_D_DDRPHY_NAO_BASE_ADDRESS +#define Channel_D_DDRPHY_NAO_BASE_ADDRESS 0x0 + +#undef Channel_A_DDRPHY_DPM_BASE_ADDRESS +#define Channel_A_DDRPHY_DPM_BASE_ADDRESS 0xD0000 //@Darren, 0x90000 + 0x40000 for DV sim +#elif(HAPS_FPFG_A60868 ==0) +#undef Channel_A_DRAMC_AO_BASE_ADDRESS +#define Channel_A_DRAMC_AO_BASE_ADDRESS 0x10230000 +#undef Channel_B_DRAMC_AO_BASE_ADDRESS +#define Channel_B_DRAMC_AO_BASE_ADDRESS 0x10240000 +#undef Channel_C_DRAMC_AO_BASE_ADDRESS +#define Channel_C_DRAMC_AO_BASE_ADDRESS 0x10250000 +#undef Channel_D_DRAMC_AO_BASE_ADDRESS +#define Channel_D_DRAMC_AO_BASE_ADDRESS 0x10260000 +#undef Channel_A_DRAMC_NAO_BASE_ADDRESS +#define Channel_A_DRAMC_NAO_BASE_ADDRESS 0x10234000 +#undef Channel_B_DRAMC_NAO_BASE_ADDRESS +#define Channel_B_DRAMC_NAO_BASE_ADDRESS 0x10244000 +#undef Channel_C_DRAMC_NAO_BASE_ADDRESS +#define Channel_C_DRAMC_NAO_BASE_ADDRESS 0x10254000 +#undef Channel_D_DRAMC_NAO_BASE_ADDRESS +#define Channel_D_DRAMC_NAO_BASE_ADDRESS 0x10264000 +#undef Channel_A_DDRPHY_AO_BASE_ADDRESS +#define Channel_A_DDRPHY_AO_BASE_ADDRESS 0x10238000 +#undef Channel_B_DDRPHY_AO_BASE_ADDRESS +#define Channel_B_DDRPHY_AO_BASE_ADDRESS 0x10248000 +#undef Channel_C_DDRPHY_AO_BASE_ADDRESS +#define Channel_C_DDRPHY_AO_BASE_ADDRESS 0x10258000 +#undef Channel_D_DDRPHY_AO_BASE_ADDRESS +#define Channel_D_DDRPHY_AO_BASE_ADDRESS 0x10268000 +#undef Channel_A_DDRPHY_NAO_BASE_ADDRESS +#define Channel_A_DDRPHY_NAO_BASE_ADDRESS 0x10236000 +#undef Channel_B_DDRPHY_NAO_BASE_ADDRESS +#define Channel_B_DDRPHY_NAO_BASE_ADDRESS 0x10246000 +#undef Channel_C_DDRPHY_NAO_BASE_ADDRESS +#define Channel_C_DDRPHY_NAO_BASE_ADDRESS 0x10256000 +#undef Channel_D_DDRPHY_NAO_BASE_ADDRESS +#define Channel_D_DDRPHY_NAO_BASE_ADDRESS 0x10266000 +#undef Channel_A_DDRPHY_DPM_BASE_ADDRESS +#define Channel_A_DDRPHY_DPM_BASE_ADDRESS 0x10940000 +#undef Channel_B_DDRPHY_DPM_BASE_ADDRESS +#define Channel_B_DDRPHY_DPM_BASE_ADDRESS 0x10A40000 +#else // A60868 FPGA Base Address +#undef Channel_A_DRAMC_AO_BASE_ADDRESS +#define Channel_A_DRAMC_AO_BASE_ADDRESS 0x40000 +#undef Channel_B_DRAMC_AO_BASE_ADDRESS +#define Channel_B_DRAMC_AO_BASE_ADDRESS 0x0 +#undef Channel_C_DRAMC_AO_BASE_ADDRESS +#define Channel_C_DRAMC_AO_BASE_ADDRESS 0x0 +#undef Channel_D_DRAMC_AO_BASE_ADDRESS +#define Channel_D_DRAMC_AO_BASE_ADDRESS 0x0 +#undef Channel_A_DRAMC_NAO_BASE_ADDRESS +#define Channel_A_DRAMC_NAO_BASE_ADDRESS 0x10000 +#undef Channel_B_DRAMC_NAO_BASE_ADDRESS +#define Channel_B_DRAMC_NAO_BASE_ADDRESS 0x0 +#undef Channel_C_DRAMC_NAO_BASE_ADDRESS +#define Channel_C_DRAMC_NAO_BASE_ADDRESS 0x0 +#undef Channel_D_DRAMC_NAO_BASE_ADDRESS +#define Channel_D_DRAMC_NAO_BASE_ADDRESS 0x0 +#undef Channel_A_DDRPHY_AO_BASE_ADDRESS +#define Channel_A_DDRPHY_AO_BASE_ADDRESS 0x70000 +#undef Channel_B_DDRPHY_AO_BASE_ADDRESS +#define Channel_B_DDRPHY_AO_BASE_ADDRESS 0x0 +#undef Channel_C_DDRPHY_AO_BASE_ADDRESS +#define Channel_C_DDRPHY_AO_BASE_ADDRESS 0x0 +#undef Channel_D_DDRPHY_AO_BASE_ADDRESS +#define Channel_D_DDRPHY_AO_BASE_ADDRESS 0x0 +#undef Channel_A_DDRPHY_NAO_BASE_ADDRESS +#define Channel_A_DDRPHY_NAO_BASE_ADDRESS 0x80000 +#undef Channel_B_DDRPHY_NAO_BASE_ADDRESS +#define Channel_B_DDRPHY_NAO_BASE_ADDRESS 0x0 +#undef Channel_C_DDRPHY_NAO_BASE_ADDRESS +#define Channel_C_DDRPHY_NAO_BASE_ADDRESS 0x0 +#undef Channel_D_DDRPHY_NAO_BASE_ADDRESS +#define Channel_D_DDRPHY_NAO_BASE_ADDRESS 0x0 +#undef Channel_A_DDRPHY_DPM_BASE_ADDRESS +#define Channel_A_DDRPHY_DPM_BASE_ADDRESS 0x100000 +#undef Channel_B_DDRPHY_DPM_BASE_ADDRESS +#define Channel_B_DDRPHY_DPM_BASE_ADDRESS 0x0 +#endif + +#define CHK_INCLUDE_LOCAL_HEADER "\n ==> Include local header but not one at DV SERVER\n\n" + + +#endif // _A60868_REGISTER_H_ diff --git a/src/vendorcode/mediatek/mt8192/include/dramc_top.h b/src/vendorcode/mediatek/mt8192/include/dramc_top.h new file mode 100644 index 000000000000..d289adc4e4cb --- /dev/null +++ b/src/vendorcode/mediatek/mt8192/include/dramc_top.h @@ -0,0 +1,641 @@ +/* SPDX-License-Identifier: BSD-3-Clause */ + +#ifndef __DRAMC_TOP_H__ +#define __DRAMC_TOP_H__ +#include "dramc_common.h" + +#if !__ETT__ +#if (FOR_DV_SIMULATION_USED==0) +//#define DDR_RESERVE_MODE +#define COMBO_MCP +//#define LAST_DRAMC +//#define VOLTAGE_SEL +//#define ENABLE_DOE +#endif +#endif + +//#define DRAM_BASE 0x40000000ULL +//#define DDR_BASE DRAM_BASE + +#if __ETT__ +#define dramc_crit printf +#define dramc_debug printf +#elif __FLASH_TOOL_DA__ +#define dramc_crit LOGD +#define dramc_debug LOGD +#else +#ifndef dramc_info +#define dramc_info print +#endif +#ifndef dramc_crit +#define dramc_crit print +#endif +#ifndef dramc_debug +#define dramc_debug printf +#endif +#endif + + +#define DRAMC_MAX_CH 2 +#define DRAMC_MAX_RK 2 +#define DRAMC_MR_CNT 4 +#define DRAMC_FREQ_CNT 7 + +struct mr_info_t { + u16 mr_index; + u16 mr_value; +}; + +enum DRAM_TYPE { + DTYPE_DDR1 = 1, + DTYPE_LPDDR2, + DTYPE_LPDDR3, + DTYPE_PCDDR3, + DTYPE_LPDDR4, + DTYPE_LPDDR4X, + DTYPE_LPDDR4P +}; + +extern struct dramc_param *dramc_params; + +int mt_get_dram_type(void); +int get_dram_channel_support_nr(void); +int get_dram_channel_nr(void); +int get_dram_rank_nr(void); +int get_dram_mr_cnt(void); +int get_dram_freq_cnt(void); +#if !__ETT__ +void get_dram_rank_size(u64 dram_rank_size[]); +void get_dram_freq_step(u32 dram_freq_step[]); +void set_dram_mr(unsigned int index, unsigned short value); +unsigned short get_dram_mr(unsigned int index); +void get_dram_mr_info(struct mr_info_t mr_info[]); +void reserve_dramc_dummy_read(void); +#endif +typedef struct _AC_TIMING_EXTERNAL_T +{ + // U 00 + U32 AC_TIME_EMI_FREQUENCY :16; + U32 AC_TIME_EMI_TRAS :8; + U32 AC_TIME_EMI_TRP :8; + + // U 01 + U32 AC_TIME_EMI_TRPAB :8; + U32 AC_TIME_EMI_TRC :8; + U32 AC_TIME_EMI_TRFC :8; + U32 AC_TIME_EMI_TRFCPB :8; + + // U 02 + U32 AC_TIME_EMI_TXP :8; + U32 AC_TIME_EMI_TRTP :8; + U32 AC_TIME_EMI_TRCD :8; + U32 AC_TIME_EMI_TWR :8; + + // U 03 + U32 AC_TIME_EMI_TWTR :8; + U32 AC_TIME_EMI_TRRD :8; + U32 AC_TIME_EMI_TFAW :8; + U32 AC_TIME_EMI_TRTW_ODT_OFF :4; + U32 AC_TIME_EMI_TRTW_ODT_ON :4; + + // U 04 + U32 AC_TIME_EMI_REFCNT :8; //(REFFRERUN = 0) + U32 AC_TIME_EMI_REFCNT_FR_CLK :8; //(REFFRERUN = 1) + U32 AC_TIME_EMI_TXREFCNT :8; + U32 AC_TIME_EMI_TZQCS :8; + + // U 05 + U32 AC_TIME_EMI_TRTPD :8; // LP4/LP3, // Olymp_us new + U32 AC_TIME_EMI_TWTPD :8; // LP4/LP3, // Olymp_us new + U32 AC_TIME_EMI_TMRR2W_ODT_OFF :8; // LP4 // Olymp_us new + U32 AC_TIME_EMI_TMRR2W_ODT_ON :8; // LP4 // Olymp_us new + + // U 06 + // Byte0 + U32 AC_TIME_EMI_TRAS_05T :2; + U32 AC_TIME_EMI_TRP_05T :2; + U32 AC_TIME_EMI_TRPAB_05T :2; + U32 AC_TIME_EMI_TRC_05T :2; + // Byte1 + U32 AC_TIME_EMI_TRFC_05T :2; + U32 AC_TIME_EMI_TRFCPB_05T :2; + U32 AC_TIME_EMI_TXP_05T :2; + U32 AC_TIME_EMI_TRTP_05T :2; + // Byte2 + U32 AC_TIME_EMI_TRCD_05T :2; + U32 AC_TIME_EMI_TWR_05T :2; + U32 AC_TIME_EMI_TWTR_05T :2; // Olymp_us modified + U32 AC_TIME_EMI_TRRD_05T :2; + // Byte3 + U32 AC_TIME_EMI_TFAW_05T :2; + U32 AC_TIME_EMI_TRTW_ODT_OFF_05T :2; + U32 AC_TIME_EMI_TRTW_ODT_ON_05T :2; + U32 AC_TIME_EMI_TRTPD_05T :2; // LP4/LP3 // Olymp_us new + + // U 07 + // Byte0 + U32 AC_TIME_EMI_TWTPD_05T :2; // LP4/LP3 // Olymp_us new + U32 AC_TIME_EMI_TMRR2W_ODT_OFF_05T :2; // Useless, no 0.5T in Olymp_us and Elbr_us + U32 AC_TIME_EMI_TMRR2W_ODT_ON_05T :2; // Useless, no 0.5T in Olymp_us and Elbr_us + + +}AC_TIMING_EXTERNAL_T; + + +typedef struct +{ + unsigned int sub_version; // sub_version: 0x1 for new version + unsigned int type; /* 0x0000 : Invalid + 0x0001 : Discrete DDR1 + 0x0002 : Discrete LPDDR2 + 0x0003 : Discrete LPDDR3 + 0x0004 : Discrete PCDDR3 + 0x0005 : Discrete LPDDR4 + 0x0006 : Discrete LPDR4X + 0x0101 : MCP(NAND+DDR1) + 0x0102 : MCP(NAND+LPDDR2) + 0x0103 : MCP(NAND+LPDDR3) + 0x0104 : MCP(NAND+PCDDR3) + 0x0201 : MCP(eMMC+DDR1) + 0x0202 : MCP(eMMC+LPDDR2) + 0x0203 : MCP(eMMC+LPDDR3) + 0x0204 : MCP(eMMC+PCDDR3) + 0x0205 : MCP(eMMC+LPDDR4) + 0x0206 : MCP(eMMC+LPDR4X) + */ + unsigned int id_length; // EMMC and NAND ID checking length + unsigned int fw_id_length; // FW ID checking length + unsigned char ID[16]; + unsigned char fw_id[8]; // To save fw id + unsigned int EMI_CONA_VAL; //@0x3000 + unsigned int EMI_CONH_VAL; + + union { + unsigned int DRAMC_ACTIME_UNION[8]; + AC_TIMING_EXTERNAL_T AcTimeEMI; + }; + + u64 DRAM_RANK_SIZE[4]; + unsigned int EMI_CONF_VAL; + unsigned int CHN0_EMI_CONA_VAL; + unsigned int CHN1_EMI_CONA_VAL; + /* Single field to store LP4 dram type (normal, byte, mixed) */ + unsigned int dram_cbt_mode_extern; + unsigned int reserved[6]; + +#if 0 + union + { + struct + { + int iLPDDR2_MODE_REG_1; + int iLPDDR2_MODE_REG_2; + int iLPDDR2_MODE_REG_3; + int iLPDDR2_MODE_REG_5; + int iLPDDR2_MODE_REG_10; + int iLPDDR2_MODE_REG_63; + }; + struct + { + int iDDR1_MODE_REG; + int iDDR1_EXT_MODE_REG; + }; + struct + { + int iPCDDR3_MODE_REG0; + int iPCDDR3_MODE_REG1; + int iPCDDR3_MODE_REG2; + int iPCDDR3_MODE_REG3; + }; + struct + { + int iLPDDR3_MODE_REG_1; + int iLPDDR3_MODE_REG_2; + int iLPDDR3_MODE_REG_3; + int iLPDDR3_MODE_REG_5; + int iLPDDR3_MODE_REG_10; + int iLPDDR3_MODE_REG_63; + }; + }; +#else + unsigned int iLPDDR3_MODE_REG_5; +#endif + unsigned int PIN_MUX_TYPE; +} EMI_SETTINGS; + +//typedef EMI_SETTINGS_v15 EMI_SETTINGS; +#if (FOR_DV_SIMULATION_USED==0) +void setup_dramc_voltage_by_pmic(void); +void switch_dramc_voltage_to_auto_mode(void); +#if ! __ETT__ +uint32 mt_set_emis(uint8* emi, uint32 len, bool use_default); //array of emi setting. +#endif +#endif + +extern int emi_setting_index; +extern EMI_SETTINGS emi_settings[]; +extern EMI_SETTINGS default_emi_setting; +extern EMI_SETTINGS emi_setting_default_lpddr3; +extern EMI_SETTINGS emi_setting_default_lpddr4; + +#include "x_hal_io.h" + +#ifdef LAST_DRAMC +#define LAST_DRAMC_MAGIC_PATTERN 0x19870611 +static void update_last_dramc_info(void); +void init_ta2_all_channel(void); +typedef struct { + unsigned int ta2_result_magic; + unsigned int ta2_result_last; + unsigned int ta2_result_past; + unsigned int ta2_result_checksum; + unsigned int reboot_count; + volatile unsigned int last_fatal_err_flag; + volatile unsigned int fatal_err_flag; + volatile unsigned int storage_api_err_flag; + volatile unsigned int last_gating_err[2][2]; // [channel][rank] + volatile unsigned int gating_err[2][2]; // [channel][rank] + unsigned short mr5; + unsigned short mr6; + unsigned short mr7; + unsigned short mr8; +} LAST_DRAMC_INFO_T; +#define DEF_LAST_DRAMC LAST_DRAMC_INFO_T + +#define OFFSET_DRAM_FATAL_ERR (31) +#define OFFSET_DRAM_TA2_ERR (23) +#define OFFSET_DRAM_GATING_ERR (7) +#define OFFSET_CPU_RW_ERR (5) +#define OFFSET_DDR_RSV_MODE_FLOW (4) +#define OFFSET_DDR_RSV_MODE_ERR (3) +#define OFFSET_EMI_DCS_ERR (2) +#define OFFSET_DVFSRC_ERR (1) +#define OFFSET_DRS_ERR (0) + +#define ERR_DRAM_TA2_RK0 (1 << 0) +#define ERR_DRAM_TA2_RK1 (1 << 1) + +#define ERR_DRAM_GATING_RK0_R (1 << 0) +#define ERR_DRAM_GATING_RK0_F (1 << 1) +#define ERR_DRAM_GATING_RK1_R (1 << 2) +#define ERR_DRAM_GATING_RK1_F (1 << 3) + +#define ERR_CPU_RW_RK0 (1 << 0) +#define ERR_CPU_RW_RK1 (1 << 1) + +/* 0x1f -> bit[4:0] is for DDR reserve mode */ +#define DDR_RSV_MODE_ERR_MASK (0x1f) + +unsigned int check_last_dram_fatal_exception(void); +unsigned int check_dram_fatal_exception(void); +void set_err_code_for_storage_api(void); +void dram_fatal_set_ta2_err(unsigned int chn, unsigned int err_code); +void dram_fatal_set_gating_err(unsigned int chn, unsigned int err_code); +void dram_fatal_set_cpu_rw_err(unsigned int err_code); +void dram_fatal_set_stberr(unsigned int chn, unsigned int rk, unsigned int err_code); + +void dram_fatal_backup_stberr(void); +void dram_fatal_init_stberr(void); +void dram_fatal_set_err(unsigned int err_code, unsigned int mask, unsigned int offset); + +#define dram_fatal_set_cpu_rw_err(err_code)\ + do {\ + dram_fatal_set_err(err_code, 0x3, OFFSET_CPU_RW_ERR);\ + } while(0) + +#define dram_fatal_set_ddr_rsv_mode_err()\ + do {\ + dram_fatal_set_err(0x1, 0x1, OFFSET_DDR_RSV_MODE_ERR);\ + } while(0) + +#define dram_fatal_set_emi_dcs_err()\ + do {\ + dram_fatal_set_err(0x1, 0x1, OFFSET_EMI_DCS_ERR);\ + } while(0) + +#define dram_fatal_set_dvfsrc_err()\ + do {\ + dram_fatal_set_err(0x1, 0x1, OFFSET_DVFSRC_ERR);\ + } while(0) + +#define dram_fatal_set_drs_err()\ + do {\ + dram_fatal_set_err(0x1, 0x1, OFFSET_DRS_ERR);\ + } while(0) + +#define dram_fatal_set_ddr_rsv_mode_flow()\ + do {\ + dram_fatal_set_err(0x1, 0x1, OFFSET_DDR_RSV_MODE_FLOW);\ + } while(0) + +#endif //LAST_DRAMC + +typedef enum { + KSHU0 = 0, + KSHU1, + KSHU2, + KSHU3, + KSHU4, + KSHU5, + KSHU6, + KSHU7, + KSHU8, + KSHU9, +} DRAM_KSHU; + +typedef enum { + TYPE_VDRAM = 0, + TYPE_VDDR1, + TYPE_VDDR2, + TYPE_VDDQ, +} TYPE_VOLTAGE; + +typedef enum { + LEVEL_VB = 0, + LEVEL_HV, + LEVEL_NV, + LEVEL_LV, +} LEVEL_VOLTAGE; + +//================================================ +//=============pmic related api for ETT HQA test ============== +//================================================ +#if (__ETT__ || CFG_DRAM_LOG_TO_STORAGE) +#define DRAM_HQA +#endif + +#define MAX_VCORE 1193750 +#define MAX_VDRAM 1300000 +#define MAX_VDDQ 1300000 +#define MAX_VMDDR 2000000 +#define MAX_VIO18 1900000 + +#define UNIT_VCORE 6250 +#define UNIT_VDRAM 5000 +#define UNIT_VDDQ 10000 +#define UNIT_VMDDR 10000 +#define UNIT_VIO18 10000 +#define UNIT_VIO18_STEP 100000 + +#define HQA_VIO18_HV 1950000 +#define HQA_VCORE_HV_LP4_KSHU0_PL 762500 +#define HQA_VCORE_HV_LP4_KSHU1_PL 725000 +#define HQA_VCORE_HV_LP4_KSHU2_PL 700000 +#define HQA_VCORE_HV_LP4_KSHU3_PL 700000 +#define HQA_VCORE_HV_LP4_KSHU4_PL 687500 +#define HQA_VCORE_HV_LP4_KSHU5_PL 687500 +#define HQA_VCORE_HV_LP4_KSHU6_PL 687500 +#define HQA_VCORE_HV_LP4_KSHU0_ETT 762500 +#define HQA_VCORE_HV_LP4_KSHU1_ETT 762500 +#define HQA_VCORE_HV_LP4_KSHU2_ETT 762500 +#define HQA_VCORE_HV_LP4_KSHU3_ETT 762500 +#define HQA_VCORE_HV_LP4_KSHU4_ETT 762500 +#define HQA_VCORE_HV_LP4_KSHU5_ETT 762500 +#define HQA_VCORE_HV_LP4_KSHU6_ETT 762500 +#define HQA_VDRAM_HV_LP4 1170000 +#define HQA_VDDQ_HV_LP4 650000 +#define HQA_VMDDR_HV_LP4 790000 + +#define HQA_VIO18_NV 1800000 +#define HQA_VCORE_NV_LP4_KSHU0_PL 725000 +#define HQA_VCORE_NV_LP4_KSHU1_PL 687500 +#define HQA_VCORE_NV_LP4_KSHU2_PL 662500 +#define HQA_VCORE_NV_LP4_KSHU3_PL 662500 +#define HQA_VCORE_NV_LP4_KSHU4_PL 650000 +#define HQA_VCORE_NV_LP4_KSHU5_PL 650000 +#define HQA_VCORE_NV_LP4_KSHU6_PL 650000 +#define HQA_VCORE_NV_LP4_KSHU0_ETT 725000 +#define HQA_VCORE_NV_LP4_KSHU1_ETT 687500 +#define HQA_VCORE_NV_LP4_KSHU2_ETT 662500 +#define HQA_VCORE_NV_LP4_KSHU3_ETT 662500 +#define HQA_VCORE_NV_LP4_KSHU4_ETT 650000 +#define HQA_VCORE_NV_LP4_KSHU5_ETT 650000 +#define HQA_VCORE_NV_LP4_KSHU6_ETT 650000 +#define HQA_VDRAM_NV_LP4 1125000 +#define HQA_VDDQ_NV_LP4 600000 +#define HQA_VMDDR_NV_LP4 750000 + +#define HQA_VIO18_LV 1730000 +#define HQA_VCORE_LV_LP4_KSHU0_PL 687500 +#define HQA_VCORE_LV_LP4_KSHU1_PL 650000 +#define HQA_VCORE_LV_LP4_KSHU2_PL 625000 +#define HQA_VCORE_LV_LP4_KSHU3_PL 625000 +#define HQA_VCORE_LV_LP4_KSHU4_PL 612500 +#define HQA_VCORE_LV_LP4_KSHU5_PL 612500 +#define HQA_VCORE_LV_LP4_KSHU6_PL 612500 +#define HQA_VCORE_LV_LP4_KSHU0_ETT 687500 +#define HQA_VCORE_LV_LP4_KSHU1_ETT 612500 +#define HQA_VCORE_LV_LP4_KSHU2_ETT 568750 +#define HQA_VCORE_LV_LP4_KSHU3_ETT 568750 +#define HQA_VCORE_LV_LP4_KSHU4_ETT 543750 +#define HQA_VCORE_LV_LP4_KSHU5_ETT 543750 +#define HQA_VCORE_LV_LP4_KSHU6_ETT 543750 +#define HQA_VDRAM_LV_LP4 1060000 +#define HQA_VDDQ_LV_LP4 570000 +#define HQA_VMDDR_LV_LP4 710000 + + +#define _SEL_PREFIX_SHU_PL(type,vol,dtype,shu) HQA_##type##_##vol##_##dtype##_##shu##_PL +#define _SEL_PREFIX_SHU_ETT(type,vol,dtype,shu) HQA_##type##_##vol##_##dtype##_##shu##_ETT +#define _SEL_PREFIX(type,vol,dtype) HQA_##type##_##vol##_##dtype +#define _SEL_VIO18(vol) HQA_VIO18_##vol + +#define STD_VIO18 _SEL_VIO18(NV) +#define STD_VCORE(dtype,shu) _SEL_PREFIX_SHU_PL(VCORE,NV,dtype,shu) +#define STD_VDRAM(dtype) _SEL_PREFIX(VDRAM,NV,dtype) +#define STD_VDDQ _SEL_PREFIX(VDDQ,NV,LP4) +#define STD_VMDDR _SEL_PREFIX(VMDDR,NV,LP4) + +#ifdef DRAM_HQA +//#define HVCORE_HVDRAM +#define NVCORE_NVDRAM +//#define LVCORE_LVDRAM +//#define HVCORE_LVDRAM +//#define LVCORE_HVDRAM + +#if defined(HVCORE_HVDRAM) + #define HQA_VCORE(dtype,shu) _SEL_PREFIX_SHU_PL(VCORE,HV,dtype,shu) + #define HQA_VDRAM(dtype) _SEL_PREFIX(VDRAM,HV,dtype) + #define HQA_VDDQ _SEL_PREFIX(VDDQ,HV,LP4) + #define HQA_VMDDR _SEL_PREFIX(VMDDR,HV,LP4) + #define HQA_VIO18 _SEL_VIO18(HV) +#elif defined(NVCORE_NVDRAM) + #define HQA_VCORE(dtype,shu) _SEL_PREFIX_SHU_PL(VCORE,NV,dtype,shu) + #define HQA_VDRAM(dtype) _SEL_PREFIX(VDRAM,NV,dtype) + #define HQA_VDDQ _SEL_PREFIX(VDDQ,NV,LP4) + #define HQA_VMDDR _SEL_PREFIX(VMDDR,NV,LP4) + #define HQA_VIO18 _SEL_VIO18(NV) +#elif defined(LVCORE_LVDRAM) + #define HQA_VCORE(dtype,shu) _SEL_PREFIX_SHU_PL(VCORE,LV,dtype,shu) + #define HQA_VDRAM(dtype) _SEL_PREFIX(VDRAM,LV,dtype) + #define HQA_VDDQ _SEL_PREFIX(VDDQ,LV,LP4) + #define HQA_VMDDR _SEL_PREFIX(VMDDR,LV,LP4) + #define HQA_VIO18 _SEL_VIO18(LV) +#elif defined(HVCORE_LVDRAM) + #define HQA_VCORE(dtype,shu) _SEL_PREFIX_SHU_PL(VCORE,HV,dtype,shu) + #define HQA_VDRAM(dtype) _SEL_PREFIX(VDRAM,LV,dtype) + #define HQA_VDDQ _SEL_PREFIX(VDDQ,LV,LP4) + #define HQA_VMDDR _SEL_PREFIX(VMDDR,LV,LP4) + #define HQA_VIO18 _SEL_VIO18(LV) +#elif defined(LVCORE_HVDRAM) + #define HQA_VCORE(dtype,shu) _SEL_PREFIX_SHU_PL(VCORE,LV,dtype,shu) + #define HQA_VDRAM(dtype) _SEL_PREFIX(VDRAM,HV,dtype) + #define HQA_VDDQ _SEL_PREFIX(VDDQ,HV,LP4) + #define HQA_VMDDR _SEL_PREFIX(VMDDR,HV,LP4) + #define HQA_VIO18 _SEL_VIO18(HV) +#else + #error "Please set HQA voltage type" +#endif + +#define SEL_PREFIX_VCORE(dtype,shu) HQA_VCORE(dtype,shu) +#define SEL_PREFIX_VDRAM(dtype) HQA_VDRAM(dtype) +#define SEL_PREFIX_VDDQ HQA_VDDQ +#define SEL_PREFIX_VMDDR HQA_VMDDR +#define SEL_VIO18 HQA_VIO18 +#else +#if !__ETT__ +#define VCORE_BIN +#endif +#define SEL_PREFIX_VCORE(dtype,shu) STD_VCORE(dtype,shu) +#define SEL_PREFIX_VDRAM(dtype) STD_VDRAM(dtype) +#define SEL_PREFIX_VDDQ STD_VDDQ +#define SEL_PREFIX_VMDDR STD_VMDDR +#define SEL_VIO18 STD_VIO18 +#endif // #define DRAM_HQA + +#if SUPPORT_SAVE_TIME_FOR_CALIBRATION + +#define PART_DRAM_DATA_SIZE 0x100000 + +#define DRAM_CALIBRATION_DATA_MAGIC 0x9502 + +typedef struct _DRAM_CALIBRATION_HEADER_T +{ + u32 pl_version; + u16 magic_number; + u32 calib_err_code; +} DRAM_CALIBRATION_HEADER_T; + +typedef struct _DRAM_CALIBRATION_MRR_DATA_T +{ + u16 checksum; + u16 emi_checksum; + DRAM_INFO_BY_MRR_T DramInfo; +} DRAM_CALIBRATION_MRR_DATA_T; + +typedef struct _DRAM_CALIBRATION_SHU_DATA_T +{ + u16 checksum; + u32 calib_err_code; + SAVE_TIME_FOR_CALIBRATION_T calibration_data; +} DRAM_CALIBRATION_SHU_DATA_T; + +typedef struct _DRAM_CALIBRATION_DATA_T +{ + DRAM_CALIBRATION_HEADER_T header; + DRAM_CALIBRATION_MRR_DATA_T mrr_info; + DRAM_CALIBRATION_SHU_DATA_T data[DRAM_DFS_SHUFFLE_MAX]; +} DRAM_CALIBRATION_DATA_T; + +/* + * g_dram_storage_api_err_code: + * bit[0:3] -> read api + * bit[4:7] -> write api + * bit[8:11] -> clean api + * bit[12:12] -> data formatted due to fatal exception + */ +#define ERR_NULL_POINTER (0x1) +#define ERR_MAGIC_NUMBER (0x2) +#define ERR_CHECKSUM (0x3) +#define ERR_PL_UPDATED (0x4) +#define ERR_BLKDEV_NOT_FOUND (0x5) +#define ERR_BLKDEV_READ_FAIL (0x6) +#define ERR_BLKDEV_WRITE_FAIL (0x7) +#define ERR_BLKDEV_NO_PART (0x8) + +#define ERR_DATA_FORMATTED_OFFSET (12) + +typedef enum { + DRAM_STORAGE_API_READ = 0, + DRAM_STORAGE_API_WRITE, + DRAM_STORAGE_API_CLEAN, +} DRAM_STORAGE_API_TPYE; + +extern u32 g_dram_storage_api_err_code; +#define SET_DRAM_STORAGE_API_ERR(err_type, api_type) \ +do {\ + g_dram_storage_api_err_code |= (err_type << (api_type * 4));\ +} while(0) + +#define SET_DATA_FORMATTED_STORAGE_API_ERR() \ +do {\ + g_dram_storage_api_err_code |= (1 << ERR_DATA_FORMATTED_OFFSET);\ +} while(0) + +int read_offline_dram_calibration_data(DRAM_DFS_SHUFFLE_TYPE_T shuffle, SAVE_TIME_FOR_CALIBRATION_T *offLine_SaveData); +int write_offline_dram_calibration_data(DRAM_DFS_SHUFFLE_TYPE_T shuffle, SAVE_TIME_FOR_CALIBRATION_T *offLine_SaveData); +int clean_dram_calibration_data(void); + +void dram_fatal_exception_detection_start(void); +void dram_fatal_exception_detection_end(void); + +#define CBT_VREF_OFFSET 2 +#define WRITE_LEVELING_OFFSET 5 +#define GATING_START_OFFSET 0 +#define GATING_PASS_WIN_OFFSET 3 +#define RX_WIN_PERBIT_OFFSET 5 +#define RX_WIN_PERBIT_VREF_OFFSET 4 +#define TX_WIN_PERBIT_OFFSET 5 +#define TX_WIN_PERBIT_VREF_OFFSET 4 +#define RX_DATLAT_OFFSET 1 +#define RX_WIN_HIGH_SPEED_TH 10 +#define RX_WIN_LOW_SPEED_TH 100 +#define TX_WIN_TH 12 + +#endif + +#if defined(SLT) + +#define SLT_ERR_NO_DATA (-1) +#define SLT_ERR_NO_DEV (-2) +#define SLT_ERR_NO_ADDR (-3) +#define SLT_ERR_WRITE_FAIL (-4) +#define SLT_ERR_READ_FAIL (-5) + +typedef struct _DRAM_SLT_HEADER_T +{ + u32 pl_version; + int stage_status; +} DRAM_SLT_HEADER_T; + +typedef struct _DRAM_SLT_DATA_T +{ + DRAM_SLT_HEADER_T header; + u32 test_result[10]; +} DRAM_SLT_DATA_T; + +int read_slt_data(DRAM_SLT_DATA_T *data); +int write_slt_data(DRAM_SLT_DATA_T *data); +int clean_slt_data(void); + +#endif + +int doe_get_config(const char* feature); +unsigned long long get_dram_size(void); + +typedef struct { + unsigned long long full_sys_addr; + unsigned int addr; + unsigned int row; + unsigned int col; + unsigned char ch; + unsigned char rk; + unsigned char bk; + unsigned char dummy; +} dram_addr_t; + +unsigned int get_dramc_addr(dram_addr_t *dram_addr, unsigned int offset); +unsigned int get_dummy_read_addr(dram_addr_t *dram_addr); +unsigned int is_discrete_lpddr4(void); + +#endif /* __DRAMC_TOP_H__ */ diff --git a/src/vendorcode/mediatek/mt8192/include/dramc_typedefs.h b/src/vendorcode/mediatek/mt8192/include/dramc_typedefs.h new file mode 100644 index 000000000000..5f92525ab48e --- /dev/null +++ b/src/vendorcode/mediatek/mt8192/include/dramc_typedefs.h @@ -0,0 +1,113 @@ +/* SPDX-License-Identifier: BSD-3-Clause */ + +#ifndef _DRAMC_TYPEDEFS_H_ +#define _DRAMC_TYPEDEFS_H_ + +#include <stdint.h> + +#define IMPORT EXTERN +#ifndef __cplusplus + #define EXTERN extern +#else + #define EXTERN extern "C" +#endif +#define LOCAL static +#define GLOBAL +#define EXPORT GLOBAL + + +#define EQ == +#define NEQ != +#define AND && +#define OR || +#define XOR(A,B) ((!(A) AND (B)) OR ((A) AND !(B))) + +#ifndef FALSE +#define FALSE 0 +#endif + +#ifndef TRUE +#define TRUE 1 +#endif + +#if 0 +#define ASSERT(expr) \ + do{ if(!(expr)){while(1);} }while(0) +#endif + +#ifndef BOOL +typedef unsigned char BOOL; +#endif + +typedef unsigned long ulong; +typedef unsigned char uchar; +typedef unsigned int uint; +typedef signed char int8; +typedef signed short int16; +typedef signed long int32; +typedef signed int intx; +typedef unsigned char uint8; +typedef unsigned short uint16; +typedef unsigned long uint32; +typedef unsigned int uintx; + +typedef signed char S8; +typedef signed short S16; +typedef signed int S32; +typedef signed long long S64; + +typedef unsigned char U8; +typedef unsigned short U16; +typedef unsigned int U32; +typedef unsigned long long U64; + +typedef unsigned char US8; +typedef unsigned short US16; +typedef unsigned int US32; +typedef unsigned long long US64; + +typedef unsigned char u8; +typedef unsigned short u16; +typedef unsigned int u32; +typedef unsigned long long u64; + +typedef unsigned char UINT8; +typedef unsigned short UINT16; +typedef unsigned int UINT32; +typedef unsigned short USHORT; +typedef signed char INT8; +typedef signed short INT16; +typedef signed int INT32; + +typedef volatile signed char *P_S8; +typedef volatile signed short *P_S16; +typedef volatile signed int *P_S32; + +typedef long LONG; +typedef unsigned char UBYTE; +typedef short SHORT; + +typedef unsigned int *UINT32P; +typedef volatile unsigned short *UINT16P; +typedef volatile unsigned char *UINT8P; +typedef unsigned char *U8P; + +typedef volatile unsigned char *P_U8; +typedef volatile unsigned short *P_U16; +typedef volatile unsigned int *P_U32; +typedef unsigned long long *P_U64; +typedef signed long long *P_S64; + +typedef unsigned int uint; + +typedef void VOID; +typedef unsigned char BYTE; +typedef float FLOAT; + + +#if FOR_DV_SIMULATION_USED +#include <stdio.h> +#include <string.h> +#endif + +#endif diff --git a/src/vendorcode/mediatek/mt8192/include/emi.h b/src/vendorcode/mediatek/mt8192/include/emi.h new file mode 100644 index 000000000000..e94f74161faa --- /dev/null +++ b/src/vendorcode/mediatek/mt8192/include/emi.h @@ -0,0 +1,68 @@ +/* SPDX-License-Identifier: BSD-3-Clause */ + +#ifndef __EMI_H__ +#define __EMI_H__ + +#include <soc/addressmap.h> +#include <dramc_top.h> + +#define EMI_APB_BASE EMI_BASE + +#if __ETT__ +#define emi_log printf +#elif __FLASH_TOOL_DA__ +#define emi_log LOGD +#else +#define emi_log(_x_...) printk(BIOS_INFO, _x_) +#endif + +struct isu_info_t { + unsigned int buf_size; + unsigned long long buf_addr; + unsigned long long ver_addr; + unsigned long long con_addr; +}; + +#define EMI_ISU_BUF_SIZE 0x800000 +#define LAST_EMI_MAGIC_PATTERN 0x19870611 +typedef struct { + unsigned int isu_magic; + unsigned int isu_ctrl; + unsigned int isu_dram_type; + unsigned int isu_diff_us; + unsigned int isu_buf_l; + unsigned int isu_buf_h; + unsigned int isu_version; + unsigned int snst_last; + unsigned int snst_past; + unsigned int os_flag_sspm; + unsigned int os_flag_ap; +} LAST_EMI_INFO_T; +#define DEF_LAST_EMI LAST_EMI_INFO_T + +void emi_init(void); +void emi_init2(void); +void clr_emi_mpu_prot(void); +void dis_emi_apb_prot(void); +int get_row_width_by_emi(unsigned int rank); +int get_channel_nr_by_emi(void); +int get_rank_nr_by_emi(void); +void get_rank_size_by_emi(unsigned long long dram_rank_size[DRAMC_MAX_RK]); +void set_cen_emi_cona(unsigned int cona_val); +void set_cen_emi_conf(unsigned int conf_val); +void set_cen_emi_conh(unsigned int conh_val); +void set_chn_emi_cona(unsigned int cona_val); +void set_chn_emi_conc(unsigned int conc_val); +unsigned int get_cen_emi_cona(void); +unsigned int get_chn_emi_cona(void); +void phy_addr_to_dram_addr(dram_addr_t *dram_addr, unsigned long long phy_addr); +unsigned int set_emi_before_rank1_mem_test(void); +void restore_emi_after_rank1_mem_test(void); +void get_emi_isu_info(struct isu_info_t *isu_info_ptr); +void reserve_emi_isu_buf(void); +void reserve_emi_mbist_buf(void); +void record_emi_snst(void); +unsigned long long platform_memory_size(void); + +#endif /* __EMI_H__ */ + diff --git a/src/vendorcode/mediatek/mt8192/include/emi_hw.h b/src/vendorcode/mediatek/mt8192/include/emi_hw.h new file mode 100644 index 000000000000..f19e1fdf2cb0 --- /dev/null +++ b/src/vendorcode/mediatek/mt8192/include/emi_hw.h @@ -0,0 +1,233 @@ +/* SPDX-License-Identifier: BSD-3-Clause */ + +#ifndef __EMI_HW_H__ +#define __EMI_HW_H__ + +/* from EMI golden setting */ +#define MARGAUX_EMI_MP_SETTING +#define MARGAUX_REAL_CHIP_EMI_GOLDEN_SETTING +//#define INFRA_DRAMC_REG_CONFIG (INFRACFG_AO_BASE + 0xB4) +//#define INFRACFG_AO_MEM_BASE (0x10002000) +//#define SUB_INFRACFG_AO_MEM_BASE (0x1030E000) +//#define MCUSYS_PAR_WRAP_BASE (0x0C530000) + +//#define EMI_BASE (0x10219000) +//#define EMI_MPU_BASE (0x10226000) +#define CHN0_EMI_BASE (IO_PHYS + 0x235000) +#define CHN1_EMI_BASE (IO_PHYS + 0x245000) + +#define EMI_CONA (EMI_BASE+0x000) +#define EMI_CONB (EMI_BASE+0x008) +#define EMI_CONC (EMI_BASE+0x010) +#define EMI_COND (EMI_BASE+0x018) +#define EMI_CONE (EMI_BASE+0x020) +#define EMI_CONF (EMI_BASE+0x028) +#define EMI_CONG (EMI_BASE+0x030) +#define EMI_CONH (EMI_BASE+0x038) +#define EMI_CONH_2ND (EMI_BASE+0x03C) +#define EMI_CONI (EMI_BASE+0x040) +#define EMI_CONJ (EMI_BASE+0x048) +#define EMI_CONM (EMI_BASE+0x060) +#define EMI_CONN (EMI_BASE+0x068) +#define EMI_CONO (EMI_BASE+0x070) +#define EMI_MDCT (EMI_BASE+0x078) +#define EMI_MDCT_2ND (EMI_BASE+0x07C) +#define EMI_IOCL (EMI_BASE+0x0D0) +#define EMI_IOCL_2ND (EMI_BASE+0x0D4) +#define EMI_IOCM (EMI_BASE+0x0D8) +#define EMI_IOCM_2ND (EMI_BASE+0x0DC) +#define EMI_TESTB (EMI_BASE+0x0E8) +#define EMI_TESTC (EMI_BASE+0x0F0) +#define EMI_TESTD (EMI_BASE+0x0F8) +#define EMI_ARBA (EMI_BASE+0x100) +#define EMI_ARBB (EMI_BASE+0x108) +#define EMI_ARBC (EMI_BASE+0x110) +#define EMI_ARBD (EMI_BASE+0x118) +#define EMI_ARBE (EMI_BASE+0x120) +#define EMI_ARBF (EMI_BASE+0x128) +#define EMI_ARBG (EMI_BASE+0x130) +#define EMI_ARBH (EMI_BASE+0x138) +#define EMI_ARBI (EMI_BASE+0x140) +#define EMI_ARBI_2ND (EMI_BASE+0x144) +#define EMI_ARBJ_2ND (EMI_BASE+0x14C) +#define EMI_ARBK (EMI_BASE+0x150) +#define EMI_ARBK_2ND (EMI_BASE+0x154) +#define EMI_SLCT (EMI_BASE+0x158) +#define EMI_MPUD0_ST (EMI_BASE+0x160) +#define EMI_MPUD1_ST (EMI_BASE+0x164) +#define EMI_MPUD2_ST (EMI_BASE+0x168) +#define EMI_MPUD3_ST (EMI_BASE+0x16C) +#define EMI_MPUD4_ST (EMI_BASE+0x170) +#define EMI_MPUD5_ST (EMI_BASE+0x174) +#define EMI_MPUD6_ST (EMI_BASE+0x178) +#define EMI_MPUD7_ST (EMI_BASE+0x17C) +#define EMI_MPUD8_ST (EMI_BASE+0x180) +#define EMI_MPUD9_ST (EMI_BASE+0x184) +#define EMI_MPUD10_ST (EMI_BASE+0x188) +#define EMI_MPUD11_ST (EMI_BASE+0x18C) +#define EMI_MPUD12_ST (EMI_BASE+0x190) +#define EMI_MPUD13_ST (EMI_BASE+0x194) +#define EMI_MPUD14_ST (EMI_BASE+0x198) +#define EMI_MPUD15_ST (EMI_BASE+0x19C) +#define EMI_MPUD16_ST (EMI_BASE+0x1A0) +#define EMI_MPUD17_ST (EMI_BASE+0x1A4) +#define EMI_MPUD18_ST (EMI_BASE+0x1A8) +#define EMI_MPUD19_ST (EMI_BASE+0x1AC) +#define EMI_MPUD20_ST (EMI_BASE+0x1B0) +#define EMI_MPUD21_ST (EMI_BASE+0x1B4) +#define EMI_MPUD22_ST (EMI_BASE+0x1B8) +#define EMI_MPUD23_ST (EMI_BASE+0x1BC) +#define EMI_MPUD24_ST (EMI_BASE+0x1C0) +#define EMI_MPUD25_ST (EMI_BASE+0x1C4) +#define EMI_MPUD26_ST (EMI_BASE+0x1C8) +#define EMI_MPUD27_ST (EMI_BASE+0x1CC) +#define EMI_MPUD28_ST (EMI_BASE+0x1D0) +#define EMI_MPUD29_ST (EMI_BASE+0x1D4) +#define EMI_MPUD30_ST (EMI_BASE+0x1D8) +#define EMI_MPUD31_ST (EMI_BASE+0x1DC) +#define EMI_MPUS (EMI_BASE+0x1F0) +#define EMI_MPUT (EMI_BASE+0x1F8) +#define EMI_MPUT_2ND (EMI_BASE+0x1FC) +#define EMI_D0_ST2 (EMI_BASE+0x200) +#define EMI_D1_ST2 (EMI_BASE+0x204) +#define EMI_D2_ST2 (EMI_BASE+0x208) +#define EMI_D3_ST2 (EMI_BASE+0x20C) +#define EMI_D4_ST2 (EMI_BASE+0x210) +#define EMI_D5_ST2 (EMI_BASE+0x214) +#define EMI_D6_ST2 (EMI_BASE+0x218) +#define EMI_D7_ST2 (EMI_BASE+0x21C) +#define EMI_D8_ST2 (EMI_BASE+0x220) +#define EMI_D9_ST2 (EMI_BASE+0x224) +#define EMI_D10_ST2 (EMI_BASE+0x228) +#define EMI_D11_ST2 (EMI_BASE+0x22C) +#define EMI_D12_ST2 (EMI_BASE+0x230) +#define EMI_D13_ST2 (EMI_BASE+0x234) +#define EMI_D14_ST2 (EMI_BASE+0x238) +#define EMI_D15_ST2 (EMI_BASE+0x23C) +#define EMI_D16_ST2 (EMI_BASE+0x240) +#define EMI_D17_ST2 (EMI_BASE+0x244) +#define EMI_D18_ST2 (EMI_BASE+0x248) +#define EMI_D19_ST2 (EMI_BASE+0x24C) +#define EMI_D20_ST2 (EMI_BASE+0x250) +#define EMI_D21_ST2 (EMI_BASE+0x254) +#define EMI_D22_ST2 (EMI_BASE+0x258) +#define EMI_D23_ST2 (EMI_BASE+0x25C) +#define EMI_D24_ST2 (EMI_BASE+0x260) +#define EMI_D25_ST2 (EMI_BASE+0x264) +#define EMI_D26_ST2 (EMI_BASE+0x268) +#define EMI_D27_ST2 (EMI_BASE+0x26C) +#define EMI_D28_ST2 (EMI_BASE+0x270) +#define EMI_D29_ST2 (EMI_BASE+0x274) +#define EMI_D30_ST2 (EMI_BASE+0x278) +#define EMI_D31_ST2 (EMI_BASE+0x27C) +#define EMI_BMEN (EMI_BASE+0x400) +#define EMI_BSTP (EMI_BASE+0x404) +#define EMI_BCNT (EMI_BASE+0x408) +#define EMI_TACT (EMI_BASE+0x410) +#define EMI_TSCT (EMI_BASE+0x418) +#define EMI_WACT (EMI_BASE+0x420) +#define EMI_WSCT (EMI_BASE+0x428) +#define EMI_BACT (EMI_BASE+0x430) +#define EMI_BSCT (EMI_BASE+0x438) +#define EMI_MSEL (EMI_BASE+0x440) +#define EMI_TSCT2 (EMI_BASE+0x448) +#define EMI_TSCT3 (EMI_BASE+0x450) +#define EMI_WSCT2 (EMI_BASE+0x458) +#define EMI_WSCT3 (EMI_BASE+0x460) +#define EMI_WSCT4 (EMI_BASE+0x464) +#define EMI_MSEL2 (EMI_BASE+0x468) +#define EMI_MSEL3 (EMI_BASE+0x470) +#define EMI_MSEL4 (EMI_BASE+0x478) +#define EMI_MSEL5 (EMI_BASE+0x480) +#define EMI_MSEL6 (EMI_BASE+0x488) +#define EMI_MSEL7 (EMI_BASE+0x490) +#define EMI_MSEL8 (EMI_BASE+0x498) +#define EMI_MSEL9 (EMI_BASE+0x4A0) +#define EMI_MSEL10 (EMI_BASE+0x4A8) +#define EMI_BMID0 (EMI_BASE+0x4B0) +#define EMI_BMID1 (EMI_BASE+0x4B4) +#define EMI_BMID2 (EMI_BASE+0x4B8) +#define EMI_BMID3 (EMI_BASE+0x4BC) +#define EMI_BMID4 (EMI_BASE+0x4C0) +#define EMI_BMID5 (EMI_BASE+0x4C4) +#define EMI_BMID6 (EMI_BASE+0x4C8) +#define EMI_BMID7 (EMI_BASE+0x4CC) +#define EMI_BMID8 (EMI_BASE+0x4D0) +#define EMI_BMID9 (EMI_BASE+0x4D4) +#define EMI_BMID10 (EMI_BASE+0x4D8) +#define EMI_BMEN1 (EMI_BASE+0x4E0) +#define EMI_BMEN2 (EMI_BASE+0x4E8) +#define EMI_BMRW0 (EMI_BASE+0x4F8) +#define EMI_BMRW1 (EMI_BASE+0x4FC) +#define EMI_TTYPE1 (EMI_BASE+0x500) +#define EMI_TTYPE2 (EMI_BASE+0x508) +#define EMI_TTYPE3 (EMI_BASE+0x510) +#define EMI_TTYPE4 (EMI_BASE+0x518) +#define EMI_TTYPE5 (EMI_BASE+0x520) +#define EMI_TTYPE6 (EMI_BASE+0x528) +#define EMI_TTYPE7 (EMI_BASE+0x530) +#define EMI_TTYPE8 (EMI_BASE+0x538) +#define EMI_TTYPE9 (EMI_BASE+0x540) +#define EMI_TTYPE10 (EMI_BASE+0x548) +#define EMI_TTYPE11 (EMI_BASE+0x550) +#define EMI_TTYPE12 (EMI_BASE+0x558) +#define EMI_TTYPE13 (EMI_BASE+0x560) +#define EMI_TTYPE14 (EMI_BASE+0x568) +#define EMI_TTYPE15 (EMI_BASE+0x570) +#define EMI_TTYPE16 (EMI_BASE+0x578) +#define EMI_TTYPE17 (EMI_BASE+0x580) +#define EMI_TTYPE18 (EMI_BASE+0x588) +#define EMI_TTYPE19 (EMI_BASE+0x590) +#define EMI_TTYPE20 (EMI_BASE+0x598) +#define EMI_TTYPE21 (EMI_BASE+0x5A0) +#define EMI_BWCT0 (EMI_BASE+0x5B0) +#define EMI_BWCT1 (EMI_BASE+0x5B4) +#define EMI_BWCT2 (EMI_BASE+0x5B8) +#define EMI_BWCT3 (EMI_BASE+0x5BC) +#define EMI_BWCT4 (EMI_BASE+0x5C0) +#define EMI_BWST0 (EMI_BASE+0x5C4) +#define EMI_BWST1 (EMI_BASE+0x5C8) +#define EMI_EX_CON (EMI_BASE+0x5D0) +#define EMI_EX_ST0 (EMI_BASE+0x5D4) +#define EMI_EX_ST1 (EMI_BASE+0x5D8) +#define EMI_EX_ST2 (EMI_BASE+0x5DC) +#define EMI_WP_ADR (EMI_BASE+0x5E0) +#define EMI_WP_ADR_2ND (EMI_BASE+0x5E4) +#define EMI_WP_CTRL (EMI_BASE+0x5E8) +#define EMI_CHKER (EMI_BASE+0x5F0) +#define EMI_CHKER_TYPE (EMI_BASE+0x5F4) +#define EMI_CHKER_ADR (EMI_BASE+0x5F8) +#define EMI_CHKER_ADR_2ND (EMI_BASE+0x5FC) +#define EMI_BWCT0_2ND (EMI_BASE+0x6A0) +#define EMI_LTCT0_2ND (EMI_BASE+0x750) +#define EMI_LTCT1_2ND (EMI_BASE+0x754) +#define EMI_LTCT2_2ND (EMI_BASE+0x758) +#define EMI_LTCT3_2ND (EMI_BASE+0x75C) +#define EMI_BWCT0_3RD (EMI_BASE+0x770) +#define EMI_BWCT0_4TH (EMI_BASE+0x780) +#define EMI_BWCT0_5TH (EMI_BASE+0x7B0) +#define EMI_BWCT0_6TH (EMI_BASE+0x7C8) +#define EMI_SNST (EMI_BASE+0x7F8) +#define EMI_SLVA (EMI_BASE+0x800) +#define EMI_THRO_CTRL1 (EMI_BASE+0x858) +#define EMI_AXI_BIST_ADR0 (EMI_BASE+0x98c) +#define EMI_AXI_BIST_ADR1 (EMI_BASE+0x990) +#define EMI_AXI_BIST_ADR2 (EMI_BASE+0x994) + +#define EMI_MPU_CTRL (EMI_MPU_BASE+0x000) +#define EMI_MPU_DBG (EMI_MPU_BASE+0x004) +#define EMI_MPU_SA0 (EMI_MPU_BASE+0x100) +#define EMI_MPU_EA0 (EMI_MPU_BASE+0x200) +#define EMI_MPU_SA(region) (EMI_MPU_SA0 + (region*4)) +#define EMI_MPU_EA(region) (EMI_MPU_EA0 + (region*4)) +#define EMI_MPU_APC0 (EMI_MPU_BASE+0x300) +#define EMI_MPU_APC(region, dgroup) (EMI_MPU_APC0 + (region*4) + ((dgroup)*0x100)) +#define EMI_MPU_CTRL_D0 (EMI_MPU_BASE+0x800) +#define EMI_MPU_CTRL_D(domain) (EMI_MPU_CTRL_D0 + (domain*4)) +#define EMI_RG_MASK_D0 (EMI_MPU_BASE+0x900) +#define EMI_RG_MASK_D(domain) (EMI_RG_MASK_D0 + (domain*4)) + +#define CHN_EMI_CONA(base) (base + 0x000) +#define CHN_EMI_CONC(base) (base + 0x010) + +#endif // __EMI_HW_H__ diff --git a/src/vendorcode/mediatek/mt8192/include/emi_mpu_mt.h b/src/vendorcode/mediatek/mt8192/include/emi_mpu_mt.h new file mode 100644 index 000000000000..bbd0730d97c4 --- /dev/null +++ b/src/vendorcode/mediatek/mt8192/include/emi_mpu_mt.h @@ -0,0 +1,17 @@ +/* SPDX-License-Identifier: BSD-3-Clause */ + +#ifndef __EMI_MPU_MT_H__ +#define __EMI_MPU_MT_H__ + +#define ENABLE_MPU 1 + +#define EMI_MPU_ALIGN_BITS 16 +#define EMI_MPU_DOMAIN_NUM 16 +#define EMI_MPU_REGION_NUM 32 +#define DRAM_OFFSET (0x40000000 >> EMI_MPU_ALIGN_BITS) + +#define SSPM_MPU_REGION_ID 4 + +#include <emi_mpu_v1.h> + +#endif /* __EMI_MPU_MT_H__ */ diff --git a/src/vendorcode/mediatek/mt8192/include/emi_mpu_v1.h b/src/vendorcode/mediatek/mt8192/include/emi_mpu_v1.h new file mode 100644 index 000000000000..51b835607ac4 --- /dev/null +++ b/src/vendorcode/mediatek/mt8192/include/emi_mpu_v1.h @@ -0,0 +1,51 @@ +/* SPDX-License-Identifier: BSD-3-Clause */ + +#ifndef __EMI_MPU_H__ +#define __EMI_MPU_H__ + +#include <emi_mpu_mt.h> + +#define NO_PROTECTION 0 +#define SEC_RW 1 +#define SEC_RW_NSEC_R 2 +#define SEC_RW_NSEC_W 3 +#define SEC_R_NSEC_R 4 +#define FORBIDDEN 5 +#define SEC_R_NSEC_RW 6 + +#define LOCK 1 +#define UNLOCK 0 + +#define EMI_MPU_DGROUP_NUM (EMI_MPU_DOMAIN_NUM / 8) +#if (EMI_MPU_DGROUP_NUM == 1) +#define SET_ACCESS_PERMISSION(apc_ary, lock, d7, d6, d5, d4, d3, d2, d1, d0) \ +do { \ + apc_ary[0] = \ + (((unsigned int) d7) << 21) | (((unsigned int) d6) << 18) | (((unsigned int) d5) << 15) | \ + (((unsigned int) d4) << 12) | (((unsigned int) d3) << 9) | (((unsigned int) d2) << 6) | \ + (((unsigned int) d1) << 3) | ((unsigned int) d0) | ((unsigned int) lock << 31); \ +} while (0) +#elif (EMI_MPU_DGROUP_NUM == 2) +#define SET_ACCESS_PERMISSION(apc_ary, lock, d15, d14, d13, d12, d11, d10, d9, d8, d7, d6, d5, d4, d3, d2, d1, d0) \ +do { \ + apc_ary[1] = \ + (((unsigned int) d15) << 21) | (((unsigned int) d14) << 18) | (((unsigned int) d13) << 15) | \ + (((unsigned int) d12) << 12) | (((unsigned int) d11) << 9) | (((unsigned int) d10) << 6) | \ + (((unsigned int) d9) << 3) | ((unsigned int) d8); \ + apc_ary[0] = \ + (((unsigned int) d7) << 21) | (((unsigned int) d6) << 18) | (((unsigned int) d5) << 15) | \ + (((unsigned int) d4) << 12) | (((unsigned int) d3) << 9) | (((unsigned int) d2) << 6) | \ + (((unsigned int) d1) << 3) | ((unsigned int) d0) | ((unsigned int) lock << 31); \ +} while (0) +#endif + +struct emi_region_info_t { + unsigned long long start; + unsigned long long end; + unsigned int region; + unsigned int apc[EMI_MPU_DGROUP_NUM]; +}; + +extern int emi_mpu_set_protection(struct emi_region_info_t *region_info); + +#endif /* __EMI_MPU_H__ */ diff --git a/src/vendorcode/mediatek/mt8192/include/memory.h b/src/vendorcode/mediatek/mt8192/include/memory.h new file mode 100644 index 000000000000..1a981435e8d6 --- /dev/null +++ b/src/vendorcode/mediatek/mt8192/include/memory.h @@ -0,0 +1,32 @@ +/* SPDX-License-Identifier: BSD-3-Clause */ + +#ifndef MT6516_MEMORY_H +#define MT6516_MEMORY_H + +#include <stdint.h> + +/************************************************************************** +* DEBUG CONTROL +**************************************************************************/ +#define MEM_TEST (1) + +// do not change the test size !!!! +#define MEM_TEST_SIZE (0x2000) + +/************************************************************************** +* DRAM SIZE +**************************************************************************/ +#define E1_DRAM_SIZE (0x10000000) +#define E2_DRAM_SIZE (0x08000000) + +/************************************************************************** +* EXPOSED API +**************************************************************************/ +extern u32 mt6516_get_hardware_ver (void); +extern void mt6516_mem_init (void); + +#if MEM_TEST +extern int complex_mem_test (unsigned int start, unsigned int len); +#endif + +#endif diff --git a/src/vendorcode/mediatek/mt8192/include/print.h b/src/vendorcode/mediatek/mt8192/include/print.h new file mode 100644 index 000000000000..78fc840d6fde --- /dev/null +++ b/src/vendorcode/mediatek/mt8192/include/print.h @@ -0,0 +1,12 @@ +/* SPDX-License-Identifier: BSD-3-Clause */ + +#ifndef PRINT_H +#define PRINT_H + +#include <console/console.h> + +//int print(const char *fmt, ...); +#define print(_x_...) printk(BIOS_INFO, _x_) +#define printf print + +#endif diff --git a/src/vendorcode/mediatek/mt8192/include/reg.h b/src/vendorcode/mediatek/mt8192/include/reg.h new file mode 100644 index 000000000000..9d3216e87590 --- /dev/null +++ b/src/vendorcode/mediatek/mt8192/include/reg.h @@ -0,0 +1,11 @@ +/* SPDX-License-Identifier: BSD-3-Clause */ + +#ifndef REG_H +#define REG_H + +#define REG32(addr) ((volatile uint32_t *)(uintptr_t)(addr)) + +#define read32(addr) (*REG32(addr)) +#define write32(addr, val) (*REG32(addr) = (val)) + +#endif diff --git a/src/vendorcode/mediatek/mt8192/include/sv_c_data_traffic.h b/src/vendorcode/mediatek/mt8192/include/sv_c_data_traffic.h new file mode 100644 index 000000000000..5f48baeb5f89 --- /dev/null +++ b/src/vendorcode/mediatek/mt8192/include/sv_c_data_traffic.h @@ -0,0 +1,313 @@ +/* SPDX-License-Identifier: BSD-3-Clause */ + +#ifndef __SV_C_DATA_TRAFFIC_H +#define __SV_C_DATA_TRAFFIC_H + +//#define STRINGIFY(x) #x +#define TOSTRING(x) STRINGIFY(x) + +#define print_svarg(arg) \ +({ \ + mcSHOW_DBG_MSG((TOSTRING(arg) "=0x%x\n", psra->arg)); \ +}) + +/* + * channel type from sv's view + */ +enum { + SV_CHN_A = 0, + SV_CHN_B +}; + + +/* + * dram type from sv's view + */ +enum { + SV_LPDDR = 0, + SV_LPDDR2, + SV_PCDDR3, + SV_LPDDR3, + SV_LPDDR4, + SV_LPDDR5 +}; + +/* + * data rate from sv's view + */ +enum { + SV_DDR4266 = 0, + SV_DDR3200, + SV_DDR1600, + SV_DDR3733, + SV_DDR2400, + SV_DDR1866, + SV_DDR1200, + SV_DDR1333, + SV_DDR800, + SV_DDR1066, + SV_DDR2667, + SV_DDR4800, + SV_DDR5500, + SV_DDR6000, + SV_DDR6400, + SV_DDR2750, + SV_DDR2133 +}; + +/* + * cal_sv_rand_args is data traffic from sv to c. + * sv randomizes these arguments for c to control + * calibration. + */ +typedef struct cal_sv_rand_args { + +/* >>>>>>>>>> common part begin>>>>>>>>>> */ + /* + * 0x4C503435 + * "LP45" + */ + int magic; + + /* + * 0: channel-a + * 1: channel-b + */ + int calibration_channel; + + /* + * 0: rank0 + * 1: rank1 + */ + int calibration_rank; + + /* + * 0: LPDDR + * 1: LPDDR2 + * 2: PCDDR3 + * 3: LPDDR3 + * 4: LPDDR4 + * 5: LPDDR5 + */ + int dram_type; + + /* + * 0: DDR4266 + * 1: DDR3200 + * 2: DDR1600 + * 3: DDR3733 + * 4: DDR2400 + * 5: DDR1866 + * 6: DDR1200 + * 7: DDR1333 + * 8: DDR800 + * 9: DDR1066 + * 10: DDR2667 + * 11: DDR4800 + * 12: DDR5500 + * 13: DDR6000 + * 14: DDR6400 + * 15: DDR2750 + * 16: DDR2133 + */ + int datarate; + + /* + * Data Mask Disable + * 0: enable + * 1: disable + */ + int dmd; + int mr2_value; /* for lp4-wirteleveling*/ + int mr3_value; + int mr13_value; + int mr12_value; + int mr16_value; + int mr18_value; /* lp5 writeleveling */ + int mr20_value; /* lp5 rddqc */ +/* ============================= */ + + +/* >>>>>>>>>> cbt part begin>>>>>>>>>> */ + /* + * 0: doesn't run cbt calibration + * 1: run cbt calibration + */ + int cbt; + + /* + * 0: rising phase + * 1: falling phase + */ + int cbt_phase; + + /* + * 0: training mode1 + * 1: training mode2 + */ + int cbt_training_mode; + + /* + * 0: normal mode + * 1: byte mode + */ + int rk0_cbt_mode; + + /* + * 0: normal mode + * 1: byte mode + */ + int rk1_cbt_mode; + + /* + * 0: cbt does NOT use autok + * 1: cbt use autok + */ + int cbt_autok; + + /* + * autok respi + * 0/1/2/3 + */ + int cbt_atk_respi; + + /* + * 0: cbt does NOT use new cbt mode + * 1: cbt use new cbt mode + */ + int new_cbt_mode; + + /* + * cbt pat0~7v + */ + int pat_v[8]; + + /* + * cbt pat0~7a + */ + int pat_a[8]; + + /* + * cbt pat_dmv + */ + int pat_dmv; + + /* + * cbt pat_dma + */ + int pat_dma; + + /* + * cbt pat_cs + */ + int pat_cs; + + /* + * new cbt cagolden sel + */ + int cagolden_sel; + + /* + * new cbt invert num + */ + int invert_num; + +/* ============================= */ + +/* >>>>>>>>>> wl part begin>>>>>>>>>> */ + /* + * 0: doesn't run wl calibration + * 1: run wl calibration + */ + int wl; + + /* + * 0: wl does NOT use autok + * 1: wl use autok + */ + int wl_autok; + + /* + * autok respi + * 0/1/2/3 + */ + int wl_atk_respi; +/* ============================= */ + +/* >>>>>>>>>> Gating part begin >>>>>> */ + /* + * 0: does not run gating calibration + * 1: run gating calibration + */ + int gating; + + /* + * 0: SW mode calibration + * 1: HW AUTO calibration + */ + int gating_autok; + + int dqsien_autok_pi_offset; + int dqsien_autok_early_break_en; + int dqsien_autok_dbg_mode_en; +/* ============================= */ + +/* >>>>>>>>>> RDDQC part begin >>>>>> */ + /* + * 0: does not run rddq calibration + * 1: run rddq calibration + */ + int rddqc; + + int low_byte_invert_golden; + int upper_byte_invert_golden; + int mr_dq_a_golden; + int mr_dq_b_golden; + int lp5_mr20_6_golden; + int lp5_mr20_7_golden; +/* ============================= */ + +/* >>>>>>>>>> TX perbit part begin >>>>>> */ + /* + * 0: does not run txperbit calibration + * 1: run txperbit calibration + */ + int tx_perbit; + + /* + * 0: does not run txperbit auto calibration + * 1: run txperbit auto calibration + */ + int tx_auto_cal; + + int tx_atk_pass_pi_thrd; + int tx_atk_early_break; +/* ============================= */ + +/* >>>>>>>>>> TX perbit part begin >>>>>> */ + /* + * 0: does not run rxperbit calibration + * 1: run rxperbit calibration + */ + int rx_perbit; + + /* + * 0: does not run rxperbit auto calibration + * 1: run rxperbit auto calibration + */ + int rx_auto_cal; + + int rx_atk_cal_step; + int rx_atk_cal_out_dbg_en; + int rx_atk_cal_out_dbg_sel; +/* ============================= */ +} cal_sv_rand_args_t; + +void set_psra(cal_sv_rand_args_t *psra); +cal_sv_rand_args_t *get_psra(void); +void print_sv_args(cal_sv_rand_args_t *psra); +u8 valid_magic(cal_sv_rand_args_t *psra); +void set_type_freq_by_svargs(DRAMC_CTX_T *p, + cal_sv_rand_args_t *psra); + +#endif /* __SV_C_DATA_TRAFFIC_H */ diff --git a/src/vendorcode/mediatek/mt8192/include/x_hal_io.h b/src/vendorcode/mediatek/mt8192/include/x_hal_io.h new file mode 100644 index 000000000000..ef75df9f80b7 --- /dev/null +++ b/src/vendorcode/mediatek/mt8192/include/x_hal_io.h @@ -0,0 +1,91 @@ +/* SPDX-License-Identifier: BSD-3-Clause */ + +#ifndef X_HAL_IO_H +#define X_HAL_IO_H + +#include "dramc_pi_api.h" +//=========================================================================== +#define REG_ACCESS_NAO_DGB 0 +#define REG_ACCESS_PORTING_DGB 0 +#define REG_SHUFFLE_REG_CHECK 0 + +// field access macro----------------------------------------------------------- + +/* field macros */ +#define Fld(wid, shft) (((U32)wid << 16) | (shft << 8)) +#define Fld_wid(fld) ((UINT8)((fld) >> 16)) +#define Fld_shft(fld) ((UINT8)((fld) >> 8)) +#define Fld_ac(fld) (UINT8)(fld) + +/* access method*/ +#define AC_FULLB0 1 +#define AC_FULLB1 2 +#define AC_FULLB2 3 +#define AC_FULLB3 4 +#define AC_FULLW10 5 +#define AC_FULLW21 6 +#define AC_FULLW32 7 +#define AC_FULLDW 8 +#define AC_MSKB0 11 +#define AC_MSKB1 12 +#define AC_MSKB2 13 +#define AC_MSKB3 14 +#define AC_MSKW10 15 +#define AC_MSKW21 16 +#define AC_MSKW32 17 +#define AC_MSKDW 18 + +#define Fld2Msk32(fld) /*lint -save -e504 */ (((U32)0xffffffff>>(32-Fld_wid(fld)))<<Fld_shft(fld)) /*lint -restore */ +#define P_Fld(val, fld) ( upk > 0 ? Fld2Msk32(fld): (((UINT32)(val) & ((1 << Fld_wid(fld)) - 1)) << Fld_shft(fld))) + +extern U32 u4Dram_Register_Read(DRAMC_CTX_T *p, U32 u4reg_addr); +extern void ucDram_Register_Write(DRAMC_CTX_T *p, U32 u4reg_addr, U32 u4reg_value); + +extern void vIO32Write4BMsk2(DRAMC_CTX_T *p, U32 reg32, U32 val32, U32 msk32); +extern void vIO32Write4BMsk_All2(DRAMC_CTX_T *p, U32 reg32, U32 val32, U32 msk32); +extern void vIO32Write4B_All2(DRAMC_CTX_T *p, U32 reg32, U32 val32); + +// ========================= +// public Macro for general use. +//========================== +#define u4IO32Read4B(reg32) u4Dram_Register_Read(p, reg32) +#define vIO32Write4B(reg32, val32) ucDram_Register_Write(p, reg32, val32) +#define vIO32Write4B_All(reg32, val32) vIO32Write4B_All2(p, reg32, val32) +#define vIO32Write4BMsk(reg32, val32, msk32) vIO32Write4BMsk2(p, reg32, val32, msk32) +#define vIO32Write4BMsk_All(reg32, val32, msk32) vIO32Write4BMsk_All2(p, reg32, val32, msk32) + +#define u4IO32ReadFldAlign(reg32, fld) /*lint -save -e506 -e504 -e514 -e62 -e737 -e572 -e961 -e648 -e701 -e732 -e571 */ \ + ((u4IO32Read4B(reg32) & Fld2Msk32(fld)) >> Fld_shft(fld)) + +#define vIO32WriteFldAlign(reg32, val, fld) /*lint -save -e506 -e504 -e514 -e62 -e737 -e572 -e961 -e648 -e701 -e732 -e571 */ \ + (vIO32Write4BMsk((reg32), ((U32)(val) << Fld_shft(fld)), Fld2Msk32(fld))) + +#define vIO32WriteFldMulti(reg32, list) /*lint -save -e506 -e504 -e514 -e62 -e737 -e572 -e961 -e648 -e701 -e732 -e571 */ \ +{ \ + UINT16 upk = 1; \ + INT32 msk = (INT32)(list); \ + { upk = 0; \ + ((U32)msk == 0xffffffff)? (vIO32Write4B(reg32, (list))): (((U32)msk)? vIO32Write4BMsk(reg32, (list), ((U32)msk)):(U32)0); \ + } \ +}/*lint -restore */ + +//========================= +// Public Macro for write all-dramC or all-PHY registers +//========================= +#define vIO32WriteFldAlign_All(reg32, val, fld) /*lint -save -e506 -e504 -e514 -e62 -e737 -e572 -e961 -e648 -e701 -e732 -e571 */ \ + (vIO32Write4BMsk_All((reg32), ((U32)(val) << Fld_shft(fld)), Fld2Msk32(fld))) + +#define vIO32WriteFldMulti_All(reg32, list) /*lint -save -e506 -e504 -e514 -e62 -e737 -e572 -e961 -e648 -e701 -e732 -e571 */ \ +{ \ + UINT16 upk = 1; \ + INT32 msk = (INT32)(list); \ + { upk = 0; \ + ((U32)msk == 0xffffffff)? (vIO32Write4B_All(reg32, (list))): (((U32)msk)? vIO32Write4BMsk_All(reg32, (list), ((U32)msk)): (void)0); \ + } \ +}/*lint -restore */ + +#ifdef __MD32__ +#include "x_hal_io_dpm.h" +#endif + +#endif // X_HAL_IO_H |