diff options
Diffstat (limited to 'src')
| -rw-r--r-- | src/soc/amd/cezanne/Kconfig | 2 | ||||
| -rw-r--r-- | src/soc/amd/cezanne/fsp_s_params.c | 11 |
2 files changed, 12 insertions, 1 deletions
diff --git a/src/soc/amd/cezanne/Kconfig b/src/soc/amd/cezanne/Kconfig index 71cca6a11bed..5da70f4e0b48 100644 --- a/src/soc/amd/cezanne/Kconfig +++ b/src/soc/amd/cezanne/Kconfig @@ -18,6 +18,7 @@ config SOC_SPECIFIC_OPTIONS select BOOT_DEVICE_SUPPORTS_WRITES if BOOT_DEVICE_SPI_FLASH select DRIVERS_USB_ACPI select DRIVERS_I2C_DESIGNWARE + select COOP_MULTITASKING select DRIVERS_USB_PCI_XHCI select FSP_COMPRESS_FSP_M_LZMA select FSP_COMPRESS_FSP_S_LZMA @@ -69,6 +70,7 @@ config SOC_SPECIFIC_OPTIONS select SOC_AMD_COMMON_FSP_DMI_TABLES select SOC_AMD_COMMON_FSP_PCI select SSE2 + select TIMER_QUEUE select UDK_2017_BINDING select X86_AMD_FIXED_MTRRS select X86_AMD_INIT_SIPI diff --git a/src/soc/amd/cezanne/fsp_s_params.c b/src/soc/amd/cezanne/fsp_s_params.c index ae51f9254af1..96dc61bf80f3 100644 --- a/src/soc/amd/cezanne/fsp_s_params.c +++ b/src/soc/amd/cezanne/fsp_s_params.c @@ -1,7 +1,8 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#include <fsp/api.h> +#include <amdblocks/apob_cache.h> #include <device/pci.h> +#include <fsp/api.h> static void fsp_assign_vbios_upds(FSP_S_CONFIG *scfg) { @@ -13,4 +14,12 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd) FSP_S_CONFIG *scfg = &supd->FspsConfig; fsp_assign_vbios_upds(scfg); + + /* + * At this point FSP-S has been loaded into RAM. If we were to start loading the APOB + * before FSP-S was loaded, we would introduce contention onto the SPI bus and + * slow down the FSP-S read from SPI. Since FSP-S takes a while to execute and performs + * no SPI operations, we can read the APOB while FSP-S executes. + */ + start_apob_cache_read(); } |