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* 3rdparty/fsp: Update to current master againNico Huber2019-12-161-0/+0
| | | | | | | | | | | | | | | | | | | | We had to role the `fsp` submodule back for a minute due to a regression with the Coffee Lake binary. Intel silently mixed FSP 2.1 features into the Coffee Lake FSP which is supposed to be FSP 2.0. With the stack and heap usage partitioned for FSP using coreboot's stack (config FSP_USES_ CB_STACK), it works again. To make this even messier: We already selected this Kconfig option for Whiskey Lake, which is supposed to use the very same FSP binary. So with either submodule pointer, something was always broken :-/ Change-Id: Id2aa17aaa2c843dcc7e0fb28779d1e5948da83c9 Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37700 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jeremy Soller <jeremy@system76.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Mimoja <coreboot@mimoja.de>
* security/vboot: Ensure firmware body size is respected againJulius Werner2019-12-131-0/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | CB:36845 simplified how coreboot finds the RW CBFS after vboot has and eliminated a layer of caching. Unfortunately, we missed the fact that the former cached value didn't exactly match the FMAP section... it was in fact truncated to the data actually used by vboot. That patch unintentionally broke this truncation which leads to performance regressions on certain CBFS accesses. This patch makes use of a new API function added to vboot (CL:1965920) which we can use to retrieve the real firmware body length as before. (Also stop making all the vb2_context pointers const. vboot generally never marks context pointers as const in its API functions, even when the function doesn't modify the context. Therefore constifying it inside coreboot just makes things weird because it prevents you from calling random API functions for no reason. If we really want const context pointers, that's a refactoring that would have to start inside vboot first.) This patch brings in upstream vboot commit 4b0408d2: 2019-12-12 Julius Werner 2lib: Move firmware body size reporting to separate function Change-Id: I167cd40cb435dbae7f09d6069c9f1ffc1d99fe13 Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37680 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Mathew King <mathewk@chromium.org>
* Update vboot submodule to upstream masterJulius Werner2019-12-131-0/+0
| | | | | | | | | | | | | | | | | | Updating from commit id 695c56dc: 2019-12-04 Julius Werner Makefile: Make loop unrolling fully controllable by the caller to commit id b10e5e32: 2019-12-09 Yu-Ping Wu vboot: Make 2nvstorage.h private to vboot_reference This brings in 19 new commits. Change-Id: I9cdccd25422aee26620d48d31f83bcf32a7b4809 Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37717 Reviewed-by: Mathew King <mathewk@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* 3rdparty/fsp: Set back commit to working version of the FSPChristian Walter2019-12-131-0/+0
| | | | | | | | | | | | | | | | | With CB:37564 (3rdparts/fsp: Update fsp submodule) a regression has been introduced to CFL platforms, such that the FSP-M fails/is broken. This commit sets the commit to checkout in the submodule FSP back to a working version. Change-Id: I8eac551211559962fc60e7edd46ff118d7bde830 Signed-off-by: Christian Walter <christian.walter@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37669 Reviewed-by: Mimoja <coreboot@mimoja.de> Reviewed-by: Patrick Rudolph <siro@das-labor.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* 3rdparts/fsp: Update fsp submoduleJohanna Schander2019-12-091-0/+0
| | | | | | | | | | | | | The name for the CoffeeLake FSP.fd was changed to Fsp.fd. Therefore the CoffeLake / WhiskeyLake default path was changed. Change-Id: I0f51e378fcaacb25392d8940a342fc968c730157 Signed-off-by: Johanna Schander <coreboot@mimoja.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37564 Reviewed-by: Felix Singer <felixsinger@posteo.net> Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* vboot: update VbExNvStorageWrite functionJoel Kitching2019-12-061-0/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | Going forwards, vb2ex_commit_data will be used to flush both nvdata and secdata. The patch that is circularly dependent on this lies between a patch that makes vboot no longer build and the patch that fixes that, so we have to pull the whole thing in at once to sort out the mess. Updating from commit id 1c4dbaa0: 2019-11-18 Julius Werner Makefile: Fix typo for MOCK_TPM to commit id 695c56dc: 2019-12-04 Julius Werner Makefile: Make loop unrolling fully controllable by the caller BUG=b:124141368, chromium:1006689 TEST=make clean && make test-abuild BRANCH=none Change-Id: Ia2612da0df101cd3c46151dbce728633a39fada1 Signed-off-by: Joel Kitching <kitching@google.com> Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37315 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
* Update vboot submodule to upstream masterTim Wawrzynczak2019-11-201-0/+0
| | | | | | | | | | | | | | | | Updating from commit id ecdca931: 2019-11-13 06:14:05 +0000 - (vboot: move vb2_context inside vb2_shared_data (persistent context)) to commit id 1c4dbaa0: 2019-11-19 06:31:23 +0000 - (Makefile: Fix typo for MOCK_TPM) This brings in 17 new commits. Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Change-Id: I1952d7a26725e2c008b5009705b2e78ac0bb82df Reviewed-on: https://review.coreboot.org/c/coreboot/+/36936 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* Update opensbi submodule to upstream masterPatrick Georgi2019-11-161-0/+0
| | | | | | | | | | | | | | | | | Updating from commit id e561c63: 2019-10-02 17:03:58 +0530 - (lib: Fix coldboot race condition observed on emulators/simulators) to commit id 215421c: 2019-11-11 16:40:34 -0800 - (lib: Remove date and time from init message) This brings in 13 new commits and allows reproducible builds with opensbi. Change-Id: I0fb9e0921b017822defa8b56df5a0f3e014d7f33 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36866 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
* 3rdparty/blobs: Add Facebook FBG1701 descriptor and Intel MEFrans Hendriks2019-11-151-0/+0
| | | | | | | | | | | | | | Upgrade to blobs version with descriptor and Intel ME binary BUG=N/A TEST=booting Facebook FBG1701 Change-Id: I2143b94a81eebfb22d99833aaf1f3743983dd80c Signed-off-by: Frans Hendriks <fhendriks@eltan.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34442 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Wim Vervoorn <wvervoorn@eltan.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* vboot: use vboot persistent contextJoel Kitching2019-11-151-0/+0
| | | | | | | | | | | | | | | | | | | vb2_context object is now stored on the workbuf as part of vb2_shared_data. Use vboot's new API functions vb2api_init and vb2api_relocate to create and move the workbuf. BUG=b:124141368, chromium:994060 TEST=Build locally BRANCH=none Change-Id: I051be1e47bf79b15a1689d49a5d4c031e9363dfa Signed-off-by: Joel Kitching <kitching@google.com> Also-Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/third_party/coreboot/+/1902339 Reviewed-on: https://review.coreboot.org/c/coreboot/+/36300 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
* Update vboot submodule to upstream masterJoel Kitching2019-11-141-0/+0
| | | | | | | | | | | | | | | | Updating from commit id b2c8984d: 2019-10-01 06:01:59 +0000 - (vboot: fix compile error with MOCK_TPM) to commit id 87276ffe: 2019-11-07 17:46:09 +0800 - (futility: updater: Clean up hard-coded section names to preserve) This brings in 48 new commits. Change-Id: Iabaadc63227b856d0a2b7f3b23fe8c41b28d8eae Signed-off-by: Joel Kitching <kitching@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36813 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
* submodules: Add 3rdparty/amd_blobsMarshall Dawson2019-10-311-0/+0
| | | | | | | | | | | | | This is currently an empty repo. The intention for amd_blobs may be found in Documentation/soc/amd/amdblobs_license.md. A subsequent patch will make the repo's init and checkout optional based on a Kconfig symbol. Change-Id: Ia93fb2711beaea4cb1c8e5d71dc3a9e0facc5485 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36441 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
* 3rdparty/libgfxinit: Update submodule pointerNico Huber2019-10-291-0/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | This includes a huge set of refactorings to support Core Display Clock (CDClk) frequency switching based on the current mode requirements. The CDClk is configurable since Haswell and runtime switching is suppor- ted since Broadwell. Always using the lowest possible frequency setting should allow some power-savings. While, on the upper end, we can support higher resolution panels now, without having to change the static confi- guration. There have also been some smaller changes and fixes, including: o Parsing of eDP 1.4+ DPCD link rates, enables panels that don't advertise a maximum link rate but only individual ones. o DP support for Ibex Peak. o Corrected limit for HDMI on G45 to 165MHz. o Reworked GMBUS reset handling and timeouts, should help with stalled GMBUS controllers when unimplemented ports were probed by accident. Tested on various boards from GM45 to KBL-R. Change-Id: I0a90bd4afe2091699a46a5a1323af9723ff43018 Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35898 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* Update arm-trusted-firmware submodule to upstream masterPatrick Georgi2019-10-031-0/+0
| | | | | | | | | | | | | | | | | Updating from commit id 42cdeb93: 2019-09-13 12:09:21 +0000 - (Merge "stm32mp1: manage CONSOLE_FLAG_TRANSLATE_CRLF and cleanup driver" into integration) to commit id ace23683: 2019-09-27 09:54:27 +0000 - (Merge changes from topic "ld/stm32-authentication" into integration) This brings in 83 new commits. Change-Id: I273b5014db76d307d8735d78a8fdd5db3d07146c Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35625 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
* Update chromeec submodule to upstream masterPatrick Georgi2019-10-031-0/+0
| | | | | | | | | | | | | | | | | Updating from commit id 860fe2962: 2018-12-29 05:45:29 -0800 - (mt_scp/ipi: Support host command.) to commit id a1afae4e0: 2019-10-02 11:47:45 +0000 - (juniper: initial setup) This brings in 1723 new commits. Change-Id: Ieb4f00b21a4354bb634c3427c73260123b54ac2a Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35624 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jacob Garber <jgarber1@ualberta.ca> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
* Update opensbi submodule to upstream masterPatrick Georgi2019-10-031-0/+0
| | | | | | | | | | | | | | | | Updating from commit id ce228ee: 2019-07-02 11:11:08 +0530 - (include: Bump-up version to 0.4) to commit id e561c63: 2019-10-02 17:03:58 +0530 - (lib: Fix coldboot race condition observed on emulators/simulators) This brings in 44 new commits. Change-Id: Ide6e3c2bb98e79750b40a9b8ca9f2f1d2c123628 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35314 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
* Update vboot submodule to upstream masterPatrick Georgi2019-10-031-0/+0
| | | | | | | | | | | | | | | | Updating from commit id e6700f4c: 2019-08-13 04:36:52 +0000 - (vboot: update vboot2 functions to use new vb2_error_t) to commit id b2c8984d: 2019-10-01 06:01:59 +0000 - (vboot: fix compile error with MOCK_TPM) This brings in 71 new commits. Change-Id: Id7cefa3ad5b30c955d18e469494fec32f6f58a48 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35315 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
* 3rdparty/chromeec: Update to latest masterElyes HAOUAS2019-09-161-0/+0
| | | | | | | | | | | | | | It's been some time and there are 1420 new commits. Including one that allows reproducible builds \o/ and one that breaks building with empty $(CC) :-/ Change-Id: I5e81d5a2f1018481b9103fc5a1f4b8c72fb9deec Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/30679 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* arm64: Uprev Arm TF and adjust to BL31 parameter changesJulius Werner2019-09-141-0/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | This patch uprevs the Arm Trusted Firmware submodule to the new upstream master (commit 42cdeb930). Arm Trusted Firmware unified a bunch of stuff related to BL31 handoff parameters across platforms which involved changing a few names around. This patch syncs coreboot back up with that. They also made header changes that now allow us to directly include all the headers we need (in a safer and cleaner way than before), so we can get rid of some structure definitions that were duplicated. Since the version of entry point info parameters we have been using has been deprecated in Trusted Firmware, this patch switches to the new version 2 parameter format. NOTE: This may or may not stop Cavium from booting with the current pinned Trusted Firmware blob. Cavium maintainers are still evaluating whether to fix that later or drop the platform entirely. Tested on GOOGLE_KEVIN (rk3399). Change-Id: I0ed32bce5585ce191736f0ff2e5a94a9d2b2cc28 Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34676 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Hung-Te Lin <hungte@chromium.org>
* 3rdparty/ffs: add open-power ffs utilsMarty E. Plummer2019-08-251-0/+0
| | | | | | | | | | | These tools are used to manipulate open-power specific partitioning and ecc algorithms. Change-Id: I0657f76aab75190244d0e81c2b1a525e50af484d Signed-off-by: Marty E. Plummer <hanetzer@startmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35007 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* vboot: update vboot2 functions to use new vb2_error_tJoel Kitching2019-08-211-0/+0
| | | | | | | | | | | | | | | | | | | | | | | To make explicit when vboot2 error codes should be returned, use the new vb2_error_t type on all functions which return VB2_ERROR_* constants. Additionally, add required vboot submodule commit id e6700f4c: 2019-07-31 14:12:30 +0800 - (vboot: update vboot2 functions to use new vb2_error_t) NOTE: This patch was merged separately on the Chromium tree: https://chromium-review.googlesource.com/c/1728499 BUG=b:124141368, chromium:988410 TEST=make clean && make test-abuild BRANCH=none Change-Id: I804c2b407e496d0c8eb9833be629b7c40118415c Signed-off-by: Joel Kitching <kitching@google.com> Cq-Depend: chromium:1728292 Reviewed-on: https://review.coreboot.org/c/coreboot/+/34860 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
* Update vboot submodule to upstream masterJoel Kitching2019-08-211-0/+0
| | | | | | | | | | | | | | | | | Updating from commit id 9c906110: 2019-08-06 06:07:01 +0000 - (vboot/tpm: fix return type inconsistencies) to commit id a5afd01f: 2019-08-08 11:02:44 -0700 - (Minor fixes for clang) This brings in 6 new commits. Change-Id: Ic334ce8a5f24a0119fa2aaf000ce76c4c9e4932a Signed-off-by: Joel Kitching <kitching@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34859 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Julius Werner <jwerner@chromium.org>
* 3rdparty/blobs: Update submodule for MT8183Dawei Chien2019-08-081-0/+0
| | | | | | | | | | | | | Update the 3rdparty/blobs submodule to the newest HEAD, which contains the SPM binary for MT8183 platforms ( https://review.coreboot.org/c/blobs/+/34543 ). Change-Id: I505ec9fffd9ddd62fffbe9514cbba50625825693 Signed-off-by: Dawei Chien <dawei.chien@mediatek.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34734 Reviewed-by: Frans Hendriks <fhendriks@eltan.com> Reviewed-by: Hung-Te Lin <hungte@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* Update vboot submodule to upstream masterJoel Kitching2019-08-081-0/+0
| | | | | | | | | | | | | | | | Updating from commit id dac763c7: 2019-05-10 10:43:55 -0700 - (Make vboot -Wtype-limits compliant) to commit id 9c906110: 2019-08-06 06:07:01 +0000 - (vboot/tpm: fix return type inconsistencies) This brings in 68 new commits. Change-Id: Ia96347d8ed94db6f0ec5f5108cb98ab0c4087bd4 Signed-off-by: Joel Kitching <kitching@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33858 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
* 3rdparty/libgfxinit: Update submodule pointerNico Huber2019-08-051-0/+0
| | | | | | | | | | | | | | | | | Update libgfxinit: o Add support for ULX (CPU Y series) variants o Add support for Kaby/Coffee/Whiskey/Amber Lakes o Publish Read_EDID() procedure o Fix certain GMBUS error conditions o Fix DP training when clock recovery needed voltage-swing increase o Fix scaling on eDP for BDW+ Change-Id: Ib252303708d2bb0524ecc47f498df45902ba774f Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/31457 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
* 3rdparty/opensbi: Bump versionPatrick Rudolph2019-07-281-0/+0
| | | | | | | | | | | | | | | | | | | | | Use latest OpenSBI that include support for dynamic firmware loader. That allows us to use OpenSBI similar to BL31 on aarch64: * coreboot loads the payload * coreboot loads OpenSBI ELF right before payload handoff * OpenSBI does platform lockdown and provides runtime services * OpenSBI hands control to already loaded payload The uncompressed compiled OpenSBI code is about 41KiB. Required to boot GNU/Linux on qemu-riscv as some instructions needs to be emulated by SBI. Change-Id: If7ed706bc54a75fb583a8aa46fdd61ae7d18c546 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34139 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
* 3rdparty/blobs: Update submoduleJulius Werner2019-07-231-0/+0
| | | | | | | | | | | | | Uprev the 3rdparty/blobs submodule to the newest HEAD, which contains the SSPM binary for MT8183 platforms ( https://review.coreboot.org/c/blobs/+/32698 ). Change-Id: I8a4dfa7eaace1ea473f5970596c3201342e48927 Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34494 Reviewed-by: Hung-Te Lin <hungte@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* 3rdparty/fsp: Update submodule pointerBora Guvendik2019-07-021-0/+0
| | | | | | | | | | | | | | Update fsp submodule pointer to Coffee Lake FSP 7.0.64.40 github commit: https://github.com/IntelFsp/FSP/commit/59964173e18950debcc6b8856c5c928935ce0b4f Change-Id: I864404a03be63aa60e81db21af16d69cda2d4e12 Signed-off-by: Bora Guvendik <bora.guvendik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33642 Reviewed-by: Lijian Zhao <lijian.zhao@intel.com> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* Add intel-microcode submodule repositoryzaolin2019-06-181-0/+0
| | | | | | | | | Change-Id: Icc5ac0a8033e371ecf2b4b28ba45dab961e86b3f Signed-off-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33550 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Lijian Zhao <lijian.zhao@intel.com>
* 3rdparty/blobs: Update submodule, SNB improvementsArthur Heymans2019-06-171-0/+0
| | | | | | | | | | | | | | | | | | | | | | | | | The sandybridge systemagent-r6 blob is modified: - To be more flexible about the location of the stack w.r.t. the heap - Place the MRC pool right below the MRC_VAR region - to work with the same DCACHE_RAM_BASE from the native raminit (could make the CAR linker symbols easily compatible if desired) This allows CAR setup compatibility between mrc.bin and native bootpath and also allows for BIOS/memory mappeds region larger than 8MB. This changes the semantics of CONFIG_DACHE_RAM_MRC_VAR_SIZE to also include the pool on top of MRC_VAR region. TESTED on T520 (boots and resumes from S3 with mrc.bin). Change-Id: I17d240656575b69a24718d90e4f2d2b7339d05a7 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33228 Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* 3rdparty: Uprev vboot submodule to upstream masterJulius Werner2019-05-131-0/+0
| | | | | | | | | | | | | This patch uprevs the vboot submodule to the new upstream HEAD commit dac763c782 Make vboot -Wtype-limits compliant Change-Id: I363e218e019b25483bc4c06315ca4e0e34599daf Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32748 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Joel Kitching <kitching@google.com> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
* 3rdparty/libgfxinit: Update for runtime CPU detectionNico Huber2019-05-121-0/+0
| | | | | | | | | | | | | | Beside one tiny fix for framebuffer scaling, this contains a major refactoring of libgfxinit's configuration infrastructure. With this, we are finally able to detect CPUs at runtime and only have to confi- gure a CPU/GPU generation. Change-Id: Iccf4557453878536f527e4a1902439a1961ab701 Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32736 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* 3rdparty/libhwbase: Update to current masterNico Huber2019-05-121-0/+0
| | | | | | | | | | | | | | Beside some refactorings that don't affect coreboot, this contains bd0ed91 (Makefile: Revise support for generated sources) that fixes an issue with upcoming libgfxinit configuration changes. Change-Id: Ib47aeff8f6426ae27ddbc235a954e3bd60029072 Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32735 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* Update vboot submodule to upstream masterJoel Kitching2019-05-071-0/+0
| | | | | | | | | | | | | | | | Updating from commit id 304aa429: 2019-03-12 10:38:56 -0700 - (futility: updater: Unit test for preserving sections using FMAP flags) to commit id e7edff66: 2019-05-03 07:02:32 -0700 - (vboot: implement DISPLAY_INIT context and SD flag) This brings in 45 new commits. Change-Id: I7493e43bddc553f9724de46130ccb4cb44e18573 Signed-off-by: Joel Kitching <kitching@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32612 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
* 3rdparty/fsp: Update submodule pointer to upstream masterMatt DeVillier2019-04-251-0/+0
| | | | | | | | | | | | Update submodule pointer to pull in newly-updated Braswell FSP. Adjust FSP_FD_PATH for soc/cannonlake due to filename case change. Change-Id: I02ee0d32fd4c04cd4971eff20fc5a7de3f9b07ec Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32420 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
* 3rdparty/opensbi: Add submodulezaolin2019-04-241-0/+0
| | | | | | | | | | * Add opensbi for RISC-v Change-Id: I1a6baa6b6c05095ff5545492aabf7408a23af181 Signed-off-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32418 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
* Update vboot submodule to upstream masterJoel Kitching2019-03-141-0/+0
| | | | | | | | | | | | | | | | Updating from commit id 1e177741: 2019-02-14 05:27:16 -0800 - (vboot: rename VB2_DISABLE_DEVELOPER_MODE) to commit id 304aa429: 2019-03-12 10:38:56 -0700 - (futility: updater: Unit test for preserving sections using FMAP flags) This brings in 18 new commits. Change-Id: Ie2889ed0217c38734eb2c496ca20f95b6a12b102 Signed-off-by: Joel Kitching <kitching@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/31872 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* 3rdparty/blobs: Update submodule pointerNico Huber2019-03-071-0/+0
| | | | | | | | | | | | * Update SMU firmware for amd/stoneyridge * Remove stale Sandy Bridge MRC binaries Change-Id: Ifd1a9f02d96bc7cf5d23706a09634c0353dfae61 Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/31786 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
* Update vboot submodule to upstream masterJoel Kitching2019-02-221-0/+0
| | | | | | | | | | | | | | | | Updating from commit id a32c930e: 2018-12-28 16:14:08 -0800 - (futility: updater: quirks: Support special released SNOW RO) to commit id 1e177741: 2019-02-14 05:27:16 -0800 - (vboot: rename VB2_DISABLE_DEVELOPER_MODE) This brings in 11 new commits. Change-Id: I59d83de49006a6d081b206716002697d39099aa4 Signed-off-by: Joel Kitching <kitching@google.com> Reviewed-on: https://review.coreboot.org/c/31542 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
* Update vboot submodule to upstream masterPatrick Georgi2019-01-161-0/+0
| | | | | | | | | | | | | | | | Updating from commit id 392211f0: 2018-04-23 13:07:25 -0700 - (Update Android signing to support signature scheme v2) to commit id a32c930e: 2018-12-28 16:14:08 -0800 - (futility: updater: quirks: Support special released SNOW RO) This brings in 159 new commits. Change-Id: I7fea9ff1e4109d4dbc979289172191f677438933 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/c/30914 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
* 3rdparty/blobs: Update for current Intel microcodeNico Huber2019-01-101-0/+0
| | | | | | | | | | | | The microcode included for `model_6xx` was for a 660, that path has changed. Change-Id: I09a41a8269cfdf8953bac10c9630922192851e73 Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: https://review.coreboot.org/c/30081 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
* 3rdparty/libgfxinit: Update submodule pointerArthur Heymans2018-12-211-0/+0
| | | | | | | | | | | | | | | | Updates to current master. This includes: - A fix for textmode scaling on G45 - Refactor things to rely less on inline proving - Increased width of modeline fields to 32 bits Change-Id: Iab2915b747f6e4fa4e78eb28fea29bb3a9b3b687 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/c/30311 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* 3rdparty/blobs: Update video BIOS to customize release binaryRichard Spiegel2018-12-071-0/+0
| | | | | | | | | | | | | | | | | | | | | A liara specific VBIOS was released and merged to blobs. Now coreboot need to point to the updated blob, so it can use liara specific VBIOS. Liara Chromebook Stoney VBIOS BRT39865 BRT39865.001 12/05/18,01:13:54 CL#1716128 @ 15.49.0.18 ATOMBuild#436504 Major Changes included: 1. First Stoney VBIOS released to Liara update eDP power up sequence. BUG=b:120534087 TEST=none Change-Id: I3b060b1ccfb311584afd0fb66258eb7cc942408d Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com> Reviewed-on: https://review.coreboot.org/c/30089 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
* 3rdparty/blobs: Add new blobRichard Spiegel2018-11-281-0/+0
| | | | | | | | | | | | | | | New VBIOS code has been added to blobs/mainboard/google/kahlee. It has been merged, so now coreboot needs to use latest blob. BUG=b:112618193 TEST=none Change-Id: If430ee06f03e0f20806bf8fd2b649814251ffcf5 Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com> Reviewed-on: https://review.coreboot.org/c/29869 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-by: Martin Roth <martinroth@google.com>
* 3rdparty/blobs: Update to include QuarkFspPatrick Georgi2018-10-121-0/+0
| | | | | | | | | Change-Id: I0032e86755750755e7ae6e2a53863e1600f96a5b Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/29030 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
* 3rdparty/fsp: update to current masterPatrick Georgi2018-10-051-0/+0
| | | | | | | | | | | This includes the SplitFspBin.py script. Change-Id: I6323a7a1a2bd9b5e11c0b21e5ea991a3fbd3daac Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/28775 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
* submodules: add FSP mirror as non-default submodulePatrick Georgi2018-09-021-0/+0
| | | | | | | | | | | | | | | | | Like the 3rdparty/blobs repo this isn't checked out by default. Right now you can manually check it out using $ git submodule init --checkout A follow up commit will add some automagic if USE_BLOBS and MAINBOARD_USES_FSP2_0 are enabled. Change-Id: Ie612495abc2a2d5947225e6ab54872aa72d4bec6 Signed-off-by: Patrick Georgi <patrick@georgi.software> Reviewed-on: https://review.coreboot.org/28303 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* 3rdparty/blobs: Update submodule pointer to pull in latest changesPatrick Rudolph2018-07-271-0/+0
| | | | | | | | | | | | | | | * Include Cavium's CN81xx BL31.elf * mainboard/google: Add folder kahlee for video binary * Stoney Ridge: PSP bootloader update * cpu/intel: remove microcode header files for model_306ax Change-Id: Ie8f3b2e8db0692e95caee245733054e4e20f61ea Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/27647 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: David Hendricks <david.hendricks@gmail.com> Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
* 3rdparty/blobs: Update submodule pointer to include latest AMD ucodePaul Menzel2018-07-021-0/+0
| | | | | | | | | | | | | | | The two commits below are added to the BLOBs repository. * fe7c6a3 pcengines/apu2: Disable ECC Exclusion range * 3854ad2 cpu/amd/family_15h: Add latest AMD ucode file The latest AMD microcode patches include Spectre mitigations. Change-Id: I4729cc054fe8267549d7369cea4d26aa51861e1c Signed-off-by: Paul Menzel <pmenzel@molgen.mpg.de> Reviewed-on: https://review.coreboot.org/27297 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
* 3rdparty/libgfxinit: Update submodule pointerArthur Heymans2018-06-081-0/+0
| | | | | | | | | | | | | | | | | | Update to current master. This includes: - G45 support - fixes scaling on eDP (needed for working textmode on eDP) - gfx_test drawing and moving cursors - Adding support for Tiling on <= Haswell - Allow changes to the framebuffer configurarion without resetting the pipe. Change-Id: I4ff3c17ec7308115de7bf2f2bb9276c2fad41253 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/26823 Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
generated by cgit v1.2.3 (git 2.25.1) at 2024-06-06 11:16:23 +0000