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* Update vboot submodule to upstream main (13f601f)Selma Bensaid2021-09-291-0/+0
| | | | | | | | | | | | | | | | Updating from commit id c5a482ed: 2021-09-08 17:16:59 +0000 - (sign_official_build: disable gsetup for reven) to commit id 13f601f: 13f601f vboot: boot from miniOS recovery kernels on disk b This brings in 14 new commits. Signed-off-by: Selma Bensaid <selma.bensaid@intel.com> Change-Id: I66788ea434a6000435b97ce64107f3b5da882414 Reviewed-on: https://review.coreboot.org/c/coreboot/+/57994 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* 3rdparty/fsp: Update submoduleArthur Heymans2021-09-231-0/+0
| | | | | | | | | | | | | This includes the Cedar Island FSP which is used by xeon_sp/cpx. Also updates EHL FSP to latest MR1 version. Change-Id: I1c2d440ce0f20a0922e5d91f615771843281fca6 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57488 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Lean Sheng Tan <lean.sheng.tan@intel.com> Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* 3rdparty/amd_blobs: update submodule pointerFelix Held2021-09-171-0/+0
| | | | | | | | | | * cezanne: Remove internal classification from PSP release notes Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I8198a1d88e98a2192ccd2ddadb1842daabf9c02f Reviewed-on: https://review.coreboot.org/c/coreboot/+/57689 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
* Update vboot submodule to upstream mainHsuan Ting Chen2021-09-151-0/+0
| | | | | | | | | | | | | | | | | Updating from commit id 4423276b: 2021-08-31 17:41:34 +0000 - (crossystem: add a hwid override mechanism from chromeos-config) to commit id c5a482ed: 2021-09-08 17:16:59 +0000 - (sign_official_build: disable gsetup for reven) This brings in 10 new commits. Signed-off-by: Hsuan Ting Chen <roccochen@chromium.org> Change-Id: I67d4bfa182eae98bb23ae487f117c991502b66ed Reviewed-on: https://review.coreboot.org/c/coreboot/+/57639 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
* Update vboot submodule to upstream mainThejaswani Putta2021-09-061-0/+0
| | | | | | | | | | | | | | | | Updating from commit id ccc56f4: vboot: add x86 SHA256 ext support to commit id 4423276: crossystem: add a hwid override mechanism from chromeos-config Signed-off-by: Thejaswani Putta <thejaswani.putta@intel.com> Change-Id: I7bd73b9f6c0492f96c336b61e21ecae37b8f3606 Reviewed-on: https://review.coreboot.org/c/coreboot/+/57322 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Thejaswani Putta <thejaswani.putta@intel.corp-partner.google.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
* 3rdparty/intel-microcode: Update submodule to 20210608 releaseTim Crawford2021-08-131-0/+0
| | | | | | | | | | | | | | | | | | | | | | Update submodule pointer to include microcode for TGL and others. Tested the following still boot: - galp3-c (WHL-U): sig=0x806eb pf=0x80 revision=0xe9 - oryp5 (CFL-H): sig=0x906ea pf=0x20 revision=0xe9 - gaze15 (CML-H): sig=0xa0652 pf=0x20 revision=0xe9 coreboot reports the revision as -1 from what it actually is. i.e., these should report revision=0xea (and that is what Linux reports). However, this behavior is not new. Change-Id: I084ba67e8eaf7383f1c05fa5589b63c92ff900b1 Signed-off-by: Tim Crawford <tcrawford@system76.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56861 Reviewed-by: Felix Singer <felixsinger@posteo.net> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* 3rdparty/qc_blobs: Uprev to new HEAD (98db386)Shelley Chen2021-08-031-0/+0
| | | | | | | | | | Now that gsi_fw blob has landed, need to uprev the qc_blobs. Change-Id: I0bf67a560ee2e5d771bdb71b60e3d3d372dad567 Signed-off-by: Shelley Chen <shchen@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56776 Reviewed-by: Julius Werner <jwerner@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* Update chromeec submodule to upstream mainPatrick Georgi2021-07-281-0/+0
| | | | | | | | | | | | | | | | Updating from commit id 1e800ac83: 2021-03-01 22:59:54 +0000 - (docs: point md files in master to main/HEAD) to commit id 4c21b57eb: 2021-07-19 11:36:07 +0000 - (pd: Fix missing polarity_rm_dts in some conditions) This brings in 3145 new commits. Change-Id: Iff2e9f766e750070d71644c2f9895ad10e8b1c9a Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56431 Reviewed-by: Julius Werner <jwerner@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* Update arm-trusted-firmware submodule to upstream integrationPatrick Georgi2021-07-281-0/+0
| | | | | | | | | | | | | | | | Updating from commit id 96404aa27: 2021-05-13 18:27:27 +0200 - (Merge "build(hooks): update Commitizen to ^4.2.4" into integration) to commit id 586aafa3a: 2021-07-19 05:36:18 +0200 - (Merge "errata: workaround for Neoverse V1 errata 1791573" into integration) This brings in 207 new commits. Change-Id: Iaf8af5ffaf377070ee1430ed7cfdc51001a1ba6b Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56416 Reviewed-by: Julius Werner <jwerner@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* 3rdparty/qc_blobs: Uprev to new HEAD (e96cde2)Shelley Chen2021-07-241-0/+0
| | | | | | | | | | Now that cpucp blobs have landed, need to uprev the qc_blobs. Change-Id: I62dc410cee7baf5efa5c0406f35ee05a535f49b1 Signed-off-by: Shelley Chen <shchen@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56574 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
* Update vboot submodule to upstream mainSubrata Banik2021-07-011-0/+0
| | | | | | | | | | | | | | Updating from commit id b38e3a63: cros_ec: Use boot mode to check if EC can be trusted to commit id ccc56f4: vboot: add x86 SHA256 ext support Signed-off-by: Subrata Banik <subrata.banik@intel.com> Change-Id: I4e170e84a12646386d3fd84ae97add6c19f23809 Reviewed-on: https://review.coreboot.org/c/coreboot/+/55992 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
* security/intel/cbnt: Build test CBnT provisioningArthur Heymans2021-06-281-0/+0
| | | | | | | | | | | This updates the intel-sec-tools submodule pointer to include a fake acm binary to be included for buildtesting. Change-Id: Id4a9e177f71306b8c5538a578da229a53d19487a Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55609 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
* 3rdparty/libgfxinit: Update to latest ToTPatrick Georgi2021-06-171-0/+0
| | | | | | | | | | | This brings in three new commits that are mostly concerned about fixing the build with gcc 11. Change-Id: I35f9100e2bfb2a261b3a0a128697550caf5840d9 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55498 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* 3rdparty/libhwbase: Update to latest ToTPatrick Georgi2021-06-151-0/+0
| | | | | | | | | | This update adds a commit to fix building libgfxinit with gcc 11 Change-Id: I5c0e3823ab7219667f9430bce74e4f2fba0c0c3a Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55497 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
* 3rdparty/intel-sec-tools: Fix submodule pointerAngel Pons2021-06-141-0/+0
| | | | | | | | | | | | | | | | The commit currently being pointed to is unreachable. Use the same commit that exists in a reachable branch. Fixes: Commit 1128817ed644e86daa3972e68eb08761fd6b0da9 (3rdparty/intel-sec-tools: Update to support Boot Guard) Signed-off-by: Angel Pons <th3fanbus@gmail.com> Change-Id: I1cfc08d48fe5471592fea1013e8b43bea5d7b565 Reviewed-on: https://review.coreboot.org/c/coreboot/+/55414 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Christian Walter <christian.walter@9elements.com> Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* 3rdparty/amd_blobs: Update submodule pointerRaul E Rangel2021-06-101-0/+0
| | | | | | | | | | * Upgrade blobs to match PI 1.0.0.3c Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: Id7d60f9b45be927afda5b9498d12443c7e19aac1 Reviewed-on: https://review.coreboot.org/c/coreboot/+/55280 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
* 3rdparty/intel-sec-tools: Update to support Boot GuardChristopher Meis2021-06-071-0/+0
| | | | | | | | | | | | Update intel-sec-tools to commit of BootGuard support. Remove --coreboot argument in src/security/intel/cbnt/Makefile.inc: was removed as argument for cbnt Change-Id: Iaf34bdb65a5f067d1d632e35d340b8fc49aaf318 Signed-off-by: Christopher Meis <christopher.meis@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55013 Reviewed-by: Christian Walter <christian.walter@9elements.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* 3rdparty/fsp: Update submodule pointer to newest masterLean Sheng Tan2021-06-071-0/+0
| | | | | | | | | | | | | | | | | | Newest master includes these changes: 1. Introduce the FSP package for Elkhart Lake SKUs 2. Introduce the FSP package for Tiger Lake IoT SKUs 3. Update the FSP package to latest version for Apollo Lake, Comet Lake and Tiger Lake (client SKUs) You can get further 3rdparty/FSP commit history here: https://github.com/intel/FSP/commits/master Signed-off-by: Lean Sheng Tan <lean.sheng.tan@intel.com> Change-Id: I96d147fec82d0fcd5c7748c277deb0672a975ceb Reviewed-on: https://review.coreboot.org/c/coreboot/+/55228 Reviewed-by: Srinidhi N Kaushik <srinidhi.n.kaushik@intel.com> Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* Update vboot submodule to upstream mainDaisuke Nojiri2021-05-301-0/+0
| | | | | | | | | | | | | | Updating from commit id e681c37: change node locked version expectations to commit id b38e3a63: cros_ec: Use boot mode to check if EC can be trusted Change-Id: Id6de185af85a61a3843b302fef6fa0d4d3c17aef Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55026 Reviewed-by: Julius Werner <jwerner@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* Update vboot submodule to upstream/main (e681c37)Aseda Aboagye2021-05-161-0/+0
| | | | | | | | | | | | | | This commit updates the vboot submodule from commit 57c0c5b: cgpt: Move all GPT on SPI-NOR infra behind a flag to e681c37: change node locked version expectations Signed-off-by: Aseda Aboagye <aaboagye@google.com> Change-Id: Ifd130e3f66f1819f59f00703f0ad0c2278b544bf Reviewed-on: https://review.coreboot.org/c/coreboot/+/54307 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
* Update arm-trusted-firmware submodule to upstream masterYu-Ping Wu2021-05-151-0/+0
| | | | | | | | | | | | | | | | | Updating from commit id 7ad39818b: 2020-10-12 09:16:21 +0000 - (Merge "mediatek: mt8192: add GIC600 support" into integration) to commit id 96404aa27: 2021-05-13 18:27:27 +0200 - (Merge "build(hooks): update Commitizen to ^4.2.4" into integration) This brings in 861 new commits. Change-Id: I912545022e4320b86ab8a382144c02e315d0c835 Signed-off-by: Yu-Ping Wu <yupingso@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/54289 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Hung-Te Lin <hungte@chromium.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
* 3rdparty/libgfxinit: Update submodule pointerAngel Pons2021-05-121-0/+0
| | | | | | | | | | | This brings in LSPCON support. Change-Id: I35cefa2aa8107b7841d7cf7a7bb61d4b591d14ae Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51147 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
* 3rdparty/qc_blobs: Uprev to new HEAD (053eb2a)Shelley Chen2021-05-111-0/+0
| | | | | | | | | | Now that Boot blobs have landed, need to uprev the qc_blobs. Change-Id: I510de2d1e4334612c81f35a082dea92d445da0bb Signed-off-by: Shelley Chen <shchen@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/54037 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
* 3rdparty/intel-sec-tools: Update submodule pointerArthur Heymans2021-05-101-0/+0
| | | | | | | | | | | | | | | Some changes: - bg-prov got renamed to cbnt-prov - cbfs support was added which means that providing IBB.Base/Size separatly is not required anymore. Also fspt.bin gets added as an IBB to secure the root of trust. Change-Id: I20379e9723fa18e0ebfb0622c050524d4e6d2717 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/52971 Reviewed-by: Christian Walter <christian.walter@9elements.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* Update vboot submodule to upstream mainBora Guvendik2021-04-221-0/+0
| | | | | | | | | | | | | | | Updating from commit id 9d4053df: 2020-11-20 01:51:08 +0000 - (Revert "Reland: Clean up implicit fall through.") to commit id 57c0c5be: 2021-04-09 11:45:39 +0800 - (cgpt: Move all GPT on SPI-NOR infra behind a flag) Signed-off-by: Bora Guvendik <bora.guvendik@intel.com> Change-Id: Id50a892f12ff3c4147c422c98b640ac047143128 Reviewed-on: https://review.coreboot.org/c/coreboot/+/52453 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* 3rdparty/qc_blobs: Uprev to new HEAD (02ba9a6)Shelley Chen2021-04-211-0/+0
| | | | | | | | Change-Id: I18fc6443a6972e22c979daaf68d0b9c046d1866f Signed-off-by: Shelley Chen <shchen@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/52558 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
* 3rdparty/blobs: Update blobs pointer to f388b6794e6fRaul E Rangel2021-04-071-0/+0
| | | | | | | | | | | | | | | | mb/google/guybrush: Update APCB - disable debug mb/google/guybrush: Add APCB to get through memory training soc/mediatek/mt8192: Add EMI Settings of 8GB Normal Mode soc/mediatek/mt8192: Update MCUPM firmware soc/mediatek/mt8192: Add version info for SSPM TEST=Boot guybrush to OS Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: I445d753c712670fe80efcdf29459736df2b76666 Reviewed-on: https://review.coreboot.org/c/coreboot/+/52112 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
* Update amd_blobs submodule to upstream masterMartin Roth2021-03-281-0/+0
| | | | | | | | | | | | | | | | Updating from commit id 3a9d7cd: 2021-03-03 15:37:08 -0700 - (picasso: Update Dali SMU firmware) to commit id dded82f: 2021-03-23 15:36:36 -0600 - (picasso: Update Dali SMU firmware) This brings in 2 new commits. Signed-off-by: Martin Roth <martin@coreboot.org> Change-Id: If71e52a2a3e50aeb8599798de7b49bc71ed26a04 Reviewed-on: https://review.coreboot.org/c/coreboot/+/51774 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
* 3rdparty/intel-sec-tools: Update submodule pointerArthur Heymans2021-03-191-0/+0
| | | | | | | | | | This includes the bg-prov tool. Change-Id: Iba8efe3bcb67694da76ef78abaa0562d47f7850b Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50408 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Christian Walter <christian.walter@9elements.com>
* Update chromeec submodule to upstream masterMartin Roth2021-03-161-0/+0
| | | | | | | | | | | | | | | | | Updating from commit id a2390f3c5: 2020-12-01 08:35:44 +0000 - (servo_v4/usb_pd_policy: Reject SNK->SRC power swap if CC_ALLOW_SRC not set) to commit id 1e800ac83: 2021-03-01 22:59:54 +0000 - (docs: point md files in master to main/HEAD) This brings in 188 new commits. Signed-off-by: Martin Roth <martin@coreboot.org> Change-Id: I5c276d7839e0bdbf14ac56f16c231d75a6ea4c3e Reviewed-on: https://review.coreboot.org/c/coreboot/+/51464 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
* Update arm-trusted-firmware submodule to upstream masterMartin Roth2021-03-161-0/+0
| | | | | | | | | | | | | | | | | Updating from commit id a4c979ade: 2020-08-26 14:59:05 +0000 - (Merge changes I6bf1db15,I8631c34a,Id76ada14 into integration) to commit id 7ad39818b: 2020-10-12 09:16:21 +0000 - (Merge "mediatek: mt8192: add GIC600 support" into integration) This brings in 222 new commits. Signed-off-by: Martin Roth <martin@coreboot.org> Change-Id: Id186df36d90563f94f17cc210a6f634adc4ec61e Reviewed-on: https://review.coreboot.org/c/coreboot/+/51463 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
* Update amd_blobs submodule to upstream masterMartin Roth2021-03-151-0/+0
| | | | | | | | | | | | | | | | | | Updating from commit id 3b1a734: 2021-03-02 11:51:18 -0700 - (picasso: Update FSP to build 0x26) to commit id 3a9d7cd: 2021-03-03 15:37:08 -0700 - (picasso: Update Dali SMU firmware) This brings in 1 new commits. Signed-off-by: Martin Roth <martin@coreboot.org> Change-Id: Iff3b4ff667f97d3804bc66477f8a95a60e23b1a0 Reviewed-on: https://review.coreboot.org/c/coreboot/+/51459 Reviewed-by: Mathew King <mathewk@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* Update blobs submodule to upstream masterMartin Roth2021-03-151-0/+0
| | | | | | | | | | | | | | | | | Updating from commit id 4fdfa1c: 2021-03-05 13:10:22 -0600 - (mb/amd/majolica: Update to use proper APCBs built for Majolica) to commit id fc2d4e2: 2021-03-12 10:31:48 -0700 - (mb/google/guybrush: Add initial APCB) This brings in 1 new commit. Signed-off-by: Martin Roth <martin@coreboot.org> Change-Id: I3003fdb8ba0bcfbc33452999c35a9a21775ecc10 Reviewed-on: https://review.coreboot.org/c/coreboot/+/51462 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Mathew King <mathewk@chromium.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
* mb/amd/majolica: Update to use proper APCBs built for MajolicaMatt Papageorge2021-03-101-0/+0
| | | | | | | | | | | | | | | | Some of the previous binaries were incorrect and should not be used for Majolica because they are templates instead of APCBs specifically built for the board. This APCB update also places the UMA region under 4G and size 32 MB which is essential for video output. TEST=Boot with UEFI BIOS and verify we can get to OS. Also verify memory region size, base and alignment. Change-Id: Id797e2ad5bd67815c09752aedc19dad7dcf8ad12 Signed-off-by: Matt Papageorge <matthewpapa07@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51014 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
* amd_blobs: update submodule pointerNikolai Vyssotski2021-03-031-0/+0
| | | | | | | | | | | | Pick up build 0x26 Picasso FSP binaries. The changes include increased FSPS UPD block size from 0x152 to 0x202. Change-Id: I11fc199ca7bc6ee7431c59d35a60d9ebd977bf10 Signed-off-by: Nikolai Vyssotski <nikolai.vyssotski@amd.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51193 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-by: Martin Roth <martinroth@google.com>
* amd_blobs: Update cezanne PSP Secure OSMarshall Dawson2021-03-011-0/+0
| | | | | | | | | | | | Avoid a Secure OS Abort. This prevents coreboot timing out on C2P mailbox commands and allows HDT unlocking. Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Change-Id: I358530a1ba959ee1896e26a47853c9918ee124b4 Reviewed-on: https://review.coreboot.org/c/coreboot/+/51109 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Raul Rangel <rrangel@chromium.org>
* amd_blobs: Add cezanne whitelist bootloaderMarshall Dawson2021-03-011-0/+0
| | | | | | | | | | Advance the pointer to pick up the PSP whitelist bootloader. Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Change-Id: I45da509ee6f782cbe64e7099f3945129282060b4 Reviewed-on: https://review.coreboot.org/c/coreboot/+/51102 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
* 3rdparty/blobs: advance submodule pointer.Ritul Guru2021-02-111-0/+0
| | | | | | | | | | This adds the apcb binary for Bilby. Change-Id: I1487369bc72734e875c5a701f27ed2d6af41cd01 Signed-off-by: Ritul Guru <ritul.bits@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50496 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
* Update chromeec submodule to upstream masterPatrick Georgi2021-02-061-0/+0
| | | | | | | | | | | | | | | | Updating from commit id a1afae4: 2019-10-02 11:47:45 +0000 - (juniper: initial setup) to commit id a2390f3: 2020-12-01 08:35:44 +0000 - (servo_v4/usb_pd_policy: Reject SNK->SRC power swap if CC_ALLOW_SRC not set) This brings in 4022 new commits. Change-Id: Ib13921aa78a60f88455223eff602296abc424ca8 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48212 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* 3rdparty/intel-microcode: Update submodule to 20201118 releaseTim Crawford2021-01-231-0/+0
| | | | | | | | | | | | | | Update submodule pointer to include microcode for CML-H and others. Change-Id: Ide211b0b163f824a3cfa6500a73aea1e2176c652 Signed-off-by: Tim Crawford <tcrawford@system76.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47914 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-by: Felix Singer <felixsinger@posteo.net> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* 3rdparty/blobs: advance submodule pointerFelix Held2021-01-191-0/+0
| | | | | | | | | | | | | | | | | | | | | | | This pulls in the following changes: * Drop geode_lx * cpu/amd/model_fxx: Drop unused microcode * cpu/amd/model_10xx: Drop unused microcode * soc/mediatek/mt8192: Add dram.elf for DRAM full calibration * soc/mediatek/mt8192: Add dpm binary * soc/mediatek/mt8192: Add 4266Mbps flag for dpm & dram blob * soc/mediatek/mt8192: add SPM firmware * soc/mediatek/mt8192: Support 26M clock off in SPM * soc/mediatek/mt8192: Add SSPM firmware * soc/mediatek/mt8192: Add MCUPM firmware * soc/mediatek/mt8192: Update MCUPM firmware * soc/mediatek/mt8192: Support discrete DRAM modules * mb/amd/majolica: Add APCB configuration files Change-Id: I5c18349307421707fac71f392b785f3e2bef3acb Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49675 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
* amd_blobs: Add new picasso VBIOSMarshall Dawson2021-01-141-0/+0
| | | | | | | | Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Change-Id: Icf1571ae360cee5698626f0360e1408360e8a7f6 Reviewed-on: https://review.coreboot.org/c/coreboot/+/49362 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
* amd_blobs: Advance pointer for picasso FSP 0x25Marshall Dawson2021-01-081-0/+0
| | | | | | | | | Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Change-Id: I2aa5f353432cd8f79005153a06ac35c1e654f6f1 Reviewed-on: https://review.coreboot.org/c/coreboot/+/49223 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
* 3rdparty/libgfxinit: Update for Cannon Point supportNico Huber2020-12-281-0/+0
| | | | | | | | | | | | | We missed that Cannon Point, the PCH usually paired with Coffee, Whiskey and Comet Lake, differs a bit from its predecessors. Hence, libgfxinit now has a new Kconfig setting for the PCH. Change-Id: I1c02c0d9abb7340aabe94185ee5e17ef4c2b0d36 Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48764 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
* 3rdparty/fsp: Update submodule pointer to newest masterFelix Singer2020-12-241-0/+0
| | | | | | | | | | Newest master introduces the FSP for Tiger Lake client SKUs. Change-Id: Id437faf72f1b8c5bc5310596bdab980e64614fa0 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48712 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* amd_blobs: Add cezanne filesMarshall Dawson2020-12-171-0/+0
| | | | | | | | | | Add blobs from the 1.0.0.1 release of CezannePI-FP6. Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Change-Id: Iebfbe819ed429a7aed1882964061e1bc98f3bc39 Reviewed-on: https://review.coreboot.org/c/coreboot/+/48647 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
* 3rdparty/amd_blobs: Update pointer for picasso SMU and FSPMarshall Dawson2020-12-021-0/+0
| | | | | | | | | | | Add the newest SMU firmware and FSP blobs for the picasso project. This supports Picasso, Dali, and Pollock devices. Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Change-Id: I75e6f3d2a59ed8b2e42afba3a6978574373ec4e5 Reviewed-on: https://review.coreboot.org/c/coreboot/+/48211 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
* Update vboot submodule to upstream masterPatrick Georgi2020-11-251-0/+0
| | | | | | | | | | | | | | | | Updating from commit id 9d4053d: 2020-11-20 01:51:08 +0000 - (Revert "Reland: Clean up implicit fall through.") to commit id 48195e5: 2020-11-24 10:23:45 +0000 - (Makefile: Test for warning flags before using them) This brings in 3 new commits. Change-Id: I64f27f346df264cb6eeeb4e3203fcca7d35f7e83 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47906 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Idwer Vollering <vidwer@gmail.com>
* Update vboot submodule to upstream masterJulius Werner2020-11-211-0/+0
| | | | | | | | | | | | | | | | | | | Updating from commit id 4c523ed1: vboot2: Add support for modexp acceleration to commit id 9d4053df: Revert "Reland: Clean up implicit fall through." This brings in 32 new commmits. Among the changes are restored support for older GCC/clang versions that do not support __attribute__((fallthrough)). Signed-off-by: Julius Werner <jwerner@chromium.org> Change-Id: I1110664bf71b4376bcdd9ba934a95031ba872c1d Reviewed-on: https://review.coreboot.org/c/coreboot/+/47784 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Joel Kitching <kitching@google.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
* 3rdparty/amd_blobs: update submodule pointerFelix Held2020-10-211-0/+0
| | | | | | | | | | | | | This now tracks a recently created upstream repository located at https://github.com/amd/firmware_binaries BUG=b:166107781 Change-Id: Ib193d646bb51cbf7b86f46828033e619c3f70e16 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46594 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
generated by cgit v1.2.3 (git 2.25.1) at 2024-06-01 04:11:07 +0000