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* 3rdparty/blobs: Update submodule pointer to include latest AMD ucodePaul Menzel2018-07-021-0/+0
| | | | | | | | | | | | | | | The two commits below are added to the BLOBs repository. * fe7c6a3 pcengines/apu2: Disable ECC Exclusion range * 3854ad2 cpu/amd/family_15h: Add latest AMD ucode file The latest AMD microcode patches include Spectre mitigations. Change-Id: I4729cc054fe8267549d7369cea4d26aa51861e1c Signed-off-by: Paul Menzel <pmenzel@molgen.mpg.de> Reviewed-on: https://review.coreboot.org/27297 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
* 3rdparty/libgfxinit: Update submodule pointerArthur Heymans2018-06-081-0/+0
| | | | | | | | | | | | | | | | | | Update to current master. This includes: - G45 support - fixes scaling on eDP (needed for working textmode on eDP) - gfx_test drawing and moving cursors - Adding support for Tiling on <= Haswell - Allow changes to the framebuffer configurarion without resetting the pipe. Change-Id: I4ff3c17ec7308115de7bf2f2bb9276c2fad41253 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/26823 Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* 3rdparty/libgfxinit: Update submodule pointerNico Huber2018-05-231-0/+0
| | | | | | | | | | | | | | Update to current master. Beside a minor workaround for GCC 8 compatibility, this includes only refactorings and preparations for G4x support. Change-Id: I6b2aa6bd9d41b852dacd8e1dfe89d92c8a548121 Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/26420 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* 3rdparty/chromeec: Update to latest masterPatrick Georgi2018-05-231-0/+0
| | | | | | | | | | Includes the necessary changes to build with gcc 8.1 Change-Id: Ie8c3dede4d702ab7838162dbff09f94df34b7c91 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-on: https://review.coreboot.org/26453 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
* 3rdparty/libhwbase: Update submodule pointerNico Huber2018-05-221-0/+0
| | | | | | | | | | Pull a minor update for GCC 8 compatibility. Change-Id: I0a4af47d56f3ca0b8ed82533e84c44041661ca35 Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/26306 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* 3rdparty/blobs: Update submodule marker for Intel microcode updatesMartin Kepplinger2018-05-151-0/+0
| | | | | | | | | | | | | | | | | | This adds the following changes to the blobs repository: 78a02a7 cpu/intel: microcode: add license agreement 1d37962 cpu/intel: add microcode updates 20180312 for new CPU models 8b8bbce cpu/intel: apply microcode updates 20180312 to currently tracked models In short: Bump Intel microcode updates. They include spectre/meltdown mitigations. Change-Id: I141f4446bc4e3bff5641bc39b70b299dc09ac8a7 Signed-off-by: Martin Kepplinger <martink@posteo.de> Reviewed-on: https://review.coreboot.org/26270 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Nico Huber <nico.h@gmx.de>
* Revert "3rdparty/blobs: Update submodule marker for Intel microcode updates"Nico Huber2018-05-121-0/+0
| | | | | | | | | | | | | | | This reverts commit 0ff9daac45d604fa4864394616e335e20af26c3e. It points to a stale commit under review; i.e. not to a commit on blob.git's master branch like it's supposed to. Change-Id: I19cb8a32b3971c3104e381673ca08ae4d3979128 Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/26241 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: David Hendricks <david.hendricks@gmail.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
* 3rdparty/blobs: Update submodule marker for Intel microcode updatesMartin Kepplinger2018-05-111-0/+0
| | | | | | | | | | | | | | | | | | | This moves the blobs submodule marker forward to include the following: b45abbd cpu/intel: microcode: add license agreement 1d37962 cpu/intel: add microcode updates 20180312 for new CPU models 8b8bbce cpu/intel: apply microcode updates 20180312 to currently tracked models in short: bump Intel's microcode updates to the latest version. This includes Spectre/Meltdown mitigations. Change-Id: I4ab74ae0bdcf2a109b0697ad233fbb812b5c4544 Signed-off-by: Martin Kepplinger <martink@posteo.de> Reviewed-on: https://review.coreboot.org/25505 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: David Hendricks <david.hendricks@gmail.com> Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
* Update vboot submodule to upstream masterDuncan Laurie2018-04-261-0/+0
| | | | | | | | | | | | | | | | Updating from commit id e0b38418: - image_signing: Add sha1sum of keys in keyset to VERSION.signer. To commit id 392211f0: - Update Android signing to support signature scheme v2 This fixes bulding with depthcharge master. Change-Id: I07b570f54b26a937a5a7c53ade464e0c7a550312 Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://review.coreboot.org/25837 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
* 3rdparty/libgfxinit: Update submodule pointerNico Huber2018-04-131-0/+0
| | | | | | | | | | | | | | | | | | | | | | Update libgfxinit to current master. Changes include: * a fix to decode the size stolen memory correctly on pre-SandyBridge hardware, * a PCI id based generation check, obsoleting the old check based on PCH audio ids, * some minor improvements around rarely used DDI ports (D and E), and * added support for tiled and rotated framebuffers on Skylake+ hardware (less interesting for coreboot, I guess?). TEST=Booted kontron/ktqm77 (Ivy Bridge) and pending kontron/bsl6 (Skylake) both with text and linear framebuffers and observed FILO's prompt showing up. Change-Id: I9a3c35c60b9edf8775f3a489df7577092910e127 Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: https://review.coreboot.org/25453 Reviewed-by: Martin Roth <martinroth@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* stoneyridge: Update AGESA binary and AGESA.hRichard Spiegel2018-03-161-0/+0
| | | | | | | | | | | | | | | | AGESA.bin was updated in the binary repo, so update the submodule pointer. Among other changes, this added a callback "AGESA_HALT_THIS_AP", which requires updated header files. BUG=b:70338633 TEST=build kahlee. Change-Id: I5a07f1c539d00aed34cfe45d6d7ef60c1dc56566 Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com> Reviewed-on: https://review.coreboot.org/25183 Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* Update chromeec submodule to upstream masterMartin Roth2018-02-221-0/+0
| | | | | | | | | | | | | | | | Updating from commit id 9fb10386a: 2017-06-21 04:19:06 -0700 (Poppy: Configure camera PMIC to low power mode.) to commit id 927b64a0b: 2018-02-15 00:10:45 -0800 (meowth: zoombini: enable CONFIG_CMD_PD_CONTROL) This brings in 1205 new commits. Change-Id: I3f7a1ceb1ea8c70d57a8f067023358b93df2670b Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/23480 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
* Update blobs submodule to upstream masterMarc Jones2018-02-051-0/+0
| | | | | | | | | | | | | | | | | | Updating from commit id a5efee5: 2018-01-04 16:24:19 -0700 - (Kahlee/Grunt: Move remaining stoneyridge blobs) to commit id 19dea8d: 2018-02-01 08:51:06 -0700 - (soc/amd/Stoneyridge: Update PSP binaries to AGESA 1.3.0.9) This brings in 2 new commits. Change-Id: I7858ad8be13d9992949effb0216723d2480fa74d Signed-off-by: Marc Jones <marcj303@gmail.com> Reviewed-on: https://review.coreboot.org/23562 Reviewed-by: Martin Roth <martinroth@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
* Update arm-trusted-firmware submodule to current upstream masterJulius Werner2018-02-021-0/+0
| | | | | | | | | | | | | | | | | | | | | | This patch updates the arm-trusted-firmware submodule from: commit 9fd4a36c408a254d887106e6e3960d496456be2c (Merge pull request #1211 from Leo-Yan/remove_ca73_cpu_nap_state) to commit 693e278e308441d716f7f5116c43aa150955da31 (Merge pull request #1245 from antonio-nino-diaz-arm/an/checkpatch) This brings in 79 new commits. Change-Id: Ieceb07760178f8ddbb5cafebabeb78f8def4072d Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/23555 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
* src/soc/amd/stoneyridge/Kconfig: Use vbios new locationRichard Spiegel2018-01-251-0/+0
| | | | | | | | | | | | | | | | | | 3rdparty/blobs was updated to move northbridge/amd/00670F00 contents into soc/amd/stoneyridge. Now soc/amd/stoneyridge/Kconfig needs to be updated to use VBIOS.bin new location. BUG=b:70785272 TEST=Update 3rdparty/blobs master branch, try to build kahlee. It should fail. Update soc/amd/stoneyridge/Kconfig, try to build kahlee again, it should work (need to rebuild .config first). CQ-DEPEND=CL:881709 Change-Id: I8cb9874eedc4a5d41d42b3f727c6d3cb9b920b5a Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com> Reviewed-on: https://review.coreboot.org/23398 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
* Update vboot submodule to upstream masterMartin Roth2018-01-231-0/+0
| | | | | | | | | | | | | | | | | Updating from commit id f6780a36: 2017-12-01 14:54:40 -0800 - (firmware: header tweaks for depthcharge) to commit id e0b38418: 2018-01-16 04:08:26 -0800 - (image_signing: Add sha1sum of keys in keyset to VERSION.signer.) This brings in 25 new commits. Change-Id: If60f19decd91eaafec1d555c1e7d3ca0249d8068 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/23332 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
* Update arm-trusted-firmware submodule to upstream masterMartin Roth2018-01-231-0/+0
| | | | | | | | | | | | | | | | | | Updating from commit id b1187232: 2017-06-20 15:34:54 +0100 - (Merge pull request #992 from davidcunado-arm/dc/fix-signed-comparisons) to commit id 9fd4a36c: 2018-01-17 17:34:29 +0000 - (Merge pull request #1211 from Leo-Yan/remove_ca73_cpu_nap_state) This brings in 596 new commits. Change-Id: Icbe7ede1583f715f3e30bf013df6ba164319e3a1 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/23331 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Julius Werner <jwerner@chromium.org>
* 3rdparty/blobs/soc/amd/stoneyridge: Use new location of stoneyridge blobRichard Spiegel2018-01-071-0/+0
| | | | | | | | | | | | | | | Stoneyridge related contents of 3rdparty/blobs/southbridge/amd/kern were moved to 3rdparty/blobs/southbridge/amd/stoneyridge. Commit the new blob to coreboot, and modify src/soc/amd/stoneyridge/Kconfig to use it. BUG=b:69613465 TEST=Build and run kahlee. Change-Id: I1784824dc7767c620e2fcbad7c6e5674934832ff Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com> Reviewed-on: https://review.coreboot.org/23125 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
* drivers/intel/gma: Power up legacy VGA block earlyNico Huber2017-12-121-0/+0
| | | | | | | | | | | | | | This is required at least on Skylake to be able to configure text mode. 3rdparty/libgfxinit is also updated by the single commit: 42fb2d065d gma: Add procedure to power up legacy VGA block Change-Id: I2fe144765e2b2acd9f6b76db375cae5b8feb5489 Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: https://review.coreboot.org/21386 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
* Update vboot submodule to upstream masterMarc Jones2017-12-091-0/+0
| | | | | | | | | | | | | | | | Updating from commit id 3b80572: 2017-10-12 16:35:30 -0700 - (tlcl, tpmc: extend GetVersion to report vendor specific data) to commit id f6780a3: 2017-12-01 14:54:40 -0800 - (firmware: header tweaks for depthcharge) This brings in 19 new commits. Change-Id: I49b1349cfd9266cd815b68759ae89bdffdd0d74b Signed-off-by: Marc Jones <marcj303@gmail.com> Reviewed-on: https://review.coreboot.org/22777 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* 3rdparty/lib{hwbase,gfxinit}: Update to latest masterNico Huber2017-10-282-0/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Simplifies our C interface function gma_gfxinit(), due to the following changes: * *libgfxinit* knows about the underlying PCI device now and can probe MMIO addresses by itself. * The framebuffer mapping is now completely handled inside the library where we validate that we neither overflow - the stolen memory, - the GTT address space, the GTT itself nor - the aperture window (i.e. resource2 of the PCI device) that we use to access the framebuffer. Other changes: * Fixes and a quirk for DP training. * Fix for DP-VGA adapters that report an analog display in EDID. * Fixes for Skylake support with coreboot. * DDI Buffer drive-strength configuration for Haswell, Broadwell and Skylake. * `gfx_test` can now be run from X windows (with glitches). * Compatibility with GCC 7 and SPARK GPL 2017. TEST=Booted lenovo/t420 and verified that everything works as usual. Change-Id: I001ba973d864811503410579fd7ad55ab8612759 Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/20606 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
* Update vboot submodule to upstream masterDaisuke Nojiri2017-10-221-0/+0
| | | | | | | | | | | | | | | | Updating from commit id a52fc548 (image_signing: Remove legacy unified build feature) to commit id 3b805725 (tlcl, tpmc: extend GetVersion to report vendor specific data) This brings in 22 new commits. Change-Id: I51e44490e0ffd2c5cc73d439c1f3f8831d816be9 Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org> Reviewed-on: https://review.coreboot.org/22004 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
* Update vboot submodule to upstream masterDaisuke Nojiri2017-09-131-0/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | Updating from commit id 3f3a496a 2017-09-01 09:20:19 (image_signing: Fix loem.ini pattern for unibuilds) to commit id 753e34e9 2017-08-31 10:12:40 (futility: Make rwsig sign command produce EC_RW image) This brings in 5 new commits. This also updates Depthcharge stable commit ID. Updating from a843f262 2016-08-16 08:41:04 (kahlee: select emmc boot first if available) to commit id f3bb31fe 2017-08-15 17:15:33 (vboot: Support EC early firmware selection) This brings in 14 new commits. Change-Id: I17d034e87fa642c5e30e933eb98bcfe5ceaaa3a8 Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org> Reviewed-on: https://review.coreboot.org/21490 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
* 3rdparty/vboot: update to latest masterPatrick Georgi2017-09-061-0/+0
| | | | | | | | | | | | | | Besides some internal changes that won't have much effect on coreboot, the newer version also supports building host tools on systems that self-designate as i686. Change-Id: I823bad862805cdec1dfecc8ba046f73ac206d3e8 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/21302 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Paul Kocialkowski <contact@paulk.fr> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
* Update vboot submodule to upstream masterMartin Roth2017-08-231-0/+0
| | | | | | | | | | | | | | | | | Updating from commit id 8b714252 - 2017-07-18 02:36:16 (crossystem: Remove defunct sw_wpsw_bootfield) to commit id 8c4b8285 - 2017-08-14 20:37:45 -0700 (detachables: Skip "Enable Developer Mode" in DEV mode) This brings in 6 new commits. Change-Id: I7769035453796a162c6313cd0c87661ef1e64f89 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/21074 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marc Jones <marc@marcjonesconsulting.com> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
* Update vboot submodule to upstream masterMartin Roth2017-07-311-0/+0
| | | | | | | | | | | | | | | | | Updating from commit id 04b3835b: 2017-06-12 06:47:41 -0700 - (Add a script to generate a keypair for signing Rose RW firmware.) to commit id 8b714252: 2017-07-18 02:36:16 -0700 - (crossystem: Remove defunct sw_wpsw_boot field) This brings in 19 new commits. Change-Id: Ib68068b1afc5a264623021325e19644e8b63f8f3 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/20702 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
* Update arm-trusted-firmware submodule to upstream masterMartin Roth2017-07-311-0/+0
| | | | | | | | | | | | | | | | | Updating from commit id 3944adca: 2017-03-18 12:16:27 +0000 - (Merge pull request #861 from soby-mathew/sm/aarch32_fixes) to commit id b1187232: 2017-06-20 15:34:54 +0100 - (Merge pull request #992 from davidcunado-arm/dc/fix-signed-comparisons) This brings in 373 new commits. Change-Id: I653007f664921305d22645f7904bb2d8eb85fe67 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/20701 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
* 3rdparty/chromeec: Update submodule to upstream masterMartin Roth2017-06-271-0/+0
| | | | | | | | | | | | | | | Update from commit bcffec7fd - reef: Cleanup battery code to commit 9fb10386a - Poppy: Configure camera PMIC to low power mode. Brings in 794 new commits from Jan 2, 2017 to Jun 21, 2017 Change-Id: I864679360bd3b211b6883a662e20812b49aefbba Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/20362 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
* 3rdparty/blobs: Update submoduleMartin Roth2017-06-271-0/+0
| | | | | | | | | | | | | Update blobs pointer to bring in the AGESA.bin changes for amd/00670F00/FP4 and amd/00670F00/FT4. Change-Id: I739124090e41edaf76210cda6189b2c7545cdf58 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/20324 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
* Update vboot submodule to upstream masterMartin Roth2017-06-171-0/+0
| | | | | | | | | | | | | | | | | | Update from commit a1c5f7c0 vboot_reference: Add support for 3072-bit exponent 3 keys to commit 04b3835b Add a script to generate a keypair for signing Rose RW firmware This brings in 34 new commits. Change-Id: Ifa304af5c2cf0bcc466dfc4878dd9d08436eec75 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/20228 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marc Jones <marc@marcjonesconsulting.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Philippe Mathieu-Daudé <philippe.mathieu.daude@gmail.com>
* 3rdparty/libgfxinit: Update submodule pointerNico Huber2017-06-081-0/+0
| | | | | | | | | | | | | | | | | | | | Update libgfxinit to the latest master. Changes: * Remove trailing whitespace in debug output. * Change some types to make it verify with SPARK Pro. * Add Broxton (Apollo Lake) support for eDP/DP/HDMI. * Add Linux user-space test tool `gfx_test`. * Add a README describing libgfxinit and the build process. TEST=Booted lenovo/t420 and verified that internal and external displays are working. Change-Id: I4d0e23b8a254234173461b831585eae58d3af58e Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: https://review.coreboot.org/20091 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
* 3rdparty/libhwbase: Update submodule pointerNico Huber2017-06-081-0/+0
| | | | | | | | | | | | | | | Update libhwbase to the current master. Some noteworthy changes: * Add prerequisites for upcoming Apollo Lake support in libgfxinit. * Add some support for Linux user-space for libgfxinit's `gfx_test`. * Fix compilation with GCC 7. Change-Id: If3c65065ef9a2ff6fce221939fda43c9e30c1eb8 Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: https://review.coreboot.org/20090 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
* 3rdparty/arm-trusted-firmware: Update to upstream masterMartin Roth2017-05-181-0/+0
| | | | | | | | | | | | | | | | | | | | | | Submodule 3rdparty/arm-trusted-firmware 236c27d21f..3944adca59 This brings in 241 new commits from the upstream arm-trusted-firmware repository, merged to the upstream tree between December 30, 2016 and March 18, 2017. 3944adca Merge pull request #861 from soby-mathew/sm/aarch32_fixes .. e0f083a0 fiptool: Prepare ground for expanding the set of images at runtime Also setup ATF builds so that unused functions don't break the build. They're harmless and they don't filter for these like we do. Change-Id: Ibf5bede79126bcbb62243808a2624d9517015920 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/18954 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
* 3rdparty/libgfxinit: Update submodule pointerNico Huber2017-04-081-0/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | Some renamings force us to update our code: * Scan_Ports() moved into a new package Display_Probing. * Ports Digital[123] are called HDMI[123] now (finally!). * `Configs_Type` became `Pipe_Configs`, `Config_Index` `Pipe_Index`. Other noteworthy changes in libgfxinit: * libgfxinit now knows about ports that share pins (e.g. HDMI1 and DP1) and refuses to enable any of them if both are connected (which is physically possible on certain ThinkPad docks). * Major refactoring of the high-level GMA code. Change-Id: I0ac376c6a3da997fa4a23054198819ca664b8bf0 Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/18770 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-by: Martin Roth <martinroth@google.com>
* 3rdparty/blobs: Update for AMD Stoney RidgeMarshall Dawson2017-03-281-0/+0
| | | | | | | | | | | Add the binaryPI file for the FT4 package and add SMU firmware to be consumed by fanless OPNs. Change-Id: I1c9b5ded6b494fac1553cc2ec7756a7a47386ecf Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/18988 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
* 3rdparty/vboot: Update to upstream masterMartin Roth2017-03-271-0/+0
| | | | | | | | | | | | This brings in 70 new commits from the upstream vboot repository, dated October 31, 2016 to March 2, 2017 Change-Id: Iac9c2b0389afbfa02c1cccc38d39a12dac4a5ac4 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/18953 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
* 3rdparty: update arm-trusted-firmware submoduleMartin Roth2017-01-121-0/+0
| | | | | | | | | | | | | | | Updated to arm-trusted-firmware TOT: 236c27d2 (Merge pull request #805 from Xilinx/zynqmp/addr_space_size) 183 commits between Sep 20, 2016 and January 10, 2017 - Also add associated change to src/soc/rockship/rk3399 Makefile.inc that is required to build the M0 Firmware. Change-Id: I49695f3287a742cd1fb603b890d124f60788f88f Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/18024 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
* chromeec: Update Chrome EC submoduleMartin Roth2017-01-101-0/+0
| | | | | | | | | | | | | | Update to Chromium TOT with bcffec7f (reef: Cleanup battery code) 292 commits between Oct 28, 2016 and Jan 2, 2017 Change-Id: I6bc356b9e458bebaa5839375ff40dd7e0d6ccff1 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/18023 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
* 3rdparty/libgfxinit: Update to latest masterNico Huber2016-12-151-0/+0
| | | | | | | | | | | | | | | | | | | | | | Changes: o Verification that the framebuffer matches the display mode o Automatic upscaling if the framebuffer resolution is lower than the display mode's o VGA-plane support o HDMI pixel rate is limited to hardware constraints o Error tolerant handling of EDID header-pattern Change-Id: Icbfdf5f37caf99f66847a71f784730aced0826ab Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: https://review.coreboot.org/17775 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
* 3rdparty/blobs: Update for AMD Stoney RidgeMarshall Dawson2016-12-151-0/+0
| | | | | | | | | | | Update the blobs submodule to bring in the binaries for 00670F00. This also corrects some formatting in the various license.txt files. Change-Id: I7a70d1168734d06ef6919d83dd73bc8f2bc4173c Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/17872 Reviewed-by: Marc Jones <marc@marcjonesconsulting.com> Tested-by: build bot (Jenkins)
* drivers/intel/gma: Hook up libgfxinitNico Huber2016-11-291-0/+0
| | | | | | | | | | | | | | | | | | | | | | | Add `libgfxinit` as another option for native graphics initialization. For that, the function gma_gfxinit() (see drivers/intel/gma/i915.h) has to be called by the respective northbridge/soc code. A mainboard port needs to select `CONFIG_MAINBOARD_HAS_LIBGFXINIT` and implement the Ada package `GMA.Mainboard` with a single function `ports` that returns a list of ports to be probed for displays. v2: Update 3rdparty/libgfxinit to its latest master commit to make things buildable within coreboot. v3: Another update to 3rdparty/libgfxinit. Including support to select the I2C port for VGA. Change-Id: I4c7be3745f32853797d3f3689396dde07d4ca950 Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: https://review.coreboot.org/16952 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
* Hook up libhwbase in ramstageNico Huber2016-11-291-0/+0
| | | | | | | | | | | | | | | | It's hidden behind a configuration option `CONFIG_RAMSTAGE_LIBHWBASE`. This also adds some glue code to use the coreboot console for debug output and our monotonic timer framework as timer backend. v2: Also update 3rdparty/libhwbase to the latest master commit. Change-Id: I8e8d50271b46aac1141f95ab55ad323ac0889a8d Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: https://review.coreboot.org/16951 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
* 3rdparty/vboot: update to latest masterFurquan Shaikh2016-11-101-0/+0
| | | | | | | | | | Require new recovery reason for rec hash space lock failure in RO. Change-Id: I606d1a1f51a3a4c127b2933f6fb00ba2ec4885fc Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/17340 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins)
* Set up 3rdparty/libgfxinitNico Huber2016-10-291-0/+0
| | | | | | | | | | | | `libgfxinit` is a SPARK library for graphics modesetting. It supports Intel integrated graphics only, strictly speaking, the Core i processor line. Change-Id: Idf4b0e5fbf37a5d974075b2e44d1fa16dc428da3 Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: https://review.coreboot.org/16949 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
* Set up 3rdparty/libhwbaseNico Huber2016-10-291-0/+0
| | | | | | | | | | | | `libhwbase` is a SPARK library that contains some basic support for i/o access, debugging, timers. Just what I put around `libgfxinit`, to make it build standalone. Change-Id: I1918680c14696215522e1c5dae072235bb4e71a3 Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: https://review.coreboot.org/16948 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
* chromeec: Update Chrome EC submoduleDuncan Laurie2016-10-291-0/+0
| | | | | | | | | | Update to Chromium TOT with ea1a8699e96425806abdd532d04da254ae093f6e Change-Id: I28b9f415a4d55442c294abd27c344a91608a06c0 Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://review.coreboot.org/17185 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins)
* chromeec: Update submoduleDuncan Laurie2016-10-281-0/+0
| | | | | | | | | | Update the chromeec submodule to current Chromium TOT. Change-Id: Ia3d913703fdea0ece02074d8e2d4b30d97e9a97c Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://review.coreboot.org/17179 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
* 3rdparty/vboot: update to latest master for rotor supportMartin Roth2016-10-211-0/+0
| | | | | | | | | | This pulls in the bdb support for futility so that rotor can build. Change-Id: Icfa432fb840bea3e1616933ed02cf34a681fa3ce Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/17061 Tested-by: build bot (Jenkins) Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
* google/gru: pass the gpio power supply enable pin to bl31Lin Huang2016-10-071-0/+0
| | | | | | | | | | | | | | | | | | | | | | | | | We need to disable some regulators when the device goes into suspend. This means that we need to pass some gpios to bl31, and disable these gpios when bl31 runs the suspend function. BRANCH=None BUG=chrome-os-partner:56423 TEST=enter suspend, measure suspend gpio go to low [pg: also update arm-trusted-firmware to match] Change-Id: Ia0835e16f7e65de6dd24a892241f0af542ec5b4b Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 0f3332ef2136fd93f7faad579386ba5af003cf70 Original-Change-Id: I03d0407e0ef035823519a997534dcfea078a7ccd Original-Signed-off-by: Lin Huang <hl@rock-chips.com> Original-Reviewed-on: https://chromium-review.googlesource.com/374046 Original-Commit-Ready: Caesar Wang <wxt@rock-chips.com> Original-Tested-by: Caesar Wang <wxt@rock-chips.com> Original-Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/16719 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
* 3rdparty/blobs: Update to get AGESA binary for pcengines/apu2Martin Roth2016-08-211-0/+0
| | | | | | | | | | | | The AGESA binary for PC Engines' APU2 board was just added to the blobs directory. Update the submodule pointer to allow access. Change-Id: Ic2995f253d12d17e229526cb71dea5bf65fa36f9 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/16253 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@googlemail.com>
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-10 03:37:36 +0000