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* mb/google/nissa/var/joxer: Add speaker ldo configTerry Chen2023-11-211-1/+5
| | | | | | | | | | | | | | Follow thermal validation, add ldo output select for speaker. BUG=b:297298847 TEST=emerge-nissa and deploy to DUT to verify audio functionality. Change-Id: Ie68f2b35f024b4dd066d831ae8fd5a662d407753 Signed-off-by: Terry Chen <terry_chen@wistron.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79111 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Derek Huang <derekhuang@google.com> Reviewed-by: Eric Lai <ericllai@google.com>
* mb/google/byra/var/*: Set LAN device type back to pciMatt DeVillier2023-11-2111-13/+13
| | | | | | | | | | | | | | | This partially reverts commit f493857c9bc1 ("mb/google/brya/var/*: Set dGPU/LAN/WLAN device type to generic"). Setting the LAN device type to generic broke programming the LAN MAC address, so set it back to pci. TEST=build/boot google/brya (osiris), verify LAN MAC address programmed correctly. Change-Id: I4fb43b7212e67b5c38724baad572860bc45b558e Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79150 Reviewed-by: Eric Lai <ericllai@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* mb/google/puff/var/*: Set LAN device type back to pciMatt DeVillier2023-11-2110-10/+10
| | | | | | | | | | | | | | | This mostly reverts commit 6c705e766f7f ("mb/google/puff/var/*: Set LAN/WLAN device type to generic"). Setting the LAN device type to generic broke programming the LAN MAC address, so set it back to pci. TEST=build/boot google/puff (wyvern), verify LAN MAC address programmed correctly. Change-Id: I558ae6dc1366d5a8a22e0383d7d597d15159df03 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79149 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <ericllai@google.com>
* util/crossgcc: Update CMake from 3.26.4 to 3.27.7Felix Singer2023-11-213-2/+2
| | | | | | | | Change-Id: I4dbe9b7a05171bb244ec1ebe6ce7d390a6373d61 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78883 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin L Roth <gaumless@gmail.com>
* acpi: Optimize enum acpi_tables layoutNaresh Solanki2023-11-201-5/+32
| | | | | | | | | | | | | Arrange ACPI table enum in a vertical and alphabetized format. This change aims to reduce conflicts between patches. Change-Id: I192339df771d6a3ae67358fe46334fe2b216b974 Signed-off-by: Naresh Solanki <naresh.solanki@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79099 Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de> Reviewed-by: Maximilian Brune <maximilian.brune@9elements.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* nb/intel/sandybridge: Use SA devid to identify PC typePatrick Rudolph2023-11-206-29/+15
| | | | | | | | | | | | | | | Instead of using MSR IA32_PLATFORM_ID read the SystemAgent device id to figure out the PC type. This follows the BWG which suggest to not use MSR IA32_PLATFORM_ID for system identification. Tested: Lenovo X220 still boots. Change-Id: Ibddf6c75d15ca7a99758c377ed956d483abe7ec1 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78826 Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
* cpu/intel/model_206ax: Lock MSR_PP_CURRENT_CONFIGPatrick Rudolph2023-11-202-0/+4
| | | | | | | | | | | | | Now that those registers are only written once set the lock bit to protect it from runtime changes. TEST: Lenovo X220 still boots. Change-Id: I4c56a3cb322a0e75eb3dd366808068093928e10c Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78608 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
* cpu/intel/model_206ax: Write MSRs in scope package only oncePatrick Rudolph2023-11-201-50/+72
| | | | | | | | | | | | | | | Write MSRs that are in scope package only once by checking for the BSP bit. While this improves performance a bit it also has the benefit that registers can be safely locked down without the need for semaphores. TEST: Lenovo X220 still boots. Change-Id: I43f5d62d782466d2796c1df6015d43c0fbf9d031 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78607 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
* nb/intel/sandybridge: Fix unitialized variable issueJeremy Compostella2023-11-201-1/+1
| | | | | | | | | | | | | commit 1e9601c5ef80 ("nb/intel/sandybridge: Standardize MRC vs. native SPD mapping API") introduced an uninitialized variable issue. Change-Id: I41b081dc4c961acc04423067e29e0eabe5f17539 Found-by: Coverity CID 1524317 Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79093 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com>
* Update vboot submodule to upstream mainJulius Werner2023-11-201-0/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Updating from commit id c59794a6: 2023-11-02 Nicholas Bishop sign_uefi: Support signing via pkcs11 to commit id f2b01bf0: 2023-10-27 Julius Werner firmware: Undeprecate VB2_RECOVERY_FW_GET_FW_BODY This brings in 66 new commits: c59794a6 sign_uefi: Support signing via pkcs11 68d4aa4b sign_uefi: Skip private key check if it's a pkcs11 URI 6b9d624b sign_uefi: Pass each key path separately 483f65e4 sign_official_build.sh: properly show errors on loem issues 516ee7bc sign_uefi: Use named args instead of positional 0eec8e25 vboot_reference-sys: Switch from Command to bindgen::Builder 46f5aab8 image_signing: support multiple release names f13af139 sign_official_build: Sudo invocation within bits of android signing 3f165374 futility: updater: Add optional serial number argument to --ccd 64379cc6 sign_official_build: add --debug flag 7160bf9f 2lib: Fix relocation issue when compiling locally with musl libc 0e27cdff vboot_reference-sys: Add vboot_host.h 2c82e73c Override use_apksigner FLAGS b43469c7 futility/cmd_show: Support --publickey FW_VBLOCK 0eb4da96 tests/futility: Update kern_preamble.bin as kernel_part.bin 68a03355 tests/futility: Move test_show_vs_verify.sh into test_show_and_verify.sh 8daf1474 tests/futility: Move 'futility show' tests to a separate file 34190e3d futility: Exit with error when metadata hash verification not supported 967aa462 firmware/2lib: Fix function comment for vb2api_get_firmware_size() f2b01bf0 firmware: Undeprecate VB2_RECOVERY_FW_GET_FW_BODY ef6d02df futility/vb2_helper: Add missing newline for error messages 886d13d7 PRESUBMIT: switch to cros format ac2e1a75 host/lib: Decouple openssl headers from HOSTLIB 86ec05f7 futility: updater: Add help info for --quirks 2850244e futility: updater: Abort if the unlock_csme_* is used on a locked device f1b5c88d devkeys: delete old unused firmware_bmpfv.bin 4444c5fe crossystem: Fix tpm_fwver for fwid < 12935 98ef339f 2lib: Prevent overwriting the value of fw_vboot2 c7517eb4 make_dev_ssd: support ChromeOS Kdump 8e3462cc tlcl: Increase the TPM_BUFFER_SIZE 740a2966 vboot_reference: Drop 'host' usage for 'internal' in flashrom.h 57877a44 vboot: Remove comments about physical dev switch 3401d16c 2lib: Fix typos, comments and formats fdf52d45 scripts/: Drop deprecated {g,s}et_gbb_flags.sh scripts bf76e9ee 2lib: Output the correct kernel_version 1ac4663e make_dev_firmware.sh: update pattern for matching wp status c57ab9f7 2lib: Add recovery reason VB2_RECOVERY_WIDEVINE_PREPARE e094ba31 tlcl: Reduce the variants of TPM2B b047600d sign_official_build: support key config for pkcs11 f8712b73 vboot: support signing with pkcs11 private key 17fe786f strip_boot_from_image.sh: sfill fast 6c856cd3 futility/updater: Fix EC software write protection logic 1dc5a421 futility: update: Deprecate --unlock_me by --quirk unlock_csme_nissa f0d88587 futility: update: Refactor the 'unlock ME' quirk(s) 81429ee9 futility: update: Do not update RO when the AP RO is locked a3beb737 futility: update: Revise the ordering or quirks 2c1844fa futility: update: Remove unused quirk 'unlock_wilco_me_for_update' 75530d32 tests/futility: Test with new signer_config.csv based firmware updater cba649fa 2lib: Expose 2hmac ab015448 2lib: Refactor hmac to vb2_hmac_calculate 3545f8b4 Revert "sign_uefi: Remove exception catching" 55f625a9 dump_fmap: Add offset and size to flash_ec format output a27ee336 keygeneration: add shellcheck source statements to help linting 055f9aa2 keygeneration: replace_recovery_key.sh: make minios key optional 6cb8ab60 scripts: delete unused values kernel command line 1f76c38b vboot: Drop phone recovery support ccf6b037 scripts: Legacy fix for set_gbb_flags.sh 8f03069e futility: Add basic README.md 88963df8 utility: Query platform wp status with futility 6c3817d2 utility: Drop cros_alias technical debt in dev_debug_vboot df85f512 scripts: Drop cros_alias technical debt in make_dev_firmware.sh 7395cd68 futility/updater_utils.c: Match on EC path to prepare for split 52518415 crossystem: Recover corrupted RW_NVRAM on flash writes 81f9ddaf futility/cmd_gbb_utility.md: Add basic GBB subcmd doc c4995268 futility/: Fix define confusion 69dab5a6 crossystem: Avoid writing duplicate entries to RW_NVRAM 6c37b520 Revert "crossystem: stop supporting legacy chromeos_acpi driver" Change-Id: Ic7ecdabcdd26df349b8abf1c5a77c806facfe1d8 Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78865 Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* mb/goog/brya/var/brya0/skolas: Disable HPS GPIOs if HPS_ABSENTNick Vaccaro2023-11-202-0/+28
| | | | | | | | | | | | | | | | Check FW_CONFIG and disable gpios for HPS if HPS_ABSENT for skolas and brya0 variants. BUG=b:311740746 BRANCH=firmware-brya-14505.B TEST=`emerge-brya coreboot chromeos-bootimage`, flash and boot skolas to kernel and verify via "cbmem -c | grep HPS". Change-Id: I8cbe4f40c41f1d06e8f511c3e88c05984566d441 Signed-off-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79123 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <ericllai@google.com>
* mb/goog/brya/var/brya0/skolas: Disable LTE GPIOs if LTE_ABSENTNick Vaccaro2023-11-202-0/+56
| | | | | | | | | | | | | | | | Check FW_CONFIG and disable gpios for LTE if LTE_ABSENT for skolas and brya0 variants. BUG=b:311459627 BRANCH=firmware-brya-14505.B TEST=`emerge-brya coreboot chromeos-bootimage`, flash and boot skolas to kernel and verify LTE gpios are disabled via "cbmem -c | grep LTE". Change-Id: I3f3bc2b536babf71cc484cce02f96f47707f729c Signed-off-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79122 Reviewed-by: Eric Lai <ericllai@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* mb/goog/brya/var/skolas: sync slolas overridetree with brya0Nick Vaccaro2023-11-201-6/+81
| | | | | | | | | | | | | | | | | Skolas uses brya0 schematic, so override tree should be almost the same for brya0 and skolas. This change sync's the skolas overridetree.cb with brya0's overridetree.cb. BUG=b:311722825 BRANCH=firmware-brya-14505.B TEST=`emerge-brya coreboot chromeos-bootimage`, flash and boot skolas to kernel. Change-Id: I14a2ed803a8ffb8614018af587c66034fb724b38 Signed-off-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79121 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <ericllai@google.com>
* sbom/Makefile.inc: Change GOPATHMaximilian Brune2023-11-201-1/+1
| | | | | | | | | | | | | | | | This changes the path where go installs its packages. Now the packages are not installed in the users home directory anymore. This solution is not perfect though, since offline build are still not possible, because go will fetch the packages at build time. -modcacherw will create the go files with rw permissions, otherwise coreboot is not able to delete the files afterwards (make distclean). Signed-off-by: Maximilian Brune <maximilian.brune@9elements.com> Change-Id: I2a35369628454057ea4758cd1225e57f07cb71c8 Reviewed-on: https://review.coreboot.org/c/coreboot/+/77780 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin L Roth <gaumless@gmail.com>
* mb/google/geralt: Remove unnecessary delay for MIPI panelYidi Lin2023-11-201-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | According to eDP panel datasheet[1], the eDP panel needs 0 <= x <=200ms delay after VDD powering on. The MIPI panel[2] does not need this delay. Move this delay to eDP path. [1] NE135FBM-N41 V8.0 Product Spec_P2 20191025.pdf [2] B5 TV110C9M-LL0 Product Specification Rev.P0 BRANCH=none BUG=none TEST=check FW screen TEST=check timestamp Before: 60:device initialization 696,422 (1) 15:starting LZMA decompress (ignore for x86) 696,587 (165) 16:finished LZMA decompress (ignore for x86) 696,675 (88) 17:starting LZ4 decompress (ignore for x86) 1,340,226 (643,551) After: 60:device initialization 724,259 (1) 15:starting LZMA decompress (ignore for x86) 724,425 (166) 16:finished LZMA decompress (ignore for x86) 724,512 (87) 17:starting LZ4 decompress (ignore for x86) 1,168,176 (443,664) Change-Id: I92bca5ec8269f4bad4dfab4ee193cdb5665de233 Signed-off-by: Yidi Lin <yidilin@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79109 Reviewed-by: Ruihai Zhou <zhouruihai@huaqin.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com> Reviewed-by: Eric Lai <ericllai@google.com> Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
* cross-repo-cherrypick: Update downstream branchJon Murphy2023-11-201-1/+1
| | | | | | | | | | | | | | | ChromeOS has switched to using the main branch, update accordingly. BUG=b:294218930 TEST=None Change-Id: I31f67ef4fb175a4e4896b5bed81d5ae1cdddb827 Signed-off-by: Jon Murphy <jpmurphy@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79143 Reviewed-by: Eric Lai <ericllai@google.com> Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
* Documentation/releases: Add 24.02 release notes templateMartin Roth2023-11-192-1/+101
| | | | | | | | | | | In preparation for the upcoming release, add the template for the 24.02 release and update index.md. Signed-off-by: Martin Roth <gaumless@gmail.com> Change-Id: I694142c31ba684e7b94640d55302b2440e25619a Reviewed-on: https://review.coreboot.org/c/coreboot/+/79073 Reviewed-by: Matt DeVillier <matt.devillier@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* sb/intel/bd82x6x: assign PCH HDA controller ops in chipset devicetreeFelix Held2023-11-182-10/+2
| | | | | | | | | | | | | | | | Since the HD audio controller in the PCH are always on the same device functions, the device operations can be statically assigned in the devicetree and there's no need to bind the host bridge device operations to the PCI device during runtime via a list of PCI IDs. TEST=Lenovo X220 still boots to Linux and audio still works Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: Patrick Rudolph <patrick.rudolph@9elements.com> Change-Id: I9bbbe9f4490dc6fb21174d63d1c8906d69ea3ee0 Reviewed-on: https://review.coreboot.org/c/coreboot/+/79118 Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* sb/intel/bd82x6x: assign PCIe root port ops in chipset devicetreeFelix Held2023-11-182-21/+9
| | | | | | | | | | | | | | | | | Since the PCIe root ports in the PCH are always on the same device functions, the device operations can be statically assigned in the devicetree and there's no need to bind the host bridge device operations to the PCI device during runtime via a list of PCI IDs. TEST=Lenovo X220 still boots to Linux and all PCIe devices on PCH are visible and working. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: Patrick Rudolph <patrick.rudolph@9elements.com> Change-Id: I05bfe8db88fd54415f320f32ea147636ca4e0df8 Reviewed-on: https://review.coreboot.org/c/coreboot/+/79117 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com>
* nb/intel/sandybridge: assign gma ops in chipset devicetreeFelix Held2023-11-182-15/+2
| | | | | | | | | | | | | | | | | Since the integrated GPU is always function 0 of device 2 on bus 0, the device operations can be statically assigned in the devicetree and there's no need to bind the host bridge device operations to the PCI device during runtime via a list of PCI IDs. TEST=Lenovo X220 still boots to Linux and graphics works in UEFI Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: Patrick Rudolph <patrick.rudolph@9elements.com> Change-Id: I20e387e626e19dc441aceda18451186d1e86cd5f Reviewed-on: https://review.coreboot.org/c/coreboot/+/79114 Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* nb/intel/sandybridge: assign host bridge ops in chipset devicetreeFelix Held2023-11-182-14/+2
| | | | | | | | | | | | | | | | | Since the host bridge is always function 0 of device 0 on bus 0, the device operations can be statically assigned in the devicetree and there's no need to bind the host bridge device operations to the PCI device during runtime via a list of PCI IDs. TEST=Lenovo X220 still boots to Linux Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: Patrick Rudolph <patrick.rudolph@9elements.com> Change-Id: Icf3d9f8cd2be2f8ef71fd9fdb5f005f3b683332e Reviewed-on: https://review.coreboot.org/c/coreboot/+/79113 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com>
* util/lint: Add linter to keep selects out of Kconfig.name4.22Martin Roth2023-11-181-0/+16
| | | | | | | | | | | | | | | | | | While having select statements in Kconfig.name files is valid in the syntax of the Kconfig language, having the selections split between the normal Kconfig file and Kconfig.name files makes it harder to see what's going on. Kconfig.name files will now be limited to their original purpose of selecting a particular board or board variant, not actually configuring that board. Signed-off-by: Martin Roth <gaumless@gmail.com> Change-Id: I2aab78e296f2958e77a938b1afa40a25a6aa82b0 Reviewed-on: https://review.coreboot.org/c/coreboot/+/78972 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Maximilian Brune <maximilian.brune@9elements.com> Reviewed-by: Julius Werner <jwerner@chromium.org>
* mb/google/brox: Use Ti50 configShelley Chen2023-11-182-1/+2
| | | | | | | | | | | | | | Brox is using Ti50, so make sure that we set the right config for that. BUG=b:300690448 BRANCH=None TEST=emerge-brox coreboot Change-Id: If4a16448eebc028b2989c1de150b9e0f9067ee92 Signed-off-by: Shelley Chen <shchen@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79100 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
* mb/google/brox: Fix GPIO assignments in gpio.hShelley Chen2023-11-182-8/+8
| | | | | | | | | | | | | | | | | Assigning the macros in gpio.h to the correct GPIOs. Also, fixing GPE configurations so that they are mapped to the proper wake sources (GPP_B, D, E groups). BUG=b:300690448 BRANCH=None TEST=emerge-brox coreboot Change-Id: I6320cd98e560e514e63c52e173cb7923cfd1cdee Signed-off-by: Shelley Chen <shchen@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78952 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
* qualcomm/sc7180: Move QCSDI and increase romstage size by 4KBJulius Werner2023-11-181-2/+2
| | | | | | | | | | | | | | | | | | We need to increase romstage size a little to make a compiler upgrade fit (CB:70771). Unfortunately the end of the romstage directly touches the QCSDI region in the current memlayout, and there is no other way to reshuffle things to make more space... so we need to move QCSDI out of the way. This means that anyone who is actually building this platform with CONFIG_QC_SDI_ENABLE (which requires a proprietary blob that's not publicly available) will need to recompile their QCSDI binary to match the new start address. Change-Id: Iaf13e4001b3c763e3ec59009779931ec75603d5d Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79074 Reviewed-by: Shelley Chen <shchen@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
* Docs/releases: Update 4.22 release notesMartin Roth2023-11-181-60/+270
| | | | | | | | | | | | These should be the final release notes prior to tagging coreboot Signed-off-by: Martin Roth <gaumless@gmail.com> Change-Id: Id723f8e1fc92ef1a36e877f48e594eef59b0ba8e Reviewed-on: https://review.coreboot.org/c/coreboot/+/79077 Reviewed-by: Jason Glenesk <jason.glenesk@gmail.com> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
* docker/coreboot-sdk: Add perl modules for gcovMartin Roth2023-11-171-0/+3
| | | | | | | | | | | These perl modules are needed to run the coverage-report target for gcov. Signed-off-by: Martin Roth <gaumless@gmail.com> Change-Id: If32a42ce17edcbae94394f770c26d3300abebcbe Reviewed-on: https://review.coreboot.org/c/coreboot/+/79072 Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* Docs/security/vboot: Update list of boards with vbootMartin Roth2023-11-171-12/+24
| | | | | | | | | | Update the vboot board list for the 4.22 release. Signed-off-by: Martin Roth <gaumless@gmail.com> Change-Id: I77c5ca2c2c36d8b1ddadad4f15d2d4148ff0b325 Reviewed-on: https://review.coreboot.org/c/coreboot/+/79071 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jason Glenesk <jason.glenesk@gmail.com>
* mb/google/herobrine: Move selects from Kconfig.name to KconfigFelix Singer2023-11-172-9/+27
| | | | | | | | | | | Selects should be done in the Kconfig file instead of Kconfig.name and not mixed over both files. Change-Id: I25b7adccf60abe515d129f8d00383165eccf6431 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79028 Reviewed-by: Martin L Roth <gaumless@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* mb/google/trogdor: Move selects from Kconfig.name to KconfigFelix Singer2023-11-172-13/+39
| | | | | | | | | | | Selects should be done in the Kconfig file instead of Kconfig.name and not mixed over both files. Change-Id: I30a15277527a1e423691ff55ff11cc2136cefc90 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79027 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin L Roth <gaumless@gmail.com>
* soc/qualcomm/{sc7180,sc7280}: Allow building without QC blobs repoFelix Singer2023-11-175-17/+9
| | | | | | | | | | | | | | | | | | Building coreboot for the Qualcomm SoCs SC7180 and SC7280 requires to include the Qualcomm blobs, which requires to accept their license. However, for various reasons it makes sense to build without blobs, e.g. static analysis or just build-testing. So in order to do that, run the steps integrating the Qualcomm blobs into the coreboot binary only if USE_QC_BLOBS is enabled and also remove guards which prevent building related mainboards when USE_QC_BLOBS is not enabled. Change-Id: I249ac477b8f10e7fa0848e967c23a3b3b9bbd27d Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79026 Reviewed-by: Martin L Roth <gaumless@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* nb/amd/pi/00730F01: add CPU and domain ops in devicetreeFelix Held2023-11-172-14/+6
| | | | | | | | | | | | | | Add the CPU and PCI domain operation bindings statically in the chipset devicetree instead of adding them during runtime. TEST=PC Engines APU2 still boots and doesn't show any new problems Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I44fa57458c408e74a6341643620c5e9ac1817557 Reviewed-on: https://review.coreboot.org/c/coreboot/+/79085 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-by: Nico Huber <nico.h@gmx.de>
* nb/amd/pi/00730F01: restructure chip opsFelix Held2023-11-176-57/+42
| | | | | | | | | | | | | | | | Since this chip is a SoC and also to bring the chipset devicetree more in line with the chipset devicetree of Sandy Bridge, merge the chip operations of the northbridge's root complex and the northbridge itself into one chip operations structure and use it at the top level of the devicetree. TEST=PC Engines APU2 still boots and doesn't show any new problems Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I8b42bac07b1409bbc797bc4428cf9f84a40e94c2 Reviewed-on: https://review.coreboot.org/c/coreboot/+/79084 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
* nb/amd/pi/00730F01: introduce and use chipset devicetreeFelix Held2023-11-176-148/+118
| | | | | | | | | | | | | | | BKDG #52740 Rev 3.05 was used as a reference for the SoC's various PCI devices. The HDA controller in the FCH at function 2 of device 0x14 on bus 0 was missing in the mainboard's devicetrees. TEST=PC Engines APU2 still boots and doesn't show any new problems Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I6970c2f6e6d661d40406586f4e6eeb05bcd07979 Reviewed-on: https://review.coreboot.org/c/coreboot/+/79083 Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
* include/device/device: drop HAVE_ACPI_TABLES guardsFelix Held2023-11-171-2/+1
| | | | | | | | | | | There's no need to remove the corresponding fields from the device_operations struct when HAVE_ACPI_TABLES isn't selected. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Iac20b6cdc44a5280566ee7003a5ef6fbe913b099 Reviewed-on: https://review.coreboot.org/c/coreboot/+/78990 Reviewed-by: Matt DeVillier <matt.devillier@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* include/device/device: drop GENERATE_SMBIOS_TABLES guardsFelix Held2023-11-171-2/+2
| | | | | | | | | | | There's no need to remove the corresponding fields from the device_operations struct when GENERATE_SMBIOS_TABLES isn't selected. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ifa24d1fd211c263b788046e63de3dd5c54cba801 Reviewed-on: https://review.coreboot.org/c/coreboot/+/79092 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
* mb/google/corsola: Configure I2C and I2S interface for ALC5650wuyang52023-11-171-2/+20
| | | | | | | | | | | | | | | | | Configure I2S1 and I2C5 for ALC5650 to support beep sound in depthcharge. BRANCH=corsola BUG=b:305828247 TEST=Verify devbeep in depthcharge console Change-Id: Ibd098adb8d5568ad338bbfece0edfd0c38cbf854 Signed-off-by: Yang Wu <wuyang5@huaqin.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79064 Reviewed-by: Yidi Lin <yidilin@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Ruihai Zhou <zhouruihai@huaqin.corp-partner.google.com> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
* MAINTAINERS: Add Dinesh Gehlot as MTL SOC and GOOGLE REX MB maintainerDinesh Gehlot2023-11-171-0/+2
| | | | | | | | Change-Id: I92d5497644338927b81fbabea2bce45f1e59f0b4 Signed-off-by: Dinesh Gehlot <digehlot@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79090 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com>
* mb/google/zork/morphius: Drop touchscreen detectionMatt DeVillier2023-11-171-1/+0
| | | | | | | | | | | | | | | | Morphius boards using pre-v3.6 schematics don't have a dedicated GPIO for touchscreen power/enable, and so fail with runtime detection enabled. Since it only has one touchscreen option, and no SKUs lack a touchscreen, we can safely assume it is present in all cases. TEST=build/boot morphius w/4k screen, verify touchscreen enabled in cbmem and functional in Linux and Windows. Change-Id: I13e07e14b5a18fa1dd3b18950cf46e9d7821eedc Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78404 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
* util/docker: Switch back to root user in jenkins-nodeMartin Roth2023-11-161-0/+1
| | | | | | | | | | | | | Leaving the user as coreboot caused the entrypoint to run as coreboot, which means we couldn't mount directories or run sshd correctly. Switching to root at the end of the file fixes this. Signed-off-by: Martin Roth <gaumless@gmail.com> Change-Id: Ie10e1d7ad4def0faafe3bcd580a77e23c3bfe948 Reviewed-on: https://review.coreboot.org/c/coreboot/+/79067 Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* util/ifdtool/ifdtool.c: Add NULL check for fmapnameMaximilian Brune2023-11-161-0/+8
| | | | | | | | | | | | | | | | | | Some boards (e.g. prodrive/hermes) that do not provide their own FMAP and therefore have been generated by the build system (+ ifdtool) experience a failure when trying to build with an IFD that contains regions which do not have equivalent fmap names (set to NULL). Therefore add a NULL check for the fmapname and ignore the region if we do not have an fmapname. Test: compile prodrive/hermes Signed-off-by: Maximilian Brune <maximilian.brune@9elements.com> Change-Id: Ib4589b7fdbd11d644214ca5601536e9aeb26882f Reviewed-on: https://review.coreboot.org/c/coreboot/+/79010 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
* ec/google/chromeec: Update ec_cmd_api.h and ec_commands.hSimon Glass2023-11-162-6/+471
| | | | | | | | | | | | | | | | | | | Generated using update_ec_headers.sh [EC-DIR]. The original include/ec_commands.h version in the EC repo is: ab9b64ac4c Add a host command to print info about AP-firmware state The original include/ec_cmd_api.h version in the EC repo is: ab9b64ac4c Add a host command to print info about AP-firmware state BUG=b:300525571 BRANCH=none TEST=none Change-Id: I3570e073a91621cb1d28a24aa35c1f4beedceaab Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79066 Reviewed-by: Caveh Jalali <caveh@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* acpi/device: Only return dev->ops->acpi_name if non-NULLCoolStar2023-11-161-2/+5
| | | | | | | | | | | | | | | | | | Returning a NULL device name can cause issues if something else does handle it. E.g. UART and GNA devices on Intel Alder Lake-N cause INTERNAL_POWER_ERROR BSOD's in Windows when enabled due to invalid packages being created from a NULL name Test: build/boot google/nissa (craaskvin) to Win11 Change-Id: I0679147ad3e330d706bbf97c30bc11b2432e2e8a Signed-off-by: CoolStar <coolstarorganization@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77413 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
* mb/google/skyrim/frostflow: Drop GPIO override for camera shutterMatt DeVillier2023-11-161-2/+0
| | | | | | | | | | | | | | | | | Appears to not be used under Windows, Linux, or ChromeOS, and causes high CPU usage at idle under Windows. BUG=none TEST=build/boot Win11, Linux on google/frostflow, verify camera shutter function unchanged, CPU usage under Windows idles where expected. Change-Id: I8a6ea3b886766bdb055b40949c75bec0264eecc5 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77678 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Eric Lai <ericllai@google.com> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
* Revert "tests: Allow specifying vboot source directory"Felix Singer2023-11-163-2/+2
| | | | | | | | | | | | | | This reverts commit 7713a2f295d9ed9a7023a78e085ce190ee1203fe. Reason for revert: breaks main branch Change-Id: I2749bea9369c222e510b838e278c7797d5dce56e Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78852 Reviewed-by: Martin L Roth <gaumless@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Patrick Georgi <patrick@coreboot.org>
* Update amd_blobs submodule to upstream main branchMatt DeVillier2023-11-161-0/+0
| | | | | | | | | | | | | | | | | Updating from commit id edd465837e26 (2023-10-20): cezanne: Update PSP binaries to release 0.11.11.75 to commit id e4519efca746 (2023-11-15): Revert "picasso: Update PSP binaries to release 0.8.13.7B" This brings in 1 new commit: e4519efca7 Revert "picasso: Update PSP binaries to release 0.8.13.7B" Change-Id: I860aa04324128199cbc91a5f310fcdf92a2cd65d Signed-off-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79065 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
* mb/system76/rpl: Allow 5600 MT/s memory for RPL-HXMatt Parnell2023-11-163-6/+6
| | | | | | | | | | | | | | | | | | System76 only sells units with memory speeds up to 5200 MT/s, but the i9-13900HX supports up to 5600 MT/s memory. Tested by running memtest and checking dmidecode reports 5600 MT/s when using 2x16 GB 5600 MT/s Crucial SODIMMs (CT2K16G56C46S5) on addw3, bonw15, serw13. Change-Id: I9bb0435769c70c1db06d2c5cca2dd28eb5331f49 Signed-off-by: Matt Parnell <mparnell@gmail.com> Signed-off-by: Tim Crawford <tcrawford@system76.com> Tested-by: Levi Portenier <levi@system76.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78912 Reviewed-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* mb/supermicro/x11: Make use of chipset devicetreeFelix Singer2023-11-165-92/+54
| | | | | | | | | | | Use the references from the chipset devicetree as this makes the comments superfluous and remove devices which are turned off. Change-Id: I5176aa56ecaa52d0f42455bc7176b0415a6199ec Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78594 Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* tests: Allow specifying vboot source directoryroccochen@chromium.com2023-11-163-2/+2
| | | | | | | | | | | | | | | | Respect VBOOT_SOURCE while including generic headers. BUG=none TEST=make clean-unit-tests && VBOOT_SOURCE=/path/to/vboot_reference/ make unit-tests -j TEST=make clean-unit-tests && make unit-tests -j BRANCH=none Change-Id: Id3bb3726c91167d2dd648d748763a3948787f28d Signed-off-by: roccochen@chromium.com <roccochen@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78849 Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* mb/google/geralt: Disable SD card support for CiriRuihai Zhou2023-11-161-1/+2
| | | | | | | | | | | | | | | According to proto schematics, the SD card is removed. BUG=b:308968270 TEST=emerge-geralt coreboot BRANCH=None Change-Id: Id4e021e7896d093560f39c40573ac616d76438c2 Signed-off-by: Ruihai Zhou <zhouruihai@huaqin.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78958 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: cong yang <yangcong5@huaqin.corp-partner.google.com> Reviewed-by: Yidi Lin <yidilin@google.com>
generated by cgit v1.2.3 (git 2.25.1) at 2024-07-17 05:10:56 +0000