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* device/dram/ddr3.c: Check SPD byte before using as a divisorMartin Roth2023-10-251-0/+4
| | | | | | | | | | | | | | The Medium Time Base (MTB) value is calculated by dividing one SPD byte by another. Return an error if the divisor is zero before using the value for division. Found-by: Coverity Scan #1469303 Signed-off-by: Martin Roth <gaumless@gmail.com> Change-Id: Ic0a70291c42b5c2d21d65de92487b2dd88609983 Reviewed-on: https://review.coreboot.org/c/coreboot/+/78613 Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
* include/device/dram: Add SPD lengths for DDR3 to DDR5Martin Roth2023-10-254-3/+12
| | | | | | | | | | | | | | DDR2 already had a define to specify the SPD length, but other memory types did not. This led to the value being coded into other locations. Unify the definition for DDR2 to DDR5 and put the value at the top of the respective header file. Signed-off-by: Martin Roth <gaumless@gmail.com> Change-Id: Id13b9c5d311984d4a98b831a8746d1659724aa96 Reviewed-on: https://review.coreboot.org/c/coreboot/+/78601 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Keith Hui <buurin@gmail.com> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
* SNB+MRC boards: Migrate MRC settings to devicetreeKeith Hui2023-10-2529-609/+333
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | For Sandy Bridge boards with MRC raminit support, migrate as much MRC settings to devicetree as possible, to stop mainboard code from needlessly overwriting entire PEI data structure, so they will not interfere with upcoming transition to one standard Haswell way of providing SPD info to northbridge. Some exceptions allowed are described below and in code comments. SPD-related items are kept out of devicetree for now. They will be migrated (with a different representation) with the Haswell SPD transition. google/{butterfly,link,parrot,stout} have max DDR3 frequency set in pei_data to 1600 (2*800), but in devicetree to 666. The reason for the difference seems to be problems with native raminit code. These are converted into ternaries tied to CONFIG_USE_NATIVE_RAMINIT, with an added "fix me" tag. asus/p8x7x-series also needs the same treatment, based on testing various memory on p8z77-m hardware. TEST=Builds on all affected boards. asus/p8z77-m still works with multiple RAM modules tested. Change-Id: Ie349a8f400eecca3cdbc196ea0790aebe0549e39 Signed-off-by: Keith Hui <buurin@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76962 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin L Roth <gaumless@gmail.com>
* cbmem.h: Drop cbmem_possible_online in favor of ENV_HAS_CBMEMArthur Heymans2023-10-259-26/+9
| | | | | | | | | | | The macro ENV_HAS_CBMEM achieves the same as this inline function. Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Change-Id: I6d65ca51c863abe2106f794398ddd7d7d9ac4b5e Reviewed-on: https://review.coreboot.org/c/coreboot/+/77166 Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jakub Czapiga <czapiga@google.com>
* soc/intel/meteorlake: Add PsysPmax configurationJakub Czapiga2023-10-242-0/+8
| | | | | | | | | | | | | | | psys_pmax_watts is configured in SoC node of devicetree. Value represents Watts the PSU provides. Zero means automatic/default configuration (not optimal). BUG=b:289853442 TEST=Build google/rex/ovis4es target board Change-Id: I69afa06110254f6384352c062891c0c9c0b23070 Signed-off-by: Jakub Czapiga <jacz@semihalf.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76796 Reviewed-by: Martin L Roth <gaumless@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* mb/google/skyrim/var/crystaldrift: Update the STT settingsYunlong Jia2023-10-241-4/+13
| | | | | | | | | | | | | | | | Adjust the STT settings. BRANCH=none BUG=b:270112575 TEST=emerge-skyrim coreboot chromeos-bootimage Then the thermal team has verified. Signed-off-by: Yunlong Jia <yunlong.jia@ecs.corp-partner.google.com> Change-Id: I1df9bbf820b5a760007dcfd7bceb21063fc24696 Reviewed-on: https://review.coreboot.org/c/coreboot/+/78523 Reviewed-by: Tim Van Patten <timvp@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
* mb/google/zork: Use device aliases in device/overridetreesMatt DeVillier2023-10-242-6/+6
| | | | | | | | | | | Replace all remaining numeric references to PCI devices with their aliases in chipset.cb. Change-Id: I636f04c06c250639867c770511095773cb0c5205 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78508 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
* Update amd_blobs submodule to upstream main branchMatt DeVillier2023-10-241-0/+0
| | | | | | | | | | | | | | | | | | | | | Updating from commit id b1741d184add (2023-10-04): PCO: Update SMU firmware to 4.30.77.200 to commit id edd465837e26 (2023-10-20): cezanne: Update PSP binaries to release 0.11.11.75 This brings in 4 new commits: edd465837e cezanne: Update PSP binaries to release 0.11.11.75 480c9d2efd picasso: Update PSP binaries to release 0.8.13.7B 1b1fd40889 Stoneyridge: Update SMU firmware for fanless/kicker to 33.10.0 c99172d385 Stoneyridge: Update SMU firmware to 26.17.0 Change-Id: I1fc1756a204e5f637ca67ef51daf4592572a6a17 Signed-off-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78515 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
* soc/amd/stoneyridge: Update SMU fw2 name in fw.cfgMatt DeVillier2023-10-241-1/+1
| | | | | | | | | | | | | | | | | | | | | Update the filename for the PSP_SMUFW2_SUB1_FILE to use the compressed and signed version (.csbin) rather than the uncompression + signed version (.sbin), in order to be consistent with the other SMU firmware files. This will also facilitate dropping the duplicate files in an upcoming update to the amd_blobs repo and updating the SMU files (all of which are .csbin). This change is actually a no-op since the .csbin and .sbin are the same file; it appears that the .sbin file was incorrectly named when added, and then the same file was added later with the correct extension. TEST=build/boot google/kahlee (liara) Change-Id: I10fa8e949ab589d315862c06b4125c902520cbbc Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78512 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
* mb/google/kahlee: Enable display backlight control in WindowsCoolStar2023-10-241-0/+1
| | | | | | | | | | | | | | | | | Utilize the SOC_AMD_COMMON_BLOCK_GRAPHICS_ATIF to provide the Windows driver with information on backlight settings. TEST: Boot google/careena to Win10. Observe display brightness controls functional after driver loads (immediately with patched driver, 30 minutes with unpatched). Change-Id: I6792a91f26a5f6e4dc478cdde776ff749f08946f Signed-off-by: CoolStar <coolstarorganization@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78429 Reviewed-by: Eric Lai <ericllai@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
* soc/amd/stoneyridge: Use common block graphics driverCoolStar2023-10-244-7/+3
| | | | | | | | | | | | | | | Select the common block graphics driver for Stoneyridge. Drop Stoney's ACPI stub for the iGPU as the device will now be generated by the common block acpigen and put into the SSDT. TEST=tested with rest of patch train Change-Id: I260b964be59c1a208ff907c474243a9ace03f206 Signed-off-by: CoolStar <coolstarorganization@gmail.com> Signed-off-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78428 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* soc/amd/common/graphics: Factor out FSP graphics initMatt DeVillier2023-10-244-10/+34
| | | | | | | | | | | | | | Factor out the FSP-dependent graphics init call and header into a separate file, so that the common graphics init can be used by non-FSP platforms (eg Stoneyridge) without any preprocessor guards. TEST=build google/skyrim Change-Id: Ib025ad3adec0945b4454892d78c30b4cc79e57a0 Signed-off-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78599 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* ec/starlabs/merlin/ite: Adjust the mirror flag handlingSean Rhodes2023-10-242-36/+7
| | | | | | | | | | | | | | | | | | | | | In EC versions older than 1.18, if the mirror flag was enabled, the EC would mirror once the system reached S5. When a mirror is successful, the system will automatically power on, as it acts like it's been in G3. This led to machines turning on when the intention was them to be off. In 1.18 and later, they're installed when turning on. The result was slower boot times when mirroring, but no unwanted powering on. Because of this, coreboot no longer needs to power off when setting the mirror flag. Change-Id: I973c1ecd59f32d3353ca392769b44aadf5fcc9c3 Signed-off-by: Sean Rhodes <sean@starlabs.systems> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78200 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
* mb/starlabs/starbook/{adl,rpl}: Disable GpioOverrideSean Rhodes2023-10-244-8/+10
| | | | | | | | | | | | | | | | Disable the GpioOverride UPD in FSP M, and comment out the Clock Request GPIOs to ensure that coreboot doesn't touch them. This solves behaviour that can only be described as weird: * Devices connected to Root Ports don't initialise * Hang seen when entering S5 * Hang when edk2 is reached Change-Id: Idf8d2112a1c44064af73bb54fd3e1a1a429e0649 Signed-off-by: Sean Rhodes <sean@starlabs.systems> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78199 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
* mb/google/hatch: Default native SD card interface to off in baseboardMatt DeVillier2023-10-2412-12/+9
| | | | | | | | | | | | | | Default SD card interface (PCI 14.5) to off in the baseboard, and have all variants which use it enable it in their override tree. This will allow for simplification when moving to using the chipset devicetree references in a later patch. Change-Id: I6e1230045f54e0fee376f5eeeca9da4fb9d5f6c4 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78550 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de> Reviewed-by: Yuchen He <yuchenhe126@gmail.com>
* mb/google/hatch: Default I2C3 (proximity sensor) to off in baseboardMatt DeVillier2023-10-248-15/+1
| | | | | | | | | | | | | | Default I2C3 (proximity sensor) to off in baseboard, since all variants which use one already enable it in their override tree. This allows variants which do not use it (the majority) to drop it from their override trees. Change-Id: If17cb4538a7f64d019e4e28285fb8977de72252f Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78549 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de> Reviewed-by: Yuchen He <yuchenhe126@gmail.com>
* mb/google/hatch: Default I2C2 (digitizer) to off in baseboardMatt DeVillier2023-10-2410-15/+1
| | | | | | | | | | | | | | Default I2C2 (digitizer) to off in the baseboard, since all variants which use one already enable it in their override tree. This allows variants which do not use it (the majority) to drop it from their override trees. Change-Id: Ife42a6b849278362c1951b80b7a95363e68a2541 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78548 Reviewed-by: Yuchen He <yuchenhe126@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
* mb/google/hatch: Default GSPI1 (FPR) to off in baseboardMatt DeVillier2023-10-245-6/+1
| | | | | | | | | | | | | | Default GSPI1 (fingerprint reader) to off in baseboard, since all variants which use one already enable it in their override tree. This allows variants which do not use it to drop it from their override trees. Change-Id: I07979e35b67635ceadd3906e37de177dd081d35a Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78547 Reviewed-by: Yuchen He <yuchenhe126@gmail.com> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* drivers/wwan/fm: Wake up modem on PEWAKE# signal changePaweł Anikiel2023-10-241-0/+54
| | | | | | | | | | | | | | | | | | Create an event handler for the PEWAKE# GPIO and notify the device driver to wake up the device. BUG=b:301150499 TEST=Compiled and tested on google/redrix: 1. Enable runtime suspend for linux mtk_t7xx driver 2. Wait for device to enter suspended state 3. Modem should be able to wake up driver, e.g. on SIM card insert/eject The interrupts should show up under /proc/interrupts as ACPI:Event Signed-off-by: Paweł Anikiel <panikiel@google.com> Change-Id: I32257689da85ea71f9de781093b3ede0cfe70a0e Reviewed-on: https://review.coreboot.org/c/coreboot/+/78297 Reviewed-by: Jakub Czapiga <czapiga@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* mb/google/brya: Set WWAN_PCIE_WAKE_ODL as interrupt on RedrixPaweł Anikiel2023-10-242-2/+2
| | | | | | | | | | | | | | | | This signal gets deasserted by the WWAN modem to reactivate the PCIe link when in low power mode. In order to handle this efficiently, the kernel needs to set up an interrupt. BUG=b:301150499 TEST=Compiled and tested on google/redrix Signed-off-by: Paweł Anikiel <panikiel@google.com> Change-Id: I37f6836aefe4a374eaff3e4bc11358be274cf563 Reviewed-on: https://review.coreboot.org/c/coreboot/+/78416 Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
* soc/intel/cannonlake: Add ACPI devices for FSPI, SRAM, HEC1Matt DeVillier2023-10-232-0/+16
| | | | | | | | | | | | | | Add ACPI devices for these components so that generated LPI constraints for them have valid device references. TEST=tested with rest of patch train Change-Id: I3b85fec3de8f33d338425a417cc8b0f5290a5e4f Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78520 Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com>
* soc/intel/tigerlake: Add ACPI devices for FSPI, SRAM, HEC1Matt DeVillier2023-10-232-0/+16
| | | | | | | | | | | | | | Add ACPI devices for these components so that generated LPI constraints for them have valid device references. TEST=tested with rest of patch train Change-Id: Ib70dc29f54d28ec1fe7b630ab3fab24bcdd08154 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78519 Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de> Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* soc/intel/common/acpi: Don't generate LPI constraints for disabled/hidden ↵Matt DeVillier2023-10-231-0/+4
| | | | | | | | | | | | | | | | | | | | | | | devices When walking the devicetree to generate the list of devices and minimum sleep states, skip any devices which have the disable or hidden flags set. This prevents adding entries for devices which are not present, which are hidden (and likely to not have a min sleep state entry), or generating duplicate entries in the case of PCIe remapping. Any of these conditions are considered invalid by Windows and will result in a BSOD with an INTERNAL_POWER_ERROR. TEST=tested with rest of patch train Change-Id: I06f64a72c82b9e03dc8af18700d24b3d10b7d3a7 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78518 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
* soc/intel/common/pcie: Disable removed RPs when updating devicetreeMatt DeVillier2023-10-231-1/+2
| | | | | | | | | | | | | | | | If a root port is not present but was enabled in the devicetree, mark it disabled so that no ACPI references will be generated by any function which walks the devicetree (eg, LPI constraints). TEST=tested with rest of patch train Change-Id: I52e23fb1c0148a599ed736fc294e593ebbd27860 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78517 Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* util/docker/coreboot-sdk: Add bash-completion to package listFelix Singer2023-10-231-0/+1
| | | | | | | | Change-Id: I97756f603e304c6b50387ba2aaac416ae31db681 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78493 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin L Roth <gaumless@gmail.com>
* mb/system76/rpl: Fix bonw15, oryp11 speaker outputLevi Portenier2023-10-232-2/+2
| | | | | | | | | | | | | | | Users have reported audio cutting in and out when playing through the speakers on bonw15 and oryp11. This issue originally only affected serw13 and was fixed before upstreaming. Apply the updated HDA verb provided by Clevo to fix speaker output on these units as well. Change-Id: I105bf165227456593863faa9bb8c4f152e49796b Signed-off-by: Levi Portenier <levi@system76.com> Signed-off-by: Tim Crawford <tcrawford@system76.com> Tested-by: Daniel Sutton <daniel@system76.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78511 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jeremy Soller <jeremy@system76.com>
* mb/google/brya/variants/anraggar: Generate 13 RAM IDswuweimin2023-10-233-2/+40
| | | | | | | | | | | | | | | | | | | | | | | | | | Vendor DRAM Part Name Type MICRON MT62F512M32D2DR-031 WT:B LPD5 HYNIX H9JCNNNBK3MLYR-N6E LPD5 HYNIX H9JCNNNCP3MLYR-N6E LPD5 MICRON MT62F1G32D4DR-031 WT:B LPD5 HYNIX H9JCNNNFA5MLYR-N6E LPD5 MICRON MT62F2G32D8DR-031 WT:B LPD5 SAMSUNG K3KL6L60GM-MGCT LPD5x MICRON MT62F1G32D2DS-026 WT:B LPD5x SAMSUNG K3KL8L80CM-MGCT LPD5x HYNIX H58G56BK7BX068 LPD5x MICRON MT62F2G32D4DS-026 WT:B LPD5x SAMSUNG K3KL9L90CM-MGCT LPD5x HYNIX H58G66BK7BX067 LPD5x BUG=b:304920262 TEST=Run part_id_gen tool without any errors Change-Id: I2968c2f0b9cdd55235f9833a3d3cdb3c83b8601b Signed-off-by: wuweimin <wuweimin@huaqin.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78389 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <ericllai@google.com>
* mb/google/rex/var/karis: Modify TCC_offset to 10Tyler Wang2023-10-231-0/+2
| | | | | | | | | | | | | | Follow thermal team request, modify tcc_offset from 20 to 10. BUG=b:306548525 TEST=Build and verified by thermal team Change-Id: I7537e103be4cd1196c934ca72dbd61e064aed371 Signed-off-by: Tyler Wang <tyler.wang@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78490 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: David Wu <david_wu@quanta.corp-partner.google.com>
* mb/google/dedede: Add HPD GPIOs on dexi variantKenneth Chan2023-10-231-0/+15
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Some Type-C monitors do not immediately assert HPD. If we enter FSP-S before HDP is asserted, display initialisation may fail. So wait for HPD. This is similar to commit b40c6009141e ("mainboard/hatch: Fix puff DP output on cold boots") on puff, except we don't use google_chromeec_wait_for_displayport() since that EC command was removed for TCPMv2 (https://crrev.com/c/4221975). Instead we use the HPD signals only. By waiting for any HPD signal (Type-C or HDMI), we skip waiting if HDMI is connected, which is the same behaviour as puff and fizz. BUG=b:303533815 BRANCH=dedede TEST=On dexi, connect a display via a Type-C to HDMI dongle and check the dev and recovery screens are now displayed correctly. Also check the logs in the following cases: Cold reboot in dev mode, Type-C to HDMI dongle: HPD ready after 800 ms Warm reboot in dev mode, Type-C to HDMI dongle: HPD ready after 0 ms Cold/warm reboot in dev mode, direct Type-C: HPD ready after 0 ms Cold/warm reboot in dev mode, direct HDMI: HPD ready after 0 ms Cold/warm reboot in dev mode, no display: HPD not ready after 3000 ms. Abort. Change-Id: Ib4fc071cac98a542072ffbeb6943bff4c988554c Signed-off-by: Kenneth Chan <kenneth.chan@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78450 Reviewed-by: Sheng-Liang Pan <sheng-liang.pan@quanta.corp-partner.google.com> Reviewed-by: Ren Kuo <ren.kuo@quanta.corp-partner.google.com> Reviewed-by: Eric Lai <ericllai@google.com> Reviewed-by: David Wu <david_wu@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* mb/google/brya/var/dochi: Update overridetree for FingerPrintMorris Hsu2023-10-233-12/+11
| | | | | | | | | | | | | | Update overridetree to correct FP_MCU fw_config settings. BUG=b:299284564, b:298328847, b:299570339 TEST=emerge-brya coreboot Change-Id: If76dd8fa3567ed01b11a6d2ba796e8c39807816c Signed-off-by: Morris Hsu <morris-hsu@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78454 Reviewed-by: Eric Lai <ericllai@google.com> Reviewed-by: Bob Moragues <moragues@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* mb/google/brya/var/dochi: Update overridetree for TouchPadMorris Hsu2023-10-231-0/+20
| | | | | | | | | | | | | | Update overridetree for TouchPad. BUG=b:299284564, b:298328847, b:299570339 TEST=emerge-brya coreboot Change-Id: I4f88fa8a34b65aaeb64746e7f02e82d9913ce21b Signed-off-by: Morris Hsu <morris-hsu@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78455 Reviewed-by: Eric Lai <ericllai@google.com> Reviewed-by: Bob Moragues <moragues@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* mb/google/nissa/var/gothrax: Supplement register settings for SX9324 P-sensorYunlong Jia2023-10-231-0/+15
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | Set the following register value to make SX9324 work normally "ph0_pin" = "{1, 3, 3}" "ph1_pin" = "{3, 2, 1}" "ph2_pin" = "{3, 3, 1}" "ph3_pin" = "{1, 3, 3}" "ph01_resolution" = "512" "ph23_resolution" = "1024" "startup_sensor" = "1" "ph01_proxraw_strength" = "2" "ph23_proxraw_strength" = "2" "avg_pos_strength" = "256" "cs_idle_sleep" = ""gnd"" "int_comp_resistor" = ""lowest"" "input_precharge_resistor_ohms" = "4000" "input_analog_gain" = "3" BUG=b:295109511 BRANCH=None TEST=emerge-nissa coreboot chromeos-bootimage & Check sar sensor data Signed-off-by: Yunlong Jia <yunlong.jia@ecs.corp-partner.google.com> Change-Id: Ib15f12d754fec8b379afd702b27d0701fac78072 Reviewed-on: https://review.coreboot.org/c/coreboot/+/78463 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <ericllai@google.com> Reviewed-by: Derek Huang <derekhuang@google.com>
* drivers/pc80/rtc/option.c: Stop resetting CMOS during s3 resumeBill XIE2023-10-231-1/+3
| | | | | | | | | | | | | | | | | | | | | | | | | After commit e12b313844da ("drivers/pc80/rtc/option.c: Allow CMOS defaults to extend to bank 1"), Thinkpad X200 with CONFIG(STATIC_OPTION_TABLE) can no longer resume from s3 (detected via bisect). Further inspection shows that DRAM training result of GM45 is stored in CMOS above 128 bytes in raminit_read_write_training.c, for s3 resume to restore, but it will be erased by sanitize_cmos(), which now clears both bank 0 and bank 1, leaving only "untrained" result restored, so s3 resume will fail. However, resetting CMOS seems unnecessary during s3 resume. Now, cmos_need_reset will be negated when acpi_is_wakeup_s3() returns true. Tested: Thinkpad X200 with CONFIG(STATIC_OPTION_TABLE) can resume from s3 again with these changes. Change-Id: I533e83f3b95f327b0e24f4d750f8812325b7770b Signed-off-by: Bill XIE <persmule@hardenedlinux.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78288 Reviewed-by: Jonathon Hall <jonathon.hall@puri.sm> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* mb/google/rex: Use upstream driver properties for SX9324Ivy Jian2023-10-232-96/+47
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Use human readable properties as upstream driver support. BUG=b:297977526 TEST=Able to get sensor values changed w/wo a hand covering the device. before this CL , SSD.dsl of STH9324 Package (0x02) { "semtech,ph0-pin", Package (0x03) { Zero, Zero, Zero }, ... Package (0x02) { "semtech,ph23-resolution", Zero }, Package (0x02) { "semtech,startup-sensor", Zero }, .... after this CL , SSD.dsl of STH9324 Package (0x02) { "semtech,ph0-pin", Package (0x03) { One, 0x02, 0x02 }, ... Package (0x02) { " semtech,ph23-resolution", 0x0400 }, Package (0x02) { "semtech,startup-sensor", One }, Change-Id: Ie0d929228f4510f33b07d9c4cfdfcd2a9a437c27 Signed-off-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78174 Reviewed-by: Eric Lai <ericllai@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Gwendal Grignou <gwendal@chromium.org>
* mb/system76: Enable BayHub driver for all TGL+Tim Crawford2023-10-232-1/+2
| | | | | | | | | | | | | | | | | Clevo had apparently swapped the Realtek card reader for the O2 Micro card reader for newer batches of all TGL models. Enable the BayHub driver on everything (except bonw15, which doesn't have a card reader) to fix LTR programming, as was done for other in commit 3d7a5bdf58e0 ("mb/system76: Enable DRIVERS_GENERIC_BAYHUB_LV2 to fix LTR issue"). Tested on system76/galp5: CPU reaches C-states deeper than C2 when idle. Change-Id: I3667e08acd23c12638159a2f7d2592737a34e63d Signed-off-by: Tim Crawford <tcrawford@system76.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78298 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jeremy Soller <jeremy@system76.com> Reviewed-by: Eric Lai <ericllai@google.com>
* mb/google/dedede/var/cret: Modify Goodix touchpad HIDDtrain Hsu2023-10-231-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Update Goodix touchpad HID to GDIX0000 for GXTP7288 and GXTP7863. BUG=b:305118852 BRANCH=firmware-dedede-13606.B TEST=Build and touchpads are workable # evtest for GXTP7863 No device specified, trying to scan all of /dev/input/event* Available devices: /dev/input/event0: Lid Switch /dev/input/event1: Power Button /dev/input/event2: AT Translated Set 2 keyboard /dev/input/event3: cros_ec_buttons /dev/input/event4: Elan Touchscreen /dev/input/event5: GDIX0000:00 27C6:0D51 Mouse /dev/input/event6: GDIX0000:00 27C6:0D51 Touchpad # evtest for GXTP7288 No device specified, trying to scan all of /dev/input/event* Available devices: /dev/input/event0: Lid Switch /dev/input/event1: Power Button /dev/input/event10: GDIX0000:00 27C6:01F5 Touchpad /dev/input/event11: sof-da7219max98360a Headset Jack /dev/input/event12: sof-da7219max98360a HDMI/DP,pcm=2 /dev/input/event13: sof-da7219max98360a HDMI/DP,pcm=3 /dev/input/event14: sof-da7219max98360a HDMI/DP,pcm=4 /dev/input/event2: AT Translated Set 2 keyboard /dev/input/event3: cros_ec_buttons /dev/input/event4: ELAN900C:00 04F3:2E5D /dev/input/event5: ELAN900C:00 04F3:2E5D UNKNOWN /dev/input/event6: ELAN900C:00 04F3:2E5D UNKNOWN /dev/input/event7: ELAN900C:00 04F3:2E5D Stylus /dev/input/event8: ELAN900C:00 04F3:2E5D Stylus /dev/input/event9: GDIX0000:00 27C6:01F5 Mouse Change-Id: Id2a6223bdbb2f0693149136baa853ca2efb57815 Signed-off-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78503 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <ericllai@google.com>
* soc/amd/*: Set AMD_FW_AB_POSITION to either 64 or 128 bytesKarthikeyan Ramasubramanian2023-10-203-6/+21
| | | | | | | | | | | | | | | | | When CBFS verification is enabled, add amdfw_a/b.rom at offset 128 bytes to account for CBFS file header with hash attribute. When CBFS verification is disabled, add amdfw_a/b.rom at offset 64 bytes to account for CBFS file header without hash attribute. BUG=None TEST=Build Skyrim, Myst BIOS images with and without CBFS verification enabled. Change-Id: Ic374ac41df0c8fb8ce59488881ce5846e9058915 Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78425 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
* soc/amd/phoenix/psp_verstage: Fix the hash file namesKarthikeyan Ramasubramanian2023-10-201-3/+3
| | | | | | | | | | | | | | | Fix the hash file names to be used to verify signed PSP binaries when booting with VBOOT FW Slot B. BUG=None TEST=Build and boot to OS in Myst with PSP Verstage enabled using both VBOOT slots A and B. Change-Id: I89f02922bc901d8ac71d48bf5128fe6ecead43a0 Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78236 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
* mb/google/myst: Enable CBFS VerificationKarthikeyan Ramasubramanian2023-10-201-5/+0
| | | | | | | | | | | | | | | Enable RO verification by GSC and RO/RW CBFS verification. BUG=b:277087492 TEST=Build and boot to OS in Myst with CBFS verification enabled using PSP verstage. Change-Id: I2dd3ce59f331f89660185309ccf60c53d50e4fad Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78235 Reviewed-by: Tim Van Patten <timvp@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <ericllai@google.com>
* soc/amd/phoenix: Disable CCP DMA in PSP VerstageKarthikeyan Ramasubramanian2023-10-201-1/+2
| | | | | | | | | | | | | | | | | | | Some stalls are observed while using CCP DMA in PSP verstage - especially with CBFS verification enabled. Also with RW CBFS verification enabled, the entire firmware body is not loaded during verstage for verification. Instead the files are verified as and when they are loaded from CBFS. Hence the impact to boot time is reduced since only few files are loaded during PSP verstage. Hence disable CCP DMA in PSP verstage until the root cause is identified. BUG=None TEST=Build and boot to OS in Myst with CBFS verification enabled. Change-Id: I22ac108b08abcfe432dfd175644393e384888e11 Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78234 Reviewed-by: Martin L Roth <gaumless@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* soc/amd/phoenix: Add build rules to enable CBFS verificationKarthikeyan Ramasubramanian2023-10-201-2/+15
| | | | | | | | | | | | | | | | | | | Add SPI flash RO ranges to be verified by GSC in order to enable CBFS verification. Also with CBFS verification enabled, CBFS metadata is more than 64 bytes. So configure the offset of amdfw_a/b to 128 bytes - next address aligned to 64 bytes. BUG=b:277087492 TEST=Build and boot to OS in Myst with and without CBFS verification enabled. Change-Id: Ibfffd3d6fce8b80ec156a7b13b387e1df8c43347 Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78233 Reviewed-by: Tim Van Patten <timvp@google.com> Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Reviewed-by: Martin L Roth <gaumless@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* soc/intel/meteorlake: Set build time physical address reserved bitsJeremy Compostella2023-10-201-0/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | Meteor Lake TME bits [42-45] are reserved regardless of if the part supports TME or not. On a device with TME fused off, we noticed some reboot hangs which have been narrowed down to internal IP routing issues when the IA accesses the Input Output Manager (IOM) which is mapped at 0x3fff0aa0000 (0x3ff upper 32 bits). It turns out since TME is fused off, coreboot uses the full physical address size reported by CPUID MAXPHYADDR (46 bits). Therefore, it allocates thunderbolt memory range on 46 bits (0x3fff upper 32 bits). Since 4 of these bits are actually reserved, it seems that this address range is "stripped down" to 42 bits (=> 0x3ff upper 32 bits) resulting in potential conflict with other devices such as IOM. BUG=b:288978352 TEST=No reboot issue on rex with TME fused off Change-Id: I96ba23ab304257003c0413243d3ac8129ce31743 Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78452 Reviewed-by: Kapil Porwal <kapilporwal@google.com> Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* cpu/intel/common: Define build time physical address reserved bitsJeremy Compostella2023-10-202-0/+11
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | According the Intel Software Developer Manual, CPUID.80000008H:EAX[15:8] reports the physical-address width supported by the processor. Unfortunately, it does not necessarily reflect the physical-address space the system can actulally use as some of those bits can be reserved for internal hardware use. It is critical for coreboot to know the actual physical address size. Overestimating this size can lead to device resource overlaps due to the hardware ignoring upper reserved bits. On rex for instance, it creates some reboot hangs due to an overlap between thunderbolt and Input Output Manager (IOM) address space. As some SoCs, such as Meteor Lake, have physical address reserved bits which cannot be probed at runtime, this commit introduces `CPU_INTEL_COMMON_RESERVED_PHYS_ADDR_BITS' Kconfig to set the number of physical address reserved bits at compilation time for those SoCs. A runtime detection by hardware probing will be attempted if the value is 0 (default). BUG=b:288978352 Change-Id: I8748fa3e5bdfd339e973d562c5a201d5616f813e Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78451 Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kapil Porwal <kapilporwal@google.com>
* Revert "mb/google/rex: Enable sending EOP from payload"Matt DeVillier2023-10-201-1/+1
| | | | | | | | | | | | This reverts commit 55b7dee2784e9fe80870c6c33ba91b98021df8b5. Reason for revert: accidentally submitted out of order / breaks tree Change-Id: Ic15d0e3688cd54f7d678998341263e7bd30e75f2 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78525 Tested-by: Martin L Roth <gaumless@gmail.com> Reviewed-by: Martin L Roth <gaumless@gmail.com>
* Revert "ec/dell/mec5035: Hook up radio enables to option API"Matt DeVillier2023-10-201-5/+0
| | | | | | | | | | | | | This reverts commit bb5fa6419dfd71950e61e75eecd48ef8203bb1b1. Reason for revert: accidentally committed out of order; reverting to unbreak tree Change-Id: I36aa1fd3a0befe49b7e9e34198676f16fb08cf73 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78524 Reviewed-by: Martin L Roth <gaumless@gmail.com> Tested-by: Martin L Roth <gaumless@gmail.com>
* ec/dell/mec5035: Hook up radio enables to option APINicholas Chin2023-10-201-0/+5
| | | | | | | | Change-Id: I52de5ea3d24b400a93adee7a6207a4439eac61db Signed-off-by: Nicholas Chin <nic.c3.14@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77535 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin L Roth <gaumless@gmail.com>
* x86: Add ramstage CBFS cache scratchpad supportJeremy Compostella2023-10-202-0/+25
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Having a CBFS cache scratchpad offers a generic way to decompress CBFS files through the cbfs_map() function without having to reserve a per-file specific memory region. This commit introduces the x86 `RAMSTAGE_CBFS_CACHE_SIZE' Kconfig to set a ramstage CBFS cache size. A cache size of zero disables the CBFS cache feature. The default size is 16 KB which seems a reasonable minimal value large enough to satisfy basic needs such as the decompression of a small configuration file. This setting can be adjusted depending on the platform needs and capabilities. To support S3 suspend/resume use-case, the CBFS cache memory cannot be released to the operating system. There are two options to meet this requirement: 1. Define a static CBFS cache buffer (located in the .bss section) 2. Create a new CBMEM entry Option #2 seems more powerful but considering that: 1. The CBFS cache is actually not a cache but just a scratch pad designed to be isolated between stages 2. postcar is a very short stage not really needing CBFS cache 3. The static initialization of the `cbfs_cache' global variable (cf. src/lib/cbfs.c) offers a simple and robust design => It is simpler to use a static buffer and limit the support to ramstage. Since some AMD SoCs (cf. `SOC_AMD_COMMON_BLOCK_NONCAR' Kconfig) define a `_cbfs_cache' region, an extra `POSTRAM_CBFS_CACHE_IN_BSS' Kconfig must be set to enable the use of a static buffer as the CBFS cache scratchpad. TEST=Decompression of vbt.bin in ramstage on rex using cbfs_map() Change-Id: I7fbb1b51cda9f84842992e365b16c5ced1010b89 Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77885 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* x86: Add pre-memory stages CBFS cache scratchpad supportJeremy Compostella2023-10-2013-0/+43
| | | | | | | | | | | | | | | | | | | | | | | | Having a CBFS cache scratchpad offers a generic way to decompress CBFS files through the cbfs_map() function without having to reserve a per-file specific memory region. This commit introduces the x86 `PRERAM_CBFS_CACHE_SIZE' Kconfig to set the pre-memory stages CBFS cache size. A cache size of zero disables the CBFS cache feature. The default value is 16 KB which seems a reasonable minimal value enough to satisfy basic needs such as the decompression of a small configuration file. This setting can be adjusted depending on the platform needs and capabilities. We have set this size to zero for all the platforms without enough space in Cache-As-RAM to accommodate the default size. TEST=Decompression of vbt.bin in romstage on rex using cbfs_map() Change-Id: Iee493f9947fddcc57576f04c3d6a2d58c7368e09 Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77290 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
* cbfstool: Skip relocation entries pointing to undefined symbolJeremy Compostella2023-10-201-0/+16
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The linker can make relocation entries of a symbol which has a value of zero point to the undefined symbol entry. It is permitted since when the symbol value is zero as the documentation of the relocation entry `r_info' field states: "If the index is STN_UNDEF, the undefined symbol index, the relocation uses 0 as the symbol value." The ELF binary does not really have any missing symbols. It is an optimization as the symbol points to the undefined symbol because its value is zero. A typical way to hit this cbfstool limitation is to define an empty region using the REGION macro in the linker script. Here is an example if we assume `CONFIG_MY_REGION' is set to 0: .car.data { [...] REGION(my_region, CONFIG_MY_REGION_SIZE) [...] } A region is defined as follow: #define REGION_SIZE(name) ((size_t)_##name##_size) #define DECLARE_REGION(name) \ extern u8 _##name[]; \ extern u8 _e##name[]; \ extern u8 _##name##_size[]; So the size of the region is actually the address of the `_##name##_size' symbol. Therefore, the `_my_region_size' symbol address is zero and the linker can make the relocation entry of this symbol point to the undefined symbol index. In such a situation, cbfstool hits a segmentation fault when it attempts to relocate the symbol in `parse_elf_to_xip_stage()' function. We resolves this issue by making cbfstool skips relocation entries pointing to the undefined symbol similarly to the way it skips relocation relative to absolute symbols. A symbol which value is zero can be considered an absolute symbol and therefore should not be relocated. Of course, we could argue that we could just prevent the declaration of an empty region as illustrated in the following example: .car.data { [...] #if CONFIG_MY_REGION_SIZE > 0 REGION(my_region, CONFIG_MY_REGION_SIZE) #endif [...] } However, this is not a satisfying solution because: 1. It requires to add unnecessary code in the linker script as an empty region is a valid declaration. Such a workaround requires the code using it to mark the region symbols as weak symbols to handle the situation where the region is not defined. 2. There could be other situations which have yet to be uncovered which would lead the same cbfstool crash. 3. A binary with an empty region is a valid ELF file and cbfstool should not crash when it is asked to create an eXecute-In-Place stage out of it. Change-Id: I2803fd3e96e7ff7a0b22d72d50bfbce7acaeb941 Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77699 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
* soc/cavium/cn81xx/bootblock_custom.S: Specify archArthur Heymans2023-10-201-0/+4
| | | | | | | | | | | | This fixes assembling with clang which complains about fpu instructions. TEST: BUILD_TIMELESS=1 remains the same. Change-Id: I175b8e749fafde5fb7ffb8101fc0dc892d9b4e0d Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74539 Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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