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* nb/i945: Fix gate graphics hardware for frequency changeElyes HAOUAS2019-07-171-1/+0
| | | | | | | | | | | | | The GCFC (Graphics Clock Frequency Control) read is not used at the line below. As the default value is zero, let's remove unused read. Found-by: scan-build 7.0.1-8 Change-Id: I82c567e3a5b0c0c4a8596ea0cb7693667c71b720 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34329 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
* amd/stoneyridge/Kconfig: Enable stage cache based on HAVE_ACPI_RESUMESubrata Banik2019-07-171-1/+1
| | | | | | | | | | | | | This patch fixes inconsistent issue with stage cache enabling with HAVE_ACPI_RESUME config enable. Only enable stage cache if CONFIG_HAVE_ACPI_RESUME=y Change-Id: I7c3b3ec4642a615e17fb3dbdedca6af8ca95ea2b Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34368 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
* sb/amd/sr5650: Add fine-grained bounds checkingJacob Garber2019-07-171-10/+22
| | | | | | | | | | | | | | | | The code currently checks that 4 <= dev_index <= 10, which after subtraction by 4 can index into an array of length at most 7. This is fine for the largest cpl array (which does have length 7), but is too large for some of the others, which are smaller. This adds bounds checks for each array access to ensure they are all within bounds. Change-Id: I1610d35ca6cbb6cfb42c251e75b0e8b22b64252b Signed-off-by: Jacob Garber <jgarber1@ualberta.ca> Found-by: Coverity CID 1229676 Reviewed-on: https://review.coreboot.org/c/coreboot/+/33458 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
* device: Move pci_irqs outside DEVTREE_EARLYKyösti Mälkki2019-07-172-13/+12
| | | | | | | | | | | Only needed in ramstage, and only for MP tables. Change-Id: Ia7c1e153b948aeefa4c3bea4920b02a91a417096 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33922 Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* site-local: Allow to read Makefile.inc w/o .configBalaji Manigandan B2019-07-171-1/+2
| | | | | | | | | | | | | Makefile.inc allows extending site-specific configurations. This change is to allow make utility to list supported options, irrespective of a .config file availability. Change-Id: I7c968c773c368ea74689b9741c4c978c35110187 Signed-off-by: Balaji Manigandan B <balaji.manigandan@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34024 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
* nb/intel/x4x: Die on invalid memory speedsJacob Garber2019-07-171-2/+2
| | | | | | | | | | | | | | | | | | The speed argument should be one of the six values from the mem_clock enum, so something is very wrong if this is not the case. Better to die now than return 0, which will cause a division-by-zero error later on where this function is called. The first two speeds are also unsupported and have the same problem with returning 0, so die on those as well. Change-Id: Ib628c0eed3d6571bdde1df27ae213ca0691ec256 Signed-off-by: Jacob Garber <jgarber1@ualberta.ca> Found-by: Coverity CID 1391088 Reviewed-on: https://review.coreboot.org/c/coreboot/+/33409 Reviewed-by: David Hendricks <david.hendricks@gmail.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* nb/intel/nehalem: Prevent out of bounds readJacob Garber2019-07-171-0/+2
| | | | | | | | | | | | | | | If the decoded SPD DRAM frequency is slower than the controller minimum, then there will be an unsigned integer underflow in the following loop, which will lead to a very large out of bounds array access. Ensure this does not happen. Change-Id: Ic8ed1293adfe0866781bd638323977abd110777e Signed-off-by: Jacob Garber <jgarber1@ualberta.ca> Found-by: Coverity CID 1229675 Reviewed-on: https://review.coreboot.org/c/coreboot/+/33383 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
* soc/rockchip/rk3288: Add fall through commentJacob Garber2019-07-171-0/+1
| | | | | | | | | | | | | | Judging from the state machine on page 281 of the Rockchip RK3288 Technical Reference Manual (Rev 1.0 - Jun 2015), the fall through from the INIT_MEM -> CONF states is intentional, since that is the only way to get to the ACCESS state. Add a comment to explain this. Change-Id: I1d0cfea07211c54d6a906f5a7481c2c760f8ef0d Signed-off-by: Jacob Garber <jgarber1@ualberta.ca> Found-by: Coverity CID 1291959 Reviewed-on: https://review.coreboot.org/c/coreboot/+/34296 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
* soc/amd/stoneyridge: Add Merlin Falcon configurationRichard Spiegel2019-07-172-6/+44
| | | | | | | | | | | | | | Add config parameter for Merlin Falcon (SOC_AMD_MERLINFALCON) and modify the Makefile.inc based on this config parameter. BUG=none. TEST=Tested later with padmelon board. Change-Id: Id9f960b8f012c5a1cfd398611d6a51838493da27 Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33621 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
* soc/intel/cannonlake: Add device Ids for new CFL SKUs supportLean Sheng Tan2019-07-178-47/+78
| | | | | | | | | | | | | | | | | | - Add CPU, MCH & IGD IDs for new Coffeelake SKUs - Add PCH, LPC, SPI IDs for CNP-H PCH CM246 & C246 - Make some minor alignments & naming corrections to align with the rest TEST= build, boot to both Linux & windows OS on CFL H & S platforms and verified all the device Id's in serial console logs. Signed-off-by: Lean Sheng Tan <lean.sheng.tan@intel.com> Change-Id: I343b11ea8d9c33eb189d7478511a473b145f4ab4 Reviewed-on: https://review.coreboot.org/c/coreboot/+/34157 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Boon Tiong Teo <boon.tiong.teo@intel.com> Reviewed-by: Nico Huber <nico.h@gmx.de>
* soc/intel: Fix regression with hidden PCI devicesKyösti Mälkki2019-07-178-15/+29
| | | | | | | | | | | | | | | | | | | | | Fix regression with commit 903b40a soc/intel: Replace uses of dev_find_slot() Platforms where FSP hides PCI devices before enumeration may halt with error message 'PCI: dev is NULL!'. The workaround here is to print an error message revealing the faulty source code function and revert to old behaviour of dev_find_slot(). Change-Id: I5eab3e7f1993b686103eaa257aacda379dc259fa Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34285 Reviewed-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-by: Maxim Polyakov <max.senia.poliak@gmail.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Christian Walter <christian.walter@9elements.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* mainboard/portwell/m107: Do initial mainboard commitFrans Hendriks2019-07-1728-0/+1816
| | | | | | | | | | | | | | Initial support for Portwell PQ7-M107 (Q7) module. Code based on Intel Strago mainboard. BUG=N/A TEST=booting SeaBIOS and Linux 4.20 kernel on PQ7-M107 Change-Id: I7d3173fdcf881f894a75cd9798ba173b425d4e62 Signed-off-by: Frans Hendriks <fhendriks@eltan.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/29470 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
* intel/i82801ix: Refactor lock_smm()Kyösti Mälkki2019-07-171-7/+8
| | | | | | | | | | | | | Move the SMM lock outside the function as it is renamed. Replace conditional !PARALLEL_MP with SMM_ASEG to better reflect the use. Change-Id: I93bf0d2f711f94a5bb741bdcd92c1e0fec228684 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34302 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
* intel/i82801gx,i82801jx: Rename lock_smm()Kyösti Mälkki2019-07-172-12/+6
| | | | | | | | | | | With PARALLEL_MP the lock has been moved elsewhere. Change-Id: I2db78fe99aa1d46c5e7bcef99a37619301c98914 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34256 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
* intel/fsp_baytrail: Avoid preprocessor with HAVE_SMI_HANDLERKyösti Mälkki2019-07-171-2/+4
| | | | | | | | | | | The code should probably set SCI routing if built with HAVE_SMI_HANDLER=n. Change-Id: I0ada4b2a16490a15d8036a9425c4f768f7b8f218 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34255 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
* mb/google/hatch: Disable Bluetooth in bootblock and enable in ramstageShelley Chen2019-07-161-0/+2
| | | | | | | | | | | | | | | | | | Currently, bluetooth FW is not loaded after a reboot. In order to do this, we have to disable the bluetooth disable gpio (GPP_C14) in bootblock and re-enable it in ramstage. BUG=b:137307516 BRANCH=None TEST=boot up Hatch device and make sure (in dmesg) that proper bluetooth FW in loaded Change-Id: Ic5e447d9de57790f7a100e9e03f36b047c19d8f9 Signed-off-by: Shelley Chen <shchen@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34354 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* mb/google/octopus/variants/garg: support LTE power sequenceMarco Chen2019-07-163-0/+103
| | | | | | | | | | | | | | | | | | | | | | GPIOs related to power sequnce are GPIO_67 - EN_PP3300 GPIO_117 - FULL_CARD_POWER_ON_OFF GPIO_161 - PLT_RST_LTE_L 1. Power on: GPIO_67 -> 0ms -> GPIO_117 -> 30ms -> GPIO_161 2. Power off: GPIO_161 -> 30ms -> GPIO_117 -> 100ms -> GPIO_67 3. Power reset: - keep GPIO_67 and GPIO_117 high and - pull down GPIO_161 for 30ms then release it. BUG=b:137033609 BRANCH=octopus TEST=build image and verify on the DUT with LTE DB. Change-Id: I7bf6fee087c885c22363b44aa98aa61f91be90b4 Signed-off-by: Marco Chen <marcochen@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34188 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
* mb/google/octopus: add variant_smi_sleepMarco Chen2019-07-162-0/+10
| | | | | | | | | | | | | | | Allow variants to customize their own smi sleep flow. BUG=b:137033609 BRANCH=octopus TEST=built Change-Id: I75db544d333a640848da9072878687c802c1c1a4 Signed-off-by: Marco Chen <marcochen@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34340 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* mb/google/octopus: add variant_early_override_gpio_tableMarco Chen2019-07-163-3/+12
| | | | | | | | | | | | | | | | Allow variants to override GPIO configurations of baseboard in the bootblock stage. BUG=b:137033609 BRANCH=octopus TEST=built Change-Id: I18d380cdf58f0f24e1bb1bff394ed8a91188a22c Signed-off-by: Marco Chen <marcochen@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34339 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
* mediatek/mt8183: add a new configuration for KodamaPeichao Wang2019-07-162-0/+6
| | | | | | | | | | | | | | These configuration files can be used to build Kodama firmware. BUG=b:135490566 TEST=check variant: kodama via make menuconfig; make -j Change-Id: I72e80e800ba041df1dda2b0f84470d1ef58bc946 Signed-off-by: Peichao Wang <peichao.wang@bitland.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33616 Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Hung-Te Lin <hungte@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* sb/amd/{cimx,}/sb{700,800,900}: Prevent uninitialized readsJacob Garber2019-07-164-12/+12
| | | | | | | | | | | | | | | | | | | There are two hard things in computer science: cache invalidation, naming things, and off-by-one errors. -- Anonymous var_num records the number of initialized entries in the reg_var array. However, this means the index of the last initialized element is one less than the value of var_num, so we need to take that into account when indexing into the array. This has already been fixed in several other places (eg. sb/amd/pi/hudson/lpc.c), so let's also do so here. Change-Id: Ibefabaca42866a3f2b22eff979c73badf86ac317 Signed-off-by: Jacob Garber <jgarber1@ualberta.ca> Found-by: scan-build 8.0.0 Reviewed-on: https://review.coreboot.org/c/coreboot/+/33790 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: David Hendricks <david.hendricks@gmail.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
* util/inteltool: Shrink buffer sizeJacob Garber2019-07-161-1/+1
| | | | | | | | | | | | | | | | 512 bytes is much too big for this buffer, which only needs to hold a path that will have a length of at most 20. The large buffer size also triggers a -Wformat-truncation warning with GCC since it is later printed into the smaller temp_string array, so shrink it down to something reasonable. Change-Id: I6a136d1a739c782b368d5035db9bc25cf5b9599b Signed-off-by: Jacob Garber <jgarber1@ualberta.ca> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33944 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Reviewed-by: David Hendricks <david.hendricks@gmail.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
* soc/intel/{cnl,icl}: Always use CAR NEM enhanced by defaultAngel Pons2019-07-162-4/+2
| | | | | | | | | | | | | | | The FSP_CAR option has additional configuration options whose default values result in boot failures. Since default values should always boot, default to the open-source CAR NEM Enhanced implementation instead. This also allows us to get rid of an unnecessary vendor-specific special case. Change-Id: I30b1808f91701c07dce6f1de08c213150e8a675a Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34287 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Subrata Banik <subrata.banik@intel.com> Reviewed-by: Lean Sheng Tan <lean.sheng.tan@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* Doc/lessons/lesson1: Fix title consistencyAngel Pons2019-07-161-2/+2
| | | | | | | | | | | | Make the title for lesson 1 match the format used for lesson 2 and the lessons index, for consistency purposes. Change-Id: I133d758ddf4974096cbf9f10ae96c148fc859efc Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34350 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Jacob Garber <jgarber1@ualberta.ca>
* soc/intel/common/block/i2c: Set controller state to active in i2c initAamir Bohra2019-07-161-0/+6
| | | | | | | | | | | | | | | | Set the controller state to D0 during the i2c init sequence, this ensures the controller is up and active. BUG=b:135941367 TEST=Verify no timeouts seen during I2C controller enumeration sequence Change-Id: I247ede44b8d1d6871e3e813b63f99a7f6398dd72 Signed-off-by: Aamir Bohra <aamir.bohra@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34273 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Subrata Banik <subrata.banik@intel.com> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* soc/intel/common/block/lpss: Add provision to set controller power stateAamir Bohra2019-07-162-0/+28
| | | | | | | | | | | | | | | | Add function to set the power state of a LPSS controller. The API implemented can be used to enforce controllers in active state(D0) during initialization. BUG=b:135941367 Change-Id: I7540924885350de64caff91d920d6cc234154616 Signed-off-by: Aamir Bohra <aamir.bohra@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34272 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Subrata Banik <subrata.banik@intel.com> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* mb/google/sarien/variants/arcada: Set data hold time for touchpadCasper Chang2019-07-151-0/+1
| | | | | | | | | | | | | | | | | Elan's touchpad requires min 0.3us data hold time. To fine tune the data hold time of i2c1 to meet specification of Elan's touchpad. BUG=None BRANCH=None TEST=Verified data hold time of i2c1 is around 320ns Signed-off-by: Casper Chang <casper_chang@wistron.corp-partner.google.com> Change-Id: I0fa9db3b50e74f193261be96bd9e305bb19841e3 Reviewed-on: https://review.coreboot.org/c/coreboot/+/34288 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nick Crews <ncrews@google.com> Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
* util/amdfwtool: Add option to build verstage binary into the PSPMartin Roth2019-07-151-2/+10
| | | | | | | | | | | | | | | | | | For AMD's Family17h processors, verstage needs to be run in the PSP, before memory is initialized. This adds that binary into the PSP directory. See the Family17h documentation in the coreboot documentation directory for more information. BUG=b:137338769 TEST=Build, add test binary to mandolin board, boot Signed-off-by: Martin Roth <martin@coreboot.org> Change-Id: I29002a1af51c59a2e6c715e15f3dc63e59cd5729 Reviewed-on: https://review.coreboot.org/c/coreboot/+/34324 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
* util/amdfwtool: Do misc cleanupMartin Roth2019-07-151-3/+5
| | | | | | | | | | | | | | | - Correct command line argument for microcode patches from -u to -O - Add #if PSP_COMBO around new_combo_dir() as it's only called when that's enabled. - Remove unused variable in integrate_bios_firmwares() - Correct enum type from amd_fw_type to amd_bios_type in register_fw_addr() Signed-off-by: Martin Roth <martin@coreboot.org> Change-Id: I51c6dbe700505bc2e32443000ae55cb644051e42 Reviewed-on: https://review.coreboot.org/c/coreboot/+/34303 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
* device: Remove device->ops from early stagesKyösti Mälkki2019-07-153-12/+4
| | | | | | | | Change-Id: I7a361187570716df94a3fd441ae78c0f805b1dda Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33921 Reviewed-by: Patrick Rudolph <siro@das-labor.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* Documentation: Add FSP bugsPatrick Rudolph2019-07-151-0/+43
| | | | | | | | | | | | | As Intel doesn't even document known bugs add a list of FSP bugs here. Change-Id: I07819b83fb0c9437fc237472dfe943f78738347a Signed-off-by: Patrick Rudolph <siro@das-labor.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34239 Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Martin Roth <martinroth@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* intel/cannonlake: Fix indentationKyösti Mälkki2019-07-151-2/+2
| | | | | | | | Change-Id: Ia3ec5fbdbbf2712fe314909e05aab1b135534630 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34301 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
* cpu/x86: Fix DEBUG_SMM_RELOCATION dependencyKyösti Mälkki2019-07-151-1/+1
| | | | | | | | | Change-Id: I8a5bf39203a5de38d03d1b54453b056ea846ca38 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34259 Reviewed-by: Patrick Rudolph <siro@das-labor.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* configs/lenovo: Drop DEBUG_SMM_RELOCATIONKyösti Mälkki2019-07-153-3/+0
| | | | | | | | | | | Not implemented for TSEG. Change-Id: I279c546a921c0504cafaddcda855bd6ea3de7f8a Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34325 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
* lib/bootmode: Include 'vboot/misc.h'Elyes HAOUAS2019-07-151-1/+1
| | | | | | | | | | | | Don't include unneeded 'vendorcode/google/chromeos/chromeos.h', when only 'vboot/misc.h' is used. Change-Id: I99484c29e5a3e13f1fea277f13c2f08a8a46bd88 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34295 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Joel Kitching <kitching@google.com>
* src: Use '#include <timestamp.h>' when neededElyes HAOUAS2019-07-158-6/+2
| | | | | | | | Change-Id: Ic0483982e8115ae99367d08d8ed77b8a316f5405 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34231 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
* soc/intel/icelake: Update FSP UPDs if IGD is disable in devicetreeSubrata Banik2019-07-142-6/+28
| | | | | | | | | | | | | This patch sets required FSP UPDs to skip IGD initialziation if devicetree has disable IGD. Change-Id: I34a02bff112f922cabd48c23bc76370892ec62d9 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33739 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Aamir Bohra <aamir.bohra@intel.com> Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* soc/intel/icelake: Make use of PCH_DEVFN_HDA macroSubrata Banik2019-07-141-1/+1
| | | | | | | | Change-Id: I3be530072a6981760e9fe31e43741b4b480d045e Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34286 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
* mb/up/squared: Enable VtdFelix Singer2019-07-131-0/+2
| | | | | | | | Change-Id: Ie935f98f84772a53de92f0dd2d13a381f5dbaf89 Signed-off-by: Felix Singer <felix.singer@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34271 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
* soc/nvidia/tegra124: Prevent implicit fallthroughJacob Garber2019-07-131-0/+1
| | | | | | | | | | | | SOR_LINK_SPEED_G5_4 is unsupported, but it is not invalid, so it suffices to return here instead of printing the next warning message. Change-Id: Ifca3c52635e9a39af42e6616821d1099c43c237c Signed-off-by: Jacob Garber <jgarber1@ualberta.ca> Found-by: Coverity CID 1293137 Reviewed-on: https://review.coreboot.org/c/coreboot/+/34293 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
* device/hypertransport.c: Remove dead assignmentJacob Garber2019-07-131-1/+0
| | | | | | | | | | | | | last_unitid is immediately overwritten in the do loop, so this assignment is not needed. This a relic from old code that commit 13f1c2af8b made obsolete, but was never removed. Change-Id: I2eecddd025f7a64b0a70fc07a61ebb43aba757d6 Signed-off-by: Jacob Garber <jgarber1@ualberta.ca> Found-by: scan-build 8.0.0 Reviewed-on: https://review.coreboot.org/c/coreboot/+/34292 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
* util/testing: Ensure coreboot-gerrit fails if libpayload build failsKeith Short2019-07-132-1/+3
| | | | | | | | | | | | | | | | | | | | The JUnit output from the libpayload builds was getting deleted by the coreinfo build. Move the libpayload to later in the coreboot-gerrit job. Also add messages to stdout indicating the various libpayload configs that are built and a message indicating when all libpayload builds are complete. BUG=b:137380189 TEST=Upload test commit that includes a libpayload compile error and verify buildbot fails. Change-Id: I43b55f402216582dcf81be34171437be345572ab Signed-off-by: Keith Short <keithshort@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34183 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* device/device_util: Fix encoding the USB device pathKarthikeyan Ramasubramanian2019-07-131-1/+1
| | | | | | | | | | | | | | | | USB device id does not get included because of the logical OR operation. Fix encoding the USB device path. BUG=None BRANCH=None TEST=Boot to ChromeOS. Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Change-Id: I79317da6d9c7cd177bd7bbbba1f1ccebe076930a Reviewed-on: https://review.coreboot.org/c/coreboot/+/34245 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* drivers/intel/wifi: Make Intel wifi driver arch agnosticKarthikeyan Ramasubramanian2019-07-131-1/+1
| | | | | | | | | | | | | | | | Mark Intel WiFi driver to depend on PCI and remove the dependency on x86 architecture. BUG=None BRANCH=None TEST=Compile and Boot to ChromeOS. Change-Id: I762007d53b43bbc78924ee8efe236d6a7ff4dc57 Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33959 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* drivers/wifi: Add generic WiFi driverKarthikeyan Ramasubramanian2019-07-137-252/+367
| | | | | | | | | | | | | | | | | Add generic WiFi driver to support common device operations across multiple types of WiFi controller. BUG=None BRANCH=None TEST=Boot to ChromeOS. Ensure that the SSDT table contains SAR tables and wakeup GPE information. Ensure that the SSDT table is same after the change. Change-Id: Ica5edf95a37c8ed60f7e159d94fd58af5d41c0ef Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33155 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
* mb/google/hatch: Fix trackpad configuration in overridetreeFurquan Shaikh2019-07-134-8/+6
| | | | | | | | | | | | | Hatch and variants use GPP_A21 for trackpad IRQ and wake. Fix overridetree.cb to advertise the right IRQ. Change-Id: Ib87c858b89e8726c3bc80f83be0729ef4625268e Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34248 Reviewed-by: Philip Chen <philipchen@google.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* mb/google/octopus: Add custom SAR values for BluebirdSeunghwan Kim2019-07-132-0/+29
| | | | | | | | | | | | | | | | | Bluebird needs to use different SAR values than Casta. Bluebird sku id is 2. CQ-DEPEND=CL:*1435310 BUG=b:129725065 BRANCH=octopus TEST=build Change-Id: I107a8519832fcf906b94f958a3dc508d19bb4727 Signed-off-by: Seunghwan Kim <sh_.kim@samsung.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34080 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* intel/i945: Fix udelay() prototypesKyösti Mälkki2019-07-138-1/+7
| | | | | | | | Change-Id: Ia157c6417bdd9c4ffbdf07683c51d0680e9356c9 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34228 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
* intel/haswell: Replace monotonic timerKyösti Mälkki2019-07-135-68/+1
| | | | | | | | | | | | Remove implementation of 24 MHz clock, available only on Haswell ULT SKUs. Use TSC_MONOTONIC_TIMER instead for all boards. Change-Id: Ic4aeb084d1b0913368f5eaa46e1bd68411435517 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34114 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
* soc/rockchip/rk3288/include/soc: Add missing include <types.h>Elyes HAOUAS2019-07-131-0/+2
| | | | | | | | Change-Id: Ibde48d7cff582c91f55ad5f1328aac64d018b3c5 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34235 Reviewed-by: Julius Werner <jwerner@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
generated by cgit v1.2.3 (git 2.25.1) at 2024-05-19 21:45:02 +0000