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* mb/facebook/watson: select VPD_SMBIOS_VERSIONJonathan Zhang2020-07-071-0/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | Select VPD, GENERATE_SMBIOS_TABLES, VPD_SMBIOS_VERSION so that "firmware_version" key value in RO_VPD is reported in smbios type 0 as BIOS version. TEST=Build coreboot image for WatsonV2, run "vpd -s firmware_version=FB_OSF_1.2 -i RO_VPD -f build/coreboot.rom" command to add firmware_version key value pair in RO_VPD, flash the image to WatsonV2 and reboot it, run dmidecode to verify: [root@localhost ~]# dmidecode -t 0 ... BIOS Information Vendor: coreboot Version: FB_OSF_1.2 ... Signed-off-by: Jonathan Zhang <jonzhang@fb.com> Change-Id: I31fb2cef01161175a0c01094c5445f7fa340f2d0 Reviewed-on: https://review.coreboot.org/c/coreboot/+/42942 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com> Reviewed-by: insomniac <insomniac@slackware.it> Reviewed-by: Christian Walter <christian.walter@9elements.com>
* smbios: Add option VPD_SMBIOS_VERSION that reads BIOS version from a VPD ↵Johnny Lin2020-07-042-20/+71
| | | | | | | | | | | | | | | | | | | | | | | | variable If VPD_SMBIOS_VERSION is selected, it would read VPD_RO variable that can override SMBIOS type 0 version. One special scenario of using this feature is to assign a BIOS version to a coreboot image without the need to rebuild from source. VPD_SMBIOS_VERSION default is n. Tested=On OCP Delta Lake, dmidecode -t 0 can see the version being updated from VPD. Change-Id: Iee62ed900095001ffac225fc629b3f2f52045e30 Signed-off-by: Johnny Lin <johnny_lin@wiwynn.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42029 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: insomniac <insomniac@slackware.it> Reviewed-by: Julius Werner <jwerner@chromium.org> (cherry picked from commit c746a748c4c5ec6421d7f9f5760717348231d091) Reviewed-on: https://review.coreboot.org/c/coreboot/+/42747 Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
* soc/intel/fsp_broadwell_de: Check if memory is 'locked'Andrey Petrov2020-06-243-0/+17
| | | | | | | | | | | | | | | | Under certain conditions TXT can "lock" memory controller for security purpose. This manifests itself in IMC's SMbus controller failing all SPD data read requests. FSP does not detect error condition and fails boot with "No memory found" issue. TEST=tested on OCP monolake in 'locked' state Change-Id: If4637e4293421794a89037ff107e87794c40114a Signed-off-by: Andrey Petrov <anpetrov@fb.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42710 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org> Reviewed-by: Christian Walter <christian.walter@9elements.com>
* mb/fb/watson/watson_v2: configure PCI bifurcationJonathan Zhang2020-05-256-0/+89
| | | | | | | | | | | | | | | | Watson V2 server has different PCIe bifurcation configuration, comparing to Watson server. Add a watson_v2 variant directory. Allow variant to customize UPD parameters. Configure UPD parameters to define PCIe bifurcation configuration for Watson V2 server. Signed-off-by: Jonathan Zhang <jonzhang@fb.com> Change-Id: I3b57c64dea6f3a468336fcdb1e948dfcd897e60c Reviewed-on: https://review.coreboot.org/c/coreboot/+/41433 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
* mb/facebook/watson: add variant watson_v2Jonathan Zhang2020-04-292-10/+67
| | | | | | | | | | | | | | | | | | | | | | | | Watson V2 is the 2nd board variant of Watson. One aspect of the difference between watson V2 and watson (V1) is: * Watson V2 has TPM2 chip instead of TPM1 chip. * Watson V2 needs to have measured boot enabled. TESTED=Made Watson V2 image, checked boot log and verfied that TPM2 is detected by both coreboot and target OS, that coreboot is measured. TPM: Measured FMAP: COREBOOT CBFS: bootblock into PCR 2 TPM: Measured FMAP: COREBOOT CBFS: fallback/romstage into PCR 2 TPM: Measured FMAP: COREBOOT CBFS: fallback/ramstage into PCR 2 TPM: Measured FMAP: COREBOOT CBFS: cpu_microcode_blob.bin into PCR 2 TPM: Measured FMAP: COREBOOT CBFS: fallback/dsdt.aml into PCR 2 TPM: Measured FMAP: COREBOOT CBFS: fallback/payload into PCR 2 Signed-off-by: Jonathan Zhang <jonzhang@fb.com> Change-Id: Iabf4183dfeabb2f9946dbb5c98c60b7c0cdba711 Reviewed-on: https://review.coreboot.org/c/coreboot/+/40575 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: David Hendricks <david.hendricks@gmail.com>
* mb/facebook/watson: Make watson as a variantJonathan Zhang2020-04-292-3/+3
| | | | | | | | | | Facebook Watson (V1) board is the first variant of Watson mainboard. Signed-off-by: Jonathan Zhang <jonzhang@fb.com> Change-Id: I1164ee9f8d07cebf8d505ca1e164823c1cb5625c Reviewed-on: https://review.coreboot.org/c/coreboot/+/40541 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: David Hendricks <david.hendricks@gmail.com>
* Makefile.inc: Ignore _HID & _ADR conflicts in Broadwell & LynxpointMartin Roth2020-03-041-0/+9
| | | | | | | | | | | | | | | | | We haven't been able to update IASL in 8 months because of this conflict. Ignoring it doesn't make things any worse than they are now. Signed-off-by: Martin Roth <martin@coreboot.org> Change-Id: Iced2e55e9f2aa7a262a5c1ffeff32af78acfa35e Reviewed-on: https://review.coreboot.org/c/coreboot/+/38810 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> (cherry picked from commit 12e9c5ee86f9aa87b1e84bfc59e6cdbab5a4b254) Reviewed-on: https://review.coreboot.org/c/coreboot/+/38959 Reviewed-by: Patrick Georgi <pgeorgi@google.com>
* Makefile.inc: Adapt $(spc) definitionNico Huber2020-02-191-1/+1
| | | | | | | | | | | | | | | | | GNU Make 4.3 is more picky about the $(spc) definition. It seems, the variable ends up empty. The old definition worked for nearly 8 years, RIP. Tested with GNU Make 4.2.1 and 4.3. Change-Id: I7981e0066b550251ae4a98d7b50e83049fc5586a Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38790 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> (cherry picked from commit 0f6f70c3942c152c512b1aa51b6f6079a05e003b) Reviewed-on: https://review.coreboot.org/c/coreboot/+/38958
* mb/ocp/monolake: Override SMBIOS data with IPMI read FRU dataJohnny Lin2019-12-122-0/+89
| | | | | | | | | | | | | | SMBIOS type 1 data fields are overwritten by FRU product info area data, SMBIOS type 2 fields are overwritten by FRU board info area data. Tested on OCP Mono Lake. Change-Id: I58cbe95055dea053b115e99f354f40d5902c6a35 Signed-off-by: Johnny Lin <johnny_lin@wiwynn.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37445 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: David Hendricks <david.hendricks@gmail.com>
* drivers/ipmi: Add IPMI Read FRU functionJohnny Lin2019-12-125-0/+494
| | | | | | | | | | | | | | | | Implemented according to IPMI "Platform Management FRU Information Storage Definition" specification v1.0 for reading FRU data Product Info Area and Board Info Area. SMBIOS data can be updated with the FRU data. Tested on OCP Mono Lake. Change-Id: Id6353f5ce3f7ddd3bb161b91364b3cf276d020b8 Signed-off-by: Johnny Lin <johnny_lin@wiwynn.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37444 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: David Hendricks <david.hendricks@gmail.com>
* mainboard/facebook/watson: Reclaim unused flash spaceAndrey Petrov2019-12-051-2/+1
| | | | | | | | | | | | | | Currently FMAP does not allocate all the usable space. This change addresses that by removing unused section and expanding CBFS section. TEST=tested on actual watson HW Change-Id: I5f407c11031822d58f11f1a4684845d57653b190 Signed-off-by: Andrey Petrov <anpetrov@fb.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37474 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
* [BACKPORT] arch/x86: SMBIOS: Improve core count reportingAndrey Petrov2019-12-051-1/+20
| | | | | | | | | | | | | | | | | | | | | | | Current code uses CPUID leaf 0x1, EBX bits 16:23 to determine number for "core count". However, it turns out this number has little to do with real number of cores. According to SDM vol 2A, it stays for "maximum number of addressable IDs for logical processors in this physical package". This does not seem to take into account fusing of giving processor. The new code determines 'core count' by dividing thread-level cpus by reported logical cores. This seems to be the only way to arrive to number of cores as it is reported in official CPU datasheet. TEST=tested on OCP monolake Change-Id: Id4ba9e3079f92ffe38f9104ffcfafe62582dd259 Signed-off-by: Andrey Petrov <anpetrov@fb.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36941 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com> (cherry picked from commit 515ef38db40cc44592770c00be8e4980bbaccc69) Reviewed-on: https://review.coreboot.org/c/coreboot/+/37089
* soc/intel/broadwell_de: Re-read SPD on CRC errorAndrey Petrov2019-12-051-3/+29
| | | | | | | | | | | | | | | I2C bus does not guarantee data integrity. As result, sometimes we end up detecting CRC errors and not adding DIMMs to SMBIOS tables. This change adds re-tries on such errors. TEST=let OCP monolake run without fan and try reading SPD data in tight loop. CRC errors were reported but subsequent retries were error free. Change-Id: I650c8cd80f75b603db332024748a91af6171f096 Signed-off-by: Andrey Petrov <anpetrov@fb.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37303 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
* Revert "console,boot_state: Exclude printk() from reported times"Kyösti Mälkki2019-12-035-67/+0
| | | | | | | | | | | | | | | | | The code in cpu/x86/lapic/apic_timer.c for timer_monotonic_get() is not SMP safe as LAPIC timers do not run as synchronised as TSCs. So the reported times with LAPIC_MONOTONIC_TIMER=y at least were incorrect. Since the approach for this improved times reporting was not completed wrt. the output format either, revert it from 4.11_branch. Change-Id: Ie7edae572cf4fee0b9d2497f7690145c2699a809 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37396 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
* mb/ocp/monolake: Override SMBIOS UUID with the value sent by BMCJohnny Lin2019-11-281-0/+6
| | | | | | | | | | | Tested on OCP Mono Lake with dmidecode -t 1 and the expected UUID is visible. Change-Id: I0aab4df67b7aaba8be6ddbb13984fffb2b14fe6b Signed-off-by: Johnny Lin <johnny_lin@wiwynn.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37086 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: David Hendricks <david.hendricks@gmail.com>
* drivers/ipmi: Add IPMI get system GUID supportJohnny Lin2019-11-282-0/+34
| | | | | | | | | | Tested on OCP Mono Lake. Change-Id: I541a23341ccce3d45239babb3f0a8a8c8542b226 Signed-off-by: Johnny Lin <johnny_lin@wiwynn.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37085 Reviewed-by: David Hendricks <david.hendricks@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* src/drivers/ipmi: Implement BMC Get Self Test Result functionMorgan Jang2019-11-272-0/+72
| | | | | | | | | | | | | | | | | According to IPMI SPEC, it is recommended that BIOS includes provisions for checking and reporting on the basic health of BMC by executing the Get Self Test Results command and checking the result. TEST=Check the result in response data to confirm the BMC status is fine or not. Change-Id: I20349cec2e8e9420d177d725de2a5560d354fe47 Signed-off-by: Morgan Jang <Morgan_Jang@wiwynn.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36638 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: David Hendricks <david.hendricks@gmail.com> (cherry picked from commit 50155024141f48cf3048272073d352906a2be0b6) Reviewed-on: https://review.coreboot.org/c/coreboot/+/37087
* Documentation/releases: Finalize 4.11, start 4.124.11Patrick Georgi2019-11-193-9/+115
| | | | | | | | | | | | | | Fill in some stats using our repo analysis scripts in util/release/, thank the contributors, add some prose about notable achievements since 4.10. Also start a new doc for 4.12. Change-Id: I10a39081762d6e01f4040f717d36662975e4c8e9 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36948 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* Documentation: Remove duplicated entryPatrick Rudolph2019-11-191-4/+0
| | | | | | | | | | The mainboard was accidently added due to bad rebase. Change-Id: Ie7215e551651dbbc8d92316c48e455405923a30b Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36077 Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* util/chromeos: Indent code blocks instead of using ```Paul Menzel2019-11-191-13/+10
| | | | | | | | | | | This uses less lines, is the original Markdown syntax, and for short blocks better readable. Change-Id: Id96ad0f65980dfb943eef3cde5626d56f97622f9 Signed-off-by: Paul Menzel <pmenzel@molgen.mpg.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35729 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* util/docker/Makefile: Add documentation docker image targetsArthur Heymans2019-11-191-0/+23
| | | | | | | | | | | | | | Run - make -C util/docker doc.coreboot.org to build the docker image - make -C util/docker docker-build-docs to build the documentation - make -C docker-livehtml-docs to serve autoupdated documentation over http://0.0.0.0:8000 Change-Id: Ic07f216f8d90d6e212383250b852dc91575304c3 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36104 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* Documentation: Reword Supermicro X10SLM+-F datasheet referencesPaul Menzel2019-11-191-3/+2
| | | | | | | | Change-Id: I24c4254ef65edcddadcf0386e0cbe996a5e99458 Signed-off-by: Paul Menzel <pmenzel@molgen.mpg.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35486 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
* configs: add google/meep cros config as regression testPatrick Georgi2019-11-191-0/+41
| | | | | | | | | | | | | | | | This config is a slightly stripped configuration of the Chromium OS configuration used in production. Apparently the bootblock fills up faster than usual on this device, resulting in address overflows. Add this config here so we'll notice early in the future. Change-Id: I3145bba63d32ddb9d00fd98d3cb774bf9ddd69a6 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36923 Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* mb/google/octopus: Disable fmap cache for meepPatrick Georgi2019-11-191-0/+1
| | | | | | | | | | | | | | By removing this code, we get approximately back to where the board was before the fmap cache feature was added, which is small enough for the Chromium OS default configuration for the board to fit into the 32KB that the bootblock can use on the chipset again. Change-Id: I52c0c30a14929913ded144bf086c12938e9c2699 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36925 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
* docs: intel fsp: add memory retraining bug on SPS systemsMichael Niewöhner2019-11-192-1/+7
| | | | | | | | | | FSP2.0 forces MRC retraining on cold boot on Intel SPS systems. Change-Id: I3ce812309b46bdb580557916a775043fda63667f Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36935 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
* sb/amd/hudson: Fix typo in GEC firmware nameMarshall Dawson2019-11-191-1/+1
| | | | | | | | | | | | Correct what looks to be errant characters in the makefile variable for the Gigabit Ethernet Controller. This should have no effect on any mainboards as none select the HUDSON_GEC_FWM symbol. Change-Id: Icb861d872973aaf2b653440cae00057d5ad89b20 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36876 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
* lib/fmap: Disable pre-RAM cache for FSP 1.0Julius Werner2019-11-195-4/+19
| | | | | | | | | | | | | | | | | | Due to the way CAR teardown is handled in FSP 1.0, the results of car_get_var_ptr() aren't always reliable, which can break things when running with FMAP cache. It might be possible to fix this but would make the code rather complicated, so let's just disable the feature on these platforms and hope they die out soon. Also allow this option to be used by platforms that don't have space for the cache and want to save a little more code. Change-Id: I7ffb1b8b08a7ca3fe8d53dc827e2c8521da064c7 Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36937 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
* xcompile: Explicitly disable warning address-of-packed-memberElyes HAOUAS2019-11-191-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | With GCC 9.x has a new warning *address-of-packed-member*. > -Waddress-of-packed-member > > Warn when the address of packed member of struct or union is > taken, which usually results in an unaligned pointer value. > This is enabled by default. This results in the build errors below, for example, with GCC 9.2 from Debian Sid/unstable. src/southbridge/intel/common/spi.c: In function 'spi_init': src/southbridge/intel/common/spi.c:298:19: error: taking address of packed member of 'struct ich7_spi_regs' may result in an unaligned pointer value [-Werror=address-of-packed-member] 298 | cntlr->optype = &ich7_spi->optype; | ^~~~~~~~~~~~~~~~~ Therefore, explicitly disable the warning. Change-Id: I01d0dcdd0f8252ab65b91f40bb5f5c5e8177a293 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Signed-off-by: Paul Menzel <pmenzel@molgen.mpg.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36940 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Jacob Garber <jgarber1@ualberta.ca> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* mmio: Fix buffer_to_fifo32() order of argumentsJulius Werner2019-11-192-2/+2
| | | | | | | | | | | buffer_to_fifo32() is a simple wrapper to buffer_to_fifo32_prefix(), but unfortunately its arguments are swapped. This patch fixes the issue. Change-Id: I6414bf51dd9de681b3b87bbaf4ea4efc815f7ae1 Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36942 Reviewed-by: Hung-Te Lin <hungte@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* include: Make stdbool.h a separate fileJulius Werner2019-11-1815-26/+32
| | | | | | | | | | | | | | This patch moves the traditional POSIX stdbool.h definitions out from stdint.h into their own file. This helps for using these definitions in commonlib code which may be compiled in different environments. For coreboot everything should chain-include this stuff via types.h anyway so nothing should change. Change-Id: Ic8d52be80b64d8e9564f3aee8975cb25e4c187f5 Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36837 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
* ipq40xx: Run python script without explicit 'python' callJulius Werner2019-11-181-1/+1
| | | | | | | | | | | | | | This patch changes the ipq40xx Makefile.inc to follow established coreboot practice of calling Python scripts directly rather than invoking the 'python' interpreter explicitly. This has the added effect of honoring the scripts shebang (which in this case is set to 'python2'). Change-Id: If96e8313527c411ef1bb6386e03b6a209c750131 Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36763 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
* build system: Add various compiler flags that enable warnings on UBPatrick Georgi2019-11-181-0/+1
| | | | | | | | | | | | | | | | | Some types of Undefined Behavior can be determined statically at compile time and gcc now has a set of flags that make it emit warnings in that case instead of doing the __builtin_trap() / optimize / UD2-opcode dance that silently breaks the resulting binary. BUG=chromium:958270 BRANCH=none TEST=abuild passes (probably not) Change-Id: I3aa5ca00c9838cc7517160069310a1ef85372027 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32814 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
* src: Ignore Redundant offset remarks in ASL codeWim Vervoorn2019-11-181-1/+4
| | | | | | | | | | | | | | | | IASL reports unnecessary/redundant use of offset operator. These messages are only masking usefull messages. Add -vw 2158 so this message isn't reported. BUG=N/A TEST=build Change-Id: Ie8507d3b3cb6f2e75cb87cd3e4bcc4280df27f77 Signed-off-by: Wim Vervoorn <wvervoorn@eltan.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36857 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* nb/intel/sandybridge/mrc: Handle P2P disabling via devicetreeNico Huber2019-11-187-49/+13
| | | | | | | | | | | | Some Sandy Bridge boards disabled the PCI-to-PCI bridge early to avoid probing by the MRC. We can do that for all boards instead, based on the devicetree setting. Change-Id: Ie64774628fde77db2a379bdba6a921a31e52fa0d Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36903 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
* sb/intel/bd82x6x: Handle enabling of GbENico Huber2019-11-183-12/+28
| | | | | | | | | | | | | | | | The integrated GbE port is toggled via the Backed-Up Control (BUC) register. We already disable it according to the devicetree setting but never enabled it. This could lead to the confusing situation that it was disabled before (different build, vendor BIOS, etc.) but shouldn't be anymore. As we need a full reset after enabling GbE, do it in early PCH init. Change-Id: I9db3d1923684b938d2c9f5b369b0953570c7fc15 Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36902 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
* mb/intel/dcp847ske: Disable xHCI via devicetreeNico Huber2019-11-182-1/+2
| | | | | | | | | | This is supported by generic PCH code now. Change-Id: Id5d764c97e47cdb08a68d03002ebebd996769914 Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36901 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
* mb/sapphire/pureplatinumh61: Don't write BUC and beyondNico Huber2019-11-181-5/+0
| | | | | | | | | | | The BUC register is actually only 8 bits wide and setting bit 5 (disabling GbE) is already done by generic code. Change-Id: I729a2a28f4b0d94eddd070dc89b7341ac0c35e4a Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36900 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
* mb/samsung: Clean up LPC and IOAPIC configurationNico Huber2019-11-182-42/+7
| | | | | | | | | | | | Don't overwrite the LPC decode config of the generic PCH code, move UART init into bootblock_mainboard_early_init() and don't enable the IOAPIC, which is already done by generic code. Change-Id: I90d090f5bff29174e68981fea3c3f04c666b1d28 Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36895 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
* mb/lenovo/s230u: Don't write BUC and beyondNico Huber2019-11-181-5/+0
| | | | | | | | | | | The BUC register is actually only 8 bits wide and setting bit 5 (disabling GbE) is already done by generic code. Change-Id: I4b8e14606c319e8bfc48d6757087f28af1bd5dfb Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36894 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
* mb/intel/emeraldlake2: Revise early initNico Huber2019-11-181-15/+2
| | | | | | | | | | | Move UART initialization to bootblock_mainboard_early_init() and don't override the generic LPC decode settings. Change-Id: Icdab36ae0324175d3d51a050784b94a53d4b3b7c Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36893 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
* mb/hp/revolve_810_g1: Don't clear BUC and beyondNico Huber2019-11-181-5/+0
| | | | | | | | | | | | The BUC register is actually 8 bits wide and shouldn't be bluntly cleared. Change-Id: I2ffd2d161005e839e730102b56af4f66efeb551e Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36892 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
* mb/google(sandybrige): Clean up LPC and IOAPIC configurationNico Huber2019-11-184-43/+2
| | | | | | | | | | | Only set LPC decode bits that the generic PCH code doesn't set yet. And don't enable the IOAPIC, which is already done by generic code. Change-Id: I9d2f6a9ad3f5d83573e07596f2763edc75f4ee64 Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36891 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
* mb/gigabyte/ga-b75m-d3h: Drop useless function-disable settingNico Huber2019-11-181-6/+0
| | | | | | | | | | | This bit is already cleared by a reset. Change-Id: Ib71496011c9621476a7327ba309f367c7fa971e4 Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36890 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
* mb/{gigabyte,lenovo}: Remove spurious setting of ETR3 bit 16Nico Huber2019-11-1811-69/+0
| | | | | | | | | | | | | This bit is used to indicate xHCI routing across reboots. If anything, coreboot should act on it, not set it during boot. ASL code would be supposed to set it. Change-Id: Id14647ac4e591cfa042ca8aad6dfc6ccda35c74a Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36889 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
* mb/compulab/intense_pc: Clean PCH and super-i/o config upNico Huber2019-11-181-21/+4
| | | | | | | | | | | | | The generic PCH code already enables a superset of LPC decoding. Move UART setup to bootblock_mainboard_early_init() where it is expected. Last but not least, remove an odd write to BUCs (RCBA+0x3414) and beyond, as it's an 8-bit register and shouldn't be bluntly zeroed. Change-Id: I24a4ccf6a529460a83f48522d2e05e6ad6614f81 Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36888 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
* mb/asus/p8h61-m*: Drop unnecessary PCH configNico Huber2019-11-182-13/+0
| | | | | | | | | | | The generic PCH code already sets up a superset of these decodings. Change-Id: I90bca37c46b89c35f323225fc3c087f1630397e4 Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36887 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tristan Corrick <tristan@corrick.kiwi> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
* mb/apple/macbookair4_2: Drop unnecessary PCH configNico Huber2019-11-181-12/+0
| | | | | | | | | | | | | | | | | | | | | mainboard_pch_lpc_setup() and mainboard_late_rcba_config() did 4 things here on top of the generic PCH code: 1. Enabling LPC decoding for gameports. It seems unlikely that anything is using these ports and there is no code to support gameports. 2. Decoding of COM3 instead of COM2. What COM? 3. Premature locking of ETR3/global reset. Bad idea. 4. Disabling the GbE port in BUC. Already done by PCH code. Change-Id: Ie92dbf5c6813435995c4d24ed807ffc8d125953a Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36886 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
* nb/intel/sandybridge: Set up console in bootblockArthur Heymans2019-11-1891-119/+133
| | | | | | | | Change-Id: Ia041b63201b2a4a2fe6ab11e3497c460f88061d1 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36784 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
* ec/hp/kbc1126: Include early_init.c in bootblockArthur Heymans2019-11-181-0/+1
| | | | | | | | Change-Id: I198709efe1eb5d2022d0fbd640901238e696eaa6 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36885 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
* nb/intel/sandybridge: Move to C_ENVIRONMENT_BOOTBLOCKArthur Heymans2019-11-1852-64/+65
| | | | | | | | | | | | | | | | There is some overlap between romstage and bootblock. LPC setup and BAR initialization is now done twice. The rationale is that the romstage should not depend too much on the bootblock, since it can reside in a RO fmap region. Enabling the console will be done in a followup patch. Change-Id: I4d0ba29111a5df6f19033f5ce95adcc0d9adc1fd Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36783 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
generated by cgit v1.2.3 (git 2.25.1) at 2024-05-10 07:13:56 +0000