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* Documentation/releases: Fill in coreboot 4.14 release notes4.144.14_branchPatrick Georgi2021-05-101-12/+70
| | | | | | | | Change-Id: I79530c91424112247e485a5a41debc666e0072d4 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/54003 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* cpu/x86/smm: Fix typoPatrick Georgi2021-05-101-1/+1
| | | | | | | | | | Change-Id: I28f262078cf7f5ec4ed707639e845710a8cc56ea Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/53926 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
* *x86: fix x2apic mode boot issueWonkyu Kim2021-05-103-17/+22
| | | | | | | | | | | | | | | | Fix booting issues on google/kahlee introduced by CB:51723. Update use inital apic id in smm_stub.S to support xapic mode error. Check more bits(LAPIC_BASE_MSR BIT10 and BIT11) for x2apic mode. TEST=Boot to OS and check apicid, debug log for CPUIDs cpuid_ebx(1), cpuid_ext(0xb, 0), cpuid_edx(0xb) etc Signed-off-by: Wonkyu Kim <wonkyu.kim@intel.com> Change-Id: Ia28f60a077182c3753f6ba9fbdd141f951d39b37 Reviewed-on: https://review.coreboot.org/c/coreboot/+/52696 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
* doc/relnotes/4.14: add Intel Xeon-SP support status changeJonathan Zhang2021-05-101-0/+24
| | | | | | | | | Signed-off-by: Jonathan Zhang <jonzhang@fb.com> Change-Id: Ibead1c75bb4e41fedc2799366b5b006d76fc8f4e Reviewed-on: https://review.coreboot.org/c/coreboot/+/52735 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Subrata Banik <subrata.banik@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* doc/releases/coreboot-4.14: Add x86 bootblock and ACPI GNVS changesKyösti Mälkki2021-05-101-0/+15
| | | | | | | | | | | Change-Id: Ifa58a9ac7c6dcc391cd9942295319a8677cd4492 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/54008 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
* AGESA boards: Drop comments about `IDS_DEBUG_PORT`Angel Pons2021-05-1025-50/+0
| | | | | | | | | | | No board defines this macro. In preparation to drop OptionsIds.h files from mainboards, remove commented-out references to `IDS_DEBUG_PORT`. Change-Id: I67a10d863aeea9e1b91c38aa02d19106b7b97659 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/53981 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com>
* AGESA boards: Drop unused `IDSOPT_HOST_SIMNOW` macroAngel Pons2021-05-1025-50/+0
| | | | | | | | | | This macro is not used anywhere in AGESA. Remove all references. Change-Id: Ibc2876a5a8419ec4fa5a793bb996f5c14d989bac Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/53980 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com>
* AGESA boards: Drop unused `IDSOPT_HOST_HDT` macroAngel Pons2021-05-1025-50/+0
| | | | | | | | | | This macro is not used anywhere in AGESA. Remove all references. Change-Id: I9cd9fa0dc25b1143f8b4c1f20beffba638437398 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/53979 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com>
* AGESA boards: Drop unused `IDSOPT_DEBUG_ENABLED` macroAngel Pons2021-05-1025-41/+0
| | | | | | | | | | This macro is not used anywhere in AGESA. Remove all references. Change-Id: Icae0ecae77a20e1568440e3191a29db33b5581d8 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/53978 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com>
* device: Drop unused `uma_memory_{base,size}` globalsAngel Pons2021-05-102-12/+0
| | | | | | | | | | These global variables are not used anywhere. Drop them. Change-Id: I3fe60b970153d913ae7b005257e2b53647d6f343 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/53977 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* src: Drop "This file is part of the coreboot project" linesAngel Pons2021-05-105-5/+0
| | | | | | | | | | | | Commit 6b5bc77c9b22c398262ff3f4dae3e14904c57366 (treewide: Remove "this file is part of" lines) removed most of them, but missed some files. Change-Id: Ib8e7ab26a74b52f86d91faeba77df3331531763f Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/53976 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Nico Huber <nico.h@gmx.de>
* soc/intel/cannonlake: Merge soc_memory_init_params() into its callerFelix Singer2021-05-101-14/+5
| | | | | | | | | | | | | | | | | soc_memory_init_params() does not only configure memory init parameters. Despite its name, it also configures many other things. Therefore, merge it into its caller function platform_fsp_memory_init_params_cb() to prevent confusions. Built clevo/l140cu with BUILD_TIMELESS=1. coreboot.rom remains the same. Change-Id: Id3b6395ea5d5cb714a412c856d66d4a9bcbd9c12 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/52491 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* soc/intel/skylake: Set proper defaults in chipset devicetreeFelix Singer2021-05-101-3/+3
| | | | | | | | | | | | | LPC, P2SB and Power Management controller are always needed. Thus, enable them by default. Change-Id: I20b8cbe536da70fccc3d11e1eedf4a5e14bfc862 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/53925 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
* inteltool: add initial support for Emmits Burg PCHJonathan Zhang2021-05-102-0/+3
| | | | | | | | | Signed-off-by: Jonathan Zhang <jonzhang@fb.com> Change-Id: I6a4027bf51b3a189e64211e77621b3dd6c80b00d Reviewed-on: https://review.coreboot.org/c/coreboot/+/52864 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Maxim Polyakov <max.senia.poliak@gmail.com> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
* inteltool: add initial suppot for Sapphire Rapids Scalable ProcessorJonathan Zhang2021-05-102-0/+3
| | | | | | | | | | | Intel Sapphire Rapids Scalable Processor is a 4th generation processor of Intel Xeon Scalable Processor family. Signed-off-by: Jonathan Zhang <jonzhang@fb.com> Change-Id: Idf492d6e7993b9d55d6cd865e721c81876cee9a4 Reviewed-on: https://review.coreboot.org/c/coreboot/+/52863 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* mb/gigabyte/ga-d510ud: Fix HDA codec configurationAngel Pons2021-05-101-16/+18
| | | | | | | | | | | The values were copied from Foxconn D41S, which uses a different codec. Adjust the codec config as per the settings dumped from vendor firmware. Change-Id: If6a4c41b5d424adb23ebef402d2d2ad21269fe25 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/53914 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
* 3rdparty/intel-sec-tools: Update submodule pointerArthur Heymans2021-05-102-5/+3
| | | | | | | | | | | | | | | Some changes: - bg-prov got renamed to cbnt-prov - cbfs support was added which means that providing IBB.Base/Size separatly is not required anymore. Also fspt.bin gets added as an IBB to secure the root of trust. Change-Id: I20379e9723fa18e0ebfb0622c050524d4e6d2717 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/52971 Reviewed-by: Christian Walter <christian.walter@9elements.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* security/intel/cbnt: Rename bg-prov to cbnt-provArthur Heymans2021-05-102-34/+34
| | | | | | | | | | | | This prepares for updating the intel-sec-tools submodule pointer. In that submodule bg-prov got renamed to cbnt-prov as Intel Bootguard uses different structures and will require a different tool. Change-Id: I54a9f458e124d355d50b5edd8694dee39657bc0d Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/52970 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
* soc/intel/adl: Allow mainboard to fill CmdMirror and DqDqsRetrainingMaulik V Vaghela2021-05-102-0/+12
| | | | | | | | | | | | | | | | | | We need to modify update CmdMirror and LpDdrDqDqsRetraining parameters for ADLRVP board. Allowing this parameters to be filled by devicetree will allow flexibility to update values as per board designs. Note that both UPDs are applicable for both DDR and Lpddr memory types. BUG=None BRANCH=None TEST=Build works and UPD values have been filled correctly Change-Id: I55b4b4aee46231c8c38e208c357b4376ecf6e9d9 Signed-off-by: Maulik V Vaghela <maulik.v.vaghela@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51027 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
* mb/google/cherry: Configure TPMYidi Lin2021-05-103-0/+19
| | | | | | | | Change-Id: I1d6ecdb31eef65d2e96d9251348390aa8598be6c Signed-off-by: Yidi Lin <yidi.lin@mediatek.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/53900 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
* mb/google/cherry: Enable Chrome ECYidi Lin2021-05-104-6/+18
| | | | | | | | Signed-off-by: Yidi Lin <yidi.lin@mediatek.com> Change-Id: Iab3549b5c4e7d845ddd284a0df3fb448e11fbdcb Reviewed-on: https://review.coreboot.org/c/coreboot/+/53899 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
* soc/amd/picasso: move acpigen_dptc_call_alib to new common alibFelix Held2021-05-106-14/+27
| | | | | | | | Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ib0f7da12429b6278d1e4bc5d6650c7ee0f3b5209 Reviewed-on: https://review.coreboot.org/c/coreboot/+/53940 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
* Revert "soc/amd/common/espi: Don't set alert pin in espi_set_initial_config"Raul E Rangel2021-05-101-0/+11
| | | | | | | | | | | | | | | | | | | | | This reverts commit 6eced03b25954e370e20e62f2cbe41f9d5626eae. This prevents zork from booting. We get the following error: eSPI cmd0-cmd2: 00080009 00000000 00000000 data: 00000000. Error: unexpected eSPI status register bits set (Status = 0x10000010) Error: Slave GET_CONFIGURATION failed! This isn't a pure revert. It is more of a fix that keeps the old behavior. BUG=b:187122344 TEST=Boot zork an no longer see eSPI error Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: If75a35d3994b0fd23945a450032d3cc81abeb136 Reviewed-on: https://review.coreboot.org/c/coreboot/+/53932 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* soc/amd/cezanne: Force resets to be coldMarshall Dawson2021-05-102-4/+10
| | | | | | | | | | | | | | | Cezanne must use cold resets. Change the warm reset request to always set TOGGLE_ALL_PWR_GOOD. And, since the bit is sticky across power cycles, set it early for good measure. BUG=b:184281092 TEST=Majolica successfully resets using 0xcf9 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Change-Id: I7d4ca5665335b20100a5c802d12d79c0d0597ad9 Reviewed-on: https://review.coreboot.org/c/coreboot/+/52982 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
* mb/google/mancomb: Fix TPM setting in devicetreeIvy Jian2021-05-101-8/+9
| | | | | | | | | | | | | | Fix I2C3 setting for TPM in devicetree. BUG=b:187341277 TEST=Build and boot into OS Signed-off-by: Ivy Jian <ivy_jian@compal.corp-partner.google.com> Change-Id: I728da76cee0c92c29df4c6ee8bfb4cd07a6366c4 Reviewed-on: https://review.coreboot.org/c/coreboot/+/53891 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com> Reviewed-by: Raul Rangel <rrangel@chromium.org>
* cezanne/psp_verstage: update SRAM addressKangheui Won2021-05-101-4/+4
| | | | | | | | | | | Loading address and size for the user app has been changed with recent PSP release. Signed-off-by: Kangheui Won <khwon@chromium.org> Change-Id: If247cdf3413c6a10f4b3c92fb7e43dd1057865d9 Reviewed-on: https://review.coreboot.org/c/coreboot/+/53904 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
* amd/cezanne: verify transfer buffer in bootblockKangheui Won2021-05-101-0/+7
| | | | | | | | | | | | Verify if transfer buffer is valid before progressing further to catch invalid transfer buffer early. Signed-off-by: Kangheui Won <khwon@chromium.org> Change-Id: I4c470b156944b50e581dcdee47b196f46b0993f3 Reviewed-on: https://review.coreboot.org/c/coreboot/+/52965 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* psp_verstage: differentiate bios entryKangheui Won2021-05-104-1/+14
| | | | | | | | | | | | AMDFW tool stores bios dir entry to bios1_entry in picasso but bios3_entry in cezanne. Separate getting bios_dir_addr into a function and implement it on each platforms. Signed-off-by: Kangheui Won <khwon@chromium.org> Change-Id: Ie18ed7979a04319c074b9b251130d419dc7f22dc Reviewed-on: https://review.coreboot.org/c/coreboot/+/52964 Reviewed-by: Martin Roth <martinroth@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* psp_verstage: move platform-specific code to chipset.cKangheui Won2021-05-106-27/+37
| | | | | | | | | | | | | | Move all platform-specific code except direct svc calls to chipset.c. There will be differences between each platforms and we can't put everything into svc.c. TEST=build firmware for zork Signed-off-by: Kangheui Won <khwon@chromium.org> Change-Id: Ie7a71d1632800072a17c26591e13e09e0269cf75 Reviewed-on: https://review.coreboot.org/c/coreboot/+/52963 Reviewed-by: Martin Roth <martinroth@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* cezanne/psp_verstage: clean up duplicated targetKangheui Won2021-05-101-3/+0
| | | | | | | | | | | psp_verstage.bin target is already defined at common/psp_verstage/Makefile.inc, thus removing it here. Signed-off-by: Kangheui Won <khwon@chromium.org> Change-Id: Ica4b09282d1c4cfc555c18ba50951458b8580826 Reviewed-on: https://review.coreboot.org/c/coreboot/+/52962 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* cezanne/psp_verstage: populate a/b firmwareKangheui Won2021-05-102-0/+63
| | | | | | | | | | | | Build amdfw_[ab] and put them into CBFS. We can reuse FW_[AB] position from zork since we have same flash layout and size. Signed-off-by: Kangheui Won <khwon@chromium.org> Change-Id: Idb31afa7a513f01593b2af75515a170dfca8d360 Reviewed-on: https://review.coreboot.org/c/coreboot/+/52961 Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Martin Roth <martinroth@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* mb/google/guybrush: Enable GFX HDA deviceKarthikeyan Ramasubramanian2021-05-101-0/+1
| | | | | | | | | | | | | Enable Display Controller Engine Audio endpoint to enable HDMI audio. BUG=b:186479763 TEST=Build and boot to OS in guybrush. Change-Id: I5e35440e8e70ee125d37c7ac30c9219ec69c7c6e Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/52974 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
* mb/google/guybrush: Enable PP5000_PENEric Peers2021-05-101-1/+1
| | | | | | | | | | | | | | Everybody wants a stylish stylus. Enable the power system to it. BUG=b:186267293 TEST=connect multimeter to PP5000_PEN and see it go from 0 to 1. MAGIC! Signed-off-by: Eric Peers <epeers@google.com> Change-Id: I11d05c118ec9451d26136c320f3650c489e02c59 Reviewed-on: https://review.coreboot.org/c/coreboot/+/53943 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Martin Roth <martinroth@google.com>
* soc/mediatek/mt8195: Add RTC driverYuchen Huang2021-05-109-2/+263
| | | | | | | | | | | | Both mt8192 and mt8195 use MT659P RTC. Move mt8192/rtc.c to common folder and rename to rtc_mt6359p.c. Signed-off-by: Yuchen Huang <yuchen.huang@mediatek.corp-partner.google.com> Signed-off-by: Yidi Lin <yidi.lin@mediatek.com> Change-Id: I73ea90512228a659657f2019249e7142c673e68e Reviewed-on: https://review.coreboot.org/c/coreboot/+/53897 Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* soc/mediatek/mt8195: Add clk_buf driverYuchen Huang2021-05-105-5/+9
| | | | | | | | | | | | Both mt8192 and mt8195 use mt6359p clk_buf. But mt8195 clk_buf uses legacy co-clock mode without srclken_rc. Signed-off-by: Yuchen Huang <yuchen.huang@mediatek.corp-partner.google.com> Change-Id: Ie9ee91449a7a14e77231493f807b321b2dbaa6a6 Signed-off-by: Yidi Lin <yidi.lin@mediatek.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/53896 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
* soc/mediatek/mt8195: Configure eMMC and SDCardWenbin Mei2021-05-103-0/+120
| | | | | | | | | Change-Id: I0ed82e860612e8a62f361e60d217280f775ab239 Signed-off-by: Wenbin Mei <wenbin.mei@mediatek.com> Signed-off-by: Yidi Lin <yidi.lin@mediatek.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/53895 Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* soc/mediatek/mt8195: Add i2c driver supportkewei xu2021-05-103-0/+230
| | | | | | | | | | TEST=write/read EEPROM on MT8195 EVB successfully Change-Id: Ia26e55512501e9758d7f5543d176730cf30ce03d Signed-off-by: kewei xu <kewei.xu@mediatek.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/53894 Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* soc/mediatek/mt8195: Add mt6360 driver for LDO accessAndrew SH Cheng2021-05-102-0/+357
| | | | | | | | Signed-off-by: Andrew SH Cheng <andrew-sh.cheng@mediatek.com> Change-Id: I68ca7067f76a67c4e797437593539f8f85909edc Reviewed-on: https://review.coreboot.org/c/coreboot/+/53893 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
* soc/amd/cezanne: Generate PCI GPP ACPI namesRaul E Rangel2021-05-091-31/+9
| | | | | | | | | | | | | | | | We can generate the names, so there is no need to hard code a table. This will make the code more generic so it can be reused with picasso in the future. BUG=b:184766519 TEST=Dump guybrush ACPI table and verify it looks correct. Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: I5134d1dba4fcb9ce8cc4bfad1c619331a95f3b11 Reviewed-on: https://review.coreboot.org/c/coreboot/+/52870 Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* soc/amd/cezanne: Enable GNB IO-APIC _PRTRaul E Rangel2021-05-091-2/+1
| | | | | | | | | | | | | | We can now use the GNB IO-APIC. BUG=b:184766519 TEST=Boot guybrush to OS with `pci=nomsi amd_iommu=off noapic` Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: I4df5a4583f14044d2efcde3a9de9dd85e898a11d Reviewed-on: https://review.coreboot.org/c/coreboot/+/53936 Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* soc/amd/cezanne: add GNB IOAPIC supportFelix Held2021-05-094-1/+29
| | | | | | | | | | | | | | | | | | To configure and enable the IOAPIC in the graphics and northbridge (GNB) container, FSP needs to write an undocumented register, so pass the GNB IOAPIC MMIO base address to make it show up at that address. BUG=b:187083211 TEST=Boot guybrush and see IO-APIC initialized IOAPIC[0]: apic_id 16, version 33, address 0xfec00000, GSI 0-23 IOAPIC[1]: apic_id 17, version 33, address 0xfec01000, GSI 24-55 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: I1e127ce500d052783f0a6e13fb2ad16a8e408b0e Reviewed-on: https://review.coreboot.org/c/coreboot/+/52905 Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* mb/google/guybrush: Populate PIC IRQ dataRaul E Rangel2021-05-091-8/+8
| | | | | | | | | | | | | | | | | | | | | | | The PIC IRQs are required so we can correctly set up the PCI_INT registers. This only matters when booting in PIC mode. We don't need to set the IO-APIC registers since the linux kernel will auto-assign those to reduce conflicts. BUG=b:184766519 TEST=Boot guybrush with `pci=nomsi,noacpi amd_iommu=off noapic` and verify xhci and graphics continue to work. $ cat /proc/interrupts 12: 285064 XT-PIC nvme0q0, nvme0q1, rtw88_pci 13: 100000 XT-PIC xhci-hcd:usb1 14: 4032 XT-PIC amdgpu, xhci-hcd:usb3 Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: I1d66ccd08a86a64242dbc909c57ff9685828f61f Reviewed-on: https://review.coreboot.org/c/coreboot/+/52915 Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* soc/amd/cezanne: Generate PCI routing tableRaul E Rangel2021-05-092-2/+30
| | | | | | | | | | | | | Use the new acpigen_write_PRT to write the _PRT for each PCI bridge. BUG=b:184766519 TEST=Dump guybrush ACPI table and verify it looks correct. Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: Idb559335435a95e73640e6d7fb224e16e0592326 Reviewed-on: https://review.coreboot.org/c/coreboot/+/51556 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
* soc/amd/cezanne: Populate PCI_INTR registersRaul E Rangel2021-05-092-0/+7
| | | | | | | | | | | | | | This uses the new FSP PCI methods to pull the routing table and populate the pirq data structure. BUG=b:184766519 TEST=Boot guybrush and verify we get Got IRQ 0x1F (disabled) messages Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: Ie21229cc2fb4fd5b85c0b9e933f7b43af24864b0 Reviewed-on: https://review.coreboot.org/c/coreboot/+/52914 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
* soc/amd/common/fsp/pci: Add helper methods for PCI IRQ tableRaul E Rangel2021-05-093-0/+51
| | | | | | | | | | | | | | These are helper methods for interacting with the AMD_FSP_PCIE_DEVFUNC_REMAP_HOB_GUID. BUG=b:184766519, b:184766197 TEST=Build guybrush Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: Id03d0b74ca12e7bcee11f8d13b0e802861c13923 Reviewed-on: https://review.coreboot.org/c/coreboot/+/52911 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
* soc/amd/picasso/pci_gpp: Switch to using acpigen_write_pci_GNB_PRTRaul E Rangel2021-05-091-63/+1
| | | | | | | | | | | | | We can now delete the picasso specific version. BUG=b:184766519 TEST=Build zork and verify SSDT has not changed Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: Ic79014e83c9ff63cc7a6757b16764ae23b36984f Reviewed-on: https://review.coreboot.org/c/coreboot/+/53935 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* soc/amd/common/block/pci: Implement acpigen_write_pci_{GNB,FCH}_PRTRaul E Rangel2021-05-093-2/+217
| | | | | | | | | | | | | | | | This is loosely based off of picasso/pcie_gpp.c. This version uses the acpigen_write_PRT_X methods to write the actual records. There are also two functions, 1 for using the GNB, and one for using the FCH. The FCH one is useful when the GNB IO-APIC has not been initialized. BUG=b:184766519 TEST=Dump guybrush ACPI and verify it looks correct Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: I926430074acb969ceb11fdb60ab56dcf91ac4c76 Reviewed-on: https://review.coreboot.org/c/coreboot/+/52917 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
* soc/amd/{picasso,common/blocks/pci}: Move populate_pirq_dataRaul E Rangel2021-05-093-30/+35
| | | | | | | | | | | | | | The method now dynamically allocates the pirq structure and uses the get_pci_routing_table method. BUG=b:184766519 TEST=Build guybrush and verify picasso SSDT has not changed. Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: I297fc3ca7227fb4794ac70bd046ce2f93da8b869 Reviewed-on: https://review.coreboot.org/c/coreboot/+/52913 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
* soc/amd/picasso: Migrate to struct pci_routing_infoRaul E Rangel2021-05-091-46/+21
| | | | | | | | | | | | | | | This allows us to use the common get_pci_routing_info and pci_calculate_irq. The IRQ field in the struct was also filled in from the PPR. BUG=b:184766519 TEST=Boot ezkinil and verify SSDT table is identical. Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: I16d90d8c89bfcf48878c0741154290ebc52a4120 Reviewed-on: https://review.coreboot.org/c/coreboot/+/53923 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* soc/amd/common/block/pci: Introduce struct pci_routing_infoRaul E Rangel2021-05-093-0/+85
| | | | | | | | | | | | | | | | | | This struct is similar to `struct pci_routing` defined in picasso/pcie_gpp.c. It additionally contains the irq used for the bridge and is structured in a way that the FSP can provide via HOB. The next set of CLs will migrate the pci routing functions used by picasso into common and enable pci routing table generation for cezanne. BUG=b:184766519 TEST=Build guybrush Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: I1a8d988d125f407f0aa7bc1722d432446aa9aff8 Reviewed-on: https://review.coreboot.org/c/coreboot/+/53922 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
generated by cgit v1.2.3 (git 2.25.1) at 2024-05-03 10:05:43 +0000