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* mb/google/brya: Add SPD configs for CrotaTerry Chen2022-02-243-2/+21
| | | | | | | | | | | | | | | | | | | | | | | Add a mem_parts_used.txt for Crota, containing the memory parts used in proto builds. Generate Makefile.inc and dram_id.generated.txt using part_id_gen. DRAM Part Name ID to assign MT62F1G32D4DR-031 WT:B 0 (0000) MT62F512M32D2DR-031 WT:B 1 (0001) H9JCNNNBK3MLYR-N6E 1 (0001) H9JCNNNCP3MLYR-N6E 0 (0000) K3LKBKB0BM-MGCP 2 (0010) BUG=b:215443524 TEST=emerge-brya coreboot Change-Id: I0ff6ffea4b879b6e1287e1e3cb9fd36a80f52ed6 Signed-off-by: Terry Chen <terry_chen@wistron.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/62262 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
* nb/intel/ironlake: Clean up `jedec_read()` functionAngel Pons2022-02-241-9/+4
| | | | | | | | | | | | Deduplicate a condition and reflow some lines. Tested on HP ProBook 6550b, still reaches TianoCore payload. Change-Id: If5786f34585e15100385d452b5b03a36da4c7c87 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/61939 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
* nb/intel/ironlake: Fix some quickpath init magicAngel Pons2022-02-243-7/+23
| | | | | | | | | | | | | | | | | | | Correct some Quickpath initialisation steps according to findings from two different Intel reference code binaries as well as MCHBAR register dump comparisons between vendor firmware and coreboot. The MSR_TURBO_POWER_CURRENT_LIMIT information comes from EDK2 sources. Tested on Apple iMac 10,1 (Clarkdale, aka desktop Ironlake), QPI init now completes successfully instead of causing hangs before raminit. Also tested on HP ProBook 6550b (Arrandale, aka mobile Ironlake), still reaches payload (e.g. TianoCore). Change-Id: Icd0139aa588dc8d948c03132b5c86866d90f3231 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60216 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
* nb/intel/ironlake: Move out HECI remainders into southbridgeAngel Pons2022-02-245-6/+7
| | | | | | | | | | | | Move the remaining HECI-related stuff to southbridge scope, as the HECI hardware is in the southbridge. Note that HECI BAR is now enabled a bit earlier than before, but this shouldn't matter. Change-Id: I4a29d0b5d5c5e22508bcdfe34a1c5459ae967c75 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/61932 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
* amdfwtool: Check the real length of PMU stringZheng Bao2022-02-241-0/+3
| | | | | | | | | | | The length should be checked before the PMU_STR_INS_INDEX(th) character is accessed, otherwise it is going to an access violation. Change-Id: I8b59eb34e1cb01fd6e2571fcebc28ef2084b6ec4 Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/62249 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
* mb/google/brya/var/vell: Corrects ACPI _PLD macro settingRobert Chen2022-02-241-8/+8
| | | | | | | | | | | | | | | | | | | | | | | This patch is to denote the correct side of ACPI _PLD usb C ports. +-------------------------+ | LCD | | | | | +-------------------------+ PORT_C2 | | PORT_C1 PORT_C3 | DB MB | PORT_C0 | | +-------------------------+ BUG=b:220634230 TEST=emerge-brya coreboot Change-Id: I84515f98b6cdab5768df75690b0f5ca1bb9ad96d Signed-off-by: Robert Chen <robert.chen@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/62252 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
* mb/google/brya/var/anahera{4es}: Add MT53E2G32D4NQ-046 WT:C supportWisley Chen2022-02-246-6/+10
| | | | | | | | | | | | | Add new memory MT53E2G32D4NQ-046 WT:C support BUG=b:220821471 TEST=emerge-brya coreboot Change-Id: I4c21254213c2107d015adebb510612e0256ffb5c Signed-off-by: Wisley Chen <wisley.chen@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/62268 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
* mb/google/brya/var/redrix{4es}: Add MT53E2G32D4NQ-046 WT:CWisley Chen2022-02-246-6/+10
| | | | | | | | | | | | | Add new memory MT53E2G32D4NQ-046 WT:C support. BUG=b:220804962 TEST=emerge-brya coreboot Change-Id: I3353d7c119798ebb0b5ee1ea32161e54b4eec826 Signed-off-by: Wisley Chen <wisley.chen@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/62267 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
* spd/lp4x: Generate initial SPD for MT53E2G32D4NQ-046 WT:CWisley Chen2022-02-243-0/+14
| | | | | | | | | | | | | Generate the initial SPD for MT53E2G32D4NQ-046 WT:C BUG=b:220804962 TEST=util/spd_tools/bin/spd_gen spd/lp4x/memory_parts.json lp4x Change-Id: I3e2b377f1d6d4b1fa45614ad2f3de81eef17c2b8 Signed-off-by: Wisley Chen <wisley.chen@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/62266 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
* payloads/tianocore: Add option for to prioritize internal devicesSean Rhodes2022-02-243-0/+11
| | | | | | | | | | | Add TIANOCORE_PRIORITIZE_INTERNAL which, when enabled, will build edk2 with boot from internal devices before external devices. Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: Ib1f73c8f3f2f2376cdc197b58d259446dc5f0138 Reviewed-on: https://review.coreboot.org/c/coreboot/+/61797 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
* payloads/tianocore: Add option for PS/2 keyboard supportSean Rhodes2022-02-243-0/+16
| | | | | | | | | | | Add TIANOCORE_PS2_SUPPORT which, when enabled, will build edk2 with PS/2 keyboard support. Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: Ibabce6ac1ac68ab958610d42c77f3c2c494528ef Reviewed-on: https://review.coreboot.org/c/coreboot/+/61760 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
* payloads/tianocore: Add option to include EFI ShellSean Rhodes2022-02-243-2/+12
| | | | | | | | | | | Add TIANOCORE_HAVE_EFI_SHELL, which when enabled, will build edk2 with the EFI Shell binary. Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: I1272f514e3f5becfe1fddd58ca0d820c5d1c1b54 Reviewed-on: https://review.coreboot.org/c/coreboot/+/61759 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
* payloads/tianocore: Add option to use follow BGRT specSean Rhodes2022-02-243-0/+13
| | | | | | | | | | | | Adds TIANOCORE_FOLLOW_BGRT_SPEC which, when enabled, will follow the BGRT Specification implemented by Microsoft and the Boot Logo will be vertically centered 38.2% from the top of the display. Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: If508166fe657d1cc032dd09a0fa231c7b60d9846 Reviewed-on: https://review.coreboot.org/c/coreboot/+/61758 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
* payloads/tianocore: Add option to use Escape for Boot ManagerSean Rhodes2022-02-243-0/+12
| | | | | | | | | | | | Add TIANOCORE_BOOT_MANAGER_ESCAPE which, when enabled, will use Escape as the hot-key to access the Boot Manager. This replaces the default key of F2. Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: I1e60d116367542f55f0ffa241a6132e4faabe446 Reviewed-on: https://review.coreboot.org/c/coreboot/+/61757 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
* security/intel/stm: Make STM setup MP safeEugene Myers2022-02-242-3/+11
| | | | | | | | | | | | | | | | | | | | | | | | Some processor families allow for SMM setup to be done in parallel. On processors that have this feature, the BIOS resource list becomes unusable for some processors during STM startup. This patch covers two cases: (1) The BIOS resource list becomes twice as long because the smm_relocation function is called twice - this is resolved by recreating the list on each invocation. (2) Not all processors receive the correct resource list pointer - this is resolved by having every processor execute the pointer calculation code, which is a lot faster then forcing all processors to spin lock waiting for this value to be calculated. This patch has been tested on a Purism L1UM-1X8C and Purism 15v4. Signed-off-by: Eugene Myers <cedarhouse@comcast.net> Change-Id: I7619038edc78f306bd7eb95844bd1598766f8b37 Reviewed-on: https://review.coreboot.org/c/coreboot/+/61689 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eugene Myers <cedarhouse1@comcast.net> Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
* security/intel/stm: Use correct SMBASE for SMM descriptor setupEugene Myers2022-02-242-7/+6
| | | | | | | | | | | | | | | | | Commit ea3376c (SMM module loader version 2) changedhow the SMBASE is calculated. This patch modifies setup_smm_descriptor to properly acquire the SMBASE. This patch has been tested on a Purism L1UM-1X8C and a Purism 15v4. Signed-off-by: Eugene Myers <cedarhouse@comcast.net> Change-Id: I1d62a36cdcbc20a19c42266164e612fb96f91953 Reviewed-on: https://review.coreboot.org/c/coreboot/+/61688 Reviewed-by: Eugene Myers <cedarhouse1@comcast.net> Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* arch/x86/Kconfig: drop HPET_ADDRESS_OVERRIDEFelix Held2022-02-241-4/+1
| | | | | | | | | | | | | | | Commit b433d26ef11b78dda353723ff7c8797d06f76f21 (arch/x86: Define HPET_ADDRESS_OVERRIDE) added this Kconfig option and referenced the via/cx700 chipset which has been dropped before the 4.9 release. No SoC in the current tree selects HPET_ADDRESS_OVERRIDE and all SoCs have their HPET mapped at 0xfed00000, so drop this unused and no longer needed Kconfig option. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I4021ed6f84473c7a9223323fc8aa5d3f935d8084 Reviewed-on: https://review.coreboot.org/c/coreboot/+/62276 Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* soc/amd/*/include/soc/iomap.h: rework HPET base address checkFelix Held2022-02-244-12/+12
| | | | | | | | | | | | | | | The AMD SoCs had a check to make sure that HPET_ADDRESS_OVERRIDE isn't set so that the HPET_ADDRESS Kconfig option will have the right default value. Instead check if the HPET_ADDRESS Kconfig value matches the HPET_BASE_ADDRESS define in the SoC code which is the case if HPET_ADDRESS_OVERRIDE isn't selected. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Icf1832eb36c031e93ba24f342e9a8a7bf13faecc Reviewed-on: https://review.coreboot.org/c/coreboot/+/62275 Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* libpayload/lpgcc: Add `--gc-sections` linker argumentNico Huber2022-02-231-1/+1
| | | | | | | | | | | To be able to link libcbfs without vboot, we need garbage collection now. Change-Id: Id9a9fe7efb9fb4409a43ae8357f4f683618805d2 Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/62247 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
* libpayload/x86: Fix boot_device_read() and hook it upNico Huber2022-02-232-1/+3
| | | | | | | | | | Casts from integer to pointer are usually a case for phys_to_virt(). Change-Id: I861d435ff2361cdc26a2abd46d43b9346fa67ccc Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/62246 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
* cr50: Increase cr50 i2c probe timeoutRob Barnes2022-02-231-3/+4
| | | | | | | | | | | | | | | | | Turns out 200ms still isn't enough in the worst reset conditions. There's been some reports of failures at 200ms with some older cr50 versions. Let's not take any chances and bump this way up since if this fails, it prevents boot. BUG=b:213828947 BRANCH=None TEST=Reboot and suspend_stress on Nipperkin Signed-off-by: Rob Barnes <robbarnes@google.com> Change-Id: I5be0a80c064546fd277f66135abc9d0572df11cb Reviewed-on: https://review.coreboot.org/c/coreboot/+/61864 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
* src/mediatek: Refactor dramc_param to share more structuresXi Chen2022-02-234-191/+73
| | | | | | | | | | | | | The ddr_base_info struct, which stores basic DDR information, should be platform independent. Currently the struct is defined in each SoC's dramc_parah.h. To prevent code duplication, move it as well as other related structs and enums to a common header. Signed-off-by: Xi Chen <xixi.chen@mediatek.corp-partner.google.com> Change-Id: I99772427f9b0755dc2c778b5f4150b2f8147bcc3 Reviewed-on: https://review.coreboot.org/c/coreboot/+/61293 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
* soc/mediatek/mt8186: disable VSRAM_CORERex-BC Chen2022-02-231-0/+4
| | | | | | | | | | | | | | | VSRAM_CORE is not used on kingler/krabby, so we disable it. This implementation is according to chapter 3.7 in MT8186 Functional Specification. BUG=b:220071688 TEST=the rail steadily shows 0V in either S0, S3, and S5. Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com> Change-Id: I5256f6a2c0ca5a951dc79f564575b526a84463fd Reviewed-on: https://review.coreboot.org/c/coreboot/+/62253 Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* drivers/mrc_cache/mrc_cache.c: Change loglevelsUwe Poeche2022-02-231-1/+1
| | | | | | | | | | | | | | | | Since commit 7cd8ba6eda (console: Add loglevel prefix to interactive consoles) on the very first boot some errors occur because no MRC data is present in the MRC cache. This is normal because the memory training is not done yet. This patch changes the loglevel to BIOS_NOTICE which will prevent an error in the log in this case. Change-Id: I1e36590e33507515e5b9dd4eb361b3dbe165511e Signed-off-by: Uwe Poeche <uwe.poeche@siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/61973 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* Documentation/community/services: Fix typoFelix Singer2022-02-231-1/+1
| | | | | | | | | | Change-Id: I9d5171bd115d676775f560306e4e0a86214a39b0 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/62218 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
* console: Fix LOG_FAST macroMario Scheithauer2022-02-221-1/+1
| | | | | | | | | | | | | | | | | | | In the LOG_FAST macro, the comparison was incorrectly made with 'level' value. Correct is the comparison with 'speed'. With the wrong comparison you cannot set a lower level for console log, the highest level is always output. TEST: - Boot mc_ehl2 with console log level 5 and check output Change-Id: Ib5b4537ae2cbf01c51c3568d312b5242c4bee7bb Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/62261 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Patrick Georgi <patrick@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
* mb/gizmosphere/gizmo/OptionsIds.h: Remove extra empty lineElyes Haouas2022-02-221-1/+0
| | | | | | | | Change-Id: I8ad968da1771004f7f5869e5434473a498edeaa2 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/61912 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
* mb/lenovo/g505s/acpi/ec.asl: Correct the path to "mainboard.h"Elyes Haouas2022-02-221-1/+1
| | | | | | | | Change-Id: I273e29a26cf1c1ba34b95eb11bcb59a1360371e1 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/61921 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
* mb/lenovo/g505s: Format codeElyes Haouas2022-02-223-11/+8
| | | | | | | | Change-Id: I9cce00e1634d62a63b3563d54a7a0c56058d0e39 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/61920 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
* sb/amd/cimx/sb800/amd_pci_int_defs.h: Fix serial IRQ INT name in commentElyes Haouas2022-02-221-3/+3
| | | | | | | | Change-Id: If351d93c47de2ef76fb24525ff6d134b35c5f3fe Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/61876 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
* sb/amd/pi/hudson/early_setup.c: Fix typo in commentElyes Haouas2022-02-221-1/+1
| | | | | | | | Change-Id: Ib631cdc0794dc91df27cb984d5c585e0eee4a2ad Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/61877 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
* southbridge/amd/*/*/reset.c: Reduce stylistic differencesElyes Haouas2022-02-223-9/+9
| | | | | | | | Change-Id: I2f58098e786e9b61b0d059723c375a90559e95a6 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/61879 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
* southbridge/amd/*/*/smbus.c: Reformat code and reduce differenceElyes Haouas2022-02-223-39/+38
| | | | | | | | | Change-Id: I43644b757a5a85864162da6a35f7f2a5335f8007 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/61880 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
* mb/gizmosphere/gizmo/acpi/gpe.asl: Remove extra blank lineElyes Haouas2022-02-221-1/+0
| | | | | | | | Change-Id: I0d9b07183b06915799f221390406e930ca253a0d Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/61911 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
* mb/gizmosphere/gizmo/devicetree.cb: Fix typo on 'pci'Elyes Haouas2022-02-221-2/+2
| | | | | | | | | | While on it, use tab for indent. Change-Id: I6cb0b4183db819d721f4882ab2168d22bcd664e3 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/61913 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
* sb/intel/i82371eb: Constify pci_devfn_t devicesElyes Haouas2022-02-223-6/+3
| | | | | | | | Change-Id: I9056464b36cde89d2fe88ff27531e467297bed0b Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/61986 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
* sb/intel/ibexpeak: Constify struct southbridge_intel_ibexpeak_configElyes Haouas2022-02-222-11/+7
| | | | | | | | Change-Id: I096ccd0ec224b98038d290422f568666bbede43a Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/61985 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
* src/Kconfig: Update the path to 'c_start.S' for GDB_STUB configElyes Haouas2022-02-221-1/+1
| | | | | | | | Change-Id: Ib31defde0d4983a9418f05e0b812a7bbbe4fe2b7 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/62057 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
* mb/starlabs/labtop: Reconfigure GPIOsSean Rhodes2022-02-221-13/+13
| | | | | | | | | | | | Reconfigure the GPIO's so that they are configured correctly. The original configuration was based on the AMI firmware, and whilst it worked, it wasn't optimal. Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: I27ecf066685f2a81ac884a9f276c518544449443 Reviewed-on: https://review.coreboot.org/c/coreboot/+/60759 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
* mb/starlabs/labtop: Reconfigure CNVi GPIOsSean Rhodes2022-02-221-3/+3
| | | | | | | | | | | | Reconfigure the CNVi GPIO's so that they are configured correctly. The original configuration was based on the AMI firmware, and whilst it worked, it wasn't optimal. Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: I9fc9963e91da0267c8740fee20a3ec41895b4953 Reviewed-on: https://review.coreboot.org/c/coreboot/+/60758 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
* mb/starlabs/labtop: Update trackpad GPIO configurationSean Rhodes2022-02-221-1/+1
| | | | | | | | | | | Update trackpad GPIO to avoid IRQ Storm, that causes high power consumption when idling or in S3. Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: Ieee27bd9079617ab95f4f1e27ef98b49e89e5b41 Reviewed-on: https://review.coreboot.org/c/coreboot/+/60757 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
* mb/starlabs/labtop: Configure TPM_IRQ GPIO for TGLSean Rhodes2022-02-221-1/+1
| | | | | | | | | | | | Configure the TPM IRQ GPIO for TGL (StarBook Mk V) so that the hardware TPM can be used. Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: Ife88075e70184b46e69f2e24c70b85ec254edd64 Reviewed-on: https://review.coreboot.org/c/coreboot/+/60756 Reviewed-by: Andy Pont <andy.pont@sdcsystems.com> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* mb/starlabs/labtop: Don't configure ESPI GPIOsSean Rhodes2022-02-221-7/+0
| | | | | | | | | | Don't configure ESPI GPIOs as the default values are correct. Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: I052fbfccd075d19340d3e27ad0c62965c80badaf Reviewed-on: https://review.coreboot.org/c/coreboot/+/60755 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth - Personal <martinroth@google.com>
* soc/intel/common/block/acpi: Drop duplicated 'fadt->header.revision'Elyes Haouas2022-02-221-2/+0
| | | | | | | | | | The 'fadt->header.revision' is already done at src/acpi/acpi.c acpi_create_fadt(). Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Change-Id: Ib9b6dc7e86ca17e0b2d374ee2c3bdf06f8b82dfc Reviewed-on: https://review.coreboot.org/c/coreboot/+/62222 Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* payloads/tianocore: Rework MakefileSean Rhodes2022-02-224-101/+118
| | | | | | | | | | | | | | | | | | | Rework edkii makefile so that the various build options are unified between CorebootPayloadPkg, uefipayload_202107 and upstream. This sets the project directory based on the git repository name i.e. https://github.com/mrchromebox/edk2 becomes mrchomebox Also builds to $(obj)/UEFIPAYLOAD.fd and allows using a commit ID without a branch. Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: I3cc274e7385dd71c2aae315162cc48444b7eaa5f Reviewed-on: https://review.coreboot.org/c/coreboot/+/61620 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-by: Martin Roth - Personal <martinroth@google.com>
* vendorcode/intel/fsp: Update FSP header file for Alder Lake N FSP v3054.02Ronak Kanabar2022-02-221-3/+3
| | | | | | | | | | | | | | | | | | The headers added are generated as per FSP v3054.02. Previous FSP version was v2503_00. Changes Include: - UPD Offset Update in FspmUpd.h BUG=b:220076892 BRANCH=None TEST=Build and boot adlnrvp Change-Id: I7b921e2aa467597a1c764fc554e2e83e5bb522e8 Signed-off-by: Ronak Kanabar <ronak.kanabar@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/62129 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com> Reviewed-by: Kangheui Won <khwon@chromium.org>
* soc/amd/sabrina/i2c: remove TODOFelix Held2022-02-222-4/+0
| | | | | | | | | | | | | | The SoC-specific I2C code and header file have been verified some time ago, but it seems that I forgot to remove the corresponding TODOs. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ifd162bda10e5993bc32db3a77588491397e3c19e Reviewed-on: https://review.coreboot.org/c/coreboot/+/62223 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com> Reviewed-by: Jason Glenesk <jason.glenesk@gmail.com> Reviewed-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-by: Raul Rangel <rrangel@chromium.org>
* treewide: Get rid of CONFIG_AZALIA_MAX_CODECSElyes Haouas2022-02-2210-38/+5
| | | | | | | | | | | | | Get rid of Kconfig symbol introduced at commit 5d31dfa8 High Definition Audio Specification Revision 1.0a says, there are 15 SDIWAKE bits. Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Change-Id: Ib8b656daca52e21cb0c7120b208a2acdd88625e1 Reviewed-on: https://review.coreboot.org/c/coreboot/+/62202 Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* src/driver/intel/mipi_camera: Update ACPI entry to provide silicon infoVarshit B Pandya2022-02-221-1/+2
| | | | | | | | | | | | CPUID_ALDERLAKE_N_A0 is ES. Add it to generate is_es = 1 in ACPI Signed-off-by: Varshit B Pandya <varshit.b.pandya@intel.com> Change-Id: Icc65c52a9dadebe4ebab3d0c30599eb0db38bc3e Reviewed-on: https://review.coreboot.org/c/coreboot/+/61862 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Reka Norman <rekanorman@chromium.org> Reviewed-by: Kangheui Won <khwon@chromium.org>
* soc/amd/common/block/lpc/espi_util: use __fallthroughFelix Held2022-02-221-5/+5
| | | | | | | | | | | | | | Using __fallthrough instead of a comment about the fall-through being intentional should make clang stop complaining about intended fall- through statements. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I940529be02e20c72f6e97b2cfa10f0dd8f7020b6 Reviewed-on: https://review.coreboot.org/c/coreboot/+/62216 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com> Reviewed-by: Jason Glenesk <jason.glenesk@gmail.com>
generated by cgit v1.2.3 (git 2.25.1) at 2024-09-29 13:45:24 +0000