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* Revert "util/cbfstool: Port elogtool to libflashrom"4.164.16_branchMartin Roth2022-02-264-254/+11
| | | | | | | | | | | | | | | | | | | | This reverts commit d74b8d9c990780ba64515b36aaff79d719d71ead. This change breaks the 'make all' build of the cbfstool tools from the util/cbfstool directory unless libflashrom-dev is installed, complaining that flashrom is not installed. Even with libflashrom-dev installed, it breaks building elogtool with the public version of libflashrom-dev. Signed-off-by: Martin Roth <martin@coreboot.org> Change-Id: I572daa0c0f3998e20a8ed76df21228fdbb384baf Reviewed-on: https://review.coreboot.org/c/coreboot/+/62404 Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: ron minnich <rminnich@gmail.com> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-by: Felix Singer <felixsinger@posteo.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* mb/google/skyrim: Enable USB controllers in devicetreeJon Murphy2022-02-261-0/+4
| | | | | | | | | | | BUG=b:214413631 TEST=builds Signed-off-by: Jon Murphy <jpmurphy@google.com> Change-Id: I9ca2c16d97e064b32400356e1de37f3f70155a07 Reviewed-on: https://review.coreboot.org/c/coreboot/+/62152 Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* mb/google/skyrim: Enable internal graphicsJon Murphy2022-02-261-0/+3
| | | | | | | | | | | | BUG=b:214416935 TEST=builds Signed-off-by: Jon Murphy <jpmurphy@google.com> Change-Id: Icc71b114bf9d8f70ae38a876eedc9d1c3c02169c Reviewed-on: https://review.coreboot.org/c/coreboot/+/62151 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Raul Rangel <rrangel@chromium.org>
* mb/google/skyrim: Enable console UARTJon Murphy2022-02-262-0/+2
| | | | | | | | | | | | BUG=b:214414501 TEST=builds Signed-off-by: Jon Murphy <jpmurphy@google.com> Change-Id: I053909ab73c1aa053f35a505b37571ff23adde89 Reviewed-on: https://review.coreboot.org/c/coreboot/+/62147 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
* mb/google/skyrim: Set up FW_CONFIGJon Murphy2022-02-262-0/+5
| | | | | | | | | | | | BUG=b:214415048 TEST=builds BRANCH=none Signed-off-by: Jon Murphy <jpmurphy@google.com> Change-Id: Ida8d226f84726f2eb03b07618907b0ce3928bec5 Reviewed-on: https://review.coreboot.org/c/coreboot/+/62146 Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* mb/google/skyrim: Enable eSPI SCI eventsJon Murphy2022-02-261-0/+15
| | | | | | | | | | | | | | Enable ESPI SCI events BUG=b:214416630 TEST=builds Signed-off-by: Jon Murphy <jpmurphy@google.com> Change-Id: If47ba561f140eb474cad30e24b0a7c85cdd76203 Reviewed-on: https://review.coreboot.org/c/coreboot/+/62149 Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* mb/google/skyrim: Add smihandlerJon Murphy2022-02-264-0/+42
| | | | | | | | | | | | | BUG=b:214415408 TEST=builds BRANCH=none Signed-off-by: Jon Murphy <jpmurphy@google.com> Change-Id: Icc52182294bb3402463a0a70a5c67779c60dfe32 Reviewed-on: https://review.coreboot.org/c/coreboot/+/62045 Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* mb/google/skyrim: Enable Chrome ECJon Murphy2022-02-268-2/+128
| | | | | | | | | | | | BUG=b:214413613 TEST=builds BRANCH=none Signed-off-by: Jon Murphy <jpmurphy@google.com> Change-Id: I15c7c482c4a5ddef22a221794b9ef03f9b7ffe05 Reviewed-on: https://review.coreboot.org/c/coreboot/+/62046 Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* mb/google/skyrim: Enable variants for SkyrimJon Murphy2022-02-265-1/+20
| | | | | | | | | | | | | BUG=b:214414033 TEST=builds BRANCH=none Signed-off-by: Jon Murphy <jpmurphy@google.com> Change-Id: I034ab8a06842bee12060103b4a1bc4e3db69e42a Reviewed-on: https://review.coreboot.org/c/coreboot/+/62145 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
* mb/google/skyrim: CONFIG_CHROMEOSJon Murphy2022-02-263-0/+19
| | | | | | | | | | | | BUG=b:214415401 TEST=builds BRANCH=none Signed-off-by: Jon Murphy <jpmurphy@google.com> Change-Id: I045f76c366a1a72814536a2be984b7ad5a438a5a Reviewed-on: https://review.coreboot.org/c/coreboot/+/62043 Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* mb/google/skyrim: Enable ACPI tablesJon Murphy2022-02-262-0/+19
| | | | | | | | | | | | | | | Add GPIO initialization and ACPI generation for tables BUG=b:214415303 TEST=builds BRANCH=none Signed-off-by: Jon Murphy <jpmurphy@google.com> Change-Id: I8f9c7d3f2fdbd5d791032637dbf97c18864ee9e7 Reviewed-on: https://review.coreboot.org/c/coreboot/+/62044 Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* soc/intel/fast_spi: Check SPI Cycle In-Progress prior start HW SeqSubrata Banik2022-02-261-0/+23
| | | | | | | | | | | | | | | | | | | | | | | | | | This fixes no practical problem, especially for coreboot where only one process should access the SPI controller. It makes the code look more spec compliant. As per EDS, SPI controller sets the HSFSTS.bit5 (SCIP) when software sets the Flash Cycle Go (FGO) bit in the Hardware Sequencing Flash Control register. Software must initiate the next SPI transaction when this bit is 0. Add non-blocking mechanism with `5sec` timeout to report back error if current SPI transaction is failing due to on-going SPI access. BUG=b:215255210 TEST=Able to boot brya and verified SPI read/write is successful. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: I4d35058244a73e77f6204c4d04d09bae9e5ac62c Reviewed-on: https://review.coreboot.org/c/coreboot/+/61849 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-by: Edward O'Callaghan <quasisec@chromium.org> Reviewed-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
* soc/amd/common/psp_verstage: Add missing post codes on S0i3 resumeRaul E Rangel2022-02-261-0/+4
| | | | | | | | | | | | | | | | We print these out in the normal flow, so lets add them for S0i3 resume as well. BUG=b:221231786 TEST=Perform suspend/resume cycle on guybrush and verify we get the new POST codes. Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: Ia7d607453d58084868cfa50770fd0f370b2ea2bd Reviewed-on: https://review.coreboot.org/c/coreboot/+/62346 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Rob Barnes <robbarnes@google.com> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
* soc/amd/{common/psp_verstage,soc/picasso}: Remove workbuf shrinkingRaul E Rangel2022-02-263-56/+11
| | | | | | | | | | | | | | This feature was never used. Let's remove it to keep things simple. BUG=221231786 TEST=Boot test guybrush and morphius and verify transfer buffer is correctly passed. Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: I93a284db919f82763dcd31cec76af4b773eb3f80 Reviewed-on: https://review.coreboot.org/c/coreboot/+/62345 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Rob Barnes <robbarnes@google.com>
* Docs/releases: Final update for 4.16 release notes before the releaseMartin Roth2022-02-251-80/+130
| | | | | | | | | | | | | | - Remove arrows from google mainboard as requested in the last review. - Make Feb25 the release date. - Cosmetic markdown changes - Rewrapping, updated for lines' lengths. - Add plan to support Resource allocator V3 on the 4.18 branch. - Add plan to deprecate LEGACY_SMP_INIT after 4.18 release Signed-off-by: Martin Roth <martin@coreboot.org> Change-Id: Id16925918511fd2277a54faeccfa56e96c6aaae5 Reviewed-on: https://review.coreboot.org/c/coreboot/+/62380 Reviewed-by: Felix Singer <felixsinger@posteo.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* mb/google/brask: Update PCH power cycle related durationsZhuohao Lee2022-02-251-0/+6
| | | | | | | | | | | | | | | | | | The power rails discharge time of brask has been measured, the longest discharge time of the power rails are smaller than 150ms so it is safe to set the pwr_cyc_dur to 1 second. Since the brask is derived from the brya, we could apply the same setting from the brya. The setting is copied from commit dee834aa. BUG=b:214454454 BRANCH=firmware-brya-14505.B TEST=`test_that firmware_ECPowerButton` passed. Change-Id: I5e5eebb79e99a52fc3e4128213c6986f20100b8d Signed-off-by: Zhuohao Lee <zhuohao@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/62286 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
* mb, soc: change mainboard_memory_init_params prototypeZhuohao Lee2022-02-256-7/+11
| | | | | | | | | | | | | | | | | | The mainboard_memory_init_params takes the struct FSP_M_CONFIG as the input which make the board has no chance to modify data in the FSPM_UPD, for example, set FspmArchUpd.NvsBufferPtr = 0. After changing the FSP_M_CONFIG to FSPM_UPD, the board can modify the value based on its requirement. BUG=b:200243989 BRANCH=firmware-brya-14505.B TEST=build pass Change-Id: Id552b1f4662f5300f19a3fa2c1f43084ba846706 Signed-off-by: Zhuohao Lee <zhuohao@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/62293 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
* payloads/tianocore: Convert BMP at build timeSean Rhodes2022-02-251-4/+4
| | | | | | | | | | | Convert BMP to the correct format at build time, which removes the requirement for any runtime checks. Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: I4f1e9c8df2ca7d66f362f9fa5688d6cb443c2581 Reviewed-on: https://review.coreboot.org/c/coreboot/+/61918 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
* payloads/tianocore: Pass SD_MMC_TIMEOUT build optionSean Rhodes2022-02-253-0/+12
| | | | | | | | | | | | | | | By default, edk2 allows 1000000μs for SD Card Readers and eMMC to initialize which is excessive and causes a boot delay. This makes the value configurable and uses a default of 1000μs which is sufficient for the majority of readers. The value of 1000μs was hardcoded in MrChromeBox's fork for around 2 years with no reported issues. Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: I873bcddf6f37a9eaae5c84991b3996d51fb460d3 Reviewed-on: https://review.coreboot.org/c/coreboot/+/61902 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
* mb/intel/adlrvp: Add support for MAX98373 codecUsha P2022-02-253-2/+48
| | | | | | | | | | | | | | | | | | - Add configurability using FW_CONFIG field in CBI, to enable/disable I2S codec support for MAX98373 codecs - AUDIO=ADL_MAX98373_ALC5682I_I2S: enable max98373 codec using expansion board Bug=None Test=With CBI FW_CONFIG set to 0x100, check I2S audio output on expansion card Signed-off-by: Usha P <usha.p@intel.com> Change-Id: I94dfe500b99a669e9b981cdf15e360f22f33d2ac Reviewed-on: https://review.coreboot.org/c/coreboot/+/61544 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kangheui Won <khwon@chromium.org> Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
* sb/intel/ibexpeak/early_pch.c: Use PCI_BASE_ADDRESS_0 macroElyes Haouas2022-02-251-1/+2
| | | | | | | | | Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Change-Id: If74e1db623d65d639041d49caf0ca1b6c0e1f2ad Reviewed-on: https://review.coreboot.org/c/coreboot/+/62326 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
* nb/intel/ironlake: Fix sending HECI messagesArthur Heymans2022-02-251-9/+14
| | | | | | | | | | | | | This code only worked when the payload (a packed struct) was 4 byte aligned. With gcc11 this happens to not be the case. Change-Id: I5bb4ca4b27f8554208b12da177c51091ea6a108f Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/61938 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
* intelblocks/pcie: Correct mapping between LCAP port and coreboot indexMAULIK V VAGHELA2022-02-258-34/+51
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | coreboot uses port index which is 0 based for all PCIe root ports. In case of PCIe remapping logic, coreboot reads LCAP register from PCIe configuration space which contains port number (mostly 1 based). This assumption might not be true for all the ports in coreboot. TBT's LCAP registers are returning port index which are based on 2. coreboot's PCIe remapping logic returns port index based on index 1. This patch adds variable to pcie_rp_config to pass lcap_port_base to the pcie remapping function, so coreboot can map any n-based LCAP encoding to 0-based indexing scheme. This patch updates correct lcap_port_base variable for all PCIe root ports for all SOCs, so that function returns correct 0-based index from LCAP port number. BUG=b:210933428 BRANCH=None TEST=Check if code compiles for all ADL boards Change-Id: I7f9c3c8e753b982e2ede1a41bf87d6355b82da0f Signed-off-by: MAULIK V VAGHELA <maulik.v.vaghela@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/61936 Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com> Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* Documentation/security/vboot: Update 4.16 vboot supported boardsJason Glenesk2022-02-251-11/+41
| | | | | | | | | | Update list of boards that support vboot. Change-Id: I7f372c5b923018bc1b744fd02d5acc976b03742a Signed-off-by: Jason Glenesk <jason.glenesk@amd.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/62310 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
* Documentation/releases: Update index.mdJason Glenesk2022-02-251-1/+2
| | | | | | | | Change-Id: I71e1fc40b3cdc1844e8d8daf00f133169b7c4a3b Signed-off-by: Jason Glenesk <jason.glenesk@amd.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/62309 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
* Documentation/releases: Update 4.16 release notesJason Glenesk2022-02-251-9/+272
| | | | | | | | | | | Update details for upcoming 4.16 release Change-Id: Iea88b3a4025ae6a57524e08bf5ecef984810baeb Signed-off-by: Jason Glenesk <jason.glenesk@amd.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/62302 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
* cpu,mb,nb,soc: use HPET_BASE_ADDRESS instead of magic numberFelix Held2022-02-258-9/+18
| | | | | | | | | Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I570f7de90007b67d811d158ca33e099d5cc2d5d3 Reviewed-on: https://review.coreboot.org/c/coreboot/+/62308 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* arch/x86: consolidate HPET base address definitionsFelix Held2022-02-2530-71/+81
| | | | | | | | | | | | | | | | | | Both the HPET_BASE_ADDRESS define from arch/x86/include/arch/hpet.h and the HPET_ADDRESS Kconfig option define the base address of the HPET MMIO region which is 0xfed00000 on all chipsets and SoCs in the coreboot tree. Since these two different constants are used in different places that however might end up used in the same coreboot build, drop the Kconfig option and use the definition from arch/x86 instead. Since it's no longer needed to check for a mismatch of those two constants, the corresponding checks are dropped too. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ia797bb8ac150ae75807cb3bd1f9db5b25dfca35e Reviewed-on: https://review.coreboot.org/c/coreboot/+/62307 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Lance Zhao Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* soc/intel/denverton/include/iomap: drop unused DEFAULT_HPET_ADDR defineFelix Held2022-02-251-1/+0
| | | | | | | | | Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ie92bd54b072d545944b3d0251e9727ce493bb864 Reviewed-on: https://review.coreboot.org/c/coreboot/+/62306 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
* sb/intel/common/hpet: use HPET_BASE_ADDRESS definitionFelix Held2022-02-251-2/+2
| | | | | | | | | | | Use the definition from arch/x86 instead of a local redefinition. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: If172cde267062a8e759a9670ac93f4e74e8c94d5 Reviewed-on: https://review.coreboot.org/c/coreboot/+/62305 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
* arch/x86: factor out and commonize HPET_BASE_ADDRESS definitionFelix Held2022-02-2529-33/+23
| | | | | | | | | | | | | | | | All x86 chipsets and SoCs have the HPET MMIO base address at 0xfed00000, so define this once in arch/x86 and include this wherever needed. The old AMD AGESA code in vendorcode that has its own definition is left unchanged, but sb/amd/cimx/sb800/cfg.c is changed to use the new common definition. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ifc624051cc6c0f125fa154e826cfbeaf41b4de83 Reviewed-on: https://review.coreboot.org/c/coreboot/+/62304 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
* soc/intel/baytrail,braswell/include/iomap: drop unused HPET_BASE_SIZEFelix Held2022-02-252-2/+0
| | | | | | | | | | Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I875916488a99af768d087691549a93f6fd5169ea Reviewed-on: https://review.coreboot.org/c/coreboot/+/62303 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
* arch/x86/Kconfig: add HPET_MIN_TICKSFelix Held2022-02-257-6/+3
| | | | | | | | | | | | | | | | Some Intel southbridges have HPET_MIN_TICKS in their Kconfig files, but the CONFIG_HPET_MIN_TICKS symbol is used in the common acpi code in acpi/acpi.c, so define this option in arch/x86/Kconfig to have it defined in all cases where the function that ends up using this information gets called. Since we now have the type information for this Kconfig option in a central place, it can be dropped from the Kconfig file of the Intel southbridges that change the default value. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ibe012069dd4b51c15a8fbc6459186ad2ea405a03 Reviewed-on: https://review.coreboot.org/c/coreboot/+/62298 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* acpi/acpi: use read32p instead of pointer dereferencingFelix Held2022-02-251-1/+2
| | | | | | | | | | | | | Using read32p to get the contents of the first 4 bytes of the HPET MMIO region instead of a pointer dereference should clarify what's done in that piece of code. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Iecf5452c63635666d7d6b17e07a1bc6aa52e72fa Reviewed-on: https://review.coreboot.org/c/coreboot/+/62297 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Lance Zhao Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* mb/google/guybrush: enable coreboot to request spl fuseJason Glenesk2022-02-251-0/+1
| | | | | | | | | | | | | | | | | | | | Enable guybrush based platforms to send fuse spl command to PSP when required. BUG=b:180701885 TEST=On a platform that supports SPL fusing. Confirm that PSP indicates fusing is required, and confirm coreboot sends command. Fusing is required when the image is built with an SPL table requiring newer minimum versions. A message indicating fusing was requested will appear in the serial log. "PSP: Fuse SPL requested" Change-Id: I7bce01513af4e613f546e491d9577c92f50cb85c Signed-off-by: Jason Glenesk <jason.glenesk@amd.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/62354 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Jon Murphy <jpmurphy@google.com>
* mb/google/volteer/var/collis: update default codec HID to 10EC5682FrankChu2022-02-251-3/+3
| | | | | | | | | | | | | | | Modify function to set default audio codec HID to be original setting 10EC5682. BUG=b:192535692 BRANCH=volteer TEST=ALC5682-VD/ALC5682I-VS audio codec can work Signed-off-by: Frank Chu <frank_chu@pegatron.corp-partner.google.com> Change-Id: I30fa886a39bd7082442a3a2b95fdf2d2b84ddd1c Reviewed-on: https://review.coreboot.org/c/coreboot/+/62024 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
* Documentation/index.md: Add "Contributing" menu entryFelix Singer2022-02-252-4/+7
| | | | | | | | | | | | Clean up the main menu by adding a new entry `Contributing` and moving all related menu entries below it. Change-Id: I04ec8a568b716df48ae7f8f826826e8753f5f88b Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/62220 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
* Documentation/index.md: Add "Community" menu entryFelix Singer2022-02-252-5/+8
| | | | | | | | | | | | | Clean up the main menu by adding a new entry `Community` and moving all related menu entries below it. Change-Id: Ib5df0156edaa739f15e6da8489968448876e1894 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/62219 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
* herobrine: Add Villager variantShelley Chen2022-02-252-1/+5
| | | | | | | | | | | | BUG=b:218415722 BRANCH=None TEST=./util/abuild/abuild -p none -t GOOGLE_VILLAGER -x -a -B Change-Id: I84935ea280023cb0df1dd51fcd2a83d80db17710 Signed-off-by: Shelley Chen <shchen@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/62356 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
* mb/google/skyrim: First pass GPIO configuriation for SkyrimJon Murphy2022-02-251-1/+133
| | | | | | | | | | | | | BUG=b:214415401 TEST=builds BRANCH=none Signed-off-by: Jon Murphy <jpmurphy@google.com> Change-Id: I60b3b3cd50eea1253df2ae3e0aea83bb89e54702 Reviewed-on: https://review.coreboot.org/c/coreboot/+/62042 Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* mb/amd/chausie/devicetree: add i2c_scl_resetFelix Held2022-02-251-0/+3
| | | | | | | | | Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I23ec6bcb6a2b3627866165972fd6ba1c75367533 Reviewed-on: https://review.coreboot.org/c/coreboot/+/62188 Reviewed-by: Jason Glenesk <jason.glenesk@gmail.com> Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* mb/amd/chausie/devicetree: enable I2C controllersFelix Held2022-02-251-0/+4
| | | | | | | | | | Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I97f37c45ffe945e6bb071c8205343943edc524ac Reviewed-on: https://review.coreboot.org/c/coreboot/+/61871 Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com> Reviewed-by: Jason Glenesk <jason.glenesk@gmail.com> Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* crossgcc: Upgrade LLVM/clang from 12.0.0 to 13.0.1Elyes HAOUAS2022-02-259-5/+5
| | | | | | | | | | Build/run not tested on board. Change-Id: I8c550d3528a5b1c891b318c08ecfba3a9255e69c Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/59400 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* mb/google/brya/var/taeko: Add GL9750 SD card reader supportKevin Chang2022-02-241-0/+2
| | | | | | | | | | | | | Add GL9750 SD card reader support. BUG=b:220987566 TEST=Build FW and check device function normally. Signed-off-by: Kevin Chang <kevin.chang@lcfc.corp-partner.google.com> Change-Id: I8f6ca45a320d34dfd820ef0b6e0d3163fab26027 Reviewed-on: https://review.coreboot.org/c/coreboot/+/62285 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
* mb/google/skyrim: Add stubs to configure GPIOsJon Murphy2022-02-246-1/+84
| | | | | | | | | | | | | BUG=b:214415401 TEST=builds BRANCH=none Signed-off-by: Jon Murphy <jpmurphy@google.com> Change-Id: Ieeda9aa0c18b5befea67d2849bd4114da0c348a3 Reviewed-on: https://review.coreboot.org/c/coreboot/+/62041 Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* soc/apollolake: Allow configuring individual USB ports on GLKSean Rhodes2022-02-241-0/+18
| | | | | | | | | | Allow configuring the limited fields that FSP-S provides. Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: I56c37338eaa978fdb2c63807331493e8aecbdf60 Reviewed-on: https://review.coreboot.org/c/coreboot/+/62056 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
* treewide: Write minor version at acpi_create_fadt() functionElyes Haouas2022-02-246-5/+1
| | | | | | | | | | | | When "fadt->FADT_MinorVersion" is not explicitly set to the right value, gcc sets it up to "0". So set it correctly for treewide. Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Change-Id: Ic9a8e097f78622cd78ba432e3b1141b142485b9a Reviewed-on: https://review.coreboot.org/c/coreboot/+/62221 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jason Glenesk <jason.glenesk@gmail.com> Reviewed-by: Lance Zhao
* mb/google/brya: Add SPD configs for CrotaTerry Chen2022-02-243-2/+21
| | | | | | | | | | | | | | | | | | | | | | | Add a mem_parts_used.txt for Crota, containing the memory parts used in proto builds. Generate Makefile.inc and dram_id.generated.txt using part_id_gen. DRAM Part Name ID to assign MT62F1G32D4DR-031 WT:B 0 (0000) MT62F512M32D2DR-031 WT:B 1 (0001) H9JCNNNBK3MLYR-N6E 1 (0001) H9JCNNNCP3MLYR-N6E 0 (0000) K3LKBKB0BM-MGCP 2 (0010) BUG=b:215443524 TEST=emerge-brya coreboot Change-Id: I0ff6ffea4b879b6e1287e1e3cb9fd36a80f52ed6 Signed-off-by: Terry Chen <terry_chen@wistron.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/62262 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
* nb/intel/ironlake: Clean up `jedec_read()` functionAngel Pons2022-02-241-9/+4
| | | | | | | | | | | | Deduplicate a condition and reflow some lines. Tested on HP ProBook 6550b, still reaches TianoCore payload. Change-Id: If5786f34585e15100385d452b5b03a36da4c7c87 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/61939 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
* nb/intel/ironlake: Fix some quickpath init magicAngel Pons2022-02-243-7/+23
| | | | | | | | | | | | | | | | | | | Correct some Quickpath initialisation steps according to findings from two different Intel reference code binaries as well as MCHBAR register dump comparisons between vendor firmware and coreboot. The MSR_TURBO_POWER_CURRENT_LIMIT information comes from EDK2 sources. Tested on Apple iMac 10,1 (Clarkdale, aka desktop Ironlake), QPI init now completes successfully instead of causing hangs before raminit. Also tested on HP ProBook 6550b (Arrandale, aka mobile Ironlake), still reaches payload (e.g. TianoCore). Change-Id: Icd0139aa588dc8d948c03132b5c86866d90f3231 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60216 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
generated by cgit v1.2.3 (git 2.25.1) at 2024-04-30 02:32:17 +0000