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* util/crossgcc: Use GitHub for downloading IASL4.18_branchFelix Singer2023-01-174-4/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | The download links from acpica.org [1] are not stable, and for some reason they named the release tarballs with .tar_0.gz. Thus, use the tarballs from their GitHub repository generated out of the release tags [2]. Tested locally and also IASL patch applies. [1] https://www.acpica.org/downloads [2] https://github.com/acpica/acpica/tags Original-signed-off-by: Felix Singer <felixsinger@posteo.net> Original-reviewed-on: https://review.coreboot.org/c/coreboot/+/70021 Original-reviewed-by: Angel Pons <th3fanbus@gmail.com> Original-reviewed-by: Elyes Haouas <ehaouas@noos.fr> Original-reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Original-tested-by: build bot (Jenkins) <no-reply@coreboot.org> Cherry-picked-from: 60a422736bde766489db8ff0dc2d56ab333c37cc Change-Id: I7b10dd1db4299aaef96bc29023bed874b660aba0 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/70857 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
* crossgcc: Upgrade IASL from 20220331 to 20221020Elyes Haouas2023-01-174-2/+2
| | | | | | | | | | | | | | | | Changes: https://acpica.org/node/201 Original-signed-off-by: Elyes Haouas <ehaouas@noos.fr> Original-reviewed-on: https://review.coreboot.org/c/coreboot/+/68929 Original-tested-by: build bot (Jenkins) <no-reply@coreboot.org> Original-reviewed-by: Felix Singer <felixsinger@posteo.net> Cherry-picked-from: a45ed44724a30303030e80898202b77c34498942 Change-Id: I386a6757a318336bc616091afe0c4ed88cd89583 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/70856 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
* Makefile.inc: Remove workaround ACPI warningsArthur Heymans2023-01-1214-56/+0
| | | | | | | | | | | | | | | | | | No boards now have a missing dependency so remove the workaround. Original-signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Original-reviewed-on: https://review.coreboot.org/c/coreboot/+/69514 Original-reviewed-by: Nico Huber <nico.h@gmx.de> Original-tested-by: build bot (Jenkins) <no-reply@coreboot.org> Original-reviewed-by: Elyes Haouas <ehaouas@noos.fr> Original-reviewed-by: Felix Held <felix-coreboot@felixheld.de> Cherry-picked-from: 457f77be37e73e6a06f7cc0c16f14bc462b682f9 Change-Id: I787f6aa588175ba620a068918c42edc9d257c3ef Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/70902 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
* {ec/superio}/acpi: Remove _PRS if no _SRS is implementedArthur Heymans2023-01-126-161/+0
| | | | | | | | | | | | | | | | | _PRS only makes sense if _SRS is implemented. Original-signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Original-reviewed-on: https://review.coreboot.org/c/coreboot/+/69513 Original-reviewed-by: Elyes Haouas <ehaouas@noos.fr> Original-tested-by: build bot (Jenkins) <no-reply@coreboot.org> Original-reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com> Cherry-picked-from: 87d4f114a24d713c7ce965a52b83974f7b089557 Change-Id: I030bd716215b5ac5738e00ebf6ed991d9d6c5ca0 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/70901 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
* superio/acpi/pnp_generic.asl: Add _PRS for each deviceArthur Heymans2023-01-121-0/+8
| | | | | | | | | | | | | | | | | | | | | | | Simply return the current resource settings in the _PRS method. This means that coreboot has to correctly set up the resources on the device. This won't result in any regression as without _PRS the ACPI OS would not know what resources settings are valid, so it would never use _SRS. Original-signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Original-reviewed-on: https://review.coreboot.org/c/coreboot/+/64218 Original-reviewed-by: Nico Huber <nico.h@gmx.de> Original-reviewed-by: Elyes Haouas <ehaouas@noos.fr> Original-tested-by: build bot (Jenkins) <no-reply@coreboot.org> Original-reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com> Cherry-picked-from: 148fd99365bb923cd7af37afcd93efdd781fd819 Change-Id: I2726714cbe076fc7c772c06883d8551400ff2baa Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/70903 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
* Makefile.inc: Decrease minimal pagesize from 4 kB to 1 kBPaul Menzel2022-12-091-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | commit ac23f9da757e8e47a6bdcfd619c54e9b4c2b906c upstream. GCC 12 incorrectly warns about an array out of bounds issue: ``` $ make V=1 # emulation/qemu-i440fx […] CC ramstage/arch/x86/ebda.o x86_64-linux-gnu-gcc-12 -MMD -Isrc -Isrc/include -Isrc/commonlib/include -Isrc/commonlib/bsd/include -Ibuild -I3rdparty/vboot/firmware/include -include src/include/kconfig.h -include src/include/rules.h -include src/commonlib/bsd/include/commonlib/bsd/compiler.h -I3rdparty -D__BUILD_DIR__=\"build\" -Isrc/arch/x86/include -D__ARCH_x86_32__ -pipe -g -nostdinc -std=gnu11 -nostdlib -Wall -Wundef -Wstrict-prototypes -Wmissing-prototypes -Wwrite-strings -Wredundant-decls -Wno-trigraphs -Wimplicit-fallthrough -Wshadow -Wdate-time -Wtype-limits -Wvla -Wdangling-else -fno-common -ffreestanding -fno-builtin -fomit-frame-pointer -fstrict-aliasing -ffunction-sections -fdata-sections -fno-pie -Wno-packed-not-aligned -fconserve-stack -Wnull-dereference -Wreturn-type -Wlogical-op -Wduplicated-cond -Wno-unused-but-set-variable -Werror -Os -Wno-address-of-packed-member -m32 -Wl,-b,elf32-i386 -Wl,-melf_i386 -m32 -fuse-ld=bfd -fno-stack-protector -Wl,--build-id=none -fno-delete-null-pointer-checks -Wlogical-op -march=i686 -mno-mmx -MT build/ramstage/arch/x86/ebda.o -D__RAMSTAGE__ -c -o build/ramstage/arch/x86/ebda.o src/arch/x86/ebda.c In file included from src/arch/x86/ebda.c:6: In function 'write_ble8', inlined from 'write_le8' at src/commonlib/include/commonlib/endian.h:155:2, inlined from 'write_le16' at src/commonlib/include/commonlib/endian.h:178:2, inlined from 'setup_ebda' at src/arch/x86/ebda.c:35:2, inlined from 'setup_default_ebda' at src/arch/x86/ebda.c:48:2: src/commonlib/include/commonlib/endian.h:27:26: error: array subscript 0 is outside array bounds of 'void[0]' [-Werror=array-bounds] 27 | *(uint8_t *)dest = val; | ~~~~~~~~~~~~~~~~~^~~~~ […] ``` [In GCC 12 the new parameter `min-pagesize` is added and defaults 4 kB.][1] It treats INTEGER_CST addresses smaller than that as assumed results of pointer arithmetics from NULL while addresses equal or larger than that as expected user constant addresses. For GCC 13 we can represent results from pointer arithmetics on NULL using &MEM[(void*)0 + offset] instead of (void*)offset INTEGER_CSTs. [1]: https://web.archive.org/web/20220711061810/https://gcc.gnu.org/bugzilla/show_bug.cgi?id=99578 TEST=No compile error with gcc (Debian 12.2.0-3) 12.2.0 Original-Change-Id: I6e36633f42cb4dc5af53212c10c919a86e451ee0 Signed-off-by: Paul Menzel <pmenzel@molgen.mpg.de> Original-Reviewed-on: https://review.coreboot.org/c/coreboot/+/62830 Original-Reviewed-by: Angel Pons <th3fanbus@gmail.com> Change-Id: I90dc714f1959e94e9dc53cd383db19dc0dd9ac37 Reviewed-on: https://review.coreboot.org/c/coreboot/+/70463 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
* soc/intel/apollolake: Skip SMI lockdown on ApollolakeMatt DeVillier2022-10-211-1/+2
| | | | | | | | | | | | | Commit d9ef02ce (soc/intel/apollolake: Lock down Global SMI) breaks SMM/SMI on Apollolake (but not Geminilake), so guard it accordingly. TEST=build/boot google/reef, verify SMM/SMI/SMMSTORE functional. Change-Id: I00cbe046b61e6c342f7961670478d0ca8d365c2e Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/68599 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
* drivers/tpm: Move TPM init to end of device init phaseMatt DeVillier2022-10-201-1/+1
| | | | | | | | | | | | | | | | | Boards which use an I2C TPM and do not use vboot will not have the I2C bus initialized/ready at the start of the device init phase. If TPM init is called before the bus, init will fail with I2C transfer timeouts and a significantly lengthened boot time. Resolves: https://ticket.coreboot.org/issues/429 TEST=build/boot google/reef w/o vboot, verify successful TPM init. Change-Id: Ic47e465db1c06d8b79a1f0a06906843149b6dacd Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/68600 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
* Documentation/security: Update list of boards supporting vboot4.18Martin Roth2022-10-161-18/+72
| | | | | | | | Signed-off-by: Martin Roth <martin.roth@amd.corp-partner.google.com> Change-Id: Ie6ecb3ed97ed0581300411962c3b1bba416e0224 Reviewed-on: https://review.coreboot.org/c/coreboot/+/68242 Reviewed-by: Felix Singer <felixsinger@posteo.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* Docs/releases: Add 4.19 relnotes template and update indexMartin Roth2022-10-162-1/+66
| | | | | | | | | | | | | The 4.19 release is planned for January 2023. Please add any updates to the coreboot code that are should go into the notes between now and then. This helps in that you get to phrase the update the way you want, and it lessens the load for the release managers. Signed-off-by: Martin Roth <martin.roth@amd.corp-partner.google.com> Change-Id: Ib5a7ddfc6cb1a8e0a485c1e1810631c86f4083c3 Reviewed-on: https://review.coreboot.org/c/coreboot/+/68459 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <felixsinger@posteo.net>
* Docs/releases: Update coreboot-4.18 release notesMartin Roth2022-10-161-34/+193
| | | | | | | | Signed-off-by: Martin Roth <gaumless@gmail.com> Change-Id: I5cf38463e44f9abaadb4dc47dbf48ef0f0514bc9 Reviewed-on: https://review.coreboot.org/c/coreboot/+/64956 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <felixsinger@posteo.net>
* mb/starlabs/lite/{glk,glkr}: Enable PMCSean Rhodes2022-10-152-0/+2
| | | | | | | | | | | | | Enable PMC in devicetree so that resources are allocated properly for it. Tested on StarLite Mk III & IV, and both can power on correctly. Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: Ib4384b55751a9979e470dd04f6814d4ca170ff34 Reviewed-on: https://review.coreboot.org/c/coreboot/+/67409 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* mb/starlabs/lite: Reset XHCI before entering S5Sean Rhodes2022-10-151-0/+17
| | | | | | | | | | | | | Reset the XHCI controller prior to S5 to avoid XHCI preventing shutdown. Linux needs to put the XHCI into D3 before shutting down but the powerstate commands do not perform a reset. Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: I3be70443eb85a7dff8055c9de0ca2fd89f4fc88d Reviewed-on: https://review.coreboot.org/c/coreboot/+/67678 Reviewed-by: Tim Wawrzynczak <inforichland@gmail.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* soc/intel/apollolake: Lock down Global SMISean Rhodes2022-10-151-4/+11
| | | | | | | | | | Enable SMI_LOCK bit to prevent writes to the Global SMI Enable bit. Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: I9377c3b65aa342f754c303148b0b8d826d05bb94 Reviewed-on: https://review.coreboot.org/c/coreboot/+/67662 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* soc/intel/apollolake: Configure FSP UPDs to allow coreboot to lockdownSean Rhodes2022-10-151-5/+7
| | | | | | | | | | | | | | | | | Configure FSP S UPDs to allow coreboot to handle the lockdown. The main change here is setting `Write Protection Support` to 0, as the default is Enabled, which shouldn't allow writes (even though it seems to). The UPDs are identical on APL and GLK, but all ones configured in this patch have been there since their initial releases. Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: I1f6e5344cab2af7aa6001b9ec0f07b043a9caa8a Reviewed-on: https://review.coreboot.org/c/coreboot/+/67754 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
* treewide: Use 'fadt->x_pm2_cnt_blk.addrl = fadt->pm2_cnt_blk'Felix Held2022-10-1511-11/+11
| | | | | | | | Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Iaecb83c3bc9c75dab427a3ca54da1e6a8f87cf9a Reviewed-on: https://review.coreboot.org/c/coreboot/+/68428 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
* treewide: Use 'fadt->x_pm1a_evt_blk.addrl = fadt->pm1a_evt_blk'Felix Held2022-10-1520-20/+20
| | | | | | | | Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Id3002dc976b82f71b1f60a6e32b16d60a7bbbead Reviewed-on: https://review.coreboot.org/c/coreboot/+/68427 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
* mb/amd/padmelon: rename to pademelonFelix Held2022-10-1529-24/+24
| | | | | | | | | | | This AMD reference board is called Pademelon and not Padmelon, so fix the name in coreboot. Also update the corresponding documentation. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Id1c7331f5f3c34dc7ec4bc5a1f5fe3d12d503474 Reviewed-on: https://review.coreboot.org/c/coreboot/+/68426 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
* soc/amd/picasso: Clean up includesElyes Haouas2022-10-144-3/+7
| | | | | | | | Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Change-Id: I4ed869627af11b607f910644b6f21898f7c7bba5 Reviewed-on: https://review.coreboot.org/c/coreboot/+/68237 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
* soc/amd/sata.c: Hook up directly in devicetreeArthur Heymans2022-10-144-21/+4
| | | | | | | | | | | | | Cezanne has two SATA controllers, but doesn't select SOC_AMD_COMMON_BLOCK_SATA, so it's not added to the SATA devices in the Cezanne chipset devicetree. Change-Id: If7f0a9638151cf981d891464a2c3a0ec5fc9c780 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/68142 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
* soc/amd/*: Hook up IOMMU ops in devicetreeArthur Heymans2022-10-148-24/+8
| | | | | | | | | | | This removed the need to maintain a PCI driver. Change-Id: I43def81d615749008fcc9de8734fa2aca752aa9d Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/68146 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
* soc/amd/*: Hook up LPC ops in devicetreeArthur Heymans2022-10-148-22/+8
| | | | | | | | | | | This removes the need for a PCI driver. Change-Id: I6674d13f434cfa27fa6514623ba305af6681f70d Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/68144 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
* soc/amd/*: Hook up SMBus ops to devicetreeArthur Heymans2022-10-148-16/+8
| | | | | | | | | | | This removes the need for a PCI driver. Change-Id: Iab75f8c28a247f1370f4425e19cc215678bfa3e5 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/68140 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
* soc/amd: factor out common eMMC codeFelix Held2022-10-1415-54/+13
| | | | | | | | Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: If5447f9272183f83bc422520ada93d3cfd96551e Reviewed-on: https://review.coreboot.org/c/coreboot/+/68415 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
* ec/google/chromeec: Demote LPC EC error printk from ERR to SPEWMatt DeVillier2022-10-141-1/+1
| | | | | | | | | | | | | | | | | Several EC host commands check for support of a given feature or msg version, and a non-zero response does not necessarily indicate an actual error. Since the caller is (should be) handling the non-zero response to the host command, demote the EC printk from ERR to SPEW to clean up the console log and prevent non-errors from causing false failures in firmware tests. BUG=b:238961053 Change-Id: Ib7afc0b7e5b571acb56252f7adb518a6b2716b62 Signed-off-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/68259 Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* util/elogtool: Add support for parsing CrOS diagnostics logHsuan Ting Chen2022-10-142-7/+98
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Remove the "_DEPRECATED_" tag from ChromeOS diagnostics event and add a subtype: "ELOG_CROS_DIAGNOSTICS_LOGS" under it. The data of "ELOG_CROS_DIAGNOSTICS_LOGS" (0x02) contains: * An uint8_t of subtype code * Any number of "ChromeOS diagnostics logs" events Each "ChromeOS diagnostics log" represents the result of one ChromeOS diagnostics test run. It is stored within an uint8_t raw[3]: * [23:19] = ELOG_CROS_DIAG_TYPE_* * [18:16] = ELOG_CROS_DIAG_RESULT_* * [15:0] = Running time in seconds Also add support for parsing this event. The parser will first calculate the number of runs it contains, and try to parse the result one by one. BUG=b:226551117 TEST=Build and boot google/tomato to OS, localhost ~ # elogtool list 0 | 2022-09-26 04:25:32 | Log area cleared | 186 1 | 2022-09-26 04:25:50 | System boot | 0 2 | 2022-09-26 04:25:50 | Firmware vboot info | boot_mode=Manual recovery | recovery_reason=0x2/0 (Recovery button pressed) | fw_tried=A | fw_try_count=0 | fw_prev_tried=A | fw_prev_result=Unknown 3 | 2022-09-26 04:25:50 | EC Event | Keyboard Recovery 4 | 2022-09-26 04:26:01 | Memory Cache Update | Normal | Success 5 | 2022-09-26 04:26:06 | System boot | 0 6 | 2022-09-26 04:26:07 | Firmware vboot info | boot_mode=Diagnostic | fw_tried=A | fw_try_count=0 | fw_prev_tried=A | fw_prev_result=Unknown 7 | 2022-09-26 04:26:07 | Diagnostics Mode | Diagnostics Logs | type=Memory check (quick), result=Aborted, time=0m0s | type=Memory check (full), result=Aborted, time=0m0s | type=Storage self-test (extended), result=Aborted, time=0m1s Change-Id: I02428cd21be2ed797eb7aab45f1ef1d782a9c047 Signed-off-by: Hsuan Ting Chen <roccochen@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/67834 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
* soc/intel/alderlake: Create helper header file for UFSSubrata Banik2022-10-141-0/+27
| | | | | | | | | | | | | | | | This patch creates helper header file (ufs.h) for UFS to keep required registers details and ACPI device id for UFS. BUG=none TEST=Able to build and boot Google/Kano. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: If08c54eb706876a4255542a708aa5fcd8bf43c55 Reviewed-on: https://review.coreboot.org/c/coreboot/+/68299 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Meera Ravindranath <meera.ravindranath@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
* soc/intel/alderlake: Add UFS PCR IDSubrata Banik2022-10-141-0/+2
| | | | | | | | | | | | | | Add UFS PID (`PID_UFSX2`) value 0x50. BUG=none TEST=Able to build and boot Google/Rex. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: I229469475cd116bf911b6530c3c819d00c808aa9 Reviewed-on: https://review.coreboot.org/c/coreboot/+/68298 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Meera Ravindranath <meera.ravindranath@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* soc/mediatek/mt8186: Add DEVAPC settings for ADSPTinghan Shen2022-10-144-3/+151
| | | | | | | | | | | | | | Add DEVAPC permission settings for ADSP and set its domain number to 6. TEST=SOF driver is functional. BUG=b:204229221 Change-Id: I37bfea70386af953e89f3c38ac51e41af6aafa6e Signed-off-by: Tinghan Shen <tinghan.shen@mediatek.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/68290 Reviewed-by: Yu-Ping Wu <yupingso@google.com> Reviewed-by: Yidi Lin <yidilin@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* soc/mediatek/mt8186: Inititalize ADSPTinghan Shen2022-10-145-0/+39
| | | | | | | | | | | | | | To use SOF correctly, we need to initialize ADSP in coreboot stage. TEST=SOF driver is functional. BUG=b:204229221 Change-Id: I45db587252ccdcdf75e0be2029743034a79925c5 Signed-off-by: Tinghan Shen <tinghan.shen@mediatek.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/68289 Reviewed-by: Yidi Lin <yidilin@google.com> Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* soc/mediatek/mt8186: Add mtcmos power-on control for ADSPMandy Liu2022-10-144-1/+44
| | | | | | | | | | | | | | To use SOF correctly, we need to enable power domain of ADSP. TEST=SOF driver is functional. BUG=b:204229221 Signed-off-by: Mandy Liu <mandyjh.liu@mediatek.com> Change-Id: I39d1357af5f901a91379fdf7e595f16952b962de Reviewed-on: https://review.coreboot.org/c/coreboot/+/68288 Reviewed-by: Yidi Lin <yidilin@google.com> Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* soc/mediatek/mt8186: Enable ADSP clockMandy Liu2022-10-141-2/+5
| | | | | | | | | | | | | | To use SOF correctly, we need to enable ADSP clock. TEST=SOF driver is functional. BUG=b:204229221 Signed-off-by: Mandy Liu <mandyjh.liu@mediatek.com> Change-Id: Ia17db889829df2668cf2af1b71c6468230de68e1 Reviewed-on: https://review.coreboot.org/c/coreboot/+/68287 Reviewed-by: Yidi Lin <yidilin@google.com> Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* mb/google/rex: Add initial fw configKapil Porwal2022-10-141-10/+62
| | | | | | | | | | | | | | | Add initial fw config as per config.star. BUG=b:253199788, b:245158908, b:244113761, b:244012065 TEST=emerge-rex coreboot. Make sure that ACPI tables are equivalent before and after this change with CBI.FW_CONFIG set to 0x1561. Signed-off-by: Kapil Porwal <kapilporwal@google.com> Change-Id: I66f8b3e4ab414c03b8d63fdd31e0f3f424619340 Reviewed-on: https://review.coreboot.org/c/coreboot/+/68220 Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Tarun Tuli <taruntuli@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* mb/google/rex: Add FW_CONFIG* to KconfigEran Mitrani2022-10-141-0/+2
| | | | | | | | | | | | BUG=b:253199788 TEST=Build and boot to Google/Rex. Change-Id: Ib729c98a4d67aa46992fdccf592010b0313605a6 Signed-off-by: Eran Mitrani <mitrani@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/66817 Reviewed-by: Tarun Tuli <taruntuli@google.com> Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* mb/google/nissa/var/yaviks: Remove fw_config probe for storage devicesReka Norman2022-10-141-9/+3
| | | | | | | | | | | | | | | | | | | | | | | When fw_config is unprovisioned, devicetree will disable all probed devices. However, boot-critical devices such as storage devices need to be enabled. As a temporary workaround while adding devicetree support for this, remove the fw_config probe for storage devices so that all storage devices are always enabled. On eMMC SKUs, UFS and ISH will be disabled by the PCI scan anyway. On UFS SKUs, eMMC is not disabled by the PCI scan, but keeping it enabled should have no functional impact, only a possible power impact. BUG=b:251055188 TEST=On yaviks eMMC and UFS SKUs, boot to OS and `suspend_stress_test -c 10` Change-Id: I6b3a20f3c14d5e9aa8d71f6ca436b5a682310797 Signed-off-by: Reka Norman <rekanorman@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/68365 Reviewed-by: Sam McNally <sammc@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* Update arm-trusted-firmware submodule to upstream masterYidi Lin2022-10-141-0/+0
| | | | | | | | | | | | | | | | | Updating from commit id 7805999e6: 2022-09-05 16:42:34 +0200 - (Merge changes from topic "st-nand-updates" into integration) to commit id c45d2febb: 2022-10-12 15:56:24 +0200 - (Merge "fix(ufs): retry commands on unit attention" into integration) This brings in 288 new commits. Signed-off-by: Yidi Lin <yidilin@chromium.org> Change-Id: I4137cab0a1a352e94e21f105717ae0b6c515b75b Reviewed-on: https://review.coreboot.org/c/coreboot/+/68386 Reviewed-by: Rex-BC Chen <rex-bc.chen@mediatek.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
* mb/google/nissa/var/xivu: Config I2C frequencyIan Feng2022-10-141-0/+49
| | | | | | | | | | | | | | | | | | | | 1.Change the TPM I2C freqeuncy to 1 MHz for xivu. 2.Config same settings as the baseboard for I2C buses 1-5. BUG=b:249953477 TEST=On xivu, all timing requirements in the spec are met. Frequencies: 1. I2C0 (TPM): 974.3 Khz 2. I2C1 (TouchScreen); 375.5 Khz 3. I2C3 （Audio): 389.0 Khz 4. I2C5 (Touchpad): 388.5 Khz Signed-off-by: Ian Feng <ian_feng@compal.corp-partner.google.com> Change-Id: I33f712c14978b95f3a4da82d6f1f5fbae1283b17 Reviewed-on: https://review.coreboot.org/c/coreboot/+/68071 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Reka Norman <rekanorman@chromium.org> Reviewed-by: Frank Wu <frank_wu@compal.corp-partner.google.com>
* soc/intel/alderlake: Fix unknown voltage in SMBIOSZhixing Ma2022-10-141-0/+1
| | | | | | | | | | | | | | | | | | The current SMBIOS for coreboot is missing processor info for Alder Lake and Raptor Lake SoC, specifically, voltage, max speed, and upgrade (socket type). This patch implements voltage function. Refer to SMBIOS spec sheet for documentation: https://web.archive.org/web/20221012222420/https://www.dmtf.org/sites/default/files/standards/documents/DSP0134_3.6.0.pdf BUG=NONE BRANCH=firmware-brya-14505.B TEST=Boot and verified that SMBIOS processor voltage value is correct. Signed-off-by: Zhixing Ma <zhixing.ma@intel.com> Change-Id: I77712b72fa47bdcb56ffddeff15cff9f3b3bbe86 Reviewed-on: https://review.coreboot.org/c/coreboot/+/68023 Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com> Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* soc/intel/alderlake: Fix unknown max speed in SMBIOSZhixing Ma2022-10-142-0/+15
| | | | | | | | | | | | | | | | | | | The current SMBIOS for coreboot is missing processor info for Alder Lake and Raptor Lake SoC, specifically, voltage, max speed, and upgrade (socket type). This patch implements max speed function. Refer to SMBIOS spec sheet for documentation: https://web.archive.org/web/20221012222420/https://www.dmtf.org/sites/default/files/standards/documents/DSP0134_3.6.0.pdf BUG=NONE BRANCH=firmware-brya-14505.B TEST=Boot and verified that SMBIOS max speed value is correct. Signed-off-by: Zhixing Ma <zhixing.ma@intel.com> Change-Id: I09bcccc6f97238f7328224af8b852751114896fe Reviewed-on: https://review.coreboot.org/c/coreboot/+/67913 Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com> Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* mb/amd/padmelon/bootblock/OemCustomize: add TODO for Prairie FalconFelix Held2022-10-141-0/+6
| | | | | | | | | | | | | | The PCIe port descriptor list seems to be specific to Merlin Falcon and Prairie Falcon has a different PCIe root port configuration. Since I neither have the board nor the different APUs, I just add a comment about this instead of trying to come up with a PCIe port descriptor list that may or may not work properly on Prairie Falcon APUs. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I8e1eb67a8f684297bbefc6e2593250d7bd45593f Reviewed-on: https://review.coreboot.org/c/coreboot/+/68407 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
* soc/amd/stoneyridge: move northbridge ops to northbridge deviceFelix Held2022-10-142-4/+4
| | | | | | | | | | | | | The northbridge ops should be added to the actual northbridge and not the first HT device. Neither of the devices has BARs on it, so read_resources implementation will still work correctly. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I2e5f21bfe5fff043d7d9afafa360764203dd61f6 Reviewed-on: https://review.coreboot.org/c/coreboot/+/68409 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* soc/amd/stoneyridge: use devicetree ops over pci driverFelix Held2022-10-144-35/+8
| | | | | | | | | | | | | | Stoneyridge is a SoC so it makes sense to statically use ops instead of matching them to PCI DID/VID at runtime. In contrast to the other AMD SoCs in the coreboot tree the PC driver used the PCI ID of the first HT PCI device function, so add the ops to the device 0x18 function 0 devicetree entry in this patch. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I500521701479aa271ebd61e22a1494c8bfaf87fb Reviewed-on: https://review.coreboot.org/c/coreboot/+/68408 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* soc/amd/stoneyridge: Hook up device_operations in chipset.cbFelix Held2022-10-143-44/+14
| | | | | | | | | | | This removes the need for a lot of boilerplate code in the soc code to hook up device_operations to devices. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Id668587e1b747c28207b213b985204b7a961a631 Reviewed-on: https://review.coreboot.org/c/coreboot/+/68410 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* mb/prodrive/atlas: Print HSIDMaximilian Brune2022-10-141-0/+15
| | | | | | | | | Signed-off-by: Maximilian Brune <maximilian.brune@9elements.com> Change-Id: Ibb7aac1204bc297d16797cac5b32b119d0a9204b Reviewed-on: https://review.coreboot.org/c/coreboot/+/68224 Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
* mb/google/rex: Implement WIFI SAR related changesSubrata Banik2022-10-143-0/+17
| | | | | | | | | | | | | | | | | 1. Add CHROMEOS_WIFI_SAR to include the SAR configs. 2. Add get_wifi_sar_cbfs_file_name() that return the wifi SAR filename. BUG=none TEST=emerge-rex coreboot Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: Ia863eaa53c9456ae0e9f0e8914e0de497a32b53b Reviewed-on: https://review.coreboot.org/c/coreboot/+/68393 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com> Reviewed-by: Kapil Porwal <kapilporwal@google.com>
* mb/google/kahlee/*/devicetree: disable unused PCIe root portsFelix Held2022-10-146-24/+6
| | | | | | | | | | | | | | | | | | Disable the unused PCIe root ports that are disabled in the PCIe port corresponding descriptor list passed to AGESA/binaryPI. This descriptor list is in src/mainboard/google/kahlee/variants/baseboard/OemCustomize.c and it only has B0D2F2 (gpp_bridge_1) and B0D2F4 (gpp_bridge_3) enabled. Since the PCIe engines marked as unused in the port descriptor list won't show up as PCI devices, don't enable those PCI devices in the devicetree so that coreboot won't complain about static PCI devices not being found on the PCI bus. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: If8378e343a2eb13de66171cf4f38d77ae3401016 Reviewed-on: https://review.coreboot.org/c/coreboot/+/68382 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
* mb/google/kahlee/*/devicetree: use device aliasesFelix Held2022-10-146-192/+120
| | | | | | | | Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I63b1053d36b284ed95b015c0b4b26bdf8e162e67 Reviewed-on: https://review.coreboot.org/c/coreboot/+/68381 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* mb/amd/padmelon/devicetree: use device aliasesFelix Held2022-10-142-26/+15
| | | | | | | | | Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I509daac75c80bdca808706f783b04843209cc313 Reviewed-on: https://review.coreboot.org/c/coreboot/+/68380 Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* mb/amd/gardenia/devicetree: disable unused gpp_bridge_2Felix Held2022-10-141-1/+0
| | | | | | | | | | | | The board's PCIe port descriptors have the PCIe engine disabled, so update the devicetree accordingly. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ic97a54c3cc762a36752d6b9f21467428912a9edd Reviewed-on: https://review.coreboot.org/c/coreboot/+/68379 Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* mb/amd/gardenia/devicetree: use device aliasesFelix Held2022-10-141-26/+14
| | | | | | | | | Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I9a429c0fd23eb3b52a19a974b22079d675e3506a Reviewed-on: https://review.coreboot.org/c/coreboot/+/68318 Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
generated by cgit v1.2.3 (git 2.25.1) at 2024-05-06 02:01:27 +0000