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* Documentation/releases: Finalize the 4.19 release notesMartin Roth2023-01-171-52/+91
| | | | | | | | | | | | | These are the final 4.19 release notes before tagging the release. Final updates to statistics and removal of comments saying "planned" and "Upcoming" will be removed after the release is tagged. Signed-off-by: Martin Roth <gaumless@gmail.com> Change-Id: Ie20ad22732ce2e1d92e47b8e48268c6a5a34ca5b Reviewed-on: https://review.coreboot.org/c/coreboot/+/71942 Reviewed-by: Felix Singer <felixsinger@posteo.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* mb/starlabs/starbook/adl: Fix alignmentSean Rhodes2023-01-171-1/+1
| | | | | | | | | Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: I4a3f871f2418438ef8e780a39935dfa2f86d8dbb Reviewed-on: https://review.coreboot.org/c/coreboot/+/71895 Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin L Roth <gaumless@gmail.com>
* soc/amd/picasso/include/acpi: introduce and use ACPI_SCI_IRQ definitionFelix Held2023-01-164-3/+8
| | | | | | | | | | | | The newer AMD SoCs define ACPI_SCI_IRQ in the SoC's acpi.h header file and use this definition in the mainboard code, so port this back to Picasso. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ib569747aa388d7953e79de747905fb52c2a05e74 Reviewed-on: https://review.coreboot.org/c/coreboot/+/71912 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
* Revert "mb/starlabs/starbook/adl: Enable the PchHdaAudioLinkHdaEnable UPD"Martin L Roth2023-01-161-4/+3
| | | | | | | | | | | | | | | | This reverts commit 0e945a3426782e3c054a920ff8be3cd865f697ba. Reason for revert: Breaks build. Need to be merged after https://review.coreboot.org/c/coreboot/+/71715 which adds the register that this patch enables Signed-off-by: Martin L Roth <gaumless@gmail.com> Change-Id: I0ac3fb1a44e23e19c9711287f3a6a8402a6ffd79 Reviewed-on: https://review.coreboot.org/c/coreboot/+/71283 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Felix Singer <felixsinger@posteo.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
* Revert ".gitmodules: Fix submodule revision to v0.1 tag"Maximilian Brune2023-01-161-1/+1
| | | | | | | | | | | | | | This reverts commit 59a1a30ae1555e654b07f7ec7d76798bc408908f. git submodule updates currently break, since apparently you can't use git tags in the .gitmodules file. Signed-off-by: Maximilian Brune <maximilian.brune@9elements.com> Change-Id: Ibbc2bee21a723bd6d602ca435cada1dc0da03091 Reviewed-on: https://review.coreboot.org/c/coreboot/+/71894 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-by: Felix Singer <felixsinger@posteo.net>
* mb/starlabs/starbook/adl: Enable the PchHdaAudioLinkHdaEnable UPDSean Rhodes2023-01-161-3/+4
| | | | | | | | | | Enable the PchHdaAudioLinkHdaEnable UPD so that the sound works. Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: Id53c9a6495d584c374e89b76d1fd4258654b6f95 Reviewed-on: https://review.coreboot.org/c/coreboot/+/71716 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com>
* commonlib/storage: Add common eMMC functionsShelley Chen2023-01-164-58/+49
| | | | | | | | | | | | | | | | | | | | Now that multiple platforms are trying to initialize eMMC in coreboot instead of depthcharge, lets move common functionality into commonlib instead of copying the same functionality between multiple platforms. Note for consistency, changed name of set_early_mmc_wake_status() to mmc_set_early_wake_status(). Also adding an mmc_send_cmd1() function for retrieving the Operating Conditions Register (OCR) contents. BUG=b:218406702 BRANCH=None TEST=emerge-herobrine coreboot chromeos-bootimage flash onto villager device and make sure still boots ChromeOS Change-Id: Id00535b05bbd379081712601ef10e762c1831747 Signed-off-by: Shelley Chen <shchen@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/71827 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
* util/kconfig: Add comment explaining difference from upstreamNicholas Chin2023-01-152-1/+11
| | | | | | | | | | | | | | | | coreboot adds a patch on top of upstream Kconfig which allows the generated Kconfig dependency files to be placed in a separate directory than the autoconfig files based on the KCONFIG_SPLITCONFIG variable. Add a comment to explain this difference. Change-Id: Ief38ab84f852ff24f896ec8bbf094aa737a172d9 Signed-off-by: Nicholas Chin <nic.c3.14@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/69952 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Martin L Roth <gaumless@gmail.com>
* util/kconfig: Fix patch to be compatible with quiltNicholas Chin2023-01-151-9/+6
| | | | | | | | | | | | | | | The patch added in commit b7f92a0b6a0f (util/kconfig: Add patch to move Kconfig deps to build/config) uses git diff formatting, which is incompatible with quilt. Change-Id: I95bfe6571e3a2cc2b38074b4338f1610a4c8a595 Signed-off-by: Nicholas Chin <nic.c3.14@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/69863 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Martin L Roth <gaumless@gmail.com>
* mb/bostentech: Update name in KconfigMartin Roth2023-01-151-1/+1
| | | | | | | | | | | | | | | The Bostentech mainboard appears out of order - this can be fixed either by renaming the mainboard to start with S, or by the simpler method used here by putting the mainboard directory name as the main name, then noting that the full name is "Shenzhen Bostrontium Teng Technology". Signed-off-by: Martin Roth <gaumless@gmail.com> Change-Id: I31b4c663b68cdcde2d175f080f011f2998e56074 Reviewed-on: https://review.coreboot.org/c/coreboot/+/71777 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Felix Singer <felixsinger@posteo.net>
* soc/intel/apollolake/pmutil.c: Fix smi_sts_bits[HSMBUS_SMI_STS_BIT]Elyes Haouas2023-01-151-1/+1
| | | | | | | | | | | Found using -Woverride-init command option. Change-Id: I9f0755de9fae678fc5d78a709453fd1098d70e50 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/71893 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sean Rhodes <sean@starlabs.systems> Reviewed-by: Subrata Banik <subratabanik@google.com>
* soc/intel/xeon_sp/Kconfig: set up HPET_MIN_TICKSTim Chu2023-01-151-0/+4
| | | | | | | | | Signed-off-by: Tim Chu <Tim.Chu@quantatw.com> Change-Id: I3256c3c6a4ea331efae00d78192355a1fd78d6d2 Reviewed-on: https://review.coreboot.org/c/coreboot/+/71140 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-by: David Hendricks <david.hendricks@gmail.com>
* soc/intel/xeon_sp: lock MSR_PPIN_CTL at BS_PAYLOAD_LOADTim Chu2023-01-152-3/+37
| | | | | | | | | | | | | | | | | MSR_PPIN_CTL may need to be read more than once, so lock PPIN CTL MSR at a late BS_PAYLOAD_LOAD boot state. This MSR is in platform scope and must only be locked once on each socket. Add a spinlock to do so. Tested=On OCP Craterlake single socket, rdmsr -a 0x04e shows 1. Signed-off-by: Johnny Lin <johnny_lin@wiwynn.com> Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Change-Id: I8deb086339267cf36e41e16f189e1378f20b82f1 Reviewed-on: https://review.coreboot.org/c/coreboot/+/71144 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: David Hendricks <david.hendricks@gmail.com>
* soc/amd/mendocino: PSP_INCLUDES_HSPKarthikeyan Ramasubramanian2023-01-156-37/+25
| | | | | | | | | | | | | | | Select HSP config to indicate that the SoC includes Hardware Security Processor. This will allow PSP verstage to get and report the HSP state. BUG=None TEST=Build Skyrim BIOS image and boot to ChromeOS on Skyrim. Verify that HSP is reported during the boot sequence. Change-Id: I22446c2bd6202529367da040c09449e6b26f9d7a Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/71209 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin L Roth <gaumless@gmail.com>
* soc/amd/common/psp_verstage: Report HSP Secure StateKarthikeyan Ramasubramanian2023-01-153-0/+21
| | | | | | | | | | | | | | Get Hardware Security Processor(HSP) state in PSP Verstage through the SVC call and report it in cbmem logs. BUG=b:198711349 TEST=Build Skyrim BIOS image and boot to OS in Skyrim. Change-Id: Ic4875d1732f22783a90434329188192b106168f4 Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/71208 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin L Roth <gaumless@gmail.com>
* vc/amd/*,soc/amd/*: Add SVC call to get HSP Secure StateKarthikeyan Ramasubramanian2023-01-154-0/+30
| | | | | | | | | | | | | | | | Add an SVC call to get the state of Hardware Security Processor (HSP) in AMD SoCs. This SVC call will be used from PSP verstage to get and report HSP state. BUG=b:198711349 TEST=Build Skyrim BIOS image and boot to OS. Ensure that the HSP state is read and reported in the firmware logs. Change-Id: I7fe3363d308a80cc09e6bdadd8d0bb1d67f7d2bf Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/71207 Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* soc/amd/mendocino/include/acpi,lpc: remove TODO after reviewFelix Held2023-01-152-4/+0
| | | | | | | | | | | | | Remove TODO comment after checking against Mendocino PPR #57243, rev 3.02. BUG=b:263563246 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ie0e35f4c68ec09304eb892888759c7e5ef3dd0ca Reviewed-on: https://review.coreboot.org/c/coreboot/+/71911 Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* mb/google/skyrim/var/winterhold: Update USB port A0 settingEricKY Cheng2023-01-151-43/+12
| | | | | | | | | | | | | | Update USB port Type-A Port A0 setting. BUG=b:261650602 TEST=emerge-skyrim coreboot. Ensure that USB-A port is enumerated correctly in the output of lusub command. Change-Id: I9563f7b141c34b613cf896f1ce92178617a62c93 Signed-off-by: EricKY Cheng <ericky_cheng@compal.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/71854 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Van Patten <timvp@google.com>
* mb/google/brya/var/marasov: Update Aux settingsFrank Chu2023-01-151-2/+11
| | | | | | | | | | | | | | | | | | | | | | | | Follow hardware design to correct aux setting on USB-C ports to fix DP monitor can not output data through type-C port 0 USB-C port 0 did not have retimer. USB-C port 1 have retimer. USB-C port 0 AUX_DC_P connect to GPP_E22. USB-C port 0 AUX_DC_N connect to GPP_E23. BUG=b:263212450 BRANCH=firmware-brya-14505.B TEST=emerge-brya coreboot chromeos-bootimage DP monitor display normally Signed-off-by: Frank Chu <Frank_Chu@pegatron.corp-partner.google.com> Change-Id: I3af7522f7b6477edcd88004ce1d5f86aeebe3393 Reviewed-on: https://review.coreboot.org/c/coreboot/+/71222 Reviewed-by: Frank Chu <frank_chu@pegatron.corp-partner.google.com> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
* mb/google/skyrim/var/winterhold: Update I2C bus0 settingsDtrain Hsu2023-01-151-0/+10
| | | | | | | | | | | | | | | | | Update settings for touchpad I2C frequency and data hold time. I2C frequency and data hold time need to meet touchpad spec. - I2C frequency: 380kHz - 400kHz - Data hold time: 0.3us - 0.9us BUG=b:262320419 TEST=On winterhold, touchpad i2c measurement from vendor, Frequencies: 395 kHz, Data hold time: 0.66 us Change-Id: I40fa6f9e88656d4ec02a4120f75a2a9413b5abaa Signed-off-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/71853 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
* docs/releases/4.19: Add note about ASL 2.0 conversionFelix Singer2023-01-151-0/+8
| | | | | | | | | Change-Id: I30d827043e3eb3bf21551b1cb6c0b4c369a70083 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/71713 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jason Glenesk <jason.glenesk@gmail.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
* docs/releases/4.19: Add toolchain updatesElyes Haouas2023-01-151-0/+9
| | | | | | | | | Change-Id: If8c3f8e18ccbec8770917cc97aa562eac7417aaf Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/71178 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jason Glenesk <jason.glenesk@gmail.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
* Documentation/releases: Start getting ready for the 4.19 releaseMartin Roth2023-01-151-13/+126
| | | | | | | | Signed-off-by: Martin Roth <gaumless@gmail.com> Change-Id: I3edbf3ebc74ebae5896196b43dd5be014f27a0ec Reviewed-on: https://review.coreboot.org/c/coreboot/+/71590 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jason Glenesk <jason.glenesk@gmail.com>
* drivers/uart/acpi: Drop 'disable_gpio_export_in_crs' flagMatt DeVillier2023-01-152-5/+2
| | | | | | | | | | | | | | | | | | | | | Exposing the GPIOs via an ACPI PowerResource and the _CRS results in the OS driver and ACPI thinking they own the GPIO. This can cause timing problems because it's not clear which system should be controlling the GPIO. There's no reason to require explicit disablement however, so drop the superfluous 'disable' flag, and change the _CRS generation to check if the GPIOs will be exported via the 'has_power_resource' flag instead. This mirrors the change made for drivers/i2c/generic. TEST=untested, as no boards selected this option. Change-Id: Icb60502a4a7c5e7a1fcf1ee60e23c77e00d6de7b Signed-off-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/71851 Reviewed-by: Martin L Roth <gaumless@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* drivers/spi/acpi: Drop 'disable_gpio_export_in_crs' flagMatt DeVillier2023-01-152-5/+2
| | | | | | | | | | | | | | | | | | | | | Exposing the GPIOs via an ACPI PowerResource and the _CRS results in the OS driver and ACPI thinking they own the GPIO. This can cause timing problems because it's not clear which system should be controlling the GPIO. There's no reason to require explicit disablement however, so drop the superfluous 'disable' flag, and change the _CRS generation to check if the GPIOs will be exported via the 'has_power_resource' flag instead. This mirrors the change made for drivers/i2c/generic. TEST=untested, as no boards selected this option. Change-Id: I4f95d0e453d89b7e1978d3efac304518304495d1 Signed-off-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/71850 Reviewed-by: Martin L Roth <gaumless@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* drivers/i2c/generic: Drop 'disable_gpio_export_in_crs' flagMatt DeVillier2023-01-1595-141/+2
| | | | | | | | | | | | | | | | | | | | | | | Exposing the GPIOs via an ACPI PowerResource and the _CRS results in the OS driver and ACPI thinking they own the GPIO. This can cause timing problems because it's not clear which system should be controlling the GPIO. Previously, we flagged as an error any device which set the 'has_power_resource' flag but did not set 'disable_gpio_export_in_crs.' There's no reason to require explicit disablement however, so drop the superfluous 'disable' flag, and change the _CRS generation to check if the GPIOs will be exported via the 'has_power_resource' flag instead. BUG=b:265055477 TEST=build/boot skyrim, dump SSDT and verify touchscreen GPIOs only listed under PRx, not under _CRS. Change-Id: I837ae6c6fe4b8e1c4e10686406cba06bdb7759d2 Signed-off-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/71849 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin L Roth <gaumless@gmail.com>
* soc/intel/common: Use 'enum cb_error' valuesSridhar Siricilla2023-01-151-32/+32
| | | | | | | | | | | | | | | | | | | The patch uses 'enum cb_error' values as return values for below functions: 1. cse_get_rw_rdev() 2. cse_erase_rw_region() 3. cse_write_rw_region() 4. cse_locate_area_as_rdev_rw() 5. cse_get_target_rdev() 6. cse_copy_rw TEST=Build, boot and perform CSE downgrade test on the Gimble board Signed-off-by: Sridhar Siricilla <sridhar.siricilla@intel.com> Change-Id: I9c664430a5015d37b9c329f85886f8622deaa497 Reviewed-on: https://review.coreboot.org/c/coreboot/+/71825 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
* soc/intel/common: Use 'enum cb_err' valuesSridhar Siricilla2023-01-153-6/+6
| | | | | | | | | | | | | The patch uses cb_err enum values as return values for function cse_get_boot_performance_data() instead of true/false. TEST=Build code for Gimble Signed-off-by: Sridhar Siricilla <sridhar.siricilla@intel.com> Change-Id: I0153d5496c96fb0c2a576eef1fe2fa7fa0db8415 Reviewed-on: https://review.coreboot.org/c/coreboot/+/71824 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
* soc/intel/common: Use enum cb_err valuesSridhar Siricilla2023-01-153-32/+32
| | | | | | | | | | | | | | | | | The patch uses cb_err enum values as return values for below functions: 1. cse_hmrfpo_enable() 2. cse_boot_to_ro() 3. cse_prep_for_rw_update() 4. cse_sub_part_get_target_rdev() 5. cse_get_sub_part_fw_version() 6. cse_prep_for_component_update() Signed-off-by: Sridhar Siricilla <sridhar.siricilla@intel.com> Change-Id: I1bdb7d6b2051a69f1021673d464bfad63dd39431 Reviewed-on: https://review.coreboot.org/c/coreboot/+/71823 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin L Roth <gaumless@gmail.com>
* drivers/intel/i210/Makefile.inc: Fix "No such file or directory" errorElyes Haouas2023-01-142-1/+1
| | | | | | | | | | | Fix: cc1: error: src/drivers/intel/i210: No such file or directory [-Werror=missing-include-dirs] Change-Id: I94b0f99353ed3a582ea590cbc6b12dec6294c75d Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/70468 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
* configs/google_skyrim.no_video: Fix typo and regenerateMartin Roth2023-01-141-2/+6
| | | | | | | | | | | | | | | | | | | | | | | There was a typo in the config disabling bootblock should have been: # CONFIG_VBOOT_STARTS_BEFORE_BOOTBLOCK is not set As the line moved, it is the missing underscore after CONFIG, preventing it from working as intended. The other changes are updates to allow it to match what we get by copying it to .config, then running: make olddefconfig; make savedefconfig Change-Id: Ic41a91e0a6ecd254a86d0872da19a0d4d321b8e3 Signed-off-by: Martin Roth <gaumless@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/71840 Reviewed-by: Jason Glenesk <jason.glenesk@gmail.com> Reviewed-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* commonlib/storage: fix int-to-pointer-cast errorShelley Chen2023-01-141-1/+1
| | | | | | | | | | | | | | | | | | | When pulling in commonlib/storage/pci_sdhci.c into herobrine, am seeing an "error: cast to pointer from integer of different size [-Werror=int-to-pointer-cast]", so fixing that. BUG=b:254092907 BRANCH=None TEST=emerge-herobrine coreboot Make sure that we can build without errors Change-Id: Ib1718f156708a619f7eeb181e19b1a8c620de1f8 Signed-off-by: Shelley Chen <shchen@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/71828 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Julius Werner <jwerner@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
* vendorcode/intel/fsp: Add Raptor Lake FSP headers for FSP RPL.3503.00Bora Guvendik2023-01-132-171/+175
| | | | | | | | | | | | | | | | The headers added are generated as per FSP v3503.00 BUG=b:261159242 BRANCH=firmware-brya-14505.B TEST=Boot to OS Cq-Depend: chrome-internal:5318308, chrome-internal:5318129 Signed-off-by: Bora Guvendik <bora.guvendik@intel.com> Change-Id: I050c0f81dce1cfc5ef64406e75d9823352564836 Reviewed-on: https://review.coreboot.org/c/coreboot/+/71758 Reviewed-by: Nick Vaccaro <nvaccaro@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Pratikkumar V Prajapati <pratikkumar.v.prajapati@intel.com>
* soc/amd/phoenix: update mmconf base address and sizeRitul Guru2023-01-131-2/+2
| | | | | | | | | | | | | 0xF8000000 was taken from old platform during phoenix porting, updating it to 0xE0000000 to make room for 256 pci busses which is required for usb4 and hotplug support. mmconf size gets set to 0x10000000 when 256 busses are used. Change-Id: Ic143171f5650aff5db48c8f477d7aca3e7f5c1e7 Signed-off-by: Ritul Guru <ritul.bits@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/71870 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* soc/amd/glinda: use common SMU S3/4/5 entry message codeFelix Held2023-01-133-20/+1
| | | | | | | | | Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I62b15d59cc4a5f214e45c3995f651228b1ae6ea7 Reviewed-on: https://review.coreboot.org/c/coreboot/+/71900 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
* soc/amd/phoenix: use common SMU S3/4/5 entry message codeFelix Held2023-01-133-20/+1
| | | | | | | | | Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ie7ded68f4732ec12a1c7e59445d572763a03c3b9 Reviewed-on: https://review.coreboot.org/c/coreboot/+/71879 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
* soc/amd/mendocino: use common SMU S3/4/5 entry message codeFelix Held2023-01-133-18/+1
| | | | | | | | | Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ief1e9c6d6fa0889b947863837bedb2fbdf3120c3 Reviewed-on: https://review.coreboot.org/c/coreboot/+/71878 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
* soc/amd/cezanne: use common SMU S3/4/5 entry message codeFelix Held2023-01-133-18/+1
| | | | | | | | | Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I4b9f1b71a5f8b2776c8b338351b2cca723d00598 Reviewed-on: https://review.coreboot.org/c/coreboot/+/71877 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
* soc/amd/picasso: use common SMU S3/4/5 entry message codeFelix Held2023-01-133-18/+1
| | | | | | | | | Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Iedd99cfb64809c4e111e0931c2260981f465035b Reviewed-on: https://review.coreboot.org/c/coreboot/+/71876 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
* soc/amd: introduce common SMU S3/4/5 entry message codeFelix Held2023-01-133-0/+26
| | | | | | | | | | | | | | | | The smu_sx_entry function is identical for all AMD SoCs, so introduce it as common code that can be selected to be included in the build via the SOC_AMD_COMMON_BLOCK_SMU_SX_ENTRY Kconfig option. The only SoC-specific difference in this function is the ID of the SMC_MSG_S3ENTRY message which is defined in each SoC's soc/smu.h include file. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Suggested-by: Elyes Haouas <ehaouas@noos.fr> Change-Id: I49758e9333a351d8e50e8f1b53a7f00fbe89866c Reviewed-on: https://review.coreboot.org/c/coreboot/+/71875 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
* mb/google/skyrim: remove morthal variantMartin Roth2023-01-134-15/+0
| | | | | | | | | | Morthal has been overcome by events. Signed-off-by: Martin Roth <gaumless@gmail.com> Change-Id: Ice46f4c7400772dbf51eb9d20b61af277daa8513 Reviewed-on: https://review.coreboot.org/c/coreboot/+/71880 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
* soc/amd/glinda: Use common fsp-s preloaderFred Reitberger2023-01-133-14/+1
| | | | | | | | | | Use the common preloader for fsp-s Signed-off-by: Fred Reitberger <reitbergerfred@gmail.com> Change-Id: I32f8ca02c4de9e882f207c2dd2378b6b44dc61ff Reviewed-on: https://review.coreboot.org/c/coreboot/+/71848 Reviewed-by: Jason Glenesk <jason.glenesk@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* soc/amd/phoenix: Use common fsp-s preloaderFred Reitberger2023-01-133-14/+1
| | | | | | | | | | Use the common preloader for fsp-s Signed-off-by: Fred Reitberger <reitbergerfred@gmail.com> Change-Id: Iea7011d37667f3f04ce842038346741fba66b1dc Reviewed-on: https://review.coreboot.org/c/coreboot/+/71847 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* mb/lenovo/t520: Disable SATA2 and Thermal on W520Angel Pons2023-01-132-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | If a discoverable device (e.g. a PCI device) does not appear in the devicetree (typically because it is removable), coreboot enables it by default. Disable the SATA2 (device for SATA ports 4 and 5, which is not used in AHCI mode) and Thermal devices on W520 as well. Both devices were only disabled on the T520. Tested, this change fixes a long boot time when using MrChromebox's edk2 payload on the W520, likely related to the following errors: AHCI: Error interrupt reported PxIS: 40000001 Non data transfer failed at retry 0 AHCI: Error interrupt reported PxIS: 40000001 Non data transfer failed at retry 1 AHCI: Error interrupt reported PxIS: 40000001 Non data transfer failed at retry 2 AHCI: Error interrupt reported PxIS: 40000001 Non data transfer failed at retry 3 AHCI: Error interrupt reported PxIS: 40000001 Non data transfer failed at retry 4 Change-Id: I0b0483aae05fa84d97987a93db634b740f830e18 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/71857 Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* mb/lenovo/t520: Also disable PCI bridge on W520Angel Pons2023-01-132-2/+1
| | | | | | | | | | As per Kendo3-WS schematics, the conventional PCI bridge is not used. Change-Id: Ic3aa11cc3a3028c31b06ad8f74875db8c5626a89 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/71856 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* mainboard: Remove duplicated <soc/gpio.h>Elyes Haouas2023-01-1373-73/+1
| | | | | | | | | | <gpio.h> chain-include <soc/gpio.h>. Change-Id: Ia57d5cd33c70b6a755babd4db56c64c0e3666f9f Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/71817 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
* soc/mediatek: Include <gpio.h> instead of <soc/gpio.h>Elyes Haouas2023-01-1320-20/+18
| | | | | | | | | | <gpio.h> chain-include <soc/gpio.h>. Change-Id: If2af7f77e2d910a3f3470d15dbfc98775a2633b6 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/71813 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Hung-Te Lin <hungte@chromium.org>
* vc/siemens/hwilib/Makefile.inc: Fix "No such file or directory" errorElyes Haouas2023-01-132-2/+2
| | | | | | | | | | | | Fix: cc1: error: src/vendorcode/siemens/hwilib: No such file or directory [-Werror=missing-include-dirs] Change-Id: I0e805ead90dddbee3ba3577d119e465f669231ba Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/70469 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
* drivers/i2c/pca9538/Makefile.inc: Remove unused pathElyes Haouas2023-01-131-4/+0
| | | | | | | | Change-Id: I435837381a966b61081d023447a6e7fdfd9a9348 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/71553 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
* mb/system76/adl-p: Enable AER on CPU PCIe RPTim Crawford2023-01-132-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | Tested with the following drives: - Crucial P5 Plus (CT500P5PSSD8) - Kingston KC3000 (SKC3000S/512G) - Sabrent Rocket NVMe 4.0 (SB-ROCKET-NVMEe4-500) - Samsung 970 EVO (MZ-V7E250) - Samsung 970 EVO Plus (MZ-V7S250) - Samsung 980 PRO (MZ-V8P2T0) - WD Black SN850X (WDS100T2XD0E) - WD Blue SN580 (WDS500G2B0C) - WD Green SN350 (WDS240G2G0C) Test: - Drive is functional and has no unrecoverable errors on boot - Drive is functional and has no unrecoverable errors after S0ix Change-Id: I51492c97c48f760d4aa9e4a2b2e57b0f1a06d090 Signed-off-by: Tim Crawford <tcrawford@system76.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/71662 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jeremy Soller <jeremy@system76.com>
generated by cgit v1.2.3 (git 2.25.1) at 2024-06-30 09:44:59 +0000