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* AMD northbridges: factor out CPU allocationKyösti Mälkki2012-08-2710-120/+124
| | | | | | | | | | | | | | | | | Factor CPU allocation out of AMD northbridge codes. As CPU topology information is required for generation of certain ACPI tables, make this code globally available. For AMDK8 and AMDFAM10 northbridge, there is a possible case of BSP CPU with lapicid!=0. We do not want to leave the lapic 0 from devicetree unused, so always use that node for BSP CPU. Change-Id: I8b1e73ed5b20b314f71dfd69a7b781ac05aea120 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/1418 Tested-by: build bot (Jenkins) Reviewed-by: Anton Kochkov <anton.kochkov@gmail.com> Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
* AMD northbridges: rewrite CPU allocationKyösti Mälkki2012-08-276-156/+104
| | | | | | | | | | | | | | | Use of alloc_find_dev() prevents creation of a device duplicates for device_path and is SMP safe. Reduce scope of variables to make the code more readable and in preparation for refactoring the allocation out of northbridge.c. Change-Id: I153dc1a5cab4f2eae4ab3a57af02841cb1a261c0 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/1186 Tested-by: build bot (Jenkins) Reviewed-by: Anton Kochkov <anton.kochkov@gmail.com> Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
* MPTABLE: check for fixed IRQ entries on all pinsSven Schnelle2012-08-251-42/+47
| | | | | | | | | | | | Don't derive the IRQ pin from the function number. Especially onboard chipset devices don't follow that rule. Instead check and add all fixed IRQ entries. Change-Id: I46c88bad39104c1d9b4154f180f8b3c42df28262 Signed-off-by: Sven Schnelle <svens@stackframe.org> Reviewed-on: http://review.coreboot.org/1461 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
* Fix mptable build troublesKyösti Mälkki2012-08-257-95/+4
| | | | | | | | | | | | | | | A missing mptable.c file got passed jenkins, got merged and broke the build. Hopefully finally fix this. Deletes unused files: src/mainboard/asus/dsbf/mptable.c src/mainboard/supermicro/x7db8/mptable.c Change-Id: Ie81f5a6c4c69ab381f86a243bc8874395e69ee26 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/1486 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
* libpayload: add controller type in usbdev_hcAnton Kochkov2012-08-235-0/+11
| | | | | | | | | | | | | | | Add controller type (UHCI, OHCI, EHCI or XHCI) into usbdev_hc (hci_t) struct, so now we know which type selected controller have. It needed to access controller specific data, if access usb tree outside of libpayload (e.g. in payload intself) Change-Id: I7df947bbb56a50d0d792ccd4d3a6b021ee95e2ea Signed-off-by: Anton Kochkov <anton.kochkov@gmail.com> Reviewed-on: http://review.coreboot.org/1145 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
* crossgcc: Update GDB patch version to 7.4.1zbao2012-08-231-12/+4
| | | | | | | | | | | libgen.h dont have to be included. Change-Id: I46a6a23a310b20784de956a577f1ab3c7931e34d Signed-off-by: Zheng Bao <zheng.bao@amd.com> Signed-off-by: zbao <fishbaozi@gmail.com> Reviewed-on: http://review.coreboot.org/1470 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
* LUMPY: Add information to generate MPTABLE from devicetree.cbSven Schnelle2012-08-222-6/+33
| | | | | | | | Change-Id: If68888e87c5197328c59dafce1301eefe000e28e Signed-off-by: Sven Schnelle <svens@stackframe.org> Reviewed-on: http://review.coreboot.org/1462 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
* Auto-declare chip_operationsKyösti Mälkki2012-08-22179-326/+8
| | | | | | | | | | | | The name is derived directly from the device path. Change-Id: If2053d14f0e38a5ee0159b47a66d45ff3dff649a Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/1471 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de> Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Reviewed-by: Anton Kochkov <anton.kochkov@gmail.com>
* mptable: bring sanity back to mptable generation (TRIVIAL)Alexandru Gagniuc2012-08-221-4/+4
| | | | | | | | | | | | | Remove extra semicolon Capitalize beginning of printk sentence Fix detection of multiple ISA-carrying IOAPICs Fix whitespace issue Change-Id: I114119b1daf3b472955c0dd00bdc449401789525 Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Reviewed-on: http://review.coreboot.org/1474 Tested-by: build bot (Jenkins) Reviewed-by: Anton Kochkov <anton.kochkov@gmail.com>
* Support use of the compression option when adding payloads to cbfs.Dave Frodin2012-08-211-1/+2
| | | | | | | | | Change-Id: Ie77e8e1628d34f1a9e7a57e994bf2882c5e55e25 Signed-off-by: Dave Frodin <dave.frodin@se-eng.com> Reviewed-on: http://review.coreboot.org/1452 Tested-by: build bot (Jenkins) Reviewed-by: Anton Kochkov <anton.kochkov@gmail.com> Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
* Change to allow coreboot to use "add-payload" instead of "add" for payload ↵Dave Frodin2012-08-211-2/+4
| | | | | | | | | | | | | | images. The current code does some argument manipulation to detect when a stage is being added to cbfs. This same manipulation needs to be done when adding a payload. Change-Id: Ief4c4a81446c9437923cbbb1ce3fa90729317587 Signed-off-by: Dave Frodin <dave.frodin@se-eng.com> Reviewed-on: http://review.coreboot.org/1451 Tested-by: build bot (Jenkins) Reviewed-by: Anton Kochkov <anton.kochkov@gmail.com> Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
* Don't write automatic IRQ entries for disabled devicesSven Schnelle2012-08-211-1/+1
| | | | | | | | Change-Id: Ib3dae4f0957a2e0057c0dffb5eb9904af20dcd40 Signed-off-by: Sven Schnelle <svens@stackframe.org> Reviewed-on: http://review.coreboot.org/1460 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
* AMD S3: Add a document about S3 on AMD platformzbao2012-08-151-0/+128
| | | | | | | | | | | | See the document. Need review. Everything should be in Authentic English. Change-Id: Idc528b8c6b0d5afe08fc4f4387b7bff30698f677 Signed-off-by: Zheng Bao <zheng.bao@amd.com> Signed-off-by: zbao <fishbaozi@gmail.com> Reviewed-on: http://review.coreboot.org/1400 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
* coreboot: Dump memory around problem area when encountering exceptionAlexandru Gagniuc2012-08-151-0/+13
| | | | | | | | | | | | | When we encounter an x86 exception, we print the problem address, dump the registers and die. This may not be sufficient information for debug. Also dump the memory around the problem instruction. This has proven useful in identifying memory issues, and DRAM burst reordering problems. Change-Id: I6411344e89f946e16d11217d7dbd73812c45d54c Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Reviewed-on: http://review.coreboot.org/1454 Tested-by: build bot (Jenkins) Reviewed-by: Anton Kochkov <anton.kochkov@gmail.com>
* coreinfo: fix build error (TRIVIAL)Alexandru Gagniuc2012-08-151-1/+1
| | | | | | | | | | | Changes to libpayload, and lack of maintenance to coreinfo, and it no longer builds. Fix that. Change-Id: I03497880671f42b5aeb6db08ddf6ce2acd243a18 Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Reviewed-on: http://review.coreboot.org/1453 Tested-by: build bot (Jenkins) Reviewed-by: Anton Kochkov <anton.kochkov@gmail.com>
* buildgcc: Remove the warning options unsupported by cygwinzbao2012-08-151-4/+8
| | | | | | | | | | | | My cygwin hostcc doesn't support -Wempty-body -Waddress -Wmissing-field-initializers Change-Id: I879e05f3bd396b36b327f204252e820552b6e12e Signed-off-by: Zheng Bao <zheng.bao@amd.com> Signed-off-by: zbao <fishbaozi@gmail.com> Reviewed-on: http://review.coreboot.org/1426 Tested-by: build bot (Jenkins) Reviewed-by: Anton Kochkov <anton.kochkov@gmail.com>
* buildgcc: Update the toolchain patches versionzbao2012-08-143-53/+5
| | | | | | | | | | | | | acpica 20120420, acpica-unix-20110922_no_unused_variables.patch is not used anymore. binutils 2.22. Change-Id: I58459bd2eba2ad752fc033e51ee0892e2e069a02 Signed-off-by: Zheng Bao <zheng.bao@amd.com> Signed-off-by: zbao <fishbaozi@gmail.com> Reviewed-on: http://review.coreboot.org/1424 Tested-by: build bot (Jenkins) Reviewed-by: Anton Kochkov <anton.kochkov@gmail.com>
* AMD Hudson: Enable HD audiozbao2012-08-139-91/+499
| | | | | | | | | | | Something about HD audio was scrubbed. Take it back. Change-Id: I0be96fd103f3ebd4e8c7ef09a184b71aa34ee3fd Signed-off-by: Zheng Bao <zheng.bao@amd.com> Signed-off-by: zbao <fishbaozi@gmail.com> Reviewed-on: http://review.coreboot.org/1427 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marcj303@gmail.com>
* gitconfig: upate commit-msg if newer one is availablezbao2012-08-101-1/+7
| | | | | | | | | | Change-Id: Iea010bf6f456a5ce5d8906821c95a7de4b577085 Signed-off-by: Zheng Bao <zheng.bao@amd.com> Signed-off-by: zbao <fishbaozi@gmail.com> Reviewed-on: http://review.coreboot.org/1429 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
* Replicate TOP_MEM and TOP_MEM2 from BSP to AP CPUKyösti Mälkki2012-08-091-28/+21
| | | | | | | | | | | | The search loop for UMA resource was only used to check for the highest RAM address below 4GB. The cached values from BSP CPU can now be used for the replication. Change-Id: I5244ffa6f8a93f5ff5aaf8a71bd006b0f9cd518a Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/1388 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
* AMD northbridge: copy TOP_MEM and TOP_MEM2 for distributionKyösti Mälkki2012-08-099-104/+74
| | | | | | | | | | | | Take a copy of BSP CPU's TOP_MEM and TOP_MEM2 MSRs to be distributed to AP CPUs and factor out the debugging info from setup_uma_memory(). Change-Id: I1acb4eaa3fe118aee223df1ebff997289f5d3a56 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/1387 Tested-by: build bot (Jenkins) Reviewed-by: Zheng Bao <zheng.bao@amd.com> Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
* Sandybridge: Fix integer overrun in romstage udelay()Stefan Reinauer2012-08-091-6/+16
| | | | | | | | | | This was broken, fixing according to related patch for i945 Change-Id: I925cd205ee5beb918181740a7b981a4209688ac6 Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/1412 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
* Synchronize rdtsc instructionsStefan Reinauer2012-08-0910-4/+40
| | | | | | | | | | | | | | | | The CPU can arbitrarily reorder calls to rdtsc, significantly reducing the precision of timing using the CPUs time stamp counter. Unfortunately the method of synchronizing rdtsc is different on AMD and Intel CPUs. There is a generic method, using the cpuid instruction, but that uses up a lot of registers, and is very slow. Hence, use the correct lfence/mfence instructions (for CPUs that we know support it) Change-Id: I17ecb48d283f38f23148c13159aceda704c64ea5 Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/1422 Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Tested-by: build bot (Jenkins)
* Do not allow modifying memory table directlyKyösti Mälkki2012-08-083-9/+2
| | | | | | | | | | | | Adding ranges directly into coreboot memory table raised issues as those methods bypassed the MTRR setup. Such regions are now added as resources, so declare the functions again as static. Change-Id: If78613da40eabc5c99c49dbe2d6047cb22a71b69 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/1415 Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Tested-by: build bot (Jenkins)
* Cleanup coreboot memory table includesKyösti Mälkki2012-08-0864-74/+0
| | | | | | | | | | | The includes removed here were previously required for struct lb_memory and lb_add_memory_range(). Change-Id: Ie6c0d4ef55c2225aa709cf3fbad30ff1080e3610 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/1391 Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Tested-by: build bot (Jenkins)
* Fix SMBIOS generationStefan Reinauer2012-08-083-3/+10
| | | | | | | | | | | | | | | | Dropping mainboard's chip.h broke execution of the mainboard's enable function and the addition of mainboard specific smbios tables. The former was fixed by Kyosti in http://review.coreboot.org/1374 This patch fixes the breakage in static.c and also backs out a small portion of Kyosti's patch (because it's not needed anymore) Change-Id: I6fdea9cbb8c6041663bd36f68f1cae4b435c1f9b Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/1421 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Anton Kochkov <anton.kochkov@gmail.com>
* gitignore: Ignore KDE backup filesAlexandru Gagniuc2012-08-081-0/+9
| | | | | | | | | | | | KDE editors love to create tons of backup files every time a file is edited. This makes it very hard to get useful information from git status and very easy to commit the wrong stuff. Add those to the gitignore list. Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Change-Id: I2fbb907f21d85d6994caa8bbe32c4e9814b5f4b4 Reviewed-on: http://review.coreboot.org/1423 Reviewed-by: Peter Stuge <peter@stuge.se> Tested-by: build bot (Jenkins)
* Drop HAVE_MAINBOARD_RESOURCESKyösti Mälkki2012-08-0884-261/+0
| | | | | | | | | | | | | These existed to provide a hook to add reserved memory regions in the coreboot memory table. Reserved memory are now added as resources. Change-Id: I9f83df33845cfa6973b018a51cf9444dbf0f8667 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/1414 Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Tested-by: build bot (Jenkins) Reviewed-by: Peter Stuge <peter@stuge.se>
* Siemens SiteMP: drop add_mainboard_resources()Kyösti Mälkki2012-08-072-21/+0
| | | | | | | | | | | Use of lb_add_memory_region() is reduntant with the MMCONF resource being set as reserved. Change-Id: I747ea34823692b6966b2e50d22aea1fb89c73c25 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/1394 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
* Move cpus_ready_for_init() to AMD K8Kyösti Mälkki2012-08-0714-23/+9
| | | | | | | | | | The function is a noop for all but amd/serengeti_cheetah. Change-Id: I09e2e710aa964c2f31e35fcea4f14856cc1e1dca Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/1184 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
* Sandy/Ivy Bridge and Cougar/Panther Point: Fix namesStefan Reinauer2012-08-073-14/+2
| | | | | | | | | | | | | The names were set at various times during development, but the way the code works, you might end up with the wrong name being displayed in the logs. Instead of doing magic, just display both names for each component Change-Id: I1f8ce44d156442f5f7d717e1a2b47ed1218d4527 Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/1413 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
* bd82x6x: Add beep commandsDylan Reid2012-08-075-0/+39
| | | | | | | | | | | Move beep commands to board-specific area as they need to be different for different codecs. Change-Id: I2a1ac938c49827cc816a95df10793a7e234942bf Signed-off-by: Dylan Reid <dgreid@chromium.org> Reviewed-on: http://review.coreboot.org/1410 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
* AMD RS690: mark MMCONF resource as reserved MEMKyösti Mälkki2012-08-061-1/+2
| | | | | | | | | | | Use IORESOURCE_RESERVE to exclude the region from system RAM table. Change-Id: I61b51022165e1304a41554f67af75b3089d892af Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/1393 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Reviewed-by: Anton Kochkov <anton.kochkov@gmail.com>
* AMD f15: Change multiply ONE_MB to bit shifting (Propagation)zbao2012-08-051-7/+7
| | | | | | | | | | | | | | | Apply the change http://review.coreboot.org/1263 to family15 northbridge. Change-Id: If1109f20ffd833a716e092c5e4f6f16ee6b968c7 Signed-off-by: Zheng Bao <zheng.bao@amd.com> Signed-off-by: zbao <fishbaozi@gmail.com> [km: rebased] Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/1405 Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Tested-by: build bot (Jenkins)
* AMD SB: Call the rtc update if needed (Propagation)zbao2012-08-056-2/+30
| | | | | | | | | | | | | Apply the change http://review.coreboot.org/1390 to all the AMD southbridge. Change-Id: I8e94014f8883a0408b68355d9aa33aea4373881f Signed-off-by: Zheng Bao <zheng.bao@amd.com> Signed-off-by: zbao <fishbaozi@gmail.com> Reviewed-on: http://review.coreboot.org/1406 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
* Technexion TIM5690: drop add_mainboard_resources()Kyösti Mälkki2012-08-052-4/+6
| | | | | | | | | | | Move the POST display to take place just before jumping the payload, a bit later than before. Change-Id: Ie1d1ff24dc6c1640e25681be7dc5740943c7f112 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/1396 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
* AMD S3: Remove the hardcoded volatile positionzbao2012-08-053-5/+10
| | | | | | | | | Change-Id: I4bcf3f3435f0ba487955d14ed1b010fd94b9f625 Signed-off-by: Zheng Bao <zheng.bao@amd.com> Signed-off-by: zbao <fishbaozi@gmail.com> Reviewed-on: http://review.coreboot.org/1408 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
* AMD Thatcher: Add BIOS callback hook for getting VBIOS Imagezbao2012-08-042-0/+14
| | | | | | | | | | | | | Apply the change http://review.coreboot.org/1351 to thatcher. Change-Id: I33e7ad0cad2ae06f5934c60939d60a18444aa24e Signed-off-by: Zheng Bao <zheng.bao@amd.com> Signed-off-by: zbao <fishbaozi@gmail.com> Reviewed-on: http://review.coreboot.org/1407 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
* Add a capability for mainboard-specific posting.Alexandru Gagniuc2012-08-042-0/+17
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Some mainboards have really nice capabilities for posting, beyond simple POST cards. Further, some can not use a POST card. This change defines a weak symbol (mainboard_post) that can be overridden by a real mainboard_post function. If, for example, you'd like to do something fancy before the payload starts, you can add this to mainboard.c: void mainboard_post(u8 value) { switch(value){ case POST_TIME_TO_PARTY: some_fancy_lights(); break; } } Maybe the post function should be an entry in the device. We're beginning to over-use weak symbols. BUG=None TEST=Build and boot a google chromebook. Observe that it still works. Use it to drive some pretty lights. Change-Id: I3512d2ec34a66c747287191851c3f68b6a7cc1b2 Signed-off-by: Ronald G. Minnich <rminnich@gmail.com> Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Reviewed-on: http://review.coreboot.org/1397 Tested-by: build bot (Jenkins)
* Perform additional programming requirements for SATAStefan Reinauer2012-08-042-5/+46
| | | | | | | | | | In accordance to PCH EDS 14.1.35.1 Change-Id: I2e6cec6d4f49f404e33a171a8fbd6e4880327896 Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/1411 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
* Make the device tree available in the rom stageStefan Reinauer2012-08-0411-31/+158
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | We thought about two ways to do this change. The way we decided to try was to 1. drop all ops from devices in romstage 2. constify all devices in romstage (make them read-only) so we can compile static.c into romstage 3. the device tree "devices" can be used to read configuration from the device tree (and nothing else, really) 4. the device tree devices are accessed through struct device * in romstage only. device_t stays the typedef to int in romstage 5. Use the same static.c file in ramstage and romstage We declare structs as follows: ROMSTAGE_CONST struct bus dev_root_links[]; ROMSTAGE_CONST is const in romstage and empty in ramstage; This forces all of the device tree into the text area. So a struct looks like this: static ROMSTAGE_CONST struct device _dev21 = { #ifndef __PRE_RAM__ .ops = 0, #endif .bus = &_dev7_links[0], .path = {.type=DEVICE_PATH_PCI,{.pci={ .devfn = PCI_DEVFN(0x1c,3)}}}, .enabled = 0, .on_mainboard = 1, .subsystem_vendor = 0x1ae0, .subsystem_device = 0xc000, .link_list = NULL, .sibling = &_dev22, #ifndef __PRE_RAM__ .chip_ops = &southbridge_intel_bd82x6x_ops, #endif .chip_info = &southbridge_intel_bd82x6x_info_10, .next=&_dev22 }; Change-Id: I722454d8d3c40baf7df989f5a6891f6ba7db5727 Signed-off-by: Ronald G. Minnich <rminnich@chromium.org> Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/1398 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
* AMD f15 nb: Remove the misleading 0x100 from the limitk (Propagation)zbao2012-08-042-3/+3
| | | | | | | | | | | | | Apply the change http://review.coreboot.org/1265 to all the AMD northbridge. Change-Id: Idf3994c1e9ec76cd19db9f740d825cf24059884f Signed-off-by: Zheng Bao <zheng.bao@amd.com> Signed-off-by: zbao <fishbaozi@gmail.com> Reviewed-on: http://review.coreboot.org/1404 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
* AMD NB: Limit the device field to 5 bits. (Propagation)zbao2012-08-045-8/+16
| | | | | | | | | | | | | Apply the change http://review.coreboot.org/1264 to all the AMD northbridge. Change-Id: Ied74d6f579d2c0350288e2619d7810f8d44fa574 Signed-off-by: Zheng Bao <zheng.bao@amd.com> Signed-off-by: zbao <fishbaozi@gmail.com> Reviewed-on: http://review.coreboot.org/1403 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
* SuperIO LPC47N217: Remove warningszbao2012-08-042-5/+6
| | | | | | | | | Change-Id: Id5756f1bb748ae7bec0bcdc21804f5338e850baa Signed-off-by: Zheng Bao <zheng.bao@amd.com> Signed-off-by: zbao <fishbaozi@gmail.com> Reviewed-on: http://review.coreboot.org/1402 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
* AMD Parmer: Remove warning.zbao2012-08-042-7/+1
| | | | | | | | | Change-Id: I4ba2d480fa6df5ee741d887d26524b32c1901d73 Signed-off-by: Zheng Bao <zheng.bao@amd.com> Signed-off-by: zbao <fishbaozi@gmail.com> Reviewed-on: http://review.coreboot.org/1399 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
* VIA Epia-N: drop add_mainboard_resources()Kyösti Mälkki2012-08-031-19/+0
| | | | | | | | | | | | The board had HAVE_MAINBOARD_RESOURCES=0 so this was never called. Drop unnecessary includes too. Change-Id: Ia7bddf29a16966c052b5cabbb47029299e6dbd12 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/1392 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Reviewed-by: Anton Kochkov <anton.kochkov@gmail.com>
* Intel CPUs: Fix counting of CPU coresKyösti Mälkki2012-08-032-9/+32
| | | | | | | | | | | | | | Detection for a hyper-threading CPU was not compatible with multicore CPUs. When using CPUID eax==4, also need to set ecx=0. CAR init tested on real hardware with hyper-threading model_f25 and under qemu 0.15.1 with multicore CPU. Change-Id: I28ac8790f94652e4ba8ff88fe7812c812f967608 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/1172 Tested-by: build bot (Jenkins) Reviewed-by: Anton Kochkov <anton.kochkov@gmail.com>
* Fix mainboard level enable_dev()Kyösti Mälkki2012-08-033-6/+3
| | | | | | | | | | | | Commit 188e3c2ff06a82f61d7d71e610b32b1a250c0a45 dropped mainboard out of the static device tree. This left dev_root->chip_ops unset, and mainboard_ops.enable_dev() was no longer called. Change-Id: I6d447c8049a66041b8bb36ec9aac3e7e0d20a99b Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/1374 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
* RTC: Add a routine to check if the CMOS date is validzbao2012-08-022-8/+40
| | | | | | | | | | | | | | | | | | | If the CMOS is cleared or someone writes some random date/time on purpose, the CMOS date register has a invalid date. This will hurts some OS, like Windows 7, which hangs at MS logo forever. When we detect that, we need to write a reasonable date in CMOS. Alexandru Gagniuc: Hmm, it would be interesting to use the date the coreboot image was built and set that as the default date. At least until time travel is invented. Change-Id: Ic1c7a2d60e711265686441c77bdf7891a7efb42e Signed-off-by: Zheng Bao <zheng.bao@amd.com> Signed-off-by: zbao <fishbaozi@gmail.com> Reviewed-on: http://review.coreboot.org/1389 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
* Limit the device field to 5 bits.zbao2012-08-021-2/+2
| | | | | | | | | | | | | | The field device in PCI_ADDRESS only takes 5 bits. So if the device number is more than 32, it will truncated to 5 bits. Before this patch, other pci devices will be incorrectly probed as processor node. Change-Id: I64dcd4f4fda7b7080a9905dce580feb829584b94 Signed-off-by: Zheng Bao <zheng.bao@amd.com> Signed-off-by: zbao <fishbaozi@gmail.com> Reviewed-on: http://review.coreboot.org/1264 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com> Reviewed-by: Anton Kochkov <anton.kochkov@gmail.com>
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