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* soc/qualcomm/sc7180: Fix set but unused variablesArthur Heymans2023-05-122-7/+0
| | | | | | | | | | | This fixes clang warnings. Change-Id: I407da6ec05ef646f61bd81e314fee1b5ea659192 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74557 Reviewed-by: Julius Werner <jwerner@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
* vendorcode/cavium: Fix set but unused variablesArthur Heymans2023-05-123-18/+2
| | | | | | | | | | | | TEST: BUILD_TIMELESS=1 remains the same. Change-Id: Id2cb37dbe4d450fe7f91a527b5cd73ac55863548 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74542 Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
* mb/prodrive/hermes: Simplify handling board cfgAngel Pons2023-05-122-28/+7
| | | | | | | | | | | | | The `get_board_settings()` function always returns non-NULL, so there is no need for NULL checks. When only one member is accessed, also drop the local variable and directly dereference the function's return value. Change-Id: I4fc62ca2454f4da7c8ade506064a7b0e6ba48749 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/75140 Reviewed-by: Christian Walter <christian.walter@9elements.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
* drivers/ocp/ewl: Add EWL driver for EWL type 3 error handlingJohnny Lin2023-05-124-0/+77
| | | | | | | | | | | | | 1. Restore the reverted 'commit 059902882ce5 ("drivers/ocp/ewl: Add EWL driver for EWL type 3 error handling")'. 2. Print more EWL type 3 error information when it occurs. Change-Id: Ib83b7653a839d18a065b929127549acd10bce7a7 Signed-off-by: Johnny Lin <johnny_lin@wiwynn.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/69280 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jonathan Zhang <jon.zhixiong.zhang@gmail.com>
* mb/siemens/mc_ehl5: Add PTN3460 eDP-to-LVDS bridgeMario Scheithauer2023-05-125-3/+105
| | | | | | | | | | | | | | | | | | | | | This mainboard contains in addition to its base variant, mc_ehl2, an LCD panel driven through the PTN3460 eDP-to-LVDS bridge. This patch enables the PTN3460 support by adding the device to devicetree.cb and board-specific configuration parameters in lcd_panel.c. BUG=none TEST=Boot with the LCD panel attached and observe whether the picture is stable and free of artifacts coming from wrong resolution and timing. Change-Id: I196d7ceeb7ac241c9b95db2ef791a5f3ff7890a7 Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74936 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jan Samek <jan.samek@siemens.com> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
* mb/siemens/mc_ehl5: Add new board variant based on mc_ehl2Mario Scheithauer2023-05-128-0/+564
| | | | | | | | | | | | | This mainboard is based on mc_ehl2. In a first step, it contains a copy of mc_ehl2 directory with minimum changes. Special adaptations for mc_ehl5 mainboard will follow in separate commits. Change-Id: Id80f8eb49dd2fed0ed1ffc479d47d8669eca84c9 Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74935 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
* mb/google/nissa/var/uldren: Fix Touch screen power sequenceIan Feng2023-05-121-0/+7
| | | | | | | | | | | | | | | | | | Based on touchscreen product spec. For uldren variants with a touchscreen, drive the enable GPIO high starting in romstage while holding in reset, then disable the reset GPIO in ramstage (done in the baseboard). BUG=b:279989974 TEST=Build and boot to OS in uldren. Touch screen is workable. Change-Id: Ib1b1ce80aa1dd8c312e3663fc50c9e9f53cc07fe Signed-off-by: Ian Feng <ian_feng@compal.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74835 Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com> Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
* mb/prodrive/atlas: Shorten FSP-M UPD statementsAngel Pons2023-05-121-24/+25
| | | | | | | | | | | | | Replace `memupd->FspmConfig.` with `mcfg->` for the sake of brevity. Change-Id: If2e7cccca955b0c1e07c1ecf100d29a923107856 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/75136 Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com> Reviewed-by: Maximilian Brune <maximilian.brune@9elements.com> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Benjamin Doron <benjamin.doron00@gmail.com>
* mb/google/rex: Set WWAN_RF_DISABLE_ODL to NCTarun Tuli2023-05-121-1/+1
| | | | | | | | | | | | | | | | This signal isn't functionally being used and is causing leakage during suspend. Set it to NC. BUG=b:279762779 TEST=builds. WWAN functional. Change-Id: I93f2b0a781e250678280b57e4ab1d80ef27ff460 Signed-off-by: Tarun Tuli <taruntuli@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/75053 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Kapil Porwal <kapilporwal@google.com>
* soc/intel/common: Define enum types for MKHI group IDs and ME SKUsSridhar Siricilla2023-05-121-8/+12
| | | | | | | | | | | | | | | The patch defines enum type for MKHI group IDs and ME SKU types instead of macros. TEST=Build code for Rex Signed-off-by: Sridhar Siricilla <sridhar.siricilla@intel.com> Change-Id: I102e802938a6a664a43a362d90a26755cff8f316 Reviewed-on: https://review.coreboot.org/c/coreboot/+/74996 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Harsha B R <harsha.b.r@intel.com> Reviewed-by: Anil Kumar K <anil.kumar.k@intel.com> Reviewed-by: Ronak Kanabar <ronak.kanabar@intel.com>
* soc/intel/common: Remove superfluous cmos_offset from ramtopSean Rhodes2023-05-121-3/+3
| | | | | | | | | | | | Having `_cmos_offset` in a CMOS offset is superfluous; remove it so the CMOS entry is just `ramtop`. Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: Ibc1e7d78d2e3ae04330d19e64c3437ff07060ea8 Reviewed-on: https://review.coreboot.org/c/coreboot/+/74516 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
* mb/prodrive/atlas: Make default SN/PN not emptyAngel Pons2023-05-121-2/+7
| | | | | | | | | | | If reading the serial/part number fails, returning an empty string is very confusing. Instead, return "INVALID" to make problems obvious. Change-Id: I3c174ca76d51b44456c7b68f4fcffb4c8f9379be Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/75132 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Benjamin Doron <benjamin.doron00@gmail.com>
* mb/asus/p8z77-m: Make onboard NIC a child device below PCIe port 5Fabian Groffen2023-05-121-1/+4
| | | | | | | | | | | | | The Realtek RTL8111F NIC is currently not defined at all, nor as a child device, resulting in the on_board flag not being set to 1. This means that Linux / udev will call the device enp3s0 rather than eno0, as it's appropriate for on-board ethernet devices. Signed-off-by: Fabian Groffen <grobian@gentoo.org> Change-Id: I95f01a466a59234d1cbe2420f208bf58ae28fcc6 Reviewed-on: https://review.coreboot.org/c/coreboot/+/75106 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
* mb/asus/p8z77-m: Add TPM configFabian Groffen2023-05-122-0/+4
| | | | | | | | | | | This board has a TPM connector, enable support for it. Signed-off-by: Fabian Groffen <grobian@gentoo.org> Change-Id: I1861df95eef15bc2bd29412240d61456eaaad8c9 Reviewed-on: https://review.coreboot.org/c/coreboot/+/75105 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
* mb/google/brya: Fix typo in gma-mainboards filenameTarun Tuli2023-05-121-0/+0
| | | | | | | | | | | | | | | | | | Small typo in brask/gma-mainboards-ads Should be brask/gma-mainboards.ads BUG=b:277861633 BRANCH=firmware-brya-14505.B TEST=Builds Change-Id: I9800870dcef13a3e16f6235137e79234a5e6bf83 Signed-off-by: Tarun Tuli <taruntuli@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/75052 Reviewed-by: Eran Mitrani <mitrani@google.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
* acpi/acpigen: add acpigen_resource_io to generate I/O resourceFelix Held2023-05-112-0/+15
| | | | | | | | | | | | Add the acpigen_resource_io helper function to generate an I/O range resource. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Change-Id: I177f59b52d4dbbff0a3ceeef5fc8c7455cef9ff8 Reviewed-on: https://review.coreboot.org/c/coreboot/+/75044 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <inforichland@gmail.com>
* acpi/acpigen: add acpigen_resource_bus_number to generate bus numberFelix Held2023-05-112-0/+16
| | | | | | | | | | | | Add the acpigen_resource_bus_number helper function to generate a bus number range resource. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Change-Id: Ib1f1da3dbe823c6bc4fc30c0622653410cfbf301 Reviewed-on: https://review.coreboot.org/c/coreboot/+/75043 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <inforichland@gmail.com>
* drivers/pcie/generic: Add DmaProperty to configMark Hasemeyer2023-05-112-0/+6
| | | | | | | | | | | | | | | | | | | | Adds the option to set the 'DmaProperty' in the device's _DSD. This can be done by setting "add_acpi_dma_property"="true". If not set (or set to false), the device descriptor generation behavior will remain unchanged. The naming convention for the config option was chosen to match that of other drivers. This partially reverts commit 5609f7a684c6 ("drivers/pcie/generic: Clean up driver") as the driver is now used on a couple mainboards which need the DmaProperty. Change-Id: I996fe4923948d13a20bf8b6b1a93dab0866d0fd4 Signed-off-by: Mark Hasemeyer <markhas@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/75094 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jan Samek <jan.samek@siemens.com> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
* soc/intel/apollolake: Only use 8 bits for afterg3Sean Rhodes2023-05-111-6/+7
| | | | | | | | | | | | In GEN_PMCON1 (Offset 1020h), Bit 0 is the "After G3 Enable" (ag3e) (source Intel document #569262). Only use 8 bits, in the same way as most other Intel SOCs do, for pmc_soc_set_afterg3_en. Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: Idb290d1480b03cb3425edc6ff29b9c78a6545df1 Reviewed-on: https://review.coreboot.org/c/coreboot/+/74955 Reviewed-by: Matt DeVillier <matt.devillier@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* util/scripts/show_platforms.sh: Fix reStructuredText table outputNicholas Chin2023-05-111-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | reStructuredText grid tables require row separators otherwise the rows get concatenated into a single cell for each column. Representative output of previous behavior: ```eval_rst +-------------------------+-------------------+------------+----------+ | Vendor/Board | Processor | Date added | Brd type | +=========================+===================+============+==========+ | 51nb/x210 | INTEL_KABYLAKE | 2020-03-16 | laptop | | acer/aspire_vn7_572g | INTEL_SKYLAKE | 2022-01-28 | laptop | | acer/g43t-am3 | INTEL_X4X | 2020-09-28 | desktop | +-------------------------+-------------------+------------+----------+ ``` Representative output of corrected behavior: ```eval_rst +-------------------------+-------------------+------------+----------+ | Vendor/Board | Processor | Date added | Brd type | +=========================+===================+============+==========+ | 51nb/x210 | INTEL_KABYLAKE | 2020-03-16 | laptop | +-------------------------+-------------------+------------+----------+ | acer/aspire_vn7_572g | INTEL_SKYLAKE | 2022-01-28 | laptop | +-------------------------+-------------------+------------+----------+ | acer/g43t-am3 | INTEL_X4X | 2020-09-28 | desktop | +-------------------------+-------------------+------------+----------+ ``` Change-Id: I83be58dd2c34c65ae2c65cf2bd98330936fb6f6a Signed-off-by: Nicholas Chin <nic.c3.14@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/72624 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
* mb/google/brya: Create gothrax variantYunlong Jia2023-05-118-0/+45
| | | | | | | | | | | | | | | | | | Create the gothrax variant of the nissa reference board by copying the template files to a new directory named for the variant. (Auto-Generated by create_coreboot_variant.sh version 4.5.0.). BUG=279614675 BRANCH=None TEST=util/abuild/abuild -p none -t google/brya -x -a make sure the build includes GOOGLE_GOTHRAX Signed-off-by: Yunlong Jia <yunlong.jia@ecs.corp-partner.google.com> Change-Id: I129e4a55e4b87091e425a45392024d04f3977c79 Reviewed-on: https://review.coreboot.org/c/coreboot/+/74748 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Derek Huang <derekhuang@google.com>
* mb/google/dedede/var/boxy: Disable EXT_VRKevin Yang2023-05-111-0/+3
| | | | | | | | | | | | | | The boxy removed the APW8738BQBI-TRG and "disable_external_bypass_vr" should be set to "1" to disable BUG=b:271407334 TEST=emerge-dedede coreboot Signed-off-by: Kevin Yang <kevin3.yang@lcfc.corp-partner.google.com> Change-Id: Ic6667e93de41e84f67363ab7554fe755fe50684a Reviewed-on: https://review.coreboot.org/c/coreboot/+/74889 Reviewed-by: Derek Huang <derekhuang@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* mb/google/dedede/var/boxy: Update devicetree and GPIO tableKevin Yang2023-05-113-18/+270
| | | | | | | | | | | | | | | | | | | | | | Create overridetree and GPIO config based on latest schematic: 1. Update PCIe ports 2. Update USB ports 3. Remove unused I2Cs 4. Remove unused peripherals (SD card, eDP, speakers) 5. Add LAN 6. Thermal policy for updated temp sensors BUG=b:277529068 BRANCH=dedede TEST=build Signed-off-by: Kevin Yang <kevin3.yang@lcfc.corp-partner.google.com> Change-Id: I5a155ebca50dbd5bdb046713ebabbee395361273 Reviewed-on: https://review.coreboot.org/c/coreboot/+/74626 Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Derek Huang <derekhuang@google.com>
* soc/intel/cmn/blk.cse: Fix check condition in store_cse_rw_fw_version()Dinesh Gehlot2023-05-111-1/+1
| | | | | | | | | | | | | | | | | | | | | | | The return value of cse_get_bp_info() is an enum integer, where zero means success and non-zero means failure. The function store_cse_rw_fw_version() calls the function cse_get_bp_info() and validates the return value as a boolean causing prematurely returns of the parent API even if cse_get_bp_info() is successful. This patch corrects this logical error by returning only if cse_get_bp_info() fails. TEST=Build and boot google/nivviks and verify that the ISH version info command is only being sent during cold boot. Signed-off-by: Dinesh Gehlot <digehlot@google.com> Change-Id: Ice278e5ac69ff2f2c9f1936b76d71ae9deb6f855 Reviewed-on: https://review.coreboot.org/c/coreboot/+/74998 Reviewed-by: Kapil Porwal <kapilporwal@google.com> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
* acpi/acpi.c: Assign coreboot_rsdp for QEMUBin Meng2023-05-111-0/+1
| | | | | | | | | | | | | | | | | | At present coreboot_rsdp remains unset for QEMU, which results in an incomplete LB_TAG_ACPI_RSDP coreboot table generated. Fix this by assigning coreboot_rsdp properly. TEST=Build coreboot for QEMU x86 i440fx (default) with U-Boot x86 as the payload, boot coreboot.rom with QEMU, and run 'acpi list' from U-Boot shell to show the ACPI tables. Signed-off-by: Bin Meng <bmeng@tinylab.org> Change-Id: I5bc3f0528d4431fd388ca52b8865f9be0e1faf92 Reviewed-on: https://review.coreboot.org/c/coreboot/+/75088 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Tim Wawrzynczak <inforichland@gmail.com>
* mb/google/brya/variant/hades: Reduce PEXVDD shutoff delay for HadesTarun Tuli2023-05-112-1/+9
| | | | | | | | | | | | | | | | | | | For the sequenced controlled shutdown path, there's a 10ms delay after the PEXVDD rail is disabled to permit discharge needed on Agah/Proxima. This can be dropped to 3ms for Hades designs Proto0 and forward. Once Agah board is dropped, "if CONFIG" can be cleaned up/removed. BUG=b:271167335 TEST=builds Signed-off-by: Tarun Tuli <taruntuli@google.com> Change-Id: I8a0d62ec76caff861adce2d6c0ba2d4e4064affa Reviewed-on: https://review.coreboot.org/c/coreboot/+/75051 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* mb/siemens/mc_apl5: Set Full Reset Bit into Reset Control RegisterMario Scheithauer2023-05-111-0/+6
| | | | | | | | | | | | | | | | | | With the introduction of a new Linux version a problem has appeared after a software initiated reset via CF9h register. The problem manifests itself in the fact that the Linux kernel does not start after the reboot. The problem is solved by setting bit 3 to 1 in Reset Control Register (I/O port CF9h). This leads to the fact that the PCH will drive SLP_S3 active low in the reset sequence. It leads to the same behavior as in commit 04ea73ee78bc ("siemens/mc_apl3: Set Full Reset Bit into Reset Control Register") explained. Change-Id: Ia8b7f997ca6234add569da751e1070144790e258 Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/75041 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jan Samek <jan.samek@siemens.com> Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
* mb/siemens/mc_apl: Correct multi-line comment style for all Siemens APL BoardsMario Scheithauer2023-05-1114-231/+153
| | | | | | | | | Change-Id: I6578aee52e6900b25441dc119383856acc480231 Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/75042 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jan Samek <jan.samek@siemens.com> Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
* mb/siemens/mc_ehl: Remove '_' from mainboard model option in Kconfig.nameMario Scheithauer2023-05-111-2/+2
| | | | | | | | | | | | | An underscore has crept into the mainboard model option for mc_ehl3 and mc_ehl4 by mistake. This patch fixes the incorrect entry. Change-Id: Ie59619877fb6341a5bbfe91c13e7692943480ad0 Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/75040 Reviewed-by: Jan Samek <jan.samek@siemens.com> Reviewed-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* mb/siemens/mc_ehl1: Use SSD type for SATA portsMario Scheithauer2023-05-111-0/+2
| | | | | | | | | | | | | | | | There are only SSD connected to SATA ports on this mainboard. To prevent misbehavior, set the correct hard drive type for enabled SATA ports. BUG=none TEST=Boot into OS and check the stability of the SSD Change-Id: I116b1e36f0582956604c3c2508961ffb3de0898a Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74947 Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jan Samek <jan.samek@siemens.com> Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
* Documentation: Fix broken URLsNicholas Chin2023-05-112-5/+6
| | | | | | | | | | | | | | | | | | | | - VBT information: The link from 01.org is dead, but appears to have been identical to the i915 page in the Linux kernel docs based on snapshots on archive.org. - Cgit: coreboot no longer has cgit running for the repos it hosts, and these links redirect to the Gitiles list of repos hosted on review.coreboot.org. Based on snapshots on archive.org, these used to link to the individual repo or tree. Replace these with an equivalent Gitiles link. Change-Id: Id0bfee7b806c851fbe1dcf357e14d9b593e8569a Signed-off-by: Nicholas Chin <nic.c3.14@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74188 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de> Reviewed-by: Patrick Georgi <patrick@coreboot.org>
* soc/intel/common: Fix long delay when ME is disabledSean Rhodes2023-05-111-3/+15
| | | | | | | | | | | | | | | | | | | | | | If the ME is disabled with the `me_state` CMOS setting, boot times are approximately 5 seconds longer: 942:before sending EOP to ME 1,240,773 (5,599) 943:after sending EOP to ME 6,263,951 (5,023,177) Total Time: 6,167,443 This is because the current code only checks if the ME is disabled for CSE LITE SKUs. With this patch, boot times are approximately 5 seconds quicker: Total Time: 1,143,932 Tested on `starbook/adl` and `starbook/tgl`. Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: I182f30d4fbf43955747c6a7a0b284a43f9c5e4ef Reviewed-on: https://review.coreboot.org/c/coreboot/+/74435 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
* util/inteltool: Add ADL-S device identificationsMaximilian Brune2023-05-115-0/+15
| | | | | | | | | | | | | R680E, Q670E, H610E are the ADL-S IoT variants see also: commit a0bc90e4abfe ("Add missing ADL-S device identification") Signed-off-by: Maximilian Brune <maximilian.brune@9elements.com> Change-Id: I1dbfa0464bc22f9bcf91d9e9fa9eb79132600175 Reviewed-on: https://review.coreboot.org/c/coreboot/+/74360 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
* vc/intel/fsp/mtl: Update header files from 3084_85 to 3165_81Kilari Raasi2023-05-112-787/+784
| | | | | | | | | | | | | | | | | | | | | | | | | | Update header files for FSP for Meteor Lake platform to version 3165_81, previous version being 3084_85. FSPM: 1. Change UPD name from 'GtExtraTurboVoltage' to 'GtAdaptiveVoltage' 2. Change UPD name from 'CoreVoltageAdaptive' to 'CoreAdaptiveVoltage' 3. Change UPD name from 'RingVoltageAdaptive' to 'RingAdaptiveVoltage' 4. Address offset changes FSPS: 1. Remove deprecated UPD 'PcieDpc' 2. Address offset changes BUG=b:280005256 TEST=Able to build and boot google/rex to ChromeOS. Signed-off-by: Kilari Raasi <kilari.raasi@intel.com> Change-Id: I67939ecf71166fca4f3d2d6cd4622215bebc5718 Reviewed-on: https://review.coreboot.org/c/coreboot/+/74803 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Ronak Kanabar <ronak.kanabar@intel.com> Reviewed-by: Dinesh Gehlot <digehlot@google.com> Reviewed-by: Kapil Porwal <kapilporwal@google.com>
* soc/intel/meteorlake: Increase pcie snoop/non-snoop latencyRavi Sarawadi2023-05-111-0/+12
| | | | | | | | | | | | | | | | This fixes an issue where pcie was not power gating and blocked S0ix entry. Overwrite pcie max non-snoop and snoop latency tolerance values to 15.73ms as stated in doc #729123 - MTL External Design Specification. BUG=none TEST=Boot google/rex, print/check values. Signed-off-by: Ravi Sarawadi <ravishankar.sarawadi@intel.corp-partner.google.com> Change-Id: I9dfb9edbac95d28d50653777466ea172be64f612 Reviewed-on: https://review.coreboot.org/c/coreboot/+/68308 Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* Documentation/tutorial: Improve clarity of Part 1Nicholas Chin2023-05-111-5/+42
| | | | | | | | | | | | | | | | | | | | | | | | Based on feedback and experiences from new coreboot users, it isn't clear that Tutorial 1 is mainly intended to set up the toolchain and will not produce a bootable ROM for their board. Thus, add a note explicitly mentioning this with a short explanation. The process of manually building and adding the payload is also unusual, since payloads are usually handled automatically by the build system. This adds a note in the summary to provide an explanation of this. The savedefconfig output is also outdated, as Kconfig now outputs additional lines (even though many of those are the same as the defaults). This has caused confusion, leading users to think that they may have configured coreboot incorrectly. Update this to the current defconfig contents and add a note that this may change depending on the coreboot version. Change-Id: I13206aa05a425ddfe33ee35feff0db490585a59f Signed-off-by: Nicholas Chin <nic.c3.14@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/73816 Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* soc/intel: Clean up some includesKyösti Mälkki2023-05-108-16/+13
| | | | | | | | Change-Id: Ibb680bb8f94fb8a2812f420ac38f15684b5c0b4f Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74978 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
* sb,soc/amd,intel: Sync FADT entries visuallyKyösti Mälkki2023-05-106-7/+13
| | | | | | | | Change-Id: I20a66dce1612ab4394c26f9b0943dac14bcdcfc4 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74912 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
* Documentation/contributing: Update sign-off procedureNicholas Chin2023-05-101-3/+5
| | | | | | | | | | | | | | | | | | | | The Linux kernel recently updated the wording of their sign-off procedure, changing the ambiguous "real name" requirement to "a known identity" and dropping "no pseudonyms". Anonymous contributions remain uncommittable [1]. As discussed in the April 19, 2023 leadership meeting, update our policy to go along with Linux and flashrom (who also updated their policy). [1] Linux kernel commit d4563201f3 (Documentation: simplify and clarify DCO contribution example language) Change-Id: Ie676334f7c1509524adcb8dbb78495fb4da35ede Signed-off-by: Nicholas Chin <nic.c3.14@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74851 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <patrick@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
* Documentation/contributing: Add sign-off procedureNicholas Chin2023-05-101-1/+51
| | | | | | | | | | | | | | Currently, this only exists on the old wiki and the developers.html page on coreboot.org, but it really ought to be somewhere in the new docs alongside the other contribution guidelines. This was largely copied from the text from the developers.html page. Change-Id: If50b3827ab36234719f9a90239caec4612eb6762 Signed-off-by: Nicholas Chin <nic.c3.14@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74825 Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
* soc/intel/cmn/pcie: Allow SoC to overwrite snoop/non-snoop latencyBora Guvendik2023-05-102-2/+14
| | | | | | | | | | | | | | | | | | The Intel SoC Meteor Lake requires a higher pcie max non-snoop and snoop latency tolerance. Add config to let SoC overwrite the common code settings if needed. BUG=none TEST=Boot google/rex and print/check if able to overwrite values. Change-Id: Ic2b9a158d219e6c6e7f6e7f0ae0f093c1183b402 Signed-off-by: Bora Guvendik <bora.guvendik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74141 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kapil Porwal <kapilporwal@google.com> Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
* soc/intel/elkhartlake: Make hard drive type for SATA ports configurableMario Scheithauer2023-05-102-0/+2
| | | | | | | | | | | | | | | | Intel's EHL FSP offers the possibility to select the connected hard drive type to SATA ports. One has the option to choose between HDD ('0' - default) and SSD ('1'). This patch provides a chip config so that this FSP parameter can be set as needed in the devicetree on mainboard level. Change-Id: Idb03aff5b6c5df592b47e2f4abe4fe58ac7151ba Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74946 Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
* mb/amd/mayan: Enable MXM PCIe slotAnand Vaikar2023-05-102-1/+19
| | | | | | | | | | Follow the EC GPIO programming sequence to enable the MXM PCIe slot. Change-Id: I75d7ac488bb005751e6f674ab9a2fd99baad571b Signed-off-by: Anand Vaikar <a.vaikar2021@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74308 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
* mb/google/link: Apply symmetry for EC events definesKyösti Mälkki2023-05-094-18/+16
| | | | | | | | | | All other boards use MAINBOARD_ prefix instead of board name. Change-Id: I97d9d28963c97e780156d75b39deac069028866a Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74602 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
* arch/x86/car.ld: Fix undefined macroArthur Heymans2023-05-091-1/+1
| | | | | | | | | | | | Processing LD flags is done without most warnings enabled, which is why this never caused problems. Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Change-Id: Ic9d82c1426a1c1d2f21c8e7560685cf9d7106a88 Reviewed-on: https://review.coreboot.org/c/coreboot/+/75033 Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* mb/google,intel: Use common ChromeEC code for lid shutdownKyösti Mälkki2023-05-0910-177/+56
| | | | | | | | | Change-Id: I4d34e5c094440dad4a6ab9adc67d3da6b71ac2bf Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74514 Reviewed-by: Matt DeVillier <matt.devillier@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
* mb/google,intel: Use common ChromeEC code for SMI APMCKyösti Mälkki2023-05-096-96/+12
| | | | | | | | | | Change-Id: If4b7c2b94e0fec84831740336ccdbea0922ffbfe Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74513 Reviewed-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
* mb/purism: Move selects from Kconfig.name to KconfigFelix Singer2023-05-096-19/+37
| | | | | | | | | | Selects should be done in the Kconfig file instead of Kconfig.name. Change-Id: I2ae03a3ac548674b8c5e7dfaff47d6c536b452f1 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/75013 Reviewed-by: Jonathon Hall <jonathon.hall@puri.sm> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* sb,soc/amd,intel: Apply minor FADT fixesKyösti Mälkki2023-05-094-9/+9
| | | | | | | | Change-Id: I27a610255e5680be1b507d45c6695cf9419ee052 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74911 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
* mb/google,intel,samsung: Use common poweroff()Kyösti Mälkki2023-05-093-7/+7
| | | | | | | | Change-Id: I3881c152663a038833d8126d7f24f2a6688426d1 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74515 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
generated by cgit v1.2.3 (git 2.25.1) at 2024-06-06 21:25:30 +0000