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* Add AP detection to stage0 to prevent APs from re-initializing mainboard setupMarc Jones2009-02-109-59/+73
| | | | | | | | | | | | | that has already been done by the BSP. For single processor systems the CPU flag is always 0, BSP. This code also moves the AP stop for K8 mainboards to after memory setup so the AP's MTRRs can be setup to match system memory. Signed-off-by: Marc Jones <marcj303@gmail.com> Acked-by: Peter Stuge <peter@stuge.se> git-svn-id: svn://coreboot.org/repository/coreboot-v3@1129 f3766cd6-281f-0410-b1cd-43a5c92072e9
* Setup the MTRRs in stage1 so that memory and cache are available throughoutMarc Jones2009-02-106-99/+169
| | | | | | | | | | | | | stage2. This fixes problems with VGA graphics ROMs access to 0xA0000-0xBFFFF. It also sets all system memory to WriteBack cached and sets the ROM area to cached. Signed-off-by: Marc Jones <marcj303@gmail.com> Acked-by: Peter Stuge <peter@stuge.se> git-svn-id: svn://coreboot.org/repository/coreboot-v3@1128 f3766cd6-281f-0410-b1cd-43a5c92072e9
* Coreboot uses the compiler option -mregparm=3 which causes variables to Marc Jones2009-02-101-1/+1
| | | | | | | | | | | | | | | | be passed in registers. This is good for size and speed but not good when we call a C function from asm. Force stage1_phase1 to use stdcall and get variables off the stack. Note that I didn't change stage1_phase3 because it doesn't use any variables. Signed-off-by: Marc Jones <marcj303@gmail.com> Acked-by: Peter Stuge <peter@stuge.se> git-svn-id: svn://coreboot.org/repository/coreboot-v3@1127 f3766cd6-281f-0410-b1cd-43a5c92072e9
* Move Plugin menu and make it depend on experimental.Myles Watson2009-02-091-2/+3
| | | | | | | | Signed-off-by: Myles Watson <mylesgw@gmail.com> Acked-by: Peter Stuge <peter@stuge.se> git-svn-id: svn://coreboot.org/repository/coreboot-v3@1126 f3766cd6-281f-0410-b1cd-43a5c92072e9
* cs5536: Fix NAND Flash setup.Mart Raudsepp2009-02-091-1/+21
| | | | | | | | | | | | | | | | | A NAND device may never be mapped above 0xEFFFFFFF, as these addresses never reach the NAND controller. Only NAND controller, as the only DIVIL component that is allowed to be memory mapped, is affected - other Geode LX and CS5536 peripherals (that are separate GLIU devices outside DIVIL component) can use addresses above that limit (see in-code comment for details). In combination with a new VSA2 version 1.02 or newer, this makes NAND flash finally work in coreboot v3. Signed-off-by: Mart Raudsepp <mart.raudsepp@artecdesign.ee> Signed-off-by: Anti Sullin <anti.sullin@artecdesign.ee> Acked-by: Ronald G. Minnich <rminnich@gmail.com> git-svn-id: svn://coreboot.org/repository/coreboot-v3@1125 f3766cd6-281f-0410-b1cd-43a5c92072e9
* cs5536: Use NANDF_CTL for NAND Flash Control Timing register constant ↵Mart Raudsepp2009-02-091-1/+1
| | | | | | | | | | | 5140001Ch define, as in data book, not mis-spelled NADF_CNTL Trivial: constant currently not used anywhere. Signed-off-by: Mart Raudsepp <mart.raudsepp@artecdesign.ee> Acked-by: Mart Raudsepp <mart.raudsepp@artecdesign.ee> git-svn-id: svn://coreboot.org/repository/coreboot-v3@1124 f3766cd6-281f-0410-b1cd-43a5c92072e9
* Fix rs690 bug about GPPSB configuration.Marc Jones2009-01-231-2/+2
| | | | | | | | Signed-off-by: Maggie Li <maggie.li@amd.com> Reviewed-by: Zheng Bao <Zheng.bao@amd.com> Acked-by: Marc Jones <marcj303@gmail.com> git-svn-id: svn://coreboot.org/repository/coreboot-v3@1123 f3766cd6-281f-0410-b1cd-43a5c92072e9
* DBE63: Update comments in irq_tables.h for DBE63 hardwareMart Raudsepp2009-01-231-3/+3
| | | | | | | Signed-off-by: Mart Raudsepp <mart.raudsepp@artecdesign.ee> Acked-by: Ronald G. Minnich <rminnich@gmail.com> git-svn-id: svn://coreboot.org/repository/coreboot-v3@1122 f3766cd6-281f-0410-b1cd-43a5c92072e9
* DBE63: Rename dbe62_msr to dbe63_msr in stage1 code after the copy from ↵Mart Raudsepp2009-01-231-5/+5
| | | | | | | | | dbe62 board code Signed-off-by: Mart Raudsepp <mart.raudsepp@artecdesign.ee> Acked-by: Ronald G. Minnich <rminnich@gmail.com> git-svn-id: svn://coreboot.org/repository/coreboot-v3@1121 f3766cd6-281f-0410-b1cd-43a5c92072e9
* DBE63 has IDE instead of NAND, adjust dts accordinglyMart Raudsepp2009-01-231-3/+3
| | | | | | | Signed-off-by: Mart Raudsepp <mart.raudsepp@artecdesign.ee> Acked-by: Ronald G. Minnich <rminnich@gmail.com> git-svn-id: svn://coreboot.org/repository/coreboot-v3@1120 f3766cd6-281f-0410-b1cd-43a5c92072e9
* Start of Artec Group ThinCan DBE63 support.Mart Raudsepp2009-01-237-0/+449
| | | | | | | | | | | | | | | | | * Copying of files from other mainboards as a starting point: amd/db800/Makefile artecgroup/dbe62/cmos.layout artecgroup/dbe62/dts amd/db800/initram.c artecgroup/dbe61/irq_tables.h artecgroup/dbe62/stage1 * Kconfig integration. Behind CONFIG_EXPERIMENTAL for now, as the board is not in the market yet. Signed-off-by: Mart Raudsepp <mart.raudsepp@artecdesign.ee> Acked-by: Ronald G. Minnich <rminnich@gmail.com> git-svn-id: svn://coreboot.org/repository/coreboot-v3@1119 f3766cd6-281f-0410-b1cd-43a5c92072e9
* artecgroup/dbe62: Don't compile in ramtest.c as we don't use ram_check for ↵Mart Raudsepp2009-01-211-1/+1
| | | | | | | | | DBE62 anymore Signed-off-by: Mart Raudsepp <mart.raudsepp@artecdesign.ee> Acked-by: Myles Watson <mylesgw@gmail.com> git-svn-id: svn://coreboot.org/repository/coreboot-v3@1118 f3766cd6-281f-0410-b1cd-43a5c92072e9
* One missed function rename in the stage2 pci resources allocation. ↵Marc Jones2009-01-201-1/+1
| | | | | | | | | phase4_assign_resources is now phase4_set_resources. (trivial) Signed-off-by: Marc Jones <marcj303@gmail.com> Acked-by: Marc Jones <marcj303@gmail.com> git-svn-id: svn://coreboot.org/repository/coreboot-v3@1117 f3766cd6-281f-0410-b1cd-43a5c92072e9
* Right from Linux. I am not comfortable inserting our headers in linux files.Ronald G. Minnich2009-01-151-0/+70
| | | | | | | | | Signed-off-by: Ronald G. Minnich <rminnich@gmail.com> Acked-by: Patrick Georgi <patrick.georgi@coresystems.de> git-svn-id: svn://coreboot.org/repository/coreboot-v3@1116 f3766cd6-281f-0410-b1cd-43a5c92072e9
* Remove redundant unused tRCD entries from dbe61/dbe62 SPD value list.Mart Raudsepp2009-01-142-3/+0
| | | | | | | | | | SPD_MIN_RAS_TO_CAS_DELAY is already set earlier in the list, so the alternative constant tRCD in the end has no effect in the memory algorithm - remove them. Signed-off-by: Mart Raudsepp <mart.raudsepp@artecdesign.ee> Acked-by: Ronald G. Minnich <rminnich@gmail.com> git-svn-id: svn://coreboot.org/repository/coreboot-v3@1115 f3766cd6-281f-0410-b1cd-43a5c92072e9
* cs5536: Remove redundant enable_ide variable from ide device.Mart Raudsepp2009-01-0910-21/+1
| | | | | | | | | | | | | | | The device infrastructure already has an enabled bit, so we don't need to duplicate it in the current form. cs5536.c:ide_init() is phase6_init, which is called only if the device is enabled, so if the device doesn't exist, or the mainboard dts says "disabled;" for it, the init is not done and an extra conditional is not necessary. Adapt all cs5536 using mainboards to it (removing enable_ide variable) - artecgroup/dbe6[12] gets the whole IDE device removed, which results in the ide_init() code not being ran as before (before it was called but early return from enable_ide == 0, now it won't be called in the first place). Signed-off-by: Mart Raudsepp <mart.raudsepp@artecdesign.ee> Acked-by: Ronald G. Minnich <rminnich@gmail.com> git-svn-id: svn://coreboot.org/repository/coreboot-v3@1114 f3766cd6-281f-0410-b1cd-43a5c92072e9
* cs5536: Add a NAND device and do the IDE PCI header disabling on time.Mart Raudsepp2009-01-094-17/+61
| | | | | | | | | | | | | | | | | | | | This implements a nand device, akin to the ide device to follow the coreboot-v3 device tree design better. It allows us to do the IDE PCI header early enough in a clean way - the hide_vpci was called way too late before - in phase6 of southbridge device, but we need the Flash header active instead of IDE in the VSA2 before bus scans happen, or the PCI device gets disabled in coreboot understanding by the time we get it enabled in VSA2. It makes NAND setup work better, but still not completely. There is a VSA2 bug for which I made a patch, but waiting on a new binary to test if after that everything works or not. A quick hack to workaround the VSA2 bug suggests something further will still need fixing. There are also more potential opportunities to shuffle NAND code around to match v3 approach better, but that's a next step for me after NAND setup actually works right in the current form. Also corrected the documentation of ide_init() to match current reality. Signed-off-by: Mart Raudsepp <mart.raudsepp@artecdesign.ee> Acked-by: Peter Stuge <peter@stuge.se> git-svn-id: svn://coreboot.org/repository/coreboot-v3@1113 f3766cd6-281f-0410-b1cd-43a5c92072e9
* This patch adds the domain's resources and all links to the tree traversal forMyles Watson2009-01-091-31/+32
| | | | | | | | | | | constraining resources. Build and boot tested on qemu, serengeti, and alix2c3. Signed-off-by: Myles Watson <mylesgw@gmail.com> Acked-by: Ward Vandewege <ward@gnu.org> git-svn-id: svn://coreboot.org/repository/coreboot-v3@1112 f3766cd6-281f-0410-b1cd-43a5c92072e9
* This patch adds reserved regions to the geode northbridge for the ROM andMyles Watson2009-01-081-0/+19
| | | | | | | | | | IOAPIC. Signed-off-by: Myles Watson <mylesgw@gmail.com> Acked-by: Marc Jones <marcj303@gmail.com> git-svn-id: svn://coreboot.org/repository/coreboot-v3@1111 f3766cd6-281f-0410-b1cd-43a5c92072e9
* Remove unused pciconf.h header with constants that everyone uses by value ↵Mart Raudsepp2009-01-085-17/+0
| | | | | | | | | instead per convention Signed-off-by: Mart Raudsepp <mart.raudsepp@artecdesign.ee> Acked-by: Peter Stuge <peter@stuge.se> git-svn-id: svn://coreboot.org/repository/coreboot-v3@1110 f3766cd6-281f-0410-b1cd-43a5c92072e9
* This is a small HT fixup until HT links get figured out better.Myles Watson2009-01-084-100/+185
| | | | | | | | | | | | | | | | | It removes processors from the list of devices on the domain's bus so that pci_scan_bus won't disable them, then scans for them, then puts them back. There are lots of other ways to do this, but this one seemed minimally invasive and ends up with a correct tree. The dts fixups I should have put in with the other K8 patch for the new resource allocator. I went to the v2 Config.lb files and tried to get them as complete as possible. Signed-off-by: Myles Watson <mylesgw@gmail.com> Acked-by: Peter Stuge <peter@stuge.se> git-svn-id: svn://coreboot.org/repository/coreboot-v3@1109 f3766cd6-281f-0410-b1cd-43a5c92072e9
* This patch implements preorder traversal for Phase 2 and Phase 6, and prints aMyles Watson2009-01-081-36/+51
| | | | | | | | | | | | | | | | | | warning that Phase 1 is obsolete if anyone implements one. The only difference between the Phase 2 and Phase 6 implementations is that phase2_fixup is always called if it's defined, but phase6_init is only called if the device is enabled. Note that any devices not found in the tree will not have their init functions called with this patch. I think that's a good thing, but it will require some dts fixes. Signed-off-by: Myles Watson <mylesgw@gmail.com> Acked-by: Peter Stuge <peter@stuge.se> git-svn-id: svn://coreboot.org/repository/coreboot-v3@1108 f3766cd6-281f-0410-b1cd-43a5c92072e9
* Port r3747, r3732, r3733 from v2 to v3 (build-tested on v3):Uwe Hermann2009-01-083-42/+11
| | | | | | | | | | | | | | | | | | | | | | | | | | | src/northbridge/intel/i945/ich7.h: Thanks to Uwe Hermann for spotting this typo. src/southbridge/intel/i82801gx/i82801gx_lpc.c: The enable_hpet() code in intel/i82801gx will not work with the ICH7 southbridge (but it might work with ICH4/ICH5 or so). The ICH7 needs a different init code. Drop the non-working code for now. src/southbridge/intel/i82801gx/i82801gx.h: Drop #defines for registers that are not existant on the ICH7. Also, fix BIOS_CNTL, which is 0xdc on ICH7. Build-tested with kontron/986lcd-m. Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Uwe Hermann <uwe@hermann-uwe.de> git-svn-id: svn://coreboot.org/repository/coreboot-v3@1107 f3766cd6-281f-0410-b1cd-43a5c92072e9
* Port relevant parts of r3741 from v2 to v3 (build-tested on v3):Uwe Hermann2009-01-083-27/+28
| | | | | | | | | | | | | | | Merge some parts of the i945 review (trivial): * fix \r\n occurence in i945 code * drop early TOLUD write * fix 16bit BCTRL1 access Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Uwe Hermann <uwe@hermann-uwe.de> git-svn-id: svn://coreboot.org/repository/coreboot-v3@1106 f3766cd6-281f-0410-b1cd-43a5c92072e9
* Port r3738 from v2 to v3 (build-tested in v3):Uwe Hermann2009-01-081-22/+23
| | | | | | | | | | | | | 945.h: Add some more comments, align data for better readability (trivial). Also, add missing C1DRA2 #define (as per public datasheet). Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Uwe Hermann <uwe@hermann-uwe.de> git-svn-id: svn://coreboot.org/repository/coreboot-v3@1105 f3766cd6-281f-0410-b1cd-43a5c92072e9
* This trivial patch adds the warnings Peter and Ron requested to the ck804 code.Myles Watson2009-01-072-0/+4
| | | | | | | | | Signed-off-by: Myles Watson <mylesgw@gmail.com> Acked-by: Myles Watson <mylesgw@gmail.com> git-svn-id: svn://coreboot.org/repository/coreboot-v3@1104 f3766cd6-281f-0410-b1cd-43a5c92072e9
* This patch updates geodelx to fit the new resource allocator better. ItMyles Watson2009-01-0710-60/+97
| | | | | | | | | | | | | splits the domain and the memory controller functions into their respective devices. It also updates the dts for all the boards that use geodelx_video_mb. Signed-off-by: Myles Watson <mylesgw@gmail.com>Acked-by: Marc Jones <marcj303@gmail.com> git-svn-id: svn://coreboot.org/repository/coreboot-v3@1103 f3766cd6-281f-0410-b1cd-43a5c92072e9
* YABEL: (trivial) add BSD license header to files missing a license headerPattrick Hueper2009-01-072-0/+20
| | | | | | | | Signed-off-by: Pattrick Hueper <phueper@hueper.net> Acked-by: Pattrick Hueper <phueper@hueper.net> git-svn-id: svn://coreboot.org/repository/coreboot-v3@1102 f3766cd6-281f-0410-b1cd-43a5c92072e9
* Add missing BSD license header to the PMM files.Uwe Hermann2009-01-062-0/+10
| | | | | | | | | Signed-off-by: Pattrick Hueper <phueper@hueper.net> Acked-by: Uwe Hermann <uwe@hermann-uwe.de> git-svn-id: svn://coreboot.org/repository/coreboot-v3@1101 f3766cd6-281f-0410-b1cd-43a5c92072e9
* This patch adds southbridge/nvidia/ck804 from v2 minimally updated for v3.Myles Watson2009-01-0532-0/+2975
| | | | | | | | | | | Peter has some valid points that need to be addressed in the future. See his Ack message. Signed-off-by: Myles Watson <mylesgw@gmail.com> Acked-by: Peter Stuge <peter@stuge.se> git-svn-id: svn://coreboot.org/repository/coreboot-v3@1100 f3766cd6-281f-0410-b1cd-43a5c92072e9
* This patch removes the offset_pciio since there is never an offset_pciio anMyles Watson2009-01-053-44/+50
| | | | | | | | | | | | offset_pciio and an offset_io. This makes it easier to port things from v2. It also updates mcp55 and some whitespace there. Signed-off-by: Myles Watson <mylesgw@gmail.com> Acked-by: Peter Stuge <peter@stuge.se> git-svn-id: svn://coreboot.org/repository/coreboot-v3@1099 f3766cd6-281f-0410-b1cd-43a5c92072e9
* This patch does some minor fixups for 8111 and 8132 and adds support for 8131.Myles Watson2009-01-058-15/+476
| | | | | | | | Signed-off-by: Myles Watson <mylesgw@gmail.com> Acked-by: Peter Stuge <peter@stuge.se> git-svn-id: svn://coreboot.org/repository/coreboot-v3@1098 f3766cd6-281f-0410-b1cd-43a5c92072e9
* This patch introduces {PCIX,PCIE,AGP...}_SUPPORT config variables.Myles Watson2009-01-054-14/+81
| | | | | | | | | | | | | | | | | | | | | | Kconfig: Add *_SUPPORT variables. Add select statements for the hardware that needs them. device/Makefile: Test *_SUPPORT variables instead of chip names. device/Kconfig: Add *_PLUGIN_SUPPORT variables. device/pci_device.c: Conditionally include headers if *_PLUGIN_SUPPORT. Update default drivers to depend on CONFIG_*_PLUGIN_SUPPORT. Signed-off-by: Myles Watson <mylesgw@gmail.com> Acked-by: Peter Stuge <peter@stuge.se> git-svn-id: svn://coreboot.org/repository/coreboot-v3@1097 f3766cd6-281f-0410-b1cd-43a5c92072e9
* This patch removes a couple of warnings from the compilation of mcp55 boards.Myles Watson2009-01-053-4/+1
| | | | | | | | | | | * #if CONFIG_HPET -> #ifdef CONFIG_HPET * unused variables Signed-off-by: Myles Watson <mylesgw@gmail.com> Acked-by: Peter Stuge <peter@stuge.se> git-svn-id: svn://coreboot.org/repository/coreboot-v3@1096 f3766cd6-281f-0410-b1cd-43a5c92072e9
* This trivial patch makes AGP support compile again. Myles Watson2009-01-052-12/+8
| | | | | | | | Signed-off-by: Myles Watson <mylesgw@gmail.com> Acked-by: Myles Watson <mylesgw@gmail.com> git-svn-id: svn://coreboot.org/repository/coreboot-v3@1095 f3766cd6-281f-0410-b1cd-43a5c92072e9
* This patch fixes up k8 for the new resource allocator. It splitsMyles Watson2009-01-056-699/+538
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | northbridge functions and makes devices children of the northbridge. northbridge/amd/k8/domain.c: Add the functions from k8/pci.c that belong to the domain. Add support for physical link numbers in resource indices. Combine find_iopair and find_mempair to find_regpair. northbridge/amd/k8/pci.c: Remove functions that went to the domain. device/hypertransport.c: Add support for HT connections from devices that aren't the bus controller. device/hypertransport.h: Change the prototype of hypertransport_scan_chain. northbridge/amd/k8/pci: Take out bridge flag. mainboard/amd/serengeti/stage1.c Change first register usage. Signed-off-by: Myles Watson <mylesgw@gmail.com> Acked-by: Ronald G. Minnich <rminnich@gmail.com> git-svn-id: svn://coreboot.org/repository/coreboot-v3@1094 f3766cd6-281f-0410-b1cd-43a5c92072e9
* This patch fixes up kontron for the new resource allocator. MoreMyles Watson2008-12-313-53/+90
| | | | | | | | | | | | | | | | | | | could be done. northbridge/intel/i945/northbridge.dts Remove bridge flag. Northbridges don't have children. The domains they implement do. northbridge/intel/i945/northbridge.c Add IORESOURCE_BRIDGE flags and change the limit for MMIO to avoid ROM. mainboard/kontron/986lcd-m/dts Make PCI devices children of the domain and add a few devices. Signed-off-by: Myles Watson <mylesgw@gmail.com> Acked-by: Ronald G. Minnich <rminnich@gmail.com> git-svn-id: svn://coreboot.org/repository/coreboot-v3@1093 f3766cd6-281f-0410-b1cd-43a5c92072e9
* This patch should serve as a porting help for other northbridges for the ↵Myles Watson2008-12-318-37/+214
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | new resource allocator. file-by-file changes: dts: There are no bus devices, remove it. Add the northbridge devices. Fix susbsytem_vendor and subsystem_device. southbridge/intel/i82371eb/ide: Make the ide enabled by default. northbridge/intel/i440bxemulation/i440bx.c: 1. Split ops into domain and northbridge A. Domain should have bus ops, scan_bus, etc. B. Northbridge should have ops for its own registers. In this case it only needs read and set resources. functions: i440bx_read_resources - set up the IO and VGA resources. VGA is fixed. i440bx_ram_resources - this should be called after resource assignment. i440bx_set_resources - call pci_set_resources then i440bx_ram_resources. i440bx_domain_read_resources - Set up system-wide resources, and reserve space for the local APIC. I put the IOAPIC here too, but it belongs somewhere in the southbridge. i440bx_domain_set_resources - Mark the domain-specific resources as stored (In a real device you'd probably need to set some registers here.) Call phase4_set_resources for children. southbridge/intel/i82371eb/i82371eb.c: 1. Add ISA read and set resources to reserve legacy IO space. - Note that since it's subtractively decoded, it doesn't need to be stored anywhere. It needs to be marked stored so pci_set_resource doesn't try to store it. Signed-off-by: Myles Watson <mylesgw@gmail.com> Acked-by: Ronald G. Minnich <rminnich@gmail.com> git-svn-id: svn://coreboot.org/repository/coreboot-v3@1092 f3766cd6-281f-0410-b1cd-43a5c92072e9
* patch: geodelx.diffMyles Watson2008-12-311-2/+20
| | | | | | | | | | | | | | | | This patch fixes up geode for the new resource allocator. This is the bare minimum. I think the functions of the northbridge should be split based on whether they are domain-specific or not. southbridge/amd/cs5536/cs5536.c: Change read resources to add a fixed IO resource for legacy decoding. Signed-off-by: Myles Watson <mylesgw@gmail.com> Acked-by: Ronald G. Minnich <rminnich@gmail.com> git-svn-id: svn://coreboot.org/repository/coreboot-v3@1091 f3766cd6-281f-0410-b1cd-43a5c92072e9
* specific-resources.diff:Myles Watson2008-12-319-83/+32
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch makes specific devices use the updated resource allocation code. The changes necessary are: 1. Remove all calls to compute_allocate_resources. 2. Don't store resources except in phase4_set_resources. northbridge/amd/k8/pci.c: Remove calls to compute_allocate_resource. Change phase4_assign_resources to phase4_set_resources southbridge/amd/amd8132/amd8132_bridge.c: Remove NPUML and NPUMB. Add a warning for bus disabling. Remove bridge_{read|set}_resources (they were there for NPUML) southbridge/nvidia/mcp55/lpc.c: southbridge/amd/sb600/lpc.c: Remove references to have_resources. southbridge/amd/amd8111/lpc.c: Add resources for subtractive IO and ROM. northbridge/amd/k8/domain.c: northbridge/intel/i440bxemulation/i440bx.c: northbridge/amd/geodelx/geodelx.c: northbridge/intel/i945/northbridge.c: northbridge/via/cn700/stage2.c: Change phase4_assign_resources->phase4_set_resources. Signed-off-by: Myles Watson <mylesgw@gmail.com> Acked-by: Ronald G. Minnich <rminnich@gmail.com> git-svn-id: svn://coreboot.org/repository/coreboot-v3@1090 f3766cd6-281f-0410-b1cd-43a5c92072e9
* This patch simplifies the resource allocator by splitting it into distinctMyles Watson2008-12-318-329/+572
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | phases. One benefit of this is that it makes the call chain easier to follow. device/device.c: Remove references to have_resources. Remove read_resources from compute allocate resources. Split compute_allocate_resources into two 1. compute_resource_needs A. Traverse the tree depth first B. Sum resources C. Adjust limits and bases D. Update bridge resources sizes 2. assign_resource_values A. Traverse the tree breadth first B. Assign resource values device/device_util.c: Remove references to have_resources. device/pci_device.c: Remove saved values stubs (they're not needed now.) 1. Sizing function restores values Fix 64-bit flag masking. Add an error message for an invalid value. Update pci_record_bridge_resource: 1. remove compute_allocate_resource call 2. remove pci_set_resource call Update pci_bus_read_resources to read children's too. Update pci_set_resource: 1. change logic for setting zero-size resources A. Set range to [limit->limit-2^gran] (Could have been any range with base > limit) 2. remove compute_allocate_resource calls 3. Change phase4_assign_resources ->phase4_set_resources device/pci_ops.c: Change an error message to be more helpful. device/root_device.c: Remove code for read_resources and set resources. Add a .id to the ops. include/device/device.h: Remove have_resources. Comment out assign_resources. I think we could comment out more here. Add debugging function prototypes. Change phase4_assign_resources to phase4_set_resources. include/device/resource.h Add a IORESOURCE_BRIDGE flag. device/cardbus_device.c Remove compute_allocate_resource call. Use probe_resource (doesn't die) instead of find_resource. Signed-off-by: Myles Watson <mylesgw@gmail.com> Acked-by: Ronald G. Minnich <rminnich@gmail.com> git-svn-id: svn://coreboot.org/repository/coreboot-v3@1089 f3766cd6-281f-0410-b1cd-43a5c92072e9
* Fix breakage of k8 targets caused by r1085. Thanks to Myles Watson for Corey Osgood2008-12-306-4/+9
| | | | | | | | | | | tracking down the offending commit. Signed-off-by: Corey Osgood <corey.osgood@gmail.com> Acked-by: Peter Stuge <peter@stuge.se> git-svn-id: svn://coreboot.org/repository/coreboot-v3@1088 f3766cd6-281f-0410-b1cd-43a5c92072e9
* This patch fixes a few small problems and gets cn700 to read from an IDE Corey Osgood2008-12-2311-158/+97
| | | | | | | | | | | disk and attempt to boot a linux kernel. Signed-off-by: Corey Osgood <corey.osgood@gmail.com> Acked-by: Corey Osgood <corey.osgood@gmail.com> git-svn-id: svn://coreboot.org/repository/coreboot-v3@1087 f3766cd6-281f-0410-b1cd-43a5c92072e9
* Subject: [PATCH] YABEL: add PMM functionality.Myles Watson2008-12-235-3/+508
| | | | | | | | Signed-off-by: Pattrick Hueper <phueper@hueper.net> Acked-by: Myles Watson <mylesgw@gmail.com> git-svn-id: svn://coreboot.org/repository/coreboot-v3@1086 f3766cd6-281f-0410-b1cd-43a5c92072e9
* Kill off stage1_mtrr.c completely, and bring in mtrr.c for stage2 from v2.Ronald G. Minnich2008-12-2310-10/+465
| | | | | | | | | | | | | | | | | Signed-off-by: Corey Osgood <corey.osgood@gmail.com> It could use some cleanup, but looks good. Acked-by: Peter Stuge <peter@stuge.se> With some cleanup. Acked-by: Ronald G. Minnich <rminnich@gmail.com> git-svn-id: svn://coreboot.org/repository/coreboot-v3@1085 f3766cd6-281f-0410-b1cd-43a5c92072e9
* This is an emergency fix for the kontron. This fix now allows us to boot to Ronald G. Minnich2008-12-231-1/+1
| | | | | | | | | | | | | | etherboot. The fix is to replace the wbinvd with an invd. The wbinvd is a bad idea, since the cache at this point is full of tags to a location that is not backed by memory. Signed-off-by: Ronald G. Minnich <rminnich@gmail.com> Acked-by: Ronald G. Minnich <rminnich@gmail.com> git-svn-id: svn://coreboot.org/repository/coreboot-v3@1084 f3766cd6-281f-0410-b1cd-43a5c92072e9
* Quick emergency fix for unitialized variable. A number of recent changes Ronald G. Minnich2008-12-231-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | have resulted in breaking the kontron port. I am trying to fix them. In case there is any concern about the initialization: this is a scalar auto being initialized. The initialization is done in code. I have verified this both by checking the object code and actually running it; this fix resolves a break introduced at some point. Other breakage remains: kontron now hangs here: run_file returns with 0 Done RAM init code Done printk() buffer move disable_car entry disable_car global_vars copy done disable_car global_vars pointer adjusted entering asm code now Signed-off-by: Ronald G. Minnich <rminnich@gmail.com> Acked-by: Ronald G. Minnich <rminnich@gmail.com> git-svn-id: svn://coreboot.org/repository/coreboot-v3@1083 f3766cd6-281f-0410-b1cd-43a5c92072e9
* Subject: [PATCH] YABEL: small cleanup fixesMyles Watson2008-12-222-40/+2
| | | | | | | | | | | | remove Makefile in yabel directory, since it is not needed (leftover from SLOF biosemu) fix dump() function output to not include \r Signed-off-by: Pattrick Hueper <phueper@hueper.net> Acked-by: Myles Watson <mylesgw@gmail.com> git-svn-id: svn://coreboot.org/repository/coreboot-v3@1082 f3766cd6-281f-0410-b1cd-43a5c92072e9
* Date: Sun, 21 Dec 2008 00:09:12 +0100Myles Watson2008-12-224-22/+39
| | | | | | | | | | Subject: [PATCH] use the rom_addr passed by coreboot, needed for ROM images from LAR Signed-off-by: Pattrick Hueper <phueper@hueper.net> Acked-by: Myles Watson <mylesgw@gmail.com> git-svn-id: svn://coreboot.org/repository/coreboot-v3@1081 f3766cd6-281f-0410-b1cd-43a5c92072e9
* This patch makes the 8151 compile and adds it to the amd serengeti board.Myles Watson2008-12-195-20/+48
| | | | | | | | Signed-off-by: Myles Watson <mylesgw@gmail.com> Acked-by: Marc Jones <marcj303@gmail.com> git-svn-id: svn://coreboot.org/repository/coreboot-v3@1080 f3766cd6-281f-0410-b1cd-43a5c92072e9
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