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* crossgcc: Upgrade CMake from 3.27.7 to version 3.28.3HEADmasterElyes Haouas2024-02-243-2/+2
| | | | | | | | Change-Id: I17758e23da25d610a0b462dfd388c53b89315242 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80648 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
* soc/amd/glinda: Update GPP_CLK_OUTPUT_AVAILABLE to 7Varshit Pandya2024-02-241-1/+1
| | | | | | | | | | | | Glinda started as a copy of mendocino and GPP_CLK_OUTPUT_AVAILABLE was not updated. GPP_CLK_OUTPUT_AVAILABLE should be 7 as per Processor Programming Reference (PPR) (#57254), table "GPP ClkREQB Mapping". Change-Id: I26e9dea58b2ddf5cbedbcccb8bcbc5f9efab3165 Signed-off-by: Varshit Pandya <pandyavarshit@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80701 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* treewide: Move list.h to commonlibMaximilian Brune2024-02-2413-17/+25
| | | | | | | | | | | It is needed in order to move device_tree.c into commonlib in a subsequent commit. Signed-off-by: Maximilian Brune <maximilian.brune@9elements.com> Change-Id: I16eb7b743fb1d36301f0eda563a62364e7a9cfec Reviewed-on: https://review.coreboot.org/c/coreboot/+/77968 Reviewed-by: Julius Werner <jwerner@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* vboot: Enable new arm64 SIMD crypto accelerationJulius Werner2024-02-244-0/+26
| | | | | | | | | | | | | | | | This patch passes the correct flag to vboot to enable SIMD crypto acceleration on arm64 devices. This uses a core part of the ISA and should thus be supported on all arm64 SoCs -- so we normally always want it enabled, but there should still be a Kconfig in case a SoC wants to use the hwcrypto interface for its own (off-CPU) crypto acceleration engine instead. (You could also disable it to save a small amount of code size at the cost of speed, if necessary.) Change-Id: I3820bd6b7505202b7edb6768385ce5deb18777a4 Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80710 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
* Update vboot submodule to upstream mainJulius Werner2024-02-241-0/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Updating from commit id 3d37d2aa: 2024-01-15 Makefile: Support FIRMWARE_ARCH=mock for firmware unit tests to commit id 09fcd218: 2024-02-22 Makefile: Test compiler for -Wincompatible-function-pointer-types This brings in 26 new commits: 09fcd218 Makefile: Test compiler for -Wincompatible-function-pointer-types 00e8c2d8 tests: Run hwcrypto RSA tests for arm64 d3387824 firmware: Add vectorized modexp() implementation for arm64 (NEON) 8856e04b tests: Stop exporting ENABLE_HWCRYPTO_RSA_TESTS to test scripts 6abd9cc0 Makefile: Separate ${ARCH_DIR}, split arm/arm64, remove symlinks e7f567d1 test_update: Skip ifdtool-dependent tests when not available 1a0f8df8 libvboot_host: Check for undefined symbols c0806280 vboot_host: Expose dynamic library 2ff5784d vboot: Remove 2kernel.c from vboot_host library 6e472468 Add crdyshim keygen script and devkeys 8a711468 scripts/keygeneration: Move generate_ed25519_key to common.sh 57e2092d scripts/image_signing: Call futility instead of its symlinks 0fa2ea47 scripts/image_signing/make_dev_ssh.sh: Improve parameter removal 1d32db3b Makefile: Remove genfuzztestcases from runtestscripts prerequisites f6ff822b README: Add 'futility sign' and 'futility verify' to useful utilities a717c83d tests: Replace vbutil_{firmware,kernel} with 'futility sign' 94c82417 *.sh: Unify indentation with 2 spaces 23d25957 utility/dev_debug_vboot: Replace vbutil_firmware with 'futility verify' fd20901f cgpt/futility: bundle as a subtool dccc5a31 image_signing: Add support for signing Flexor kernel image 660b6675 futility/cmd_show: Add "::verified" summary to vblock parseable output 2fcff1e4 tests/*.sh: Replace vbutil_firmware with 'futility verify' c6b13823 make_dev_firmware.sh: Replace vbutil_firmware with 'futility show' d260d094 firmware: 2modpow_sse2: Clean up calculation of `mu` 2596679a Add -Wint-conversion and -Wincompatible-function-pointer-types 39fb6201 futility: update: Use ifdtool to unlock ME f8016c2b make_keyblock: change to parsing key prefix Change-Id: Ibc6daef30092b1b31f3dd08f3aed02ba31fd12d2 Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80709 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
* soc/amd/common/acp: use clrsetbits32p to avoid need for castsFelix Held2024-02-232-2/+2
| | | | | | | | | | | Use clrsetbits32p instead of clrsetbits32 to not need to cast the uintptr_t address to void * in the function call. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ic29bf04866a7e1d5c831422f31803a724a41069b Reviewed-on: https://review.coreboot.org/c/coreboot/+/80700 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
* vc/amd/opensil/genoa_poc/mpio/chip: fix typo in pcie_aspm enum nameFelix Held2024-02-231-2/+2
| | | | | | | | Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I60ac259d2aa0bd500063a5c841ba33e576e022f7 Reviewed-on: https://review.coreboot.org/c/coreboot/+/80702 Reviewed-by: Elyes Haouas <ehaouas@noos.fr> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* soc/amd/glinda: Use gpp_clk_setup_common functionVarshit Pandya2024-02-233-53/+2
| | | | | | | | | | | In follow up to commit 0452d0939e7d ("soc/amd: Factor out gpp_clk_setup function") use gpp_clk_setup_common for glinda as well. Change-Id: If0c1cda0d36de48c7f7315a1b8203b0e53f63f75 Signed-off-by: Varshit Pandya <pandyavarshit@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80699 Reviewed-by: Anand Vaikar <a.vaikar2021@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
* arch/x86/ioapic: use uintptr_t for IOAPIC base addressFelix Held2024-02-2335-86/+89
| | | | | | | | | | | | | | | Use uintptr_t for the IOAPIC base parameter of the various IOAPIC- related functions to avoid needing type casts in the callers. This also allows dropping the VIO_APIC_VADDR define and consistently use the IO_APIC_ADDR define instead. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I912943e923ff092708e90138caa5e1daf269a69f Reviewed-on: https://review.coreboot.org/c/coreboot/+/80358 Reviewed-by: Elyes Haouas <ehaouas@noos.fr> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
* soc/amd/glinda: Use pcie_gpp_dxio_update_clk_req_configVarshit Pandya2024-02-233-6/+7
| | | | | | | | | | | | | | | This function turns off gpp_clk for the devices which are disabled, and adds the code to fix up the clock configuration depending on dxio descriptors. Also this brings glinda in line with cezanne, mendocino, phoenix and picasso. This also prepares glinda to use the common function gpp_clk_setup_common. Change-Id: Id66d1b7f0d8ec9a7cbd378ad6ad7d68eeab531f0 Signed-off-by: Varshit Pandya <pandyavarshit@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80415 Reviewed-by: Anand Vaikar <a.vaikar2021@gmail.com> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* soc/intel/adl: Set slp-s0 counter frequencyMarx Wang2024-02-231-0/+5
| | | | | | | | | | | | | | | | | System sleep time (SLP_S0 signal asserted) is measured in ticks, for Alder Lake soc in 122us (i.e. ~8197Hz) granularity/ticks. BUG=b:301854636 TEST=/sys/devices/system/cpu/cpuidle/ low_power_idle_system_residency_us" will show system idle residency time Change-Id: I449f7ed0d9ef891ae5266e8fd784a063a75e38eb Signed-off-by: Marx Wang <marx.wang@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80665 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sukumar Ghorai <sukumar.ghorai@intel.com> Reviewed-by: Kapil Porwal <kapilporwal@google.com> Reviewed-by: Subrata Banik <subratabanik@google.com>
* vc/intel/fsp2/twinlake: Add FSP headersKapil Porwal2024-02-235-0/+7655
| | | | | | | | | | | | | | | Add FSP header files for Twin Lake. Currently these are just a copy of ADL-N headers. BUG=none BRANCH=firmware-nissa-15217.B TEST=Build and boot Google/Yaviks with Twin Lake kconfig enabled Signed-off-by: Kapil Porwal <kapilporwal@google.com> Change-Id: I37579335c784866ebbf978e28936abf046a85b48 Reviewed-on: https://review.coreboot.org/c/coreboot/+/80698 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com>
* soc/intel/xeon_sp: Locate PCI devices by Ven/Dev IDPatrick Rudolph2024-02-231-35/+44
| | | | | | | | | | | | | | | | | Since the ACPI code is looking for VtdBars, that only appear on Vtd devices, search for the Vtd device in devicetree. With the previous commit the VtdBar is now exposed as a resource on the Vtd device and thus can easily be accessed and used. Drop the FSP HOB parsing and just use coreboot native functions. Allows the code to work with multiple PCI segment groups. Change-Id: I2c752dc595ac4c901f2b3a96718e256e413c76a7 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80551 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Shuo Liu <shuo.liu@intel.com>
* soc/intel/xeon_sp: Add helper functionsPatrick Rudolph2024-02-232-0/+83
| | | | | | | | | | | | | | | | | | Provide a helper function to locate PCI devices on a given socket by their PCI vendor and device IDs and functions to return information about the current device, like the corresponding stack and socket. In addition add functions to return "location" information, like stack and socket affiliation. This becomes handy when locating devices and generating ACPI code. Change-Id: I266360588548ba579f46b228c4d5b3ae6e39a029 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80094 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Shuo Liu <shuo.liu@intel.com> Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
* soc/intel/xeon_sp/uncore: Read VtdBarPatrick Rudolph2024-02-234-4/+19
| | | | | | | | | | | | | | Read the VtdBar and add it to the resources of the host bridge PCI device. The BAR is already marked as PciResourceMem32 in the parent PCI domain. This allows easy probing for VTD devices with enabled VtdBars in the next commit, without the need to look up the stack HOB. Change-Id: Id579a94e653473f3dd0dccea6e33dc64f792d028 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80550 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
* riscv/mb/qemu: fix qemu invocation commentPhilipp Hug2024-02-222-2/+5
| | | | | | | | | | | Change-Id: I773fb39801f180fead584942dfb385fcde9d2680 Signed-off-by: Philipp Hug <philipp@hug.cx> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80262 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Maximilian Brune <maximilian.brune@9elements.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: ron minnich <rminnich@gmail.com>
* soc/intel/common/lpc: Skip setting resources for disabled devicesMatt DeVillier2024-02-221-0/+3
| | | | | | | | | | | | | | | | | If a downstream LPC device (eg, SIO function) is disabled, we shouldn't attempt to open PMIO windows for it, as those functions often have unset IO bases (which default to 0), resulting in false errors like: [ERROR] LPC IO decode base 0! TEST=build/boot purism/librem_cnl (Mini v2), verify no LPC IO errors in cbmem log for disabled SIO functions. Change-Id: I92c79fc01be21466976f3056242f6d1824878eab Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80646 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Nico Huber <nico.h@gmx.de>
* soc/intel/braswell/gpio_support: drop unused get_gpioFelix Held2024-02-222-6/+0
| | | | | | | | | | | The get_gpio function in this file is both unused and it shouldn't use a signed int to pass in the MMIO base address and offset. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I3b08bad040ad175b37175ef21d0a0a29525c4478 Reviewed-on: https://review.coreboot.org/c/coreboot/+/80690 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
* libpayload: Remove legacy CBFS APIJulius Werner2024-02-2218-1268/+0
| | | | | | | | | | | | | | | It's been several years already since we announced the deprecation of the legacy CBFS API for payloads. It's time to remove it completely. Change-Id: I0ed157ac2d1376b8dff4537af9a63731064b45f6 Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80650 Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Jakub Czapiga <czapiga@google.com> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Maximilian Brune <maximilian.brune@9elements.com>
* mb/google/brox: Disable Early EC SyncShelley Chen2024-02-221-1/+0
| | | | | | | | | | | | | | | | Early EC Sync does not need to be enabled in coreboot as EFS2 is being enabled in the EC. BUG=b:326152804 BRANCH=None TEST=emerge-brox coreboot To be tested with EC sync enabled Change-Id: I08bdbe9f3dcea837b0b148adc137c03d3461877a Signed-off-by: Shelley Chen <shchen@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80689 Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* soc/intel/xeon_sp: Print device path when reporting resourcesPatrick Rudolph2024-02-221-2/+2
| | | | | | | | | | | | As there are multiple Vtd devices, print the path of each when reporting resource registers. Change-Id: I5d3a6484ed7c7b9760fce0f3a02a15ca26c2cbd2 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80549 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Shuo Liu <shuo.liu@intel.com>
* soc/intel/xeon_sp: Align resources to 4KPatrick Rudolph2024-02-222-3/+2
| | | | | | | | | | | | | | | | | | | | | | The lower bit of the BAR might be used for something else, like enable bits, so mask the lower 12 bits and align all base address to 4K. Confirmed that all BARs have a minimum alignment of 4K, so that masking the lower bits doesn't change the reported address. The alignment of the VTD BARs is: - VTD_MMCFG_BASE_CSR 64 MiB - VTD_MMIOL_CSR 1 MiB - VTD_NCMEM_BASE_CSR 64 MiB - VTD_TSEG_BASE_CSR 1 MiB - VTD_BAR_CSR 4 KiB Change-Id: I9a7b963c0074246616968dd15c147f4916297d59 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80548 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
* soc/intel/xeon_sp: Refactor IOAT compiler optimization outsShuo Liu2024-02-222-9/+2
| | | | | | | | | | | | | | | | | IOAT logics are optimized out for non-IOAT platforms where CONFIG(HAVE_IOAT_DOMAINS) as false. This patch puts CONFIG(HAVE_IOAT_DOMAINS) check together ahead of is_ioat_iio_stack_res() check in the corresponding if statement to fulfill the optimization outs. TEST=intel/archercity CRB Change-Id: I2d16c6ff5320bc9195a1033b6d55e3d997b19b88 Signed-off-by: Shuo Liu <shuo.liu@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80683 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* soc/intel/alderlake: Remove Alder Lake M SKUSean Rhodes2024-02-225-33/+2
| | | | | | | | | | | ADL-M is not commercially available, so it can be removed. Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: If769989f7a0434e32ebbcc8eac9b965b70ca71ed Reviewed-on: https://review.coreboot.org/c/coreboot/+/80614 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Kapil Porwal <kapilporwal@google.com>
* mb/intel/adlrvp: Remove ADLRVP_M mainboardSean Rhodes2024-02-2211-151/+14
| | | | | | | | | | | These boards are not commerically available so can be removed. Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: Icc853a9df44a4a770db76e119644f0b4c7fcc2c8 Reviewed-on: https://review.coreboot.org/c/coreboot/+/80613 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kapil Porwal <kapilporwal@google.com> Reviewed-by: Subrata Banik <subratabanik@google.com>
* soc/intel/alderlake: Sync UPD Usb4CmMode with KconfigSean Rhodes2024-02-221-0/+4
| | | | | | | | | | | | | | | The ACPI is adjusted based on SOFTWARE_CONNECTION_MANAGER, so set the UPD to match this to avoid the connection type being mismatched. If it's mismatched, the TBT port will time out. Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: I8a99db165301ce08caf55aac0e33ca1994559d62 Reviewed-on: https://review.coreboot.org/c/coreboot/+/80486 Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-by: Kapil Porwal <kapilporwal@google.com>
* mb/google/rex/variants/deku: Enable PCIe wifi deviceTony Huang2024-02-221-0/+13
| | | | | | | | | | | | BUG=b:320203629 BRANCH=firmware-rex-15709.B TEST=emerge-ovis coreboot built FW image correctly. Change-Id: I8db065e25e21406f1966d8020a3b926b3a62ae12 Signed-off-by: Tony Huang <tony-huang@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80685 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kapil Porwal <kapilporwal@google.com>
* mb/google/nissa/var/glassway: Generate SPD ID for supported memory partsDaniel Peng2024-02-223-2/+20
| | | | | | | | | | | | | | | | | | | | | | | | | | Add supported memory parts in mem_parts_used list, and generate SPD ID for these parts. DRAM Part Name ID to assign K3KL8L80CM-MGCT 0 (0000) K3KL6L60GM-MGCT 1 (0001) H58G56AK6BX069 2 (0010) H9JCNNNBK3MLYR-N6E 3 (0011) BUG=b:319071869 BRANCH=firmware-nissa-15217.B TEST=Run command "go run ./util/spd_tools/src/part_id_gen/\ part_id_gen.go ADL lp5 \ src/mainboard/google/brya/variants/glassway/memory/ \ src/mainboard/google/brya/variants/glassway/memory/\ mem_parts_used.txt" Change-Id: I00ae3efe8e554f44cee5a27ac88c5d65eb95f7fb Signed-off-by: Daniel Peng <Daniel_Peng@pegatron.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80686 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <ericllai@google.com> Reviewed-by: Daniel Peng <daniel_peng@pegatron.corp-partner.google.com>
* tests/lib/ux_locales-test: Simplify macrosYu-Ping Wu2024-02-221-41/+15
| | | | | | | | | | | | | | | The cmocka problem of sanitizing XML strings has been fixed in CB:80382. Therefore the helper macros UX_LOCALES_GET_TEXT_FOUND_TEST() and UX_LOCALES_GET_TEXT_NOT_FOUND_TEST() can be merged into one. TEST=make unit-tests JUNIT_OUTPUT=y -j Change-Id: Ic3199e2a061550282fb08122943994c835845543 Signed-off-by: Yu-Ping Wu <yupingso@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80621 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <ericllai@google.com> Reviewed-by: Hsuan-ting Chen <roccochen@google.com>
* i2c/drivers/generic: Add support for including a rotation matrixSean Rhodes2024-02-212-0/+32
| | | | | | | | | | | | | | | | | | | | | The Rotation Matrix allows the specification of a 3x3 matrix representing the orientation of devices, such as accelerometers. Each value in the matrix can be one of -1, 0, or 1, indicating the transformation applied to the device's axes. It is expected by Linux and required for the OS to interpret the data from the device correctly. It is used by various drivers, mainly in `iio/accel`. It was tested on Ubuntu, by rotating the device and verifying the orientation was correct. Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: Id4a940d999a0e300a6fe21269f18bab6e3c0523c Reviewed-on: https://review.coreboot.org/c/coreboot/+/80179 Reviewed-by: Matt DeVillier <matt.devillier@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
* mb/amd/birman_plus: Add Birman+ board support for Phoenix SOCAnand Vaikar2024-02-2117-0/+1345
| | | | | | | | | | | 1) Initial commit for upstreaming Birmanplus mainboard changes. 2) Add the DXIO descriptors for Birmanplus mainboard. Change-Id: I075dcf0214f8dc8b33b0e429d83d270b2f0952e1 Signed-off-by: Anand Vaikar <a.vaikar2021@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80353 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
* 3rdparty/fsp: Update submodule to upstream masterFelix Singer2024-02-211-0/+0
| | | | | | | | | | | | | | | | | | | | | | Updating from commit id 507ef01: 2024-01-11 10:49:14 +0800 - (IoT ADL-S MR6 (4115_09) FSP) to commit id dd98487: 2024-02-16 17:16:05 -0800 - (Fix EagleStreamFspBinPkg Path) This brings in 6 new commits: dd98487 Fix EagleStreamFspBinPkg Path fcf623b Fix MAX_VMD_STACKS_PER_SOCKET e07f875 Fix EagleStream BSF File 85f37ab Idaville FSP - New UPDs for SSC 98e497f IoT RPL-P MR1 (4445_03) FSP fc5e3c9 IoT RPL-P MR1 (4445_03) FSP Change-Id: If7d852e1a92d8409a5161797c0aa3a55a71c8b49 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80615 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
* lib/lzmadecode: Allow for 8 byte reads on 64bitArthur Heymans2024-02-212-10/+12
| | | | | | | | | | | | | | | | | | | | | | | | | | This adds an optimization to lzma decode to also read from the boot medium in chunks of 8 bytes if that is the general purpose register length instead of always 4 bytes. It depends on the cache / memory / spi controller whether this is faster, but it's likely to be either the same or faster. TESTED - google/vilboz: cached boot medium 64bit before - 32bit - 64bit after load FSP-M: 35,674 - 35,595 - 34,690 load ramstage: 42,134 - 43,378 - 40,882 load FSP-S: 24,954 - 25,496 - 24,368 - foxconn/g41m: uncached boot medium for testing 64bit before - 32bit - 64bit after load ramstage: 51,164 - 51,872 - 51,894 Change-Id: I890c075307c0aec877618d9902ea352ae42a3bfa Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/70175 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com> Reviewed-by: Julius Werner <jwerner@chromium.org>
* mb/ocp/*: Remove unused ACPI opregionArthur Heymans2024-02-213-575/+1
| | | | | | | | | | | | The base for this region is a magic number and none for the fields are used, which likely means this was simply copied from a different firmware. Change-Id: I217bbd0b098cd15ef296854cc6262d651f11d10e Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/73183 Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* mb/google/brya/var/xol: Add support memory partsSeunghwan Kim2024-02-214-5/+17
| | | | | | | | | | | | | | | | | | | | Add support memory parts for Xol. - Samsung K3KL6L60GM-MGCT - Samsung K3KL8L80CM-MGCT BUG=b:319506033 BRANCH=firmware-brya-14505.B TEST=FW_NAME=xol emerge-brya coreboot chromeos-bootimage Proto board can boot to ChromeOS. Change-Id: Ic6a36e40f0f93109f296c5cc67a368ace81bd217 Signed-off-by: Seunghwan Kim <sh_.kim@samsung.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80637 Reviewed-by: Eric Lai <ericllai@google.com> Reviewed-by: Kapil Porwal <kapilporwal@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com>
* mb/google/brya/var/xol: Update memory configurationSeunghwan Kim2024-02-212-0/+75
| | | | | | | | | | | | | | | | | Update memory configuration following proto schematics. BUG=b:319506033 BRANCH=firmware-brya-14505.B TEST=FW_NAME=xol emerge-brya coreboot chromeos-bootimage Proto board can boot to ChromeOS. Change-Id: I59aabe0870317092f59701bdf88b53bf9731377a Signed-off-by: Seunghwan Kim <sh_.kim@samsung.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80326 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Kapil Porwal <kapilporwal@google.com> Reviewed-by: Eric Lai <ericllai@google.com>
* soc/intel/alderlake: Include ADL-N ID 5Sean Rhodes2024-02-211-0/+2
| | | | | | | | | | This patch adds support for using ADL N 4-core MCH ID 0x4618. Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: I7b9fc64ccf8e2401dcd55607e8f09b348efb3182 Reviewed-on: https://review.coreboot.org/c/coreboot/+/80166 Reviewed-by: Kapil Porwal <kapilporwal@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* mb/google/brya/var/xol: Update thermal policySeunghwan Kim2024-02-211-1/+3
| | | | | | | | | | | | | | | | | | | Update initial DTT policy and TCC setting for Xol. The setting values are from internal power team. - Critical CPU temparature: 105 -> 99 - TCC offset: 90 -> 94 BUG=b:323989520 BRANCH=firmware-brya-14505.B TEST=FW_NAME=xol emerge-brya coreboot chromeos-bootimage Change-Id: I546b313a1e6af16029309174a5bed2d1e4aa4d11 Signed-off-by: Seunghwan Kim <sh_.kim@samsung.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80410 Reviewed-by: Eric Lai <ericllai@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com>
* mb/google/nissa/var/anraggar: Change tdp_pl1_override from 6 W to 15 WWeimin Wu2024-02-211-2/+9
| | | | | | | | | | | | | | | | Set tdp_pl1_override to 15 for performance required by the thermal team. Fix policies.critical index from 2 to 0. BUG=b:313833488 TEST=emerge-nissa coreboot Change-Id: I5341bd3d4842f9298a2f5d9e589918bb1b06ba69 Signed-off-by: Weimin Wu <wuweimin@huaqin.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80620 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Eric Lai <ericllai@google.com>
* mb/google/volteer: Disable PM ACPI timer to fix S0i3 regressionMatt DeVillier2024-02-211-0/+3
| | | | | | | | | | | | | | | | | | | | | | | | Keeping the PM timer enabled will disqualify an ADL system from entering S0i3, and will also cause an increase in power during suspend states. The PM timer is not required for brya boards, therefore disabling it. Fixes: 0e90580 (soc/intel: transition full control over PM Timer from FSP to coreboot) This mirrors an identical commit for google/brya: 1ce0f3aab72d ("mb/google/brya: Fix S0i3 regression") TEST=Boot Linux on google/drobit, verify S0i3 counter incrementing after exiting S0ix suspend states. Change-Id: I644e42388c0f6127512bf52e774b79721601ecc9 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80612 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Eric Lai <ericllai@google.com> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* mb/google/brya: Create glassway variantDaniel Peng2024-02-218-0/+48
| | | | | | | | | | | | | | | | | | Create the glassway variant of the nivviks reference board by copying the template files to a new directory named for the variant. BUG=b:319071869 BRANCH=firmware-nissa-15217.B TEST=None Change-Id: I597666a5be6f71b82c7baddbe343da3d5117dd1c Signed-off-by: Daniel Peng <Daniel_Peng@pegatron.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80636 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kapil Porwal <kapilporwal@google.com> Reviewed-by: Daniel Peng <daniel_peng@pegatron.corp-partner.google.com> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Eric Lai <ericllai@google.com>
* 3rdparty/cmocka: Update cmocka to latest stable-1.1Jakub Czapiga2024-02-211-0/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | New patches: 8be3737 cmocka: Fix assert_memory_equal() display fb38de9 cmake: disable `-Wdeclaration-after-statement` a74d9cd Sanitize XML strings. 4e92198 Improve c_strreplace implementation ea6ab8b cmake: Set CMOCKA_LIBRARIES in package config for backwards compatibility 53de473 cmocka: Add overflow check for test_calloc() e738d6e tests: Add test for test_calloc() a01cc69 Bump version to 1.1.7 123f00e cpack: Update ignore files for source package generation f1e1615 Bump version 1.1.6 35dd06e tests: The exception handler doesn't work on Windows 9d72cf9 tests: Raise segmantation fault 2b20a4d tests: Rename exceptions tests array 4cd1fda tests: Better match for test_exception_handler 8ad2c4e cmake: Fix path relocation in pkgconfig file for mingw 3137fa5 cmake: Do not use CMAKE_(BINARY|SOURCE)_DIR for compile_commands.json 6e9d32f Improve INSTALL.md c4da7e1 doc: Link to the examples for mocking b13f29b include: Update copyright year info 98c451d include: Define strtok_r with Visual Studio 4aae816 gitlab-ci: Move memory and ub sanitizer to analysis stage 559381b gitlab-ci: Move freebsd to test stage ce43813 examples: Add missing compile and link options 5ead982 gitlab-ci: Introduce stages 5f366b6 gitlab-ci: Fix typo in fedora/mingw32 build 77476f7 gitlab-ci: Use gitlab windows runners 200393b gitlab-ci: Reformat yaml 406591a tests: Initialize 'struct stat' in test_assert_macros.c b201da5 cmake: Fix path where to find cmocka.dll a47b3da include: Improved call ordering documentation 61b1fb9 doc: Remove redundant words 2cc8cba Fix issue with fail_msg TEST=make unit-tests TEST=make unit-tests JUNIT_OUTPUT=y TEST=(cd payloads/libpayload; make unit-tests) TEST=(cd payloads/libpayload; make unit-tests JUNIT_OUTPUT=y) Change-Id: I60b37021e2587cc32c755719ef40a650a1c14b59 Signed-off-by: Jakub Czapiga <czapiga@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80382 Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* lib/hardwaremain: align '\' in multi-line macroFelix Held2024-02-201-2/+2
| | | | | | | | Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I5967cebad3ad52b5cbc7babc0c808039d7da5227 Reviewed-on: https://review.coreboot.org/c/coreboot/+/80635 Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* mb/google/brox: enable DPTF functionality for broxSumeet Pawnikar2024-02-201-0/+82
| | | | | | | | | | | | | | Enable DPTF functionality for brox board BRANCH=None BUG=b:324360936 TEST=Built and tested on brox board Change-Id: I0315f7f45688ccc36d321d6be4fa4fac7559a16b Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80418 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <ericllai@google.com>
* soc/intel/xeon_sp: Put SRAT util macros into Xeon-SP ACPI headerShuo Liu2024-02-204-12/+3
| | | | | | | | | | | | | | | Macros MAX_ACPI_MEMORY_AFFINITY_COUNT and MAX_SRAT_MEM_ENTRIES_PER_IMC are ACPI table specific, and could be used across Xeon-SP SoCs. This patch moves their definition from FSP header to Xeon-SP layer ACPI header. TEST=intel/archercity CRB Signed-off-by: Shuo Liu <shuo.liu@intel.com> Change-Id: I6c3a84b04a452bc8d4217947a7d12f050c94b56b Reviewed-on: https://review.coreboot.org/c/coreboot/+/80629 Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* soc/intel/xeon_sp: Use ACPI common flags in SRAT generationShuo Liu2024-02-205-18/+7
| | | | | | | | | | | | | | Move the definition of SRAT memory flags (SRAT_ACPI_MEMORY_ENABLED and SRAT_ACPI_MEMORY_NONVOLATILE) from FSP header to ACPI common codes. TEST=intel/archercity CRB Signed-off-by: Shuo Liu <shuo.liu@intel.com> Change-Id: I6aa5c20c9556fd5d680406518d19a83801b0852c Reviewed-on: https://review.coreboot.org/c/coreboot/+/80630 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com>
* soc/intel/xeon_sp: Add support for is_ioat_iio_stack_resShuo Liu2024-02-205-18/+25
| | | | | | | | | | | | | | | | IOAT is the term for the on-chip accelerator technology of Xeon-SP. In CPX and SPR, IOAT stack is also named as DINO stack. Different SoC has different check criteria for IOAT stacks, this patch introduces an util function to abstract these differences as well as cleaning up the usage of names. TEST=intel/archercity CRB Change-Id: I376928ad89b68b294734000678dad6f070d3c97d Signed-off-by: Shuo Liu <shuo.liu@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80578 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* treewide: Remove unused CHIPsArthur Heymans2024-02-205-20/+0
| | | | | | | | | | No devicetree uses these anymore. Change-Id: Ia65a0a56a6668a13761bad35f6a44ed8f6a35a78 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/72600 Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* util/crossgcc: Update LLVM from 16.0.6 to 17.0.6Felix Singer2024-02-2011-6/+6
| | | | | | | | Change-Id: Ifed410f4b7fdc358535f01850328c642d19ff1f6 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78884 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
* crossgcc: Upgrade binutils from 2.41 to 2.42Elyes Haouas2024-02-205-2/+2
| | | | | | | | Change-Id: I6e9b2dac6fed702e8e353290971699cb9ee05dfc Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80606 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>