summaryrefslogtreecommitdiffstats
path: root/Documentation/Intel
Commit message (Collapse)AuthorAgeFilesLines
* Documentation/Intel: Add NativeRaminit documentationPatrick Rudolph2017-12-099-0/+1798
| | | | | | | | | | | | | | | | Add documentation for Intel native raminit on Intel SandyBridge. Documented so far: * Register * Read training * Frequency selection * SMBIOS type 17 memory reporting * Various Kconfig options and features Change-Id: I3b977460ecb29c9a54e3fab82349982fca9918e7 Signed-off-by: Patrick Rudolph <siro@das-labor.org> Reviewed-on: https://review.coreboot.org/22275 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
* Documentation/Intel/vboot: Remove double word *after*Werner Zeh2017-11-141-1/+1
| | | | | | | | | Change-Id: I5332c5760987d6ca6e92ac8aae7f3d43e09e8e4e Signed-off-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-on: https://review.coreboot.org/22442 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
* Documentation/Intel/vboot: Fix spelling of *following*Paul Menzel2017-11-031-1/+1
| | | | | | | | Change-Id: I26cf3cb049fb5520c59316ff7397b0bcfe6ee48d Signed-off-by: Paul Menzel <pmenzel@molgen.mpg.de> Reviewed-on: https://review.coreboot.org/22178 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
* Documentation: change coreboot to lowercaseMartin Roth2017-06-121-1/+1
| | | | | | | | | | | | | | | The word 'coreboot' should always be written in lowercase, even at the start of a sentence. Unfortunately, some external websites and projects are spelling coreboot with an uppercase C, so references to those pages can't be changed without breaking the link. Change-Id: I79824da8a9ed36a1e4fe23a1711a89535267bf5f Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/20031 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
* fsp/gop: Add running the GOP to the choice of gfx initNico Huber2017-06-081-1/+0
| | | | | | | | | | | | | | | | The new config choice is called RUN_FSP_GOP. Some things had to happen on the road: * Drop confusing config GOP_SUPPORT, * Add HAVE_FSP_GOP to chipsets that support it, * Make running the GOP an option for FSP2.0 by returning 0 in random VBT getters. Change-Id: I92f88424004a4c0abf1f39cc02e2a146bddbcedf Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: https://review.coreboot.org/19815 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
* Use more secure HTTPS URLs for coreboot sitesPaul Menzel2017-06-073-50/+50
| | | | | | | | | | | | | | | | | | | The coreboot sites support HTTPS, and requests over HTTP with SSL are also redirected. So use the more secure URLs, which also saves a request most of the times, as nothing needs to be redirected. Run the command below to replace all occurences. ``` $ git grep -l -E 'http://(www.|review.|)coreboot.org' | xargs sed -i 's,http://\(.*\)coreboot.org,https://\1coreboot.org,g' ``` Change-Id: If53f8b66f1ac72fb1a38fa392b26eade9963c369 Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-on: https://review.coreboot.org/20034 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
* Documentation/Intel: Add vboot documentationLee Leahy2017-05-032-0/+403
| | | | | | | | | | | | | Add documentation which describes how to build and sign a coreboot image which enables vboot. TEST=None Change-Id: Ie17b8443772f596de0c9d8afe6f4ec3ac4d4fef8 Signed-off-by: Lee Leahy <Leroy.P.Leahy@intel.com> Reviewed-on: https://review.coreboot.org/19534 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
* Documentation/Intel/Soc: Update Quark FSP build instructionsLee Leahy2016-09-301-3/+44
| | | | | | | | | | | | | | | Update the FSP build instructions for Quark: * Discuss multiple types BRANCH=none BUG=None TEST=Build Quark FSP using new instructions Change-Id: Ibc4bfe32d0eb3877d3b988bc185c73be58d44878 Signed-off-by: Lee Leahy <Leroy.P.Leahy@intel.com> Reviewed-on: https://review.coreboot.org/16826 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
* soc/intel/quark: Pass in the memory initialization parametersLee Leahy2016-07-081-5/+5
| | | | | | | | | | | | | | Specify the memory initialization parameters in mainboard/intel/galileo/devicetree.cb. Pass these values into FSP to initialize memory. TEST=Build and run on Galileo Gen2 Change-Id: I83ee196f5fb825118a3a74b61f73f3728a1a1dc6 Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: https://review.coreboot.org/15260 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
* Documentation/Intel: Add feature documentation tableLee Leahy2016-07-081-3/+45
| | | | | | | | | | | | | | Add table containing feature documentation: * Feature name with link to specification or documentation * Linux utility name with link to utility documentation * EDK-II utility name with link to utility documentation Change-Id: Ie33d8563320697c12b34974286bffcadf92c016e Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: https://review.coreboot.org/15256 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Martin Roth <martinroth@google.com>
* Documentation/Intel/Board: Update the Galileo checklistLee Leahy2016-06-121-4/+36
| | | | | | | | | | | | Update the Galileo board implementation checklist. TEST=Build and run on Galileo Gen2 Change-Id: I1c88e9500d304273a3176d8b034a805920aab9bb Signed-off-by: Lee Leahy <Leroy.P.Leahy@intel.com> Reviewed-on: https://review.coreboot.org/15137 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
* Documentation/Intel/Board: Add Galileo checklistLee Leahy2016-06-022-0/+131
| | | | | | | | | | | | Add the Galileo implementation checklist. TEST=None Change-Id: I47e87a496cf3ae125d45c09fe6a36200f5fe724f Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: https://review.coreboot.org/15012 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
* Documentation/Intel/Board: Add analog switch linkLee Leahy2016-05-311-0/+1
| | | | | | | | | | | | Add link for TI TS5A23159 specification. TEST=None Change-Id: I2756ded963fc7597e4db1fa151bf62630b1108d9 Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: https://review.coreboot.org/15003 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
* Documentation/Intel: Update the documentationLee Leahy2016-05-183-81/+68
| | | | | | | | | | | | | | | | | | | | | | | | | | | index.html: * Separate the sections on the main page * Move the documentation links to the main page * Add links for FSP 1.0 and 2.0 specifications * Add link for UEFI specifications * Add link to MinnowBoard MAX coreboot fsp1_1.html: * Use Integration instead of Documentation SoC/quark.html: * Move documentation to main page * Update build instructions for CorebootPayloadPkg * Remove FatPkg since it is now part of edk2 tree * Add source location for QuarkFspPkg * Add build instructions for QuarkFspPkg TEST=None Change-Id: I48bd1bf98a6d8bc43bdd3b4c51dfd119a1e0f61b Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: https://review.coreboot.org/14882 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
* lib: remove FLASHMAP_OFFSET config variableAaron Durbin2016-05-111-2/+1
| | | | | | | | | | | | | | | The FLASHMAP_OFFSET config variable is used in lib/fmap.c, however the fmdtool creates a fmap_config.h with a FMAP_OFFSET #define. Those 2 values are not consistent. Therefore, remove the Kconfig variable and defer to the #define generated by fmdtool. Change-Id: Ib4ecbc429e142b3e250106eea59fea1caa222917 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/14765 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Leroy P Leahy <leroy.p.leahy@intel.com>
* Documentation: x86 MTRR setup, TempRamExit and MTRR loadingLee Leahy2016-03-211-0/+16
| | | | | | | | | | | | Document how to test TempRamExit and verify the MTRR setup and loading. TEST=None Change-Id: I57a604fa139edac4b05453547d3caf185db491e0 Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: https://review.coreboot.org/14113 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
* Documentation/Intel: Add more Galileo Gen2 linksLee Leahy2016-03-211-0/+6
| | | | | | | | | | | | | Add datasheet links for the components supporting GPIO. This includes I2C I/O ports, I2C PWMs, bus buffers and multiplexers. TEST=None Change-Id: I0a1d222d6f9bdbd824b78edf2338cd797e83ebba Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: https://review.coreboot.org/14114 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
* Documentation: x86 shadow ROM disableLee Leahy2016-03-212-2/+24
| | | | | | | | | | | | | Add documentation on disabling the SPI flash which is mapped (shadowed) into the x86 address space at 0x000e0000 - 0x000fffff. TEST=None Change-Id: I1d94d84c6cade97886a3274a7e7403f7b3275c5a Signed-off-by: Lee Leahy <Leroy.P.Leahy@intel.com> Reviewed-on: https://review.coreboot.org/14112 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
* Documentation/Intel: Add EDK-II linksLee Leahy2016-03-071-1/+3
| | | | | | | | | | | | | Add a link to the "Driver Writer's Guide" and a link to the "EDK II firmware for Intel Quark SoC X1000" document. TEST=None Change-Id: I8d629d06accfe24a0b8971b5b5868849587c3db7 Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: https://review.coreboot.org/13893 Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Tested-by: build bot (Jenkins)
* Documentation/Intel: Making a bootable SD cardLee Leahy2016-03-071-1/+2
| | | | | | | | | | | | Add a link to "Making a bootable SD card" TEST=None Change-Id: I5682fdd51a4ba37f97ad35475e11d9843f1498fb Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: https://review.coreboot.org/13892 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
* Documentation/Intel: More CorebootPayloadPkg documentationLee Leahy2016-02-294-5/+82
| | | | | | | | | | | | | | Add more documentation on the features that the EDK-II CorebootPayloadPkg is using. Add 8254 and 8259 documentation links. Add EDK-II documentation links. TEST=Boot CorebootPayloadPkg to shell prompt Change-Id: I66df1be0ba908b51b5ddb44a8671b2d7bdb46493 Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: https://review.coreboot.org/13851 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
* Documentation/Intel: Add ACPI link and more FADT documentationLee Leahy2016-02-292-12/+75
| | | | | | | | | | | | | | | Add a link to the ACPI specification. Update the FADT table to better describe the use and ACPI specification reference for the various fields. TEST=None Change-Id: I77cd925800d71398be6d677de48874099ea26479 Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: https://review.coreboot.org/13765 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Martin Roth <martinroth@google.com>
* Documentation/Intel: Add minimal APCI and TempRamExit documentationLee Leahy2016-02-243-3/+116
| | | | | | | | | | | | | Update the documentation to add the minimal ACPI support. Also add TempRamExit entry to the FSP features table. TEST=None Change-Id: I7a4576d58005a0b6834188dfeca97f1683d03cb0 Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: https://review.coreboot.org/13757 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
* Documentation/Intel: Update EDK2 CorebootPayloadPkg build instructionsLee Leahy2016-02-221-5/+42
| | | | | | | | | | | | | Update the build instructions for CorebootPayloadPkg to target the Galileo Gen2 platform. TEST=Build and run on the Galileo Gen2 platform. Change-Id: I9ca8a67811eff988f81f04d4c01c77115356c050 Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: https://review.coreboot.org/13756 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
* Documentation: x86 device tree processing and memory mapLee Leahy2016-02-193-3/+287
| | | | | | | | | | | | | | | | | Add documentation on: * FSP Silicon Init * How to start the x86 device tree processing for ramstage * Disabling the PCI devices * Generic PCI device drivers * Memory map support TEST=None Change-Id: If8f729a0ea1d48db4d5ec1d4ae3ad693e9fe44f0 Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: https://review.coreboot.org/13718 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
* Documentation: x86 add EDK2 CorebootPayloadPkg and documentation linksLee Leahy2016-02-191-13/+107
| | | | | | | | | | | | | Add EDK2 CorebootPayloadPkg build instructions, EDK2 documentation links and EDK2 BIOS build instructions. TEST=None Change-Id: I236405914c5fa8e33a7826cc4fa60f6dbf0e7724 Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: https://review.coreboot.org/13717 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
* Documentation: Add Quark EDK2 build instructions for LinuxLee Leahy2016-02-091-0/+10
| | | | | | | | | | | | Document the Linux build instructions for EDK2. TEST=Build EDK2 for Quark on Ubuntu 14.04 Change-Id: I5f87eb2c5879f2fd4dd18880908756089a0c7a51 Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: https://review.coreboot.org/13644 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
* Documentation: x86 add sleep state and minimal memory setupLee Leahy2016-02-053-0/+190
| | | | | | | | | | | | Document how to add the sleep state and minimal memory setup. TEST=None Change-Id: Ibebeef34269dbf2366f1bea6d734f6bade4e4028 Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: https://review.coreboot.org/13446 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
* Documentation: x86 Enable Serial OutputLee Leahy2016-02-054-0/+111
| | | | | | | | | | | | Document the steps necessary to enable serial output TEST=None Change-Id: Ifc0e700d7ef54fb1e28ca9bca34b94cccd3633ac Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: https://review.coreboot.org/13444 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
* Documentation: Add the x86 FSP BinaryLee Leahy2016-02-053-0/+155
| | | | | | | | | | | | Document how to add the FSP binary to the SPI flash image. TEST=None Change-Id: I51b16600ea69853240282ac2eb0d84935b8e2a71 Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: https://review.coreboot.org/13442 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
* Documentation: Add Galileo Gen 1 DocumentationLee Leahy2016-02-051-12/+38
| | | | | | | | | | TEST=None Change-Id: Ic5a732dc27e772c4708a090ecd0c0af17dc5b056 Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: https://review.coreboot.org/13606 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
* Documentation: Fix links to Intel/documentation.htmlLee Leahy2016-02-057-11/+11
| | | | | | | | | | | | | Fix links to the documenation.html page which was renamed from x86Documenation.html. TEST=Verified documentation links and searched for x86Documenation.html Change-Id: Icee79bab4c05ac9b8010dc7acdde8dd5e2ab2909 Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: https://review.coreboot.org/13592 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
* Documentation: Add x86 bootblock supportLee Leahy2016-02-042-0/+97
| | | | | | | | | | | | Document what is involved with adding the bootblock support. TEST=None Change-Id: I6c8cc38e1b9346b4962588b33ca5e4ab8eac24c3 Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: https://review.coreboot.org/13441 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
* Documenation: x86 Quark/Galileo remove i586 warningLee Leahy2016-02-022-60/+19
| | | | | | | | | | | | Leverage patch 13552 by adding USE_MARCH_586 to soc/intel/quark/Kconfig. TEST=None Change-Id: Ifac947db53e967b98b9494db3f6c3f8ee039ac73 Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: https://review.coreboot.org/13561 Reviewed-by: Martin Roth <martinroth@google.com> Tested-by: build bot (Jenkins)
* Documentation: Add x86 documentation for required filesLee Leahy2016-02-027-0/+556
Document the required files to perform a minimal coreboot/FSP build for x86. TEST=None Change-Id: I65b2947114634fce982ce82fb7c577fd5f47ed10 Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: https://review.coreboot.org/13438 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
generated by cgit v1.2.3 (git 2.25.1) at 2024-09-21 01:17:25 +0000