summaryrefslogtreecommitdiffstats
path: root/Documentation
Commit message (Collapse)AuthorAgeFilesLines
* Documentation: Mention newer Intel μ-code updates in 4.13 release notesPaul Menzel2020-11-221-0/+24
| | | | | | | | | | Start a new section *Notes* for these kind of information. Change-Id: I86be22cebb96e6f07676a9bc52794a4c12dad3e4 Signed-off-by: Paul Menzel <pmenzel@molgen.mpg.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47762 Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* Doc/releases/checklist.md: Fix up URLsAngel Pons2020-11-221-5/+5
| | | | | | | | | | | Use angle brackets so that they appear as links, and update a link to a Gerrit change to use the current format. Change-Id: I41f82986429dcfd1cbc5b5c088a0c47bd24a57c4 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47812 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* Doc/releases/checklist.md: Add reminder to unpack relnotesAngel Pons2020-11-221-1/+2
| | | | | | | | | | Explicitly add this easy-to-forget step. Also add a missing period. Change-Id: Iaf13155fcc8a70f3565fb2404cef886524fa5161 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47811 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* mb/kontron: Add Kontron mAL10 COMe module supportMaxim Polyakov2020-11-222-0/+110
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch adds support for the Kontron mAL10 COMe module with the Apollo Lake SoC together with Kontron T10-TNI carrierboard. Working: - UART console and I2C on Kontron kempld; - USB2/3 - Ethernet controller - eMMC - SATA - PCIe ports - IGD/DP - SMBus - HWM Not tested: - IGD/LVDS - SDIO TODO: - HDA (codec IDT 92HD73C1X5, currently disabled) Tested payloads: - SeaBIOS - Tianocore, UEFIPayload - without video, EFI-shell in console only Tested on COMe module with Intel Atom x5-E3940 processor (4 Core, 1.6/1.8GHz, 9.5W TDP). Xubuntu 18.04.2 was used as a bootable OS (5.0.0-32-generic linux kernel) Change-Id: Ib8432e10396f77eb05a71af1ccaaa4437a2e43ea Signed-off-by: Maxim Polyakov <max.senia.poliak@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39133 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
* Documentation/releases: Update for 4.134.13Angel Pons2020-11-204-21/+139
| | | | | | | | | | | Fill in some blanks for 4.13, mark it done, add template for 4.14. Also update the list of vboot supported boards. Change-Id: Ie593efe515136a3b06620db6f0dbe3da00df7e9b Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47801 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
* mb/clevo/kbl-u: Add Clevo N130WU/N131WUFelix Singer2020-11-202-0/+51
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Working: - TianoCore - NVMe, SATA3 - USB2, USB3 - Thunderbolt - Graphics (GOP and libgfxinit) - Sound - Webcam - WLAN, LAN, Bluetooth, LTE - Keyboard, touchpad - TPM - flashrom support; reading / flashing from Linux - ACPI S3 WIP: - Documentation Not working: - EC ACPI (e.g. Fn keys, battery and power information) Boots Arch Linux (Linux 5.8.12) successfully. Change-Id: I364f5849ef88f43b85efbd7a635a27e54d08c513 Signed-off-by: Felix Singer <felixsinger@posteo.net> Signed-off-by: Paul Menzel <pmenzel@molgen.mpg.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/28640 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
* doc/relnotes/4.13: Remove duplicated `CPU`Angel Pons2020-11-191-1/+1
| | | | | | | | | | | | | Change-Id: Ib423a0d4341560301138e06b00a704c2baae4867 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47767 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Christian Walter <christian.walter@9elements.com> Reviewed-by: Felix Singer <felixsinger@posteo.net> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* doc/relnotes/4.13: Fix random spelling mistakesNico Huber2020-11-191-3/+3
| | | | | | | | | | Change-Id: I7486124fbe43f15bfbbf0875a58935133639b35f Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47670 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Felix Singer <felixsinger@posteo.net> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* Doc/relnotes/4.13: Add details about resource allocator v4Furquan Shaikh2020-11-191-0/+29
| | | | | | | | | | | This change adds details about the new resource allocator v4 in coreboot to the release notes for 4.13. Change-Id: I7071bdf0faffda61fc5941886c963181939c07e3 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47660 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
* doc/relnotes/4.13: Add changes to log-level configurabilityNico Huber2020-11-191-0/+12
| | | | | | | | Change-Id: Ia7ef57d20ea5099f344ccbf58d76597cb0e82c85 Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47669 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* doc/relnotes/4.13: Add note about PCI bus mastering Kconfig optionsFelix Singer2020-11-191-0/+31
| | | | | | | | | | Change-Id: I66a636f554d18e08a209a7cfd6a59cf13a88f2e1 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47409 Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* Doc/relnotes/4.13: Add several relevant changesAngel Pons2020-11-131-0/+21
| | | | | | | | | | While some of these have little impact, they are worth mentioning here. Change-Id: Idbf629ae77b8918ff1d93edb7b6c4669bbbe17df Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47444 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
* Delete mainboard/google/chezaJulius Werner2020-11-121-1/+0
| | | | | | | | | | | | Work on this mainboard was abandoned and never finished. It's not really usable in its current state, so let's get rid of it. Signed-off-by: Julius Werner <jwerner@chromium.org> Change-Id: I4cd2e2cd0ee69d9846472653a942fa074e2b924d Reviewed-on: https://review.coreboot.org/c/coreboot/+/47427 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
* Documentation/releases: Add ASan to 4.13 relnotesHarshit Sharma2020-11-111-0/+9
| | | | | | | | Change-Id: I2953729c69dfcfa8b34192b3e1623fdfad87ca3a Signed-off-by: Harshit Sharma <harshitsharmajs@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45118 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* mb/hp: Add HP EliteBook Folio 9480mIru Cai2020-11-103-0/+157
| | | | | | | | | | | | | | | | | | | | The code is based on autoport, with necessary modifications. This laptop uses SMSC MEC1322 embedded controller, but the EC interface is the same as the EliteBook laptops of previous generations that use KBC1126 EC. So it still uses ec/hp/kbc1126, but does not need EC firmware inserted into CBFS. We also need to leave the end of the OEM flash content untouched, so the default ROM size is set to 12MiB instead of 16MiB, and we need to modify the IFD when flashing. Thanks to persmule for providing the laptop and pointing out how to program the system flash chip of it. Change-Id: I2328c43cbb1f488aa1d0ddd9116814d971e5d8ae Signed-off-by: Iru Cai <mytbk920423@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45578 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
* Documentation: Introduce HP Sure Start and the method to bypass itIru Cai2020-11-092-0/+61
| | | | | | | | Change-Id: Id198afdaa13b4c361e1b77a56d5a2436ed1c4c86 Signed-off-by: Iru Cai <mytbk920423@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45577 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* mb/purism/librem_cnl: Add new variant 'Librem Mini v2'Matt DeVillier2020-11-091-17/+23
| | | | | | | | | | | | Add Kconfig entries, and update existing documentation to accomodate both v1/v2 versions of the board. Change-Id: I856bb914941211cfbec4fed871ba2a5a038e23c3 Signed-off-by: Matt DeVillier <matt.devillier@puri.sm> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46984 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* docs/librem_mini: update CPU, known issues sectionMatt DeVillier2020-10-311-6/+7
| | | | | | | | | | | | | | Both 8565U and 8665U CPUs are used in the Librem Mini. SATA issue updated based on addition of HSIO PHY tuning params and resulting changes. Change-Id: I33a093ccfea077402e1b3651f9ca5d6d8a2818f8 Signed-off-by: Matt DeVillier <matt.devillier@puri.sm> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46983 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
* fw_config: Convert fw_config to a 64-bit fieldTim Wawrzynczak2020-10-301-5/+5
| | | | | | | | | | | | | | | | | We all knew this was coming, 32 bits is never enough. Doing this early so that it doesn't affect too much code yet. Take care of every usage of fw_config throughout the codebase so the conversion is all done at once. BUG=b:169668368 TEST=Hacked up this code to OR 0x1_000_0000 with CBI-sourced FW_CONFIG and verify the console print contained that bit. Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Change-Id: I6f2065d347eafa0ef7b346caeabdc3b626402092 Reviewed-on: https://review.coreboot.org/c/coreboot/+/45939 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* .gitignore: Split into subdirectory filesPatrick Georgi2020-10-301-0/+7
| | | | | | | | | | | | | | There's no need for the global list of files to ignore, so use git's ability to work with more local configuration. Change-Id: I50882e6756cbc0fdfd899353cc23962544690fb3 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46879 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-by: Christian Walter <christian.walter@9elements.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* drivers/smmstore: Implement SMMSTORE version 2Patrick Rudolph2020-10-222-0/+222
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | SMMSTORE version 2 is a complete redesign of the current driver. It is not backwards-compatible with version 1, and only one version can be used at a time. Key features: * Uses a fixed communication buffer instead of writing to arbitrary memory addresses provided by untrusted ring0 code. * Gives the caller full control over the used data format. * Splits the store into smaller chunks to allow fault tolerant updates. * Doesn't provide feedback about the actual read/written bytes, just returns error or success in registers. * Returns an error if the requested operation would overflow the communication buffer. Separate the SMMSTORE into 64 KiB blocks that can individually be read/written/erased. To be used by payloads that implement a FaultTolerant Variable store like TianoCore. The implementation has been tested against EDK2 master. An example EDK2 implementation can be found here: https://github.com/9elements/edk2-1/commit/eb1127744a3a5d5c8ac4e8eb76f07e79c736dbe2 Change-Id: I25e49d184135710f3e6dd1ad3bed95de950fe057 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Signed-off-by: Christian Walter <christian.walter@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40520 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
* mb/supermicro/x11-lga1151-series: add x11ssh-f board as a variantBill XIE2020-10-201-0/+103
| | | | | | | | | | | This adds another X11 series board, the X11SSH-F, which is similiar to X11SSH-TF but differs in PCIe interfaces/devices, ethernet interfaces. Signed-off-by: Bill XIE <persmule@hardenedlinux.org> Change-Id: I92c32bff861f0b5697aea52ff282fae76b3b78ac Reviewed-on: https://review.coreboot.org/c/coreboot/+/45229 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
* Documentation: Fix spelling of *assumptions*Paul Menzel2020-10-191-1/+1
| | | | | | | | Change-Id: I36e0e713647cfc0d25e6b4ead81aa212be530afb Signed-off-by: Paul Menzel <pmenzel@molgen.mpg.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33742 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* drivers/intel/usb4: Add driver for USB4 retimer deviceDuncan Laurie2020-10-191-0/+40
| | | | | | | | | | | | | | | | The USB4 retimer device needs to declare a _DSM with specific functions that allow for GPIO control to turn off the power when an external device is not connected. This driver allows the mainboard to provide the GPIO that is connected to the power control. BUG=b:156957424 Change-Id: Icfb85dc3c0885d828aba3855a66109043250ab86 Signed-off-by: Duncan Laurie <dlaurie@google.com> Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44918 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* lenovo/t440p: Add HDA verbs from the OEM firmwareIru Cai2020-09-301-1/+0
| | | | | | | | | | | | | | | | To get the HDA verbs from the OEM firmware, open the firmware with UEFITool, search for the existing HDA verbs, extract the UEFI module and look for the verbs. Copy the consecutive 4 dword sets that look like HDA verbs. It is tested to make audio output from both the speaker and headphone work. Change-Id: Ie359fdf6785b1c0be8dc201cd76176c0a7fe7942 Signed-off-by: Iru Cai <mytbk920423@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45693 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
* doc/mb/ocp: update deltalake server documentationJonathan Zhang2020-09-281-10/+16
| | | | | | | | | | | Upon completion of 2nd build/test/release cycle of Deltalake server alternative firmware engineering, update the document. Signed-off-by: Jonathan Zhang <jonzhang@fb.com> Change-Id: I1806526bd477ed407bb7fd36c7fe4ce0e57b72f0 Reviewed-on: https://review.coreboot.org/c/coreboot/+/45707 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
* Documentation/mainboard: Add Missing OCP Delta Lake LinkChristian Walter2020-09-281-0/+1
| | | | | | | | Change-Id: I379d6a7b72a0398c34ea8eeda09ccd663fc372ce Signed-off-by: Christian Walter <christian.walter@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45659 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
* Documentation/getting_started/kconfig.md: Add a note about Kconfig defaultsElyes HAOUAS2020-09-251-0/+2
| | | | | | | | | | | | | | When the declaration is done after the default, menuconfig will see that symbol defined at the first place where kconfig tool will find it. For example, if we run menuconfig and search for 'MAINBOARD_VENDOR', we will see it defined at ""src/mainboard/51nb/Kconfig" which is odd. Change-Id: I215a1817e60e6deb6931679f139d110ba762d3c8 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45127 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Nico Huber <nico.h@gmx.de>
* Documentation: Add ASan documentationHarshit Sharma2020-09-212-0/+303
| | | | | | | | | Change-Id: I710ea495798597189941620c7e48fd5aa7476781 Signed-off-by: Harshit Sharma <harshitsharmajs@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44814 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
* strongbad / coachz : Add Initial SupportBob Moragues2020-09-111-0/+1
| | | | | | | | | | | | | BUG=b:162409909 BUG=b:164196066 BRANCH=NONE TEST=Verify build of strongbad target Signed-off-by: Bob Moragues <moragues@chromium.org> Change-Id: If83bd2c8f25fdd3c9625f40121e55c3c922a66fe Reviewed-on: https://review.coreboot.org/c/coreboot/+/45276 Reviewed-by: Julius Werner <jwerner@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* soc/amd/picasso: Move APCB generation out of picassoRob Barnes2020-09-101-38/+3
| | | | | | | | | | | | | | | | | | Move APCB generation out of the picasso makefile and into the mainboard makefile. APCB generation tends to be mainboard specific and does not belong in the soc makefile. BUG=b:168099242 TEST=Build mandolin and check for APCB in coreboot binary Build and boot ezkinil Change-Id: Ib85ad94e515f2ffad58aafe06c1f1d4043e9303c Signed-off-by: Rob Barnes <robbarnes@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45222 Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* Documentation: Discuss how we use languagePatrick Georgi2020-08-312-0/+137
| | | | | | | | | | Change-Id: I44fa30af538c78760821401c8d3c52029d95b72b Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43420 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
* Documentation: Update release notes for x86_64Patrick Rudolph2020-08-311-0/+9
| | | | | | | | | Change-Id: I7d8d39bde3b3364ff6ce93030aa2bab34598acd8 Signed-off-by: Patrick Rudolph <siro@das-labor.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44781 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
* Doc/soc/intel: Add info about microcode updatesAngel Pons2020-08-262-0/+137
| | | | | | | | | | | | Document a general overview of when and how microcode should be updated. Also explain what microcode updates are, and why they are required. Change-Id: I6dbe25122fa45a416ed64180ef1bfb11afe676ba Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44400 Reviewed-by: Patrick Rudolph <siro@das-labor.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* docs/purism/librem_mini: Fixup CPU model, markup linksMatt DeVillier2020-08-211-3/+5
| | | | | | | | Change-Id: I26c0936c912490fc0ba28ee53139e3a1f3a00911 Signed-off-by: Matt DeVillier <matt.devillier@puri.sm> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44555 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
* mb/emulation/qemu-q35,qemu-i440fx: Add x86_64 supportPatrick Rudolph2020-08-194-15/+144
| | | | | | | | | | | | | | | | | | | | | * Enable optional x86_64 romstage, postcar and ramstage * Add Kconfig for x86_64 compilation * Add documentation for x86 qemu mainboards * Increase CAR stack as x86_64 uses more than 0x4000 bytes Working: * Boots to Linux * Boots to SeaBIOS * Drops to protected mode at end of ramstage * Enumerates PCI devices * Relocateable ramstage * SMM Change-Id: If2f02a95b2f91ab51043d4e81054354f4a6eb5d5 Signed-off-by: Patrick Rudolph <siro@das-labor.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/29667 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* arch/x86/boot: Jump to payload in protected modePatrick Rudolph2020-08-191-1/+3
| | | | | | | | | | | | | | | | | | * On ARCH_RAMSTAGE_X86_64 jump to the payload in protected mode. * Add a helper function to jump to arbitrary code in protected mode, similar to the real mode call handler. * Doesn't affect existing x86_32 code. * Add a macro to cast pointer to uint32_t that dies if it would overflow on conversion Tested on QEMU Q35 using SeaBIOS as payload. Tested on Lenovo T410 with additional x86_64 patches. Change-Id: I6552ac30f1b6205e08e16d251328e01ce3fbfd14 Signed-off-by: Patrick Rudolph <siro@das-labor.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/30118 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
* arch/arm: Enable FIT payloadsSam Lewis2020-08-191-0/+8
| | | | | | | | | | | | | | | | Implements fit_payload_arch for the arm (aarch32) architecture, so that FIT images can be used. The implementation is very similar to the existing implementations for arm64 and riscv, and has mostly been lifted from these other ports. TEST: Booted Beaglebone Black (in progress port, to be submitted soon!) with a FIT image containing a 5.4 kernel, dtb and initramfs. Change-Id: I6b50c6f06b83c00a5b3622b5bbafe67130b6d233 Signed-off-by: Sam Lewis <sam.vr.lewis@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44377 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
* documentation: Add documentation for Purism Librem MiniMatt DeVillier2020-08-184-0/+124
| | | | | | | | | Change-Id: Ie5699942f48d2d5b1417f447a9a36b98e4b18156 Signed-off-by: Matt DeVillier <matt.devillier@puri.sm> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42882 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* mainboard: Add HP EliteBook 2560pIru Cai2020-08-173-0/+100
| | | | | | | | | | | | Most of the code is generated by autoport. The laptop works well under coreboot with SeaBIOS 1.13.0 payload, running Arch Linux with kernel 5.4.39 and 5.6.11. Change-Id: I126916e201fb8e4b9067f2dececebfb5bae6df73 Signed-off-by: Iru Cai <mytbk920423@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41159 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
* cpu/x86/smm: Introduce SMM module loader version 2Rocky Phagura2020-08-151-0/+10
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Xeon-SP Skylake Scalable Processor can have 36 CPU threads (18 cores). Current coreboot SMM is unable to handle more than ~32 CPU threads. This patch introduces a version 2 of the SMM module loader which addresses this problem. Having two versions of the SMM module loader prevents any issues to current projects. Future Xeon-SP products will be using this version of the SMM loader. Subsequent patches will enable board specific functionality for Xeon-SP. The reason for moving to version 2 is the state save area begins to encroach upon the SMI handling code when more than 32 CPU threads are in the system. This can cause system hangs, reboots, etc. The second change is related to staggered entry points with simple near jumps. In the current loader, near jumps will not work because the CPU is jumping within the same code segment. In version 2, "far" address jumps are necessary therefore protected mode must be enabled first. The SMM layout and how the CPUs are staggered are documented in the code. By making the modifications above, this allows the smm module loader to expand easily as more CPU threads are added. TEST=build for Tiogapass platform under OCP mainboard. Enable the following in Kconfig. select CPU_INTEL_COMMON_SMM select SOC_INTEL_COMMON_BLOCK_SMM select SMM_TSEG select HAVE_SMI_HANDLER select ACPI_INTEL_HARDWARE_SLEEP_VALUES Debug console will show all 36 cores relocated. Further tested by generating SMI's to port 0xb2 using XDP/ITP HW debugger and ensured all cores entering and exiting SMM properly. In addition, booted to Linux 5.4 kernel and observed no issues during mp init. Change-Id: I00a23a5f2a46110536c344254868390dbb71854c Signed-off-by: Rocky Phagura <rphagura@fb.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43684 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
* arch/x86/postcar: Add x86_64 supportPatrick Rudolph2020-08-141-1/+1
| | | | | | | | | | | | | | | * Add support for loading GDT on x86_64. * Add x86_64 assembly code to do the same as the x86_32 code. * Separate x86_32 and x86_64 code. Tested on qemu x86_32 and x86_64 using additional MTRRs. Tested on Lenovo T410 with additional x86_64 patches. Change-Id: I1c190627f5f0ed6f82738cb99423892382899d7b Signed-off-by: Patrick Rudolph <siro@das-labor.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/30500 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* doc/mb/ocp: update Delta Lake documentationJonathan Zhang2020-08-141-19/+31
| | | | | | | | | | | Update Delta Lake documentation following ww30 to ww33 build/test/release cycle. Signed-off-by: Jonathan Zhang <jonzhang@fb.com> Change-Id: I9bb3a4daa423503d487045f2f069a43d2cc09129 Reviewed-on: https://review.coreboot.org/c/coreboot/+/44360 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
* mb/asus: Add Asus A88XM-E FM2+ with documentationBalazs Vinarz2020-08-131-0/+170
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | The port is based on the F2A85-M, the main differences are: - 2 DDR3 dimms - 2 PS/2 ports - 2*USB2.0 and 2*USB3.0 ports - 3+2 phase VRM - 6 channel audio - 6 SATA ports - ASP1206 VRM controller - Bolton D4 chipset - no optical SPDIF/IO Successfully booted configurations: -RAM: 2*8GB Kingston KVR 1333Mhz LP, 2*8GB Crucial BLT8G3D1869DT1TX0 -CPU: AMD A8-6500 (Richland), AMD A10-6700 (Richland) -OS: Arch Linux 4.19 (SATA, USB), Linux Mint 19.3, Artix Linux 2019 -SeaBIOS: 1.12 and 1.13 Known problems: - IRQ routing is done incorrect way - common problem of fam15h boards - Windows 7 can't boot because of the incomplete ACPI implementation Change-Id: I60fa0636ba41f5f1a6a3faa2764bf2f0a968cf90 Signed-off-by: Balazs Vinarz <vinibali1@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/30987 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* Documentation: Fix sphinx configurationPatrick Georgi2020-08-041-1/+1
| | | | | | | | | | | | | | Without the brackets, the string seems to be added as a list of characters, and since there's no extension called 's', sphinx bails out. Change-Id: If0fc9c1a74f334b6154df3cb26836509de913567 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44114 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* Doc/mb/facebook/monolith: Correct grammar by removing plural *s*Paul Menzel2020-08-031-1/+1
| | | | | | | | Change-Id: I2d14902f9d975e89cd2842f4c12eab8ca4018fbf Signed-off-by: Paul Menzel <pmenzel@molgen.mpg.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44018 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* Doc/mb/lenovo: Mark up file name as code/monospacePaul Menzel2020-08-031-1/+1
| | | | | | | | Change-Id: I397b1dc0c3faf65811889d4c5814d6dcca7fe6b4 Signed-off-by: Paul Menzel <pmenzel@molgen.mpg.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43748 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* doc/getting_started: update name of file generated by "make savedefconfig"Jonathan Zhang2020-07-291-1/+1
| | | | | | | | | | | Update kconfig.md to reflect that defconfig (instead of mini-config) file is generated by running "make savedefconfig". Signed-off-by: Jonathan Zhang <jonzhang@fb.com> Change-Id: I4075e5b51e3c504eaad25e3abfc52ba593364ee9 Reviewed-on: https://review.coreboot.org/c/coreboot/+/43973 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
* Documentation: Revise "24 hours wait period" rulesPatrick Georgi2020-07-291-9/+36
| | | | | | | | | | | | They're more or less the same but reworked for hopefully some more clarity. There have been some best practices around documenting the reason for expedited processing so let's make them official, too. Change-Id: I620e48016a1ceda2ac43f26624ed21af01f6a0a5 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43484 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* Doc/mb/facebook/monolith: Use correct TianoCore commit hashPaul Menzel2020-07-281-1/+1
| | | | | | | | | | | The commit hash is the same as the SeaBIOS one, and is indeed from the SeaBIOS repository. Change-Id: I820b9b748778050fc694c13b1e2b2fc80885b4f1 Signed-off-by: Paul Menzel <pmenzel@molgen.mpg.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43749 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
generated by cgit v1.2.3 (git 2.25.1) at 2024-06-06 21:50:07 +0000