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* Documentation: xx30 ThinkPads internal flashingEvgeny Zinoviev2020-02-056-0/+373
| | | | | | | | | | | | Add detailed instructions on how to unlock protected SPI ranges and flash coreboot internally on Lenovo ThinkPad Ivy Bridge series by exploiting stock BIOS security issues. Change-Id: I8d8551910c31fd2e6ff728e17dafaea45970166b Signed-off-by: Evgeny Zinoviev <me@ch1p.io> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36666 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
* Documentation/vendorcode/eltan: Update security documentWim Vervoorn2020-01-301-23/+96
| | | | | | | | | | | | | | | | Update the security document to reflect the current state of the coreboot implementation. Add more detail and document the change to the public vboot API. BUG=N/A TEST=build Change-Id: I228d0faae0efde70039680a981fea9a436d2384f Signed-off-by: Wim Vervoorn <wvervoorn@eltan.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38591 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* Documentation/mainboard/facebook/monolith.md: Update to beta statusWim Vervoorn2020-01-301-10/+27
| | | | | | | | | | | | | | Update to reflect the beta status of the code. BUG=N/A TEST=build Change-Id: I9d1c42d24578c9420569da7e294d5c723da3c772 Signed-off-by: Wim Vervoorn <wvervoorn@eltan.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38607 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Frans Hendriks <fhendriks@eltan.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
* Documentation/mainboard/facebook/monolith.md: Add flash componentsWim Vervoorn2020-01-291-0/+38
| | | | | | | | | | | | | | Add description of the procedure to create the flash components for this system. BUG=N/A TEST=N/A Change-Id: I2690dfbe715fa120f840d98c57fdc3fd7e8b45b1 Signed-off-by: Wim Vervoorn <wvervoorn@eltan.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38588 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
* Doc/mb/lenovo: Shrink picture for x301Bill XIE2020-01-271-0/+0
| | | | | | | | | | | Fix a non-standard larger picture not handled in time before merging. Change-Id: Ia494484cd0eff6b19408b065264911d0093ceeb0 Signed-off-by: Bill XIE <persmule@hardenedlinux.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38582 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Idwer Vollering <vidwer@gmail.com>
* mainboard/system76: Add System76 Lemur Pro (lemp9)Jeremy Soller2020-01-271-0/+73
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The System76 Lemur Pro (lemp9) is an upcoming laptop computer. Support in coreboot is developed by System76 and provided as the default firmware option. Testing is done on a pre-production model expected to be identical from a firmware perspective to the production model. Working: - Payload - Tianocore - CPU - Intel i7-10510U - Intel i5-10210U - EC - ITE IT5570E running https://github.com/system76/ec - Backlit Keyboard, with standard PS/2 keycodes and SCI hotkeys - Battery - Charger, using AC adapter or USB-C PD - Suspend/resume - Touchpad - GPU - Intel UHD Graphics 620 - GOP driver is recommended, VBT is provided - eDP 14-inch 1920x1080 LCD - HDMI video - USB-C DisplayPort video - Memory - Channel 0: 8-GB on-board DDR4 Samsung K4AAG165WA-BCTD - Channel 1: 8-GB/16-GB/32-GB DDR4 SO-DIMM - Networking - M.2 PCIe/CNVi WiFi/Bluetooth - Sound - Realtek ALC293D - Internal speaker - Internal microphone - Combined headphone/microphone 3.5-mm jack - HDMI audio - USB-C DisplayPort audio - Storage - M.2 PCIe/SATA SSD-1 - M.2 PCIe/SATA SSD-2 - RTS5227S MicroSD card reader - USB - 1280x720 CCD camera - USB 3.1 Gen 2 Type-C (left) - USB 3.1 Gen 2 Type-A (left) - USB 3.1 Gen 1 Type-A (right) Not working: - TPM2 - SPI bus 0, chip select 2 is used. Chip selects other than 0 are not currently supported by the intel fast_spi driver. Signed-off-by: Jeremy Soller <jeremy@system76.com> Change-Id: Ib0a32bbc6f89a662085ab4a254676bc1fad7dc60 Reviewed-on: https://review.coreboot.org/c/coreboot/+/38463 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
* Documentation: link asus p5q on mainboard pageFelix Held2020-01-231-0/+1
| | | | | | | | | Change-Id: Ia3f58cc15897bff87dd699ab1fb1c42545119f0b Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38518 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
* mb/asus/p5qc: Add ASUS P5Q as a variant (with documentation)Ivan Vatlin2020-01-211-0/+77
| | | | | | | | Change-Id: I6c7bbb89af88cce1a53c21a4b4d8bc1c284e1cb2 Signed-off-by: Ivan Vatlin <jenrus@tuta.io> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38143 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
* Documentation/superio: add generic PNP device documentationFelix Held2020-01-202-0/+115
| | | | | | | | | Change-Id: Iee75faaef713dd6ec6b6e2d536df09a41010eebf Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38016 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
* documentation: Add documentation on setting up mainboard GPIOsTim Wawrzynczak2020-01-182-0/+137
| | | | | | | | | | | | | The new documentation describes typical ways that mainboards will set up their GPIOs, as well as the distinction between "early" and "normal" GPIOs. It also describes the typical properties that GPIO configuration will cover. Change-Id: I279eec4ed2bb0248a2bdb363fb73b40b8272267f Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37802 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Justin TerAvest <teravest@chromium.org>
* Documentation: document non-Docker sphinx installation and usageFelix Held2020-01-141-2/+19
| | | | | | | | | | | Also update the known-good versions of the needed tools. Change-Id: I0f63860beb0a8a00360752318236e302c7170977 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37952 Reviewed-by: Patrick Rudolph <siro@das-labor.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* {Documentation,soc/intel}: Fix typoElyes HAOUAS2020-01-101-1/+1
| | | | | | | | | Change-Id: I708ab503ece37f44cc38511aad2383ab2cec3368 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37468 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* acpi: Be more ACPI compliant when generating _UIDPatrick Rudolph2020-01-092-0/+16
| | | | | | | | | | | | | | | | | | * Add function to generate unique _UID using CRC32 * Add function to write the _UID based on a device's ACPI path ACPI devices that have the same _HID must use different _UID. Linux doesn't care about _UID if it's not used. Windows 10 verifies the ACPI code on boot and BSODs if two devices with the same _HID share the same _UID. Fixes BSOD seen on Windows 10. Change-Id: I47cd5396060d325f9ce338afced6af021e7ff2b4 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37695 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
* util/supermicro: Add and use new tool smcbiosinfoPatrick Rudolph2020-01-062-0/+33
| | | | | | | | | | | | | | | | | | | | | | | | | | | The BMC and tools interacting with it depend on metadata placed inside the ROM in order the flash the BIOS. Add a new tool smcbiosinfo, integrate it into the build system, and generate a 128byte metadata file called smcbiosinfo.bin on build. You need to provide the BoardID for every SMC mainboard through a new Kconfig symbol: SUPERMICRO_BOARDID Some fields are unknown, but it's sufficient to flash it using SMC vendor tools. Tested on Supermicro X11SSH: * Flashing using the WebUI works * Flashing using SMCIPMITool works No further validation is done on the firmware. Change-Id: Id608c2ce78614b45a2fd0b26d97d666f02223998 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35484 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com> Reviewed-by: Nico Huber <nico.h@gmx.de>
* Doc/tutorial/part2.md: Align headings with part1.mdAngel Pons2019-12-261-13/+13
| | | | | | | | | | | Substitute `Part` with `Step` on this file's headings and use present tense instead of gerund. Change-Id: Ic130ed9865be43716e7de3121534761d9fc2ae8d Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37933 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jacob Garber <jgarber1@ualberta.ca>
* Doc/tutorial/part1.md: Fix minor formatting issuesAngel Pons2019-12-261-2/+2
| | | | | | | | | | Make sure all titles are capitalized, and add a missing period. Change-Id: I48b8d6c85b915cc422bdfa3a89804f92f46800ba Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37932 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jacob Garber <jgarber1@ualberta.ca>
* Doc/index.md: Fix a typoAngel Pons2019-12-261-1/+1
| | | | | | | | Change-Id: Ib2f48d03e78f6da97383e67b1d50dfe859e59612 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37934 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
* Doc/releases/checklist.md: Correct some inconsistenciesAngel Pons2019-12-261-17/+17
| | | | | | | | | | | Use periods on every element of a list, and make `IRC` uppercase. Also, correct a grammar mistake that slipped through. Change-Id: Id05865719c7c845265416e89bfd9b02b6d22ca6c Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37709 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
* superio/common: Add more ACPI methodsPatrick Rudolph2019-12-221-4/+25
| | | | | | | | | | | | | | | | | | | * Make use of introduced SSDT config mode access * Make use of introduced SSDT mutex * Provide ACPI functions to safely access SIO config space * Implement method to query LDN enable state * Implement method to set LDN enable state * Use introduced functions to implement _DIS and _STA in the device * Update documentation Tested on Aspeed AST2500 and Linux 5.2. Manually verified ACPI code that generates no errors in Linux. Change-Id: I520b29de925f368cd71ff8f1f58d2d57d72eff8d Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37640 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
* Documentation: Extend release checklist (list to-be deprecated boards)Patrick Georgi2019-12-161-0/+3
| | | | | | | | | | | | | | Make it part of the release process to note not only what config flags / code properties etc will be deprecated, but to also spell out which boards would be affected at the time of the release. Change-Id: I0ef1404e75182ea4bacae31edb0a843e7a359545 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37702 Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* Doc/mb/gigabyte/ga-h61m-s2pv: Correct IFD sectionAngel Pons2019-12-131-12/+8
| | | | | | | | | Change-Id: Ic94dd7381e9a107081011d083286d27005148557 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36301 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Reviewed-by: Nico Huber <nico.h@gmx.de>
* Documentation: Fix EC type for facebook and portwell boardsWim Vervoorn2019-12-123-3/+3
| | | | | | | | | | | | | | | | Board description contained incorrect EC type. Change EC type to ITE8528 BUG=N/A TEST=build Change-Id: Ib5af79fb00bfdfc5dbe001b60010a74bddc696e2 Signed-off-by: Wim Vervoorn <wvervoorn@eltan.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37657 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
* Documentation: enable ditaa integrationPatrick Georgi2019-12-121-0/+2
| | | | | | | | | | | For prettier diagrams: http://ditaa.sourceforge.net/ Change-Id: Ic28dc5ea9d82ff6bf8654e2e33e675a536348654 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37646 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
* Documentation: Fix table and layoutPatrick Georgi2019-12-111-3/+3
| | | | | | | | | | | | | | | The table wasn't pretty enough so sphinx complained, while the second paragraph had trailing whitespace, could be wrapped differently and also came with a typo. Change-Id: I6c16a3a1fcc306d0b12043ebec7d4e69e9339d7d Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37642 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Wim Vervoorn <wvervoorn@eltan.com> Reviewed-by: Frans Hendriks <fhendriks@eltan.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
* Documentation: Describe how to deal with snooping https proxiesPatrick Georgi2019-12-101-0/+14
| | | | | | | | | | | | | | | | | | | | Disabling SSL verification is far from optimal, but depending on the circumstances may be the most practical way, so describe how to do that instead of leaving users confused. It's also not _that_ bad because git's hashing scheme should uncover most attempts to tamper with code, either when checking signed tags or when people push (and see lots of modified commits). State the command in a way that isn't conductive to careless copy & paste. Change-Id: Idbd52ba5d6e8b0f0e891fca16e4159ccef10771a Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37599 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
* Documentation: Move ACPI documentation in a subindexArthur Heymans2019-12-092-2/+12
| | | | | | | | Change-Id: I17c5263674b805a73d98aaa3e7090083905e37ef Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37242 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
* Documentation: Remove redundant 'documentation'Arthur Heymans2019-12-091-10/+10
| | | | | | | | | | | We are already in documentation so it should be obvious that other links point to other documentation. Change-Id: I7a021a09bdb88418ec85dbf433465f26445057d0 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37241 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
* mb/facebook/monolith: Add Facebook MonolithWim Vervoorn2019-12-062-0/+79
| | | | | | | | | | | | | | | The board is booting Linux and has been briefly tested. SeaBIOS, TianoCore payload and Linux as payload all seem to work fine. BUG=N/A TEST=tested on Facebook Monolith Change-Id: I65a2e03334af65cfb3f825d43fa0daa6e6c75913 Signed-off-by: Wim Vervoorn <wvervoorn@eltan.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37516 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
* Documentation/4.12-relnotes.md: Add SMMSTORE as production readyArthur Heymans2019-11-291-0/+4
| | | | | | | | | Change-Id: I9fa0473dd8ab9d0476400fc2f40c684db0188fc3 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37244 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* Documentation: Add SMMSTORE documentationArthur Heymans2019-11-292-0/+124
| | | | | | | | | | This documents the smmstore API. Change-Id: I992c04c0cf9b3f03755cf3fede2c82c6471a5ef4 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37243 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
* Documentation: Rework staging and commit informationDavid Hendricks2019-11-281-7/+4
| | | | | | | | | | | | | | This patch does two things: - The CLI and Git Cola sections contained some duplicated information about pushing patches, which is now factored out into its own section. - The draft workflow is now disabled, so that part has been reworded to describe how to submit a private patch. Signed-off-by: David Hendricks <david.hendricks@gmail.com> Change-Id: I562c101ab2ee78d901be7e99165daba7473dc3c1 Reviewed-on: https://review.coreboot.org/c/coreboot/+/37256 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
* Documentation/releases: Update checklistPatrick Georgi2019-11-221-2/+3
| | | | | | | | | | | | | | | | | | | | | Having the release notes mostly ready one week before the release allows for better review. Some statistics, the actual release date and commit ID can only be filled in on release day, but there's a tried & true technique for that: placeholders. It's also a nice touch to have the release notes of a release within its source tarballs, so push them right before creating the release (since changes in Documentation/releases won't break coreboot in any way). Change-Id: Iad7ba1ba4fc841bf437f2a997428b7f636e15422 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36957 Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* Documentation/releases: Drop reference to piratenpadPatrick Georgi2019-11-201-3/+1
| | | | | | | | | | Piratenpad is dead. Change-Id: Id9cfb68f6c6e05d1af2a526c817713a92220d370 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36958 Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* Documentation/releases: Releasing includes announcing on the listPatrick Georgi2019-11-201-0/+1
| | | | | | | | Change-Id: I063997d51a80b1b244a0cb35ae90446610ef2c21 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36975 Reviewed-by: Jacob Garber <jgarber1@ualberta.ca> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* Documentation/releases: 4.11 isn't "upcoming" anymore.Patrick Georgi2019-11-201-2/+2
| | | | | | | | Change-Id: I7102519b171c3e5269fefaa66d12d605f5d9ddb5 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36974 Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* Remove MIPS architectureJulius Werner2019-11-201-2/+2
| | | | | | | | | | | | | | | | | The MIPS architecture port has been added 5+ years ago in order to support a Chrome OS project that ended up going nowhere. No other board has used it since and nobody is still willing or has the expertise and hardware to maintain it. We have decided that it has become too much of a mainenance burden and the chance of anyone ever reviving it seems too slim at this point. This patch eliminates all MIPS code and MIPS-specific hacks. Change-Id: I5e49451cd055bbab0a15dcae5f53e0172e6e2ebe Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34919 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Hung-Te Lin <hungte@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* Remove imgtec/pistachio SoCJulius Werner2019-11-201-3/+0
| | | | | | | | | | | | After removing urara no board still uses this SoC, and there are no plans to add any in the future (I'm not sure if the chip really exists tbh...). Change-Id: Ic4628fdfacc9fb19b6210394d96431fdb5f8e8f1 Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36491 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* Documentation/releases: Finalize 4.11, start 4.124.11Patrick Georgi2019-11-193-9/+115
| | | | | | | | | | | | | | Fill in some stats using our repo analysis scripts in util/release/, thank the contributors, add some prose about notable achievements since 4.10. Also start a new doc for 4.12. Change-Id: I10a39081762d6e01f4040f717d36662975e4c8e9 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36948 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* Documentation: Remove duplicated entryPatrick Rudolph2019-11-191-4/+0
| | | | | | | | | | The mainboard was accidently added due to bad rebase. Change-Id: Ie7215e551651dbbc8d92316c48e455405923a30b Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36077 Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* Documentation: Reword Supermicro X10SLM+-F datasheet referencesPaul Menzel2019-11-191-3/+2
| | | | | | | | Change-Id: I24c4254ef65edcddadcf0386e0cbe996a5e99458 Signed-off-by: Paul Menzel <pmenzel@molgen.mpg.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35486 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
* docs: intel fsp: add memory retraining bug on SPS systemsMichael Niewöhner2019-11-192-1/+7
| | | | | | | | | | FSP2.0 forces MRC retraining on cold boot on Intel SPS systems. Change-Id: I3ce812309b46bdb580557916a775043fda63667f Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36935 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
* Documentation/releases: Add libgfxinit changes in 4.11Nico Huber2019-11-181-0/+13
| | | | | | | | Change-Id: Id7babdc9b1d908fa90ebac098a019615fa00b973 Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36920 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
* Documentation/releases: Add more c-env-bb platforms for 4.11Nico Huber2019-11-181-0/+2
| | | | | | | | Change-Id: Ie5c83befc8e595016c63729a19e7e71438c996b5 Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36919 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
* Documentation/mb/facebook/fbg1701.md: Update microcode blobFrans Hendriks2019-11-151-2/+1
| | | | | | | | | | | | | | The microcode is available in 3rdparty microcode now. This ucode can be used. BUG=N/A TEST=build Change-Id: I52a04c7dc97608f868ee0b415bbbb328937f18f7 Signed-off-by: Wim Vervoorn <wvervoorn@eltan.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36855 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
* Documentation/mb/portwell/pq7-m107.md: Update microcode blobWim Vervoorn2019-11-151-2/+1
| | | | | | | | | | | | | | | The microcode is available in 3rdparty microcode now. This ucode can be used. BUG=N/A TEST=build Change-Id: I1d83a58e9051fa9402666f05e4f2c43e76026dfb Signed-off-by: Wim Vervoorn <wvervoorn@eltan.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36854 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Frans Hendriks <fhendriks@eltan.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* Documentation: Add more entries to 4.11 release notesPatrick Georgi2019-11-121-3/+42
| | | | | | | | | Change-Id: I1b013c4d7012f1db9591bea98ec1fe7acbc85afe Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36751 Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* Documentation: Add some significant 4.11 release notesKyösti Mälkki2019-11-111-0/+9
| | | | | | | | Change-Id: I0f9a5afe85068e6ef2a0b0d088557b0dd1e5bd91 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36697 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
* Documentation: Add some significant 4.11 release notesPatrick Rudolph2019-11-111-0/+19
| | | | | | | | | Change-Id: Ia881cfa9382d0b2fa2652696b912030af942b68a Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36625 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
* arch/riscv: Pass cbmem_top to ramstage via calling argumentArthur Heymans2019-11-101-0/+3
| | | | | | | | | | Tested on the Qemu-Virt target both 32 and 64 bit. Change-Id: I5c74cd5d3ee292931c5bbd2e4075f88381429f72 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36558 Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* lib/cbfs: Add fallback to RO region to cbfs_boot_locateWim Vervoorn2019-11-071-0/+20
| | | | | | | | | | | | | | | | | | | | | | | With this change cbfs_boot_locate will check the RO (COREBOOT) region if a file can not be found in the active RW region. By doing so it is not required to duplicate static files that are not intended to be updated to the RW regions. The coreboot image can still be updated by adding the file to the RW region. This change is intended to support VBOOT on systems with a small flash device. BUG=N/A TEST=tested on facebook fbg1701 Change-Id: I81ceaf927280cef9a3f09621c796c451e9115211 Signed-off-by: Wim Vervoorn <wvervoorn@eltan.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36545 Reviewed-by: Frans Hendriks <fhendriks@eltan.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
generated by cgit v1.2.3 (git 2.25.1) at 2024-06-02 15:37:27 +0000