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* arch/power8: Rename to ppc64Jonathan Neuschäfer2018-11-301-2/+2
| | | | | | | | | | | | | | | POWER8 is a specific implementation of ppc64, which is by now outdated (POWER9 has been on the market for a while). Rename arch/power8/ to potentially cover a wider range of hardware. TEST=Toolchains built before/after this commit can build coreboot for emulation/qemu-power8 from before/after this commit. Change-Id: I2d6f08b12a9ffc8a652ddcd6f24ad85ecb33ca52 Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net> Reviewed-on: https://review.coreboot.org/c/29943 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Timothy Pearson <tpearson@raptorengineering.com>
* broadcom: Remove SoC and board supportPhilipp Deppenwiese2018-11-301-2/+0
| | | | | | | | | | | | | | | | | | The reason for this code cleanup is the legacy Google Purin board which isn't available anymore and AFAIK never made it into the stores. * Remove broadcom cygnus SoC support * Remove /util/broadcom tool * Remove Google Purin mainboard * Remove MAINTAINERS entries Change-Id: I148dd7eb0192d396cb69bc26c4062f88a764771a Signed-off-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com> Reviewed-on: https://review.coreboot.org/c/29905 Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* MAINTAINERS: Add myself as a maintainerMatt DeVillier2018-11-301-0/+25
| | | | | | | | | | | | | Add myself as a maintainer for legacy Intel-based ChromeOS devices for which I provide coreboot images as a comminuty member, and as a maintainer for Purism devices in a professional capacity. Change-Id: I70df3b9e4e36c2e5d73f8888fe0ec220aa8a91b7 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/29913 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
* MAINTAINERS: Update 9eSec maintainersPhilipp Deppenwiese2018-11-271-4/+28
| | | | | | | | | | Update 9elements Cyber Security maintainers. Change-Id: Ib683cb1b6a338667b065a71b05bdd3a4294e0296 Signed-off-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com> Reviewed-on: https://review.coreboot.org/c/29820 Reviewed-by: Patrick Rudolph <siro@das-labor.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* MAINTAINERS: Drop "the rest" componentPatrick Georgi2018-11-241-7/+0
| | | | | | | | | | | | | The semantics in util/scripts/maintainers.go have changed in that a file can be part of multiple components. This means that all files are part of "the rest" now, which doesn't make much sense. Change-Id: I220afe27e78aa5358fca61851242812f2d763992 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/c/29657 Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* MAINTAINERS: Add maintainer for all Siemens mc_xxxx mainboardsWerner Zeh2018-11-231-0/+7
| | | | | | | | | Change-Id: If8f662d088bf57fd27c5a01a47bc094dcb53a4de Signed-off-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-on: https://review.coreboot.org/c/29806 Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com> Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* MAINTAINERS: Add myself as maintainer for the getac/p470Patrick Georgi2018-11-231-0/+5
| | | | | | | | Change-Id: Iae87a2e6f223f1d6e39034be4c8b511187eca6f5 Signed-off-by: Patrick Georgi <patrick@georgi.software> Reviewed-on: https://review.coreboot.org/c/29782 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* northbridge/intel/fsp_*: Remove legacy SoCszaolin2018-11-191-12/+0
| | | | | | | | | | | | | | | * Remove FSP Sandy/Ivybrige which are unused. * Open Source implementation isn't final but good enough to replace FSP version. * For new ports use NORTHBRIDGE_INTEL_IVYBRIDGE and NORTHBRIDGE_INTEL_SANDYBRIDGE Change-Id: I7b6bc4bfdd0481c8fe5b2b3d8f8b2eb9aa3c3b9e Signed-off-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com> Reviewed-on: https://review.coreboot.org/29402 Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* MAINTAINERS: Clarify this is about active upstream developmentNico Huber2018-11-141-3/+17
| | | | | | | | | | | | | | | | | | | | | | <vendor> seems to be confused about the meaning of our maintainers list. I get the feeling some use it to organize corporate internal teams and branches, adding names to the list that don't show up in Gerrit and even if, often don't react to reviewing requests (within months). Maybe they even don't know that this is about coreboot.org? To clarify this: o Add an introductory paragraph mentioning development on coreboot.org. o Explicitly state that maintainers should be registered to Gerrit. o If a topic is tagged as `Supported` or `Maintained`, expect that somebody reacts to review requests. Change-Id: I9ee038dc5ee1f4993ba1d230ef6e737f20e2ff8a Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: https://review.coreboot.org/29471 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: David Guckian
* MAINTAINERS: Update RISC-V entry with SiFive and utilsJonathan Neuschäfer2018-10-041-0/+3
| | | | | | | | | | Change-Id: Idd9e51fe2cb7a8497381f5b7440666cd709166b8 Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net> Reviewed-on: https://review.coreboot.org/28757 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Philipp Hug <philipp@hug.cx> Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
* mb/lowrisc: Remove the Nexys4DDR portJonathan Neuschäfer2018-09-261-2/+0
| | | | | | | | | | | | | | | This board doesn't support the newest RISC-V Privileged Architecture spec (1.10), and it's based on an FPGA so it's a moving target. Now that there's actual RISC-V silicon out there (from SiFive), mb/lowrisc/nexys4ddr will only continue to bitrot. Change-Id: I4e3e715106a1a94381a563dc4a56781c35883c2d Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net> Reviewed-on: https://review.coreboot.org/28706 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Philipp Hug <philipp@hug.cx> Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
* util/ifdfake: Remove deprecated utilityAngel Pons2018-08-231-1/+0
| | | | | | | | | | | | | | Since ifdfake has been deprecated in favor of better alternatives, there is no need to support it any further. Remove it from "util/", as well as any leftover references in other files. Change-Id: I45fe3d9fd606a61d5c3b9d0e6489a1df6d6510f0 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/28234 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
* MAINTAINERS: change second PC Engines maintainerPiotr Król2018-03-211-1/+1
| | | | | | | | | Change-Id: I5eac0ae55e759ac9eb26783c11057db15fa62574 Signed-off-by: Piotr Król <piotr.krol@3mdeb.com> Reviewed-on: https://review.coreboot.org/25254 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Martin Roth <martinroth@google.com>
* MAINTAINERS: Update INTEL FSP DENVERTON-NS SOC & HARCUVAR CRB MaintainersVanessa Eusebio2018-02-261-1/+3
| | | | | | | | | | | | * Add David, Jeff, and Shine * Remove Fei Change-Id: I2803af80ac8c2b1d04ecd125c0cb123e736cdf7e Signed-off-by: Vanessa Eusebio <vanessa.f.eusebio@intel.com> Reviewed-on: https://review.coreboot.org/23847 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Mariusz Szafranski Reviewed-by: David Hendricks <david.hendricks@gmail.com>
* MAINTAINERS: add maintainers for all PC Engines mainboardsPiotr Król2017-10-311-0/+6
| | | | | | | | | | | Change-Id: Ic5855257900fe6e1e8dd3551f1427a4fe51924b1 Signed-off-by: Piotr Król <piotr.krol@3mdeb.com> Reviewed-on: https://review.coreboot.org/21732 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kamil Wcisło <kamil.wcislo@3mdeb.com> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com> Reviewed-by: Martin Roth <martinroth@google.com>
* MAINTAINERS: Remove extra unnecessary spaceSumeet Pawnikar2017-09-151-2/+2
| | | | | | | | | | | | Remove extra unnecessary space at end of line. Change-Id: I27688c3b8df71b875f1dc1020465d838756362be Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar@intel.com> Reviewed-on: https://review.coreboot.org/21521 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
* MAINTAINERS: Add Julius as LZ4 maintainerJulius Werner2017-09-151-0/+7
| | | | | | | | | | | | I imported the LZ4 compression code and want to keep an eye on it to ensure that our sources stay in sync with upstream. Change-Id: I249ce24f6630d66d451d993198cd267478e5743e Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/21488 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Martin Roth <martinroth@google.com>
* MAINTAINERS: Add INTEL FSP DENVERTON-NS SOC & HARCUVAR CRBMariusz Szafranski2017-09-151-0/+9
| | | | | | | | | | | | Add Intel FSP Atom C3000 SoC ("Denverton" and "Denverton-NS") and Harcuvar CRB to the list. Change-Id: I1c4bfd0900e8d425b95b5ef6c541b1e988846667 Signed-off-by: Mariusz Szafranski <mariuszx.szafranski@intel.com> Reviewed-on: https://review.coreboot.org/21515 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: FEI WANG <wangfei.jimei@gmail.com>
* MAINTAINERS: Update support listMartin Roth2017-07-151-18/+46
| | | | | | | | | | | | | | | | | | | | I sent out an email to all of the maintainers asking to verify their status. - The email I sent to Marcin Wojciechowski bounced, so I'm removing the Little Plains mainboard support. - I'm removing myself from areas that I'm not currently maintaining. - Due to Damien's schedule, he asked that the level for his pieces be changed from "Maintained" to "Odd Fixes". I've added a list of infrastructure owners and backup owners - This is strictly informational. Change-Id: I39715611e8025bb535cdf1012be2bf05bf91fdaa Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/20400 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Damien Zammit <damien@zamaudio.com> Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
* MAINTAINERS: Update maintainer address (APLK and FSP 2.0)Andrey Petrov2017-07-131-5/+4
| | | | | | | | | | | | | Update my email address for Apollolake and FSP 2.0 driver. Also downgrade support from "supported" to "maintained" as currently no other Intel persons are assigned for the role. Change-Id: I3033fc5ec8b0882ce79eeb15ee3eb13a228611a4 Signed-off-by: Andrey Petrov <andrey.petrov@intel.com> Reviewed-on: https://review.coreboot.org/20550 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
* MAINTAINERS: Add Julius as ARM architecture maintainerJulius Werner2017-06-121-8/+17
| | | | | | | | | | | | | | | | | I'm pretty much already doing this anyway, so I might as well document it. Separating out some older ARM SoCs that were added by other people and are pretty much orphaned now. I can also fill out the MISSING: MEMLAYOUT point (since I wrote that). Change-Id: I8b78d592a1ed68a42e5785ebdc13df2edf9007bf Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/20137 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Philippe Mathieu-Daudé <philippe.mathieu.daude@gmail.com>
* Use www.coreboot.org over coreboot.orgPaul Menzel2017-06-071-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | <https://coreboot.org> is redirected to <https://www.coreboot.org>. ``` $ curl -I https://coreboot.org HTTP/1.1 301 Moved Permanently Server: nginx/1.8.1 Date: Mon, 05 Jun 2017 10:41:33 GMT Content-Type: text/html Content-Length: 184 Connection: keep-alive Location: https://www.coreboot.org/ ``` So use the command below to use the final location to save a redirect. ``` $ git grep -l https://coreboot.org \ | xargs sed -i 's,https://coreboot.org,https://www.coreboot.org,g' ``` Change-Id: I4176c20ef31399f0063b41e3a0029cca0c1b0ff3 Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-on: https://review.coreboot.org/20035 Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
* Use more secure HTTPS URLs for coreboot sitesPaul Menzel2017-06-071-3/+3
| | | | | | | | | | | | | | | | | | | The coreboot sites support HTTPS, and requests over HTTP with SSL are also redirected. So use the more secure URLs, which also saves a request most of the times, as nothing needs to be redirected. Run the command below to replace all occurences. ``` $ git grep -l -E 'http://(www.|review.|)coreboot.org' | xargs sed -i 's,http://\(.*\)coreboot.org,https://\1coreboot.org,g' ``` Change-Id: If53f8b66f1ac72fb1a38fa392b26eade9963c369 Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-on: https://review.coreboot.org/20034 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
* MAINTAINERS: Add Felix as superio maintainerMartin Roth2017-05-301-2/+6
| | | | | | | | Change-Id: Ib53f591e5c8b03cd45b3fbd3db36ea2c28e4e060 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/19951 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
* MAINTAINERS: Update listMartin Roth2017-03-081-6/+22
| | | | | | | | | | | | | | | - Fix whitespace: Change some spaces to tabs - Add myself as an abuild maintainer - Add util/xcompile and util/genbuild_h to the BUILD SYSTEM section - Add new sections for utilities: docker, toolchain, and git - Remove GENERIC DRAM section - Remove the mailing list. We don't want it to be added as a reviewer. Change-Id: I78692fcac174d7b7c4d65911c85e4e2dacefcfc0 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/18578 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
* MAINTAINERS: Add myself as me_cleaner maintainerNicola Corna2017-03-021-0/+6
| | | | | | | | | Change-Id: Ia95f6beb1546efdb75a49bccfe293822f0785d7a Signed-off-by: Nicola Corna <nicola@corna.info> Reviewed-on: https://review.coreboot.org/18474 Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com> Tested-by: build bot (Jenkins)
* MAINTAINERS: Add lowrisc files to RISC-VJonathan Neuschäfer2016-11-121-0/+2
| | | | | | | | Change-Id: I8e9ff5821e15cd9a5966927a8cd8bd95f7021d58 Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net> Reviewed-on: https://review.coreboot.org/17402 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
* MAINTAINERS: Add Jonathan Neuschäfer as RISC-V co-maintainerJonathan Neuschäfer2016-10-151-0/+1
| | | | | | | | | | Change-Id: I53ba5ba790ae683082e712dc0b92f1ac5bf27ddb Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net> Reviewed-on: https://review.coreboot.org/16990 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Alexander Couzens <lynxis@fe80.eu>
* MAINTAINERS/RISCV: Cover mb/emulation/spike-riscvJonathan Neuschäfer2016-10-151-1/+1
| | | | | | | | | Change-Id: Id5f3f7f25041189d137ef4daa9f63a3b478763bc Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net> Reviewed-on: https://review.coreboot.org/16988 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
* intel/amenia: Remove Amenia mainboardAndrey Petrov2016-09-241-5/+0
| | | | | | | | | | | | | The mainboard is not being worked on anymore, not available outside of Intel and thus has litle practical use. Remove mainboard code completely. Change-Id: Ic2c7ea3810ee70afc01a42786f8ccba9313134e4 Signed-off-by: Andrey Petrov <andrey.petrov@intel.com> Reviewed-on: https://review.coreboot.org/16725 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Lijian Zhao <lijian.zhao@intel.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
* MAINTAINERS: Add myself as tpm support maintainer.Philipp Deppenwiese2016-07-071-0/+7
| | | | | | | | | | | | The tpm software stack, drivers and trustedboot needs to be maintained. Change-Id: I7b9ff9c4d7504c861de98ef3d8fcda53b20657c4 Signed-off-by: Philipp Deppenwiese <zaolin@das-labor.org> Reviewed-on: https://review.coreboot.org/15312 Reviewed-by: Vadim Bendebury <vbendeb@chromium.org> Reviewed-by: Alexander Couzens <lynxis@fe80.eu> Tested-by: build bot (Jenkins)
* MAINTAINERS: Add myself for Apollolake SoC, FSP2.0, and Amenia mbAndrey Petrov2016-05-261-0/+15
| | | | | | | | | Change-Id: I9931263f0f51d6c726bd7c72042fae1155affb6e Signed-off-by: Andrey Petrov <andrey.petrov@intel.com> Reviewed-on: https://review.coreboot.org/14963 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
* MAINTAINERS: Add maintainer for Pineview & x4x chipsets & boardsMartin Roth2016-04-191-0/+20
| | | | | | | | Change-Id: I3c34f6e69b3760a10e67bdc41c8ef0e629beb881 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/14129 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
* MAINTAINERS: Add Intel Broadwell-DE SOC and Camelback Mountain CRBYork Yang2016-04-171-12/+19
| | | | | | | | | | Add Intel Broadwell-DE SOC and Camelback Mountain CRB to the list Change-Id: I3f0c3ae8b38ecf3c3676fe497ade8b74ba94485d Signed-off-by: York Yang <york.yang@intel.com> Reviewed-on: https://review.coreboot.org/14382 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
* MAINTAINERS: add myselfPatrick Rudolph2016-04-131-0/+3
| | | | | | | | | | Add myself to MAINTAINERS file. Change-Id: I959ef193b69095b05ae9e42bd10d3b21001e0bc8 Signed-off-by: Patrick Rudolph <siro@das-labor.org> Reviewed-on: https://review.coreboot.org/14262 Tested-by: build bot (Jenkins) Reviewed-by: Alexander Couzens <lynxis@fe80.eu>
* MAINTAINERS: Add maintainer for the intelmetoolPhilipp Deppenwiese2016-03-261-0/+4
| | | | | | | | | If you want to be a maintainer Damien just add yourself to the list. Change-Id: I15c646fc23d0804a8172da66d9297ab7977e6e6a Reviewed-on: https://review.coreboot.org/14157 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
* MAINTAINERS: Add maintainer for Braswell SOC & Reference boardMartin Roth2016-03-221-0/+11
| | | | | | | | | Change-Id: If3b49c3056abe6e1c1a14578d6c62a866bc6834d Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/14127 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-by: Hannah Williams <hannah.williams@intel.com>
* MAINTAINERS: Add maintainers for power8 architectureMartin Roth2016-03-211-0/+8
| | | | | | | | Change-Id: I0eedda5f31c2809db7871b81ceb3045b782f9df1 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/14126 Tested-by: build bot (Jenkins) Reviewed-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
* MAINTAINERS: Add maintainer to lint scripts, board status & payloadsMartin Roth2016-03-211-0/+4
| | | | | | | | Change-Id: I3efd4116da1ffda2dbc768d1a447141d8ec76f81 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/14128 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
* MAINTAINERS: Add Timothy Pearson to the maintainers listMartin Roth2016-03-071-0/+40
| | | | | | | | Change-Id: Ic0ae87ca1fff6d912702190d3fe8ab21285c8630 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/13920 Tested-by: build bot (Jenkins) Reviewed-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
* MAINTAINERS: Designate Intel maintainers for FSP 1.0 BaytrailAlexandru Gagniuc2015-12-301-5/+13
| | | | | | | | | | | | | | | | | | | | | | | After several internal discussions, teams at Intel with stakes in coreboot have decided to each assign one or more maintainers. These maintainers can be expected to provide a point of contact for assistance with technical (code-related) issues, testing on real hardware, and making sure that their FSP-related areas continue to function with upstream coreboot. They understand that the inclusion of their information in the MAINTAINERS file does not give them any extra power over their areas. At the same time, nobody expects any community process to change. The one expectation is that reasonable efforts be made to contact these maintainers when making fundamental changes to their areas, or when discussing code removal. Change-Id: I62b2eaec8270ac1fce5bfbee3b3da68aba116b0f Signed-off-by: Alexandru Gagniuc <alexandrux.gagniuc@intel.com> Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/11894 Reviewed-by: York Yang <york.yang@intel.com> Tested-by: build bot (Jenkins)
* MAINTAINERS: Designate Intel maintainer for FSP 1.0 Ivy BridgeMartin Roth2015-12-291-0/+12
| | | | | | | | | | | | | | | | | | | | | | | | | After several internal discussions, teams at Intel with stakes in coreboot have decided to each assign one or more maintainers. These maintainers can be expected to provide a point of contact for assistance with technical (code-related) issues, testing on real hardware, and making sure that their FSP-related areas continue to function with upstream coreboot. They understand that the inclusion of their information in the MAINTAINERS file does not give them any extra power over their areas. At the same time, nobody expects any community process to change. The one expectation is that reasonable efforts be made to contact these maintainers when making fundamental changes to their areas, or when discussing code removal. Change-Id: I33d95db12d9e394360a207c8fbcfbc15723115c6 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/12642 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-by: York Yang <york.yang@intel.com>
* MAINTAINERS: Define all subsystems and their filesStefan Reinauer2015-12-091-1/+155
| | | | | | | | | | | | Initial list of subsystems and the files that belong to that subsystem, so we can define maintainers for them. Change-Id: Icde0f387b486bea1bb63f9bbdf6330fa0a3ebcfa Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/10530 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins)
* MAINTAINERS: Designate Intel maintainers for FSP 1.0 RangeleyMartin Roth2015-12-071-0/+15
| | | | | | | | | | | | | | | | | | | | | | After several internal discussions, teams at Intel with stakes in coreboot have decided to each assign one or more maintainers. These maintainers can be expected to provide a point of contact for assistance with technical (code-related) issues, testing on real hardware, and making sure that their FSP-related areas continue to function with upstream coreboot. They understand that the inclusion of their information in the MAINTAINERS file does not give them any extra power over their areas. At the same time, nobody expects any community process to change. The one expectation is that reasonable efforts be made to contact these maintainers when making fundamental changes to their areas, or when discussing code removal. Change-Id: I7af7b37a5e3a233cc29adb20dd5bb8fa07dbdd53 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/12643 Tested-by: build bot (Jenkins) Reviewed-by: David Guckian <david.guckian@intel.com>
* MAINTAINERS: Designate Intel maintainers for FSP 1.1Martin Roth2015-12-061-0/+8
| | | | | | | | | | | | | | | | | | | | | | After several internal discussions, teams at Intel with stakes in coreboot have decided to each assign one or more maintainers. These maintainers can be expected to provide a point of contact for assistance with technical (code-related) issues, testing on real hardware, and making sure that their FSP-related areas continue to function with upstream coreboot. They understand that the inclusion of their information in the MAINTAINERS file does not give them any extra power over their areas. At the same time, nobody expects any community process to change. The one expectation is that reasonable efforts be made to contact these maintainers when making fundamental changes to their areas, or when discussing code removal. Change-Id: I1aa135838984973f648dec5dbb35ff73992e9289 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/12644 Tested-by: build bot (Jenkins) Reviewed-by: Leroy P Leahy <leroy.p.leahy@intel.com>
* MAINTAINERS: add myself to lenovo boards + ecAlexander Couzens2015-12-061-0/+10
| | | | | | | | | Change-Id: I94835e85046b5d2b63b9b822c0dc670bf939e57e Signed-off-by: Alexander Couzens <lynxis@fe80.eu> Reviewed-on: https://review.coreboot.org/12650 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Martin Roth <martinroth@google.com>
* MAINTAINERS: Add myself to a few itemsMartin Roth2015-11-211-0/+17
| | | | | | | | Change-Id: I407cee76cf1eb695732ad54287831a151a8ae3f5 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: http://review.coreboot.org/12491 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
* MAINTAINERS: Fix format for file entries (F:)Stefan Reinauer2015-10-221-7/+7
| | | | | | | | | | | | | | | | According to the documentation further up in the file: F: drivers/net/ all files in and below drivers/net F: drivers/net/* all files in drivers/net, but not below F: */net/* all files in "any top level directory"/net Add trailing slashes to directory names. Change-Id: I7bfd2eb2528a75fb6af79a990acb89f5e4251383 Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-on: http://review.coreboot.org/12118 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
* MAINTAINERS: grab build system responsibilityPatrick Georgi2015-05-221-0/+8
| | | | | | | | | | | Since nobody else stepped up, I hereby claim responsibility for the build system. Change-Id: I580b906d15fc2f049f0072e7b4608b1f19db83ab Signed-off-by: Patrick Georgi <patrick@georgi-clan.de> Reviewed-on: http://review.coreboot.org/10277 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
* MAINTAINERS: Add lint scriptsStefan Reinauer2015-05-071-0/+5
| | | | | | | | Change-Id: I54fea74897010718cf495ffb51667c9cb15869b9 Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-on: http://review.coreboot.org/10124 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <edward.ocallaghan@koparo.com>
generated by cgit v1.2.3 (git 2.25.1) at 2024-06-10 15:56:29 +0000