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* Treewide: Add some gcc's warning optionsElyes HAOUAS2020-03-111-0/+1
| | | | | | | | Change-Id: I789c8906542c59477b0037d39e7aa4fb2dcf22c0 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39406 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
* treewide: Capitalize 'CMOS'Elyes HAOUAS2020-02-241-1/+1
| | | | | | | | | Change-Id: I1d36e554618498d70f33f6c425b0abc91d4fb952 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38928 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Peter Lemenkov <lemenkov@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* Makefile.inc: Adapt $(spc) definitionNico Huber2020-02-121-1/+1
| | | | | | | | | | | | | | | GNU Make 4.3 is more picky about the $(spc) definition. It seems, the variable ends up empty. The old definition worked for nearly 8 years, RIP. Tested with GNU Make 4.2.1 and 4.3. Change-Id: I7981e0066b550251ae4a98d7b50e83049fc5586a Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38790 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* Makefile.inc: Use `define` for cbfs-files-processor-defconfigNico Huber2020-02-121-2/+3
| | | | | | | | | | | | | | | The body contains a `#` and GNU make 4.3 disagrees with earlier versions if it should be treated as a comment. Turn it into a `define` which has clearer semantics regarding comments (interpretation is supposed to be deferred until the variable is expanded). Change-Id: I589542abbd14082c3ecc4a2456ebd809fb6911ea Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38793 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* Makefile.inc: Ignore _HID & _ADR conflicts in Broadwell & LynxpointMartin Roth2020-02-111-0/+9
| | | | | | | | | | | | | | We haven't been able to update IASL in 8 months because of this conflict. Ignoring it doesn't make things any worse than they are now. Signed-off-by: Martin Roth <martin@coreboot.org> Change-Id: Iced2e55e9f2aa7a262a5c1ffeff32af78acfa35e Reviewed-on: https://review.coreboot.org/c/coreboot/+/38810 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
* xcompile: Disable null pointer optimizationsJacob Garber2020-02-031-1/+0
| | | | | | | | | | | | | | | | | | | According to the C standard, accessing the NULL pointer (memory at address zero) is undefined behaviour, and so GCC is allowed to optimize it out. Of course, accessing this memory location is sometimes necessary, so this optimization can be disabled using -fno-delete-null-pointer-checks. This is already done in coreboot, but adding it to xcompile will also disable it for all the payloads. For example, coreinfo compiled with LTO libpayload crashes when this flag isn't set, presumably because the compiler is optimizing something out that it shouldn't. Change-Id: I4492277f02418ade3fe7a75304e8e0611f49ef36 Signed-off-by: Jacob Garber <jgarber1@ualberta.ca> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38289 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* commonlib: Add commonlib/bsdJulius Werner2020-01-281-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch creates a new commonlib/bsd subdirectory with a similar purpose to the existing commonlib, with the difference that all files under this subdirectory shall be licensed under the BSD-3-Clause license (or compatible permissive license). The goal is to allow more code to be shared with libpayload in the future. Initially, I'm going to move a few files there that have already been BSD-licensed in the existing commonlib. I am also exracting most contents of the often-needed <commonlib/helpers.h> as long as they have either been written by me (and are hereby relicensed) or have an existing equivalent in BSD-licensed libpayload code. I am also relicensing <commonlib/compression.h> (written by me) and <commonlib/compiler.h> (same stuff exists in libpayload). Finally, I am extracting the cb_err error code definitions from <types.h> into a new BSD-licensed header so that future commonlib/bsd code can build upon a common set of error values. I am making the assumption here that the enum constants and the half-sentence fragments of documentation next to them by themselves do not meet the threshold of copyrightability. Change-Id: I316cea70930f131e8e93d4218542ddb5ae4b63a2 Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38420 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
* Make: Add supermicro/smcbiosinfo to toolsPatrick Rudolph2020-01-081-1/+1
| | | | | | | | | | | | | | | Build the smcbiosinfo tool with other tools. Fixes possible race condition on jenkins. Change-Id: I38f7ee2fdef2818ad685b3de53ad74f7da50600f Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38270 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Christian Walter <christian.walter@9elements.com> Reviewed-by: ron minnich <rminnich@gmail.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
* util/supermicro: Add and use new tool smcbiosinfoPatrick Rudolph2020-01-061-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | The BMC and tools interacting with it depend on metadata placed inside the ROM in order the flash the BIOS. Add a new tool smcbiosinfo, integrate it into the build system, and generate a 128byte metadata file called smcbiosinfo.bin on build. You need to provide the BoardID for every SMC mainboard through a new Kconfig symbol: SUPERMICRO_BOARDID Some fields are unknown, but it's sufficient to flash it using SMC vendor tools. Tested on Supermicro X11SSH: * Flashing using the WebUI works * Flashing using SMCIPMITool works No further validation is done on the firmware. Change-Id: Id608c2ce78614b45a2fd0b26d97d666f02223998 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35484 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com> Reviewed-by: Nico Huber <nico.h@gmx.de>
* Makefile: Remove romccElyes HAOUAS2019-12-271-12/+2
| | | | | | | | | Change-Id: I2fe7fa8b23da3b909adc2b8bce59304acfb5b807 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37788 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jacob Garber <jgarber1@ualberta.ca>
* Makefiles: Remove -D__PRE_RAM__Kyösti Mälkki2019-11-221-3/+3
| | | | | | | | | | | | All cases of testing for __PRE_RAM__ have been converted to equivalent ENV_xxx definitions from <rules.h>. Change-Id: Ib6cd598f17109cc1072818cebe4791f7410c3428 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37075 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
* Remove imgtec/pistachio SoCJulius Werner2019-11-201-6/+1
| | | | | | | | | | | | After removing urara no board still uses this SoC, and there are no plans to add any in the future (I'm not sure if the chip really exists tbh...). Change-Id: Ic4628fdfacc9fb19b6210394d96431fdb5f8e8f1 Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36491 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* build system: Add various compiler flags that enable warnings on UBPatrick Georgi2019-11-181-0/+1
| | | | | | | | | | | | | | | | | Some types of Undefined Behavior can be determined statically at compile time and gcc now has a set of flags that make it emit warnings in that case instead of doing the __builtin_trap() / optimize / UD2-opcode dance that silently breaks the resulting binary. BUG=chromium:958270 BRANCH=none TEST=abuild passes (probably not) Change-Id: I3aa5ca00c9838cc7517160069310a1ef85372027 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32814 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
* src: Ignore Redundant offset remarks in ASL codeWim Vervoorn2019-11-181-1/+4
| | | | | | | | | | | | | | | | IASL reports unnecessary/redundant use of offset operator. These messages are only masking usefull messages. Add -vw 2158 so this message isn't reported. BUG=N/A TEST=build Change-Id: Ie8507d3b3cb6f2e75cb87cd3e4bcc4280df27f77 Signed-off-by: Wim Vervoorn <wvervoorn@eltan.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36857 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* lib/fmap: Add optional pre-RAM cacheJulius Werner2019-11-141-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch adds an optional pre-RAM cache for the FMAP which most platforms should be able to use, complementing the recently added post-RAM FMAP cache in CBMEM. vboot systems currently read the FMAP about half a dozen times from flash in verstage, which will all be coalesced into a single read with this patch. It will also help future vboot improvements since when FMAP reads become "free" vboot doesn't need to keep track of so much information separately. In order to make sure we have a single, well-defined point where the new cache is first initialized, eliminate the build-time hardcoding of the CBFS section offsets, so that all CBFS accesses explicitly read the FMAP. Add FMAP_CACHEs to all platforms that can afford it (other than the RISC-V things where I have no idea how they work), trying to take the space from things that look like they were oversized anyway (pre-RAM consoles and CBFS caches). Change-Id: I2820436776ef620bdc4481b5cd4b6957764248ea Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36657 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Joel Kitching <kitching@google.com>
* cpu/qemu-x86: Add x86_64 bootblock supportPatrick Rudolph2019-11-041-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | Add support for x86_64 bootblock on qemu. Introduce a new approach to long mode support. The previous patch set generated page tables at runtime and placed them in heap. The new approach places the page tables in memory mapped ROM. Introduce a new tool called pgtblgen that creates x86 long mode compatible page tables and writes those to a file. The file is included into the CBFS and placed at a predefined offset. Add assembly code to load the page tables, based on a Kconfig symbol and enter long in bootblock. The code can be easily ported to real hardware bootblock. Tested on qemu q35. Change-Id: Iec92c6cea464c97c18a0811e2e91bc22133ace42 Signed-off-by: Patrick Rudolph <siro@das-labor.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35680 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
* Makefile, Kconfig: Add AMD dependency for amd_blobs repoMarshall Dawson2019-10-311-0/+3
| | | | | | | | | | | | | | | | Add a Kconfig option for indicating agreement to use the contents of amd_blobs. Users should only download the repo after implicitely agreeing to AMD's License text. No formal documented agreement is required. Update Makfile.inc, similar to other submodules, to initialize and checkout the submodule once the Kconfig option is selected. Change-Id: I4ae807659db16756453dc3db2c51848291c681b8 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36416 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
* Makefile.inc: Consolidate submodule commentsMarshall Dawson2019-10-301-4/+2
| | | | | | | | | | | | | Reduce duplicated comments explaining that submodules' settings in .gitmodules are update=none, and that --checkout is required. This prepares for another submodule, and makes adding a third set of comments unnecessary. Change-Id: I7721333a61122284ed9975ecd2adc3271a879728 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36440 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
* Makefile.inc: Add a class 'all' to link files in all stage except SMMArthur Heymans2019-10-301-0/+4
| | | | | | | | Change-Id: I955dd2dc22cb3cfc4fdf1198cfd32f56475f97c9 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33198 Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* build: Mark bootblock files on x86 as IBBPatrick Rudolph2019-10-181-0/+16
| | | | | | | | | | | * Add cbfsoption --ibb to mark files as IBB * Will be used by "Legacy FIT TXT" boot Change-Id: I83313f035e7fb7e1eb484b323862522e28cb73d4 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/31497 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
* util/sconfig: Issue header for exposed PCI and PNP namesNico Huber2019-10-051-1/+2
| | | | | | | | | | | | | | | | | Let `sconfig` output a C header file with the symbol names that we generate since 5e2a2cd5e7 (util/sconfig: Expose usable PCI and PNP device names). We add another command line argument for the path to the header file. As the file is similar in nature to our `config.h` we simply put it in $(obj)/ too. Change-Id: I8f87288c82f2844b61eba6534797a42b978b47bb Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35488 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
* Makefile: Create the build directory before bootblock.binMartin Roth2019-09-241-2/+2
| | | | | | | | | | | This was causing a failure when building platforms with no bootblock when building with make -jXX Change-Id: Ic4cd4fe8ac82bd1e9ce114dbd53763538d125af3 Signed-off-by: Martin Roth <martinroth@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35531 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
* Makefile: Pass .xcompile into genbuild_hRaul E Rangel2019-08-281-1/+1
| | | | | | | | | | | | | | | | I'm moving the .xcompile file into the $(obj) directory so we can leave the source pristine. We need to pass the location of .xcompile into genbuild_h.sh. BUG=b:112267918 TEST=Ran genbuild_h with and without an .xcompile and verified it was passed. Change-Id: I8b3a75b478fad92a0b09246f0a00b0580f8c4aef Signed-off-by: Raul E Rangel <rrangel@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34240 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
* build system: add kconfig/toada to tools listPatrick Georgi2019-08-271-1/+1
| | | | | | | | | | | | Without this, we're lacking a serialization point in abuild when doing parallel builds. This manifests in parallel attempts to write the toada binary, which fails. Change-Id: Id6ebbb3750284225670608e4927d80c4eea96afb Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35107 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: David Hendricks <david.hendricks@gmail.com>
* Makefile.inc, payloads: Enable -WvlaJacob Garber2019-08-201-1/+1
| | | | | | | | | | | Variable length arrays are dangerous, so let's make sure they don't sneak back into coreboot or any of the payloads. Change-Id: Idf2488cf0efab51c9569a3789ae953368b61880c Signed-off-by: Jacob Garber <jgarber1@ualberta.ca> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33846 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* Makefile: Support HAVE_BOOTBLOCK=n caseKyösti Mälkki2019-08-071-0/+5
| | | | | | | | | | | | | | | | With HAVE_BOOTBLOCK=n build of bootblock-class is skipped. Inserts an empty 64-byte bootblock-region to coreboot.rom file, cbfstool will fill in the CBFS master header relative location at the end. Change-Id: Iaee9200f72f31175aca597865e3c74fc68bec8a6 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34477 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
* Makefile.inc: Enable -Wimplicit-fallthroughJacob Garber2019-07-191-1/+1
| | | | | | | | | Change-Id: Ic81ed9eb2ed5255a221082326b81c375456a6499 Signed-off-by: Jacob Garber <jgarber1@ualberta.ca> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34300 Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* util/cbfstool: Add AMD BIOS compression tool for PSPMarshall Dawson2019-07-031-1/+5
| | | | | | | | | | | | | | | | | | | | | | | | Add a utility to generate a compressed BIOS image for AMD Family 17h. If the input is an elf file, the utility extracts the program portion for compression. Otherwise the file is compressed as-is. In modern AMD systems, the PSP brings up DRAM then uncompresses the BIOS image into memory prior to x86 beginning execution. The PSP supports a zlib engine, and interprets the first 256 bytes as a header, where offset 0x14 containing the uncompressed size. For further details, see AMD Platform Security Processor BIOS Architecture Design Guide for AMD Family 17h Processors (NDA only, #55758). BUG=b:127766506 TEST=Use with WIP Picasso Change-Id: Id1c54e0a6dae9e4a0362c6635fe8b8aa48a369d8 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33401 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
* Makefile: Use ifittool to update FITPatrick Rudolph2019-06-241-11/+34
| | | | | | | | | | | | | | | | | | Depend on ifittool and use it to update FIT instead cbfstool FIT code. Move the TOPSWAP / microcode handling out of cbfstool and implement it in the Makefile. The new FIT looks like the old one and has been tested on Broadwell-DE. The TOPSWAP / microcode code path needs test on real hardware. Change-Id: I687469d62557f81e9d88398cfc93182164fdac95 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/31495 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com> Reviewed-by: Christian Walter <christian.walter@9elements.com>
* Move -Wlogical-op into xcompileNico Huber2019-06-211-1/+1
| | | | | | | | | | | | | Clang doesn't know `-Wlogical-op`, so let's move it into xcompile where we can easily distinguish between the two. However, this requires us to split out `GCC_ADAFLAGS*` from `GCC_CFLAGS*`. Change-Id: I6a50de0bc5372f61337f237383d32645ba86b0fd Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33579 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* Makefile.inc: Update 3rdparty/intel-microcode on USE_BLOBSArthur Heymans2019-06-181-1/+2
| | | | | | | | Change-Id: I0caeff3ff5613a594a79441e849440ebdc9a9b87 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33553 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
* Makefile.inc: Add -Wlogical-op warning optionElyes HAOUAS2019-06-151-1/+1
| | | | | | | | | | Change-Id: Ie0491817a3a69c9f8e6f0f0d3cb755c642819df9 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33385 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* Rampayload: Able to build coreboot without ramstageSubrata Banik2019-06-111-3/+10
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch removes all possible dependencies in order to build platform with CONFIG_RAMPAYLOAD enable(without ramstage). A. Create coreboot separate stage kconfigs This patch creates seperate stage configs as below 1. HAVE_BOOTBLOCK 2. HAVE_VERSTAGE 3. HAVE_ROMSTAGE 4. HAVE_POSTCAR 5. HAVE_RAMSTAGE B. Also ensures below kconfigs are aligned with correct stage configs 1. COMPRESS_RAMSTAGE and RELOCATABLE_RAMSTAGE are now enable if CONFIG_HAVE_RAMSTAGE is selected. 2. COMPRESS_BOOTBLOCK will enable if CONFIG_HAVE_BOOTBLOCK is set 3. COMPRESS_PRERAM_STAGES will enable if CONFIG_HAVE_VERSTAGE || CONFIG_HAVE_ROMSTAGE is selected. C. Also fix compilation issue with !CONFIG_HAVE_RAMSTAGE On x86 platform: Case 1: ramstage do exist: CONFIG_HAVE_RAMSTAGE=1 >> rmodules_$(ARCH-ramstage-y) will evaluate as rmodules_x86_32 Case 2: ramstage doesn't exist: CONFIG_HAVE_RAMSTAGE=0 >> rmodules_$(ARCH-ramstage-y) will evaluate as rmodules_ This patch fixes Case 2 usecase where platform doesn't select CONFIG_HAVE_RAMSTAGE. Also add option to create sipi_vector.manual based on $(TARGET_STAGE) variable. $(TARGET_STAGE)=ramstage if user selects CONFIG_HAVE_RAMSTAGE $(TARGET_STAGE)=postcar if user selects CONFIG_RAMPAYLOAD Change-Id: I0f7e4174619016c5a54c28bedd52699df417a5b7 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33142 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
* Makefile.inc: Extend version string for timeless buildsNico Huber2019-05-291-1/+1
| | | | | | | | | | | | | | | With the version string "TIMELESS", binaries are slightly smaller than for a regular build. This may lead to false positive build tests if the space is limited (e.g. bootblock). So let's make the string a little longer. Change-Id: I3bbf6f71d5bcd74728a3fe39734312690901d0ec Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32986 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* Reland "Makefile.inc: Enable -Wtype-limits""Julius Werner2019-05-131-1/+1
| | | | | | | | | | | | | | This reverts commit 99e836c843e6a8536348d5cc9581b5a17512a263. This relands commit c4ab50cdde4bfd01ec7509012b105c88bcf4c953. The issues with -Wtype-limits in the vboot submodule have been resolved now, so we can enable this flag again. Change-Id: I32e8cc88e69072e7ee66cf443b578a9a8ea0ebe2 Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32749 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Joel Kitching <kitching@google.com>
* Revert "Makefile.inc: Enable -Wtype-limits"Patrick Georgi2019-05-071-1/+1
| | | | | | | | | | | | | | | | This reverts commit c4ab50cdde4bfd01ec7509012b105c88bcf4c953. Reason for revert: vboot recently was changed so that -Wtype-limits fails, and that was just brought upstream. Since vboot internals are more likely to be used elsewhere while -Wtype-limits is less critical, revert this until vboot is resolved, then bring -Wtype-limits back again. Change-Id: I9cce10462b9e57189513fa49e11fd27ebe35ba51 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32670 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* Makefile.inc: Enable -Wtype-limitsJulius Werner2019-05-061-1/+1
| | | | | | | | | | | | | | | | | | | | This patch enables -Wtype-limits for the whole repository, which disallows checking for a condition that must be always true or always false based on type width (e.g. checking whether an unsigned variable is negative or whether a 32-bit integer is larger than 4G). This helps avoid easy to make and hard to find (because they often only affect error paths) mistakes like size_t size = fmap_read_area(...); if (size < 0) die("If only the compiler could've told me to use ssize_t instead"); Change-Id: I19edabfd092d09dad720e3fc47b44838163bfe25 Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32536 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* Makefile.inc: Update fsp submodule for all FSP platformsMatt DeVillier2019-05-031-6/+3
| | | | | | | | | | | | Rather than selectively update the fsp submodule based on FSP version or platform selection, update it when building for any FSP-enabled platform, so all have latest version available. Change-Id: If07d55828a1863623e04a4ecdd1514c3cb6d9c11 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32526 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
* Makefile: Check for errors in ACPI decompilation, tooNico Huber2019-04-291-1/+8
| | | | | | | | | | | | | | We only grep'ed for "ACPI Warning" resulting in an actual more severe "ACPI Error" being ignored. Change-Id: I9cec8a388f5558b1ffc383cc2fc69405252cbb37 Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32469 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Frans Hendriks <fhendriks@eltan.com> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
* Makefile: Reduce scope of oprom include pathsKyösti Mälkki2019-03-051-1/+4
| | | | | | | | | Change-Id: Ibaa5428df1832d3f18946d456fb0b6d2fff65c32 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/31694 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* Makefile.inc: Keep .asl intermediatesNico Huber2019-02-211-2/+2
| | | | | | | | | | | We used .aml as the file extension for preprocessed ASL code. That file gets overwritten with the compilation results, fix that. Change-Id: I11a03dfbcebb0fd762da7b27862a7bdb9a581b92 Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: https://review.coreboot.org/c/31523 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
* Makefile.inc: Create a default SMMSTORE regionArthur Heymans2019-02-061-1/+18
| | | | | | | | Change-Id: I7b7b75050e0139ea9a0a4f2ad3c0d69a482fb38b Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/30421 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
* Makefile.inc: Make sure the BIOS region is 64K alignedArthur Heymans2019-02-061-2/+3
| | | | | | | | | | | | | If a non aligned CONFIG_CBFS_SIZE is used the region RW_MRC_CACHE and CONSOLE could end up non aligned. Currently this is only possible if the user messes with CONFIG_CBFS_SIZE in menuconfig, but better be safe than sorry. Change-Id: Ieb7e3c7112bd4b3f9733c36af21b1d59b3836811 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/30420 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* Makefile.inc: Optimize generating the default x86 fmapArthur Heymans2019-02-061-15/+11
| | | | | | | | | | | | | Put the FMAP FMAP region right above the coreboot CBFS region. The other regions like RW_MRC_CACHE and CONSOLE often have alignment requirements so it makes sense to put those on top. This also simplifies the code the generate the default fmap a little. Change-Id: I24fa6c89ecf85fb9002c0357f14aa970ee51b1df Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/30419 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* Hook up Kconfig Ada spec fileNico Huber2019-02-061-1/+3
| | | | | | | | | | | | | We generate a $(obj)/cb-config.ads once and copy it per stage that uses it to $(obj)/<stage>/cb-config.ads (to simplify the gnat-bind step). The Ada package is called `CB.Config`. As there was no `CB` package yet, add that too. Change-Id: I963a6517ef4bcf84f2c8e9ae8d24a0d6b971d2b0 Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/c/30584 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
* buildsystem: Promote rules.h to default includeKyösti Mälkki2019-01-161-0/+1
| | | | | | | | | | Does not fix 3rdparty/, *.S or *.ld or yet. Change-Id: I66b48013dd89540b35ab219d2b64bc13f5f19cda Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/17656 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
* vendorcode/intel/fsp1_0/broadwell_de: Use FSP from 3rdparty/fspPatrick Rudolph2019-01-151-0/+5
| | | | | | | | | | | | | | | | | | | | Default to FSP binary and headers shiped in 3rdparty/fsp. * Drop headers and code from vendorcode/intel/fsp1_0/broadwell_de * Select HAVE_FSP_BIN to build test the platform * Fetch FSP repo as submodule * Make FSP_HEADER_PATH known from FSP2.0 useable on FSP1.0 * Introduce FSP_SRC_PATH for FSP source file * Add sane defaults for FSP_FILE Tested on wedge100s. Change-Id: I46f201218d19cf34c43a04f57458f474d8c3340d Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/30742 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Jay Talbott <JayTalbott@sysproconsulting.com>
* Untangle CBFS microcode updatesNico Huber2019-01-101-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | The option to specify a binary file name was added later for platforms that do not provide microcode updates in our blobs repository. Alas, it wasn't visible what platforms these are. And if you specified a file for a platform that already had one, they were all included together. Make it visible which platforms don't provide binaries with the new con- figs MICROCODE_BLOB_NOT_IN_BLOB_REPO, MICROCODE_BLOB_NOT_HOOKED_UP and MICROCODE_BLOB_UNDISCLOSED. Based on that we can decide if we want to include binaries by default or explicitly show that no files are inclu- ded (default to CPU_MICROCODE_CBFS_NONE). Also split CPU_MICROCODE_CBFS_GENERATE into the more explicit CPU_MICROCODE_CBFS_DEFAULT_BINS and CPU_MICROCODE_CBFS_EXTERNAL_BINS. And clean up the visibility of options: Don't show CBFS related options on platforms that don't support it and don't show external file options if the platform uses special rules for multiple files (CPU_MICROCODE_ MULTIPLE_FILES). Change-Id: Ib403402e240d3531640a62ce93b7a93b4ef6ca5e Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: https://review.coreboot.org/c/29934 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* util/gitconfig/pre-commit: Use clang-format to sanitise commitsEdward O'Callaghan2019-01-041-1/+7
| | | | | | | | | | | | | | | | | | | | | | Use the `git-format' tool to sanitise coreboot commits such that they conform to coreboot's coding style. This fancy piece of machinary allows one to have LibFormat from Clang to automatically check your commit conforms to coreboot's coding style, fix any issues automatically and provides you a diff you may review and apply at your convenience. N.B. When the `clang-format' binary is not found we issue a warning that the test was skipped and carry on as usual. Hence, this is strictly non-enforcing at this current time. You may use it at your leisure. Change-Id: If49017ea82f0707efd47cae5978a286a9af8f3b7 Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-on: https://review.coreboot.org/c/8037 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* Fix typos involving "the the"Jonathan Neuschäfer2018-12-181-1/+1
| | | | | | | | Change-Id: I179264ee6681a7ba4488b9f1c6bce1a19b4e1772 Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net> Reviewed-on: https://review.coreboot.org/c/30160 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
generated by cgit v1.2.3 (git 2.25.1) at 2024-06-06 01:54:04 +0000