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* src/mainboard/emulation/qemu-power9/*: add QEMU POWER9 mainboardYaroslav Kurlaev2022-02-111-0/+1
| | | | | | | | | | | Add initial implementation for booting on QEMU POWER9 emulation. Change-Id: I079c5b9ad564024dd13296ef75c263bdc40c9d39 Signed-off-by: Yaroslav Kurlaev <yaroslav.kurlaev@3mdeb.com> Signed-off-by: Sergii Dmytruk <sergii.dmytruk@3mdeb.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57079 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com>
* configs/i440fx: Build-test PARALLEL_MPArthur Heymans2022-02-071-0/+1
| | | | | | | | | Change-Id: If30d715c5a3b44be2832c96316003dc9d139b53f Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/59695 Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* configs: Add build test configs for CBFS verificationJulius Werner2022-01-082-0/+9
| | | | | | | | | | | | | Now that CBFS verification is available as an optional feature in menuconfig (CB:59982), we should add build test configs to ensure it doesn't break without notice. One Arm and one x86 board should be good enough for now. Signed-off-by: Julius Werner <jwerner@chromium.org> Change-Id: I530dfd37472e63b80a67badd22a13d54d2c4621b Reviewed-on: https://review.coreboot.org/c/coreboot/+/60467 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jakub Czapiga <jacz@semihalf.com>
* configs: Add config for Prodrive HermesAngel Pons2021-12-201-0/+13
| | | | | | | | | | | | Build-test the configuration Prodrive uses to build coreboot for their Hermes mainboard. Change-Id: I62e79d3143851bf14dfdbe70e60c60f13dd06c3f Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57168 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Justin van Son <justin.van.son@prodrive-technologies.com>
* configs/config.facebook_fbg1701: Remove CONFIG_ONBOARD_SAMSUNG_MEMFrans Hendriks2021-12-091-1/+0
| | | | | | | | | | | | | | | | CONFIG_ONBOARD_SAMSUMG_MEM was used to force Samsung memory. CPLD is used to determine the memory type leaving CONFIG_ONBOARD_SAMSUNG_MEM unused. Remove this config. BUG = N/A TEST = Boot Facebook FBG1701 Rev 1.0 - 1.4 Change-Id: I60626552f2e2338cf5cbaaf4dca1b1eb2756d8df Signed-off-by: Frans Hendriks <fhendriks@eltan.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/59755 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* configs/config.google_meep_cros: don't select ADD_FSP_BINARIESFelix Held2021-09-041-1/+0
| | | | | | | | | | | | | | This config selected ADD_FSP_BINARIES even though HAVE_INTEL_FSP_REPO is only defined for Apollolake and not Geminilake that resides in the same SoC directory and uses the same Kconfig file. This results in the paths to the FSP binaries not being defined, in which case the ADD_FSP_BINARIES option shouldn't be selected. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I95123c4930b44a3b76c87768e130eb7359bbf625 Reviewed-on: https://review.coreboot.org/c/coreboot/+/57351 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
* AGESA f15tn: Fix building IDS tracing supportAngel Pons2021-08-221-0/+7
| | | | | | | | | | Also add a config file to ensure the code gets build-tested. Change-Id: I530eccd2a194bc79de5ee354d98260d93423cd5b Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/53986 Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* configs: Explicitly specify vendor and mainboardAngel Pons2021-07-0713-0/+17
| | | | | | | | | | | | | | | Relying on the implicit defaults for these settings can cause issues in the future. For example, commit 8cc4c5a1e76c0c8aee3a14618c15d38e3bd2bd61 (config.dell_optiplex_9010_sff: Specify board model) was done to prevent a build failure when adding support for other Dell mainboards which make the default board change. Change-Id: Ie0da6254def8b38e9fb053fc7d530dfb46760861 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56079 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* configs/config.foxconn_g41m: Build test with X86_64Arthur Heymans2021-07-061-0/+3
| | | | | | | | | | Change-Id: I755f2037bc9368e610eb97a2633aa66da7f626b0 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56042 Reviewed-by: Patrick Rudolph <siro@das-labor.org> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* configs: Build test x86_64 on Sandy BridgePatrick Rudolph2021-07-051-0/+3
| | | | | | | | | | | Add defconfig to build test x86_64 code on Sandy Bridge. Change-Id: I2c18af8bfa87636c68741e4759059276c287d052 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55472 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrik Tesarik <depate@das-labor.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
* src: Consolidate x86_64 support KconfigAngel Pons2021-07-021-1/+1
| | | | | | | | | | | | | Introduce `USE_EXP_X86_64_SUPPORT` in `src/arch/x86/Kconfig` and guard it with `HAVE_EXP_X86_64_SUPPORT`. Replace the per-CPU implementations of the same functionality with the newly-added Kconfig options. Update documentation and the config file for QEMU accordingly. Change-Id: I550216fd2a8323342d6b605306b0b95ffd5dcd1c Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55760 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
* security/intel/cbnt: Build test CBnT provisioningArthur Heymans2021-06-281-0/+8
| | | | | | | | | | | This updates the intel-sec-tools submodule pointer to include a fake acm binary to be included for buildtesting. Change-Id: Id4a9e177f71306b8c5538a578da229a53d19487a Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55609 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
* soc/intel/broadwell: Re-do SerialIO UART console supportAngel Pons2021-06-141-0/+5
| | | | | | | | | | | | | Use the same code from Lynx Point on Broadwell, and adjust as needed. Also add a config file to ensure the code gets build-tested. Tested on out-of-tree Compal LA-A992P (Haswell ULT), UART 0 works. Change-Id: I527024098738700d5fbaf3e27cf4db331a0322bd Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37553 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
* sb/intel/lynxpoint: Add SerialIO UART console supportAngel Pons2021-06-091-0/+5
| | | | | | | | | | | | | | | | | | | | | | | Derived from Broadwell and adapted to follow what soc/intel does. Note that SERIALIO_UART_CONSOLE is meant to be selected from the mainboards which expose a SerialIO UART. UART_FOR_CONSOLE also needs to be set in mainboard Kconfig accordingly. It is possible that some of the UART configuration steps in bootblock are unnecessary. However, some of the steps turn off power management features and others are undocumented: omitting them could cause weird issues. Finally, add a config file to ensure the code gets build-tested. Tested on out-of-tree Compal LA-A992P, SerialIO UART 0 can be used to receive coreboot and SeaBIOS logs. Change-Id: Ifb3460dd50ed03421a38f03c80f91ae9fd604022 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/52489 Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* config.dell_optiplex_9010_sff: Specify board modelAngel Pons2021-06-091-0/+1
| | | | | | | | | | | | Add `CONFIG_BOARD_DELL_OPTIPLEX_9010=y` to avoid issues when other Dell mainboards get added. Change-Id: Ice2073a3073a345aeb9ead7398cb4129453dd5ba Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55274 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
* configs: Update configs for OCP Delta Lake LinuxBoot payloadJohnny Lin2021-06-011-1/+10
| | | | | | | | | | | | | | | | | | | OCP Delta Lake is developed and validated against LinuxBoot payload. Need to put the respective binary blobs in site-local/deltalake to build the final coreboot image. Add LINUX_COMMAND_LINE for LinuxBoot payload kernel cmdline, CPU_UCODE_BINARIES for CPU microcode binary, CONSOLE_SERIAL_57600 is the serial baud rate used by OCP Delta Lake, DEFAULT_CONSOLE_LOGLEVEL_4 is for a faster boot time. Tested=On OCP Delta Lake it can boot up target CentOS 8 GNU/Linux OS. Change-Id: Ib494e4170a7ebb445d9e11df83c370b40a9e5194 Signed-off-by: Johnny Lin <johnny_lin@wiwynn.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55058 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* tpm: Remove USER_TPMx options, make TPM1/TPM2 menuconfig visibleJulius Werner2021-05-272-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | We would like to have an easy way to completely disable TPM support on a board. For boards that don't pre-select a TPM protocol via the MAINBOARD_HAS_TPMx options, this is already possible with the USER_NO_TPM option. In order to make this available for all boards, this patch just removes the whole USER_TPMx option group and directly makes the TPM1 and TPM2 options visible to menuconfig. The MAINBOARD_HAS_TPMx options can still be used to select defaults and to prevent selection of a protocol that the TPM is known to not support, but the NO_TPM option always remains available. Also fix some mainboards that selected TPM2 directly, which they're not supposed to do (that's what MAINBOARD_HAS_TPM2 is for), and add a missing dependency to TPM_CR50 so it is set correctly for a NO_TPM scenario. Signed-off-by: Julius Werner <jwerner@chromium.org> Change-Id: Ib0a73da3c42fa4e8deffecb53f29ee38cbb51a93 Reviewed-on: https://review.coreboot.org/c/coreboot/+/54641 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Christian Walter <christian.walter@9elements.com>
* cpu/x86/smm: Drop the V1 smmloaderArthur Heymans2021-04-191-2/+0
| | | | | | | | Change-Id: I536a104428ae86e82977f2510b9e76715398b442 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51187 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
* mb/system76/gaze15: Add System76 Gazelle 15Tim Crawford2021-03-241-0/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Tested with TianoCore payload (UefiPayloadPkg). Working: - PS/2 keyboard, touchpad - Both DIMM slots - Both NVMe ports - SATA port - All USB ports - Webcam - Ethernet - Integrated graphics using Intel GOP driver - Internal microphone - Internal speakers - S3 suspend/resume - Flashing with flashrom - Booting to Ubuntu Linux 20.10 and Windows 10 Not working: - Discrete/Hybrid graphics This requires a new driver to work correctly, which will be added and enabled later. Change-Id: I10667fa26ac7c4b8eb67da11f3e963062bd0db47 Signed-off-by: Jeremy Soller <jeremy@system76.com> Signed-off-by: Tim Crawford <tcrawford@system76.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47822 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* configs: Build-test QEMU i440fx with AddressSanitizer (ASan)Paul Menzel2021-03-191-0/+1
| | | | | | | | | | | The artifacts can then be run on test system. Change-Id: I2300af7b9be5fbb42a874566971854b93292885e Signed-off-by: Paul Menzel <pmenzel@molgen.mpg.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51293 Reviewed-by: Harshit Sharma <harshitsharmajs@gmail.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* cpu/qemu-x86: Add an option to use the smmloader v2Arthur Heymans2021-03-181-0/+4
| | | | | | | | | | | The idea is to get rid of having 2 different smmloaders so add this option only to qemu/q35 to get it buildtested. Change-Id: Id4901784c4044e945b7f258b3acdc8d549665f3a Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51525 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* configs/config.google_volteer.build_test_purposes: Add fileAngel Pons2021-03-031-0/+32
| | | | | | | | | | | This is meant to build-test Crashlog and various debug options. Change-Id: Ie9bbfa538e38a4d835c1f8b0d45feb2f0fe803f8 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51155 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Francois Toguo Fotso <francois.toguo.fotso@intel.com>
* configs/config.asrock_b85m_pro4...: Build-test ASanAngel Pons2021-02-221-0/+2
| | | | | | | | | | | | | | | | This build-tests ASan support for both romstage and ramstage, because the Haswell northbridge selects the HAVE_ASAN_IN_ROMSTAGE option. x86 Kconfig selects the HAVE_ASAN_IN_RAMSTAGE option, and Haswell is x86. Change-Id: I892881d2315c09aa6d9d80903a8399d0f4d648e4 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50903 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Harshit Sharma <harshitsharmajs@gmail.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
* Document Gigabyte GA-G41M-ES2LAlexey Vazhnov2021-02-221-0/+13
| | | | | | | | | | | | | | | | | To replace wiki page https://www.coreboot.org/Board:gigabyte/ga-g41m-es2l + configs/config.gigabyte_ga-g41m-es2l + lshw output examples + memory modules compatibility Tested in Devuan 4 Chimaera. Tested from exact steps from this documentation. Change-Id: Ib45cfea15b43d7399e9d209f7ba7c6b24fe860dd Signed-off-by: Alexey Vazhnov <vazhnov@boot-keys.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50368 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Evgeny Zinoviev <me@ch1p.io>
* mb/system76/oryp5: Add System76 Oryx Pro 5Tim Crawford2021-01-281-0/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Tested with TianoCore payload (UefiPayloadPkg). Working: - PS/2 keyboard, touchpad - Both DIMM slots - Both NVMe ports - SATA port - All USB ports - Webcam - Ethernet - Integrated graphics - Internal microphone - S3 suspend/resume - Flashing with flashrom - Booting to Ubuntu Linux and Windows Not working: - Discrete/Hybrid graphics - Internal speakers These two require new drivers to work correctly, which will be added and enabled later. Change-Id: Iae6e530dcd52df3642cdfe74b65bfff5aa0dd402 Signed-off-by: Tim Crawford <tcrawford@system76.com> Signed-off-by: Jeremy Soller <jeremy@system76.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47892 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
* arch/x86: Remove most C_ENV_BOOTBLOCK_SIZE limitsKyösti Mälkki2021-01-281-1/+0
| | | | | | | | | | | | With top-aligned bootblock this is no longer globally needed. The default maximum is now a generous 256 KiB with couple platforms having lower limits of 32 KiB and 64 KiB. Change-Id: Ib1aee44908c0dcbc17978d3ee53bd05a6200410c Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47600 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
* configs: Add a weird config for Asus P8Z77-V LX2Angel Pons2020-12-141-0/+38
| | | | | | | | | | | | | | | | This is not meant for actual use, but to build-test several options. Please do not try to use it on real hardware. Or maybe do try. The purpose of this config is to build-test the individual options, not their combination. So, for instance, if it would be hard to keep options x, y and z build together in the future, this config shouldn't block a change but should instead be adapted, e.g. split into multiple chunks. Change-Id: I80e8fe3982025b61148e7c2b05dd0727d65ee2f4 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48546 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
* configs: Add a sample config for scaleway tagadaJulien Viard de Galbert2020-11-201-0/+15
| | | | | | | | Signed-off-by: Julien Viard de Galbert <julien@vdg.name> Change-Id: I39fd9aabe7285d39e1883622ee9d6a60c6651b6e Reviewed-on: https://review.coreboot.org/c/coreboot/+/47341 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
* configs: Add a weird config for Portwell M107Angel Pons2020-11-031-0/+41
| | | | | | | | | | | | | | | | This is not meant for actual use, but to build-test several options. Please do not try to use it on real hardware. Or maybe do try. The purpose of this config is to build-test the individual options, not their combination. So, for instance, if it would be hard to keep options x, y and z build together in the future, this config shouldn't block a change but should instead be adapted, e.g. split into multiple chunks. Change-Id: Ife40d055e4c9b295c54cfc6a27af06e9358f7761 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45974 Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* configs/config.asrock_b85m_pro4...: Select X86_SMM_LOADER_VERSION2Angel Pons2020-11-031-0/+2
| | | | | | | | | | | This allows build-testing the code while it isn't used anywhere. Change-Id: I754c661fbad0bc5fbddfab9747607e664ad1e2b6 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44174 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* configs/config.asrock_b85m_pro4...: Clarify its purposeAngel Pons2020-11-031-1/+4
| | | | | | | | | | | | | | The purpose of this config is to build-test the individual options, not their combination. So, for instance, if it would be hard to keep options x, y and z build together in the future, this config shouldn't block a change but should instead be adapted, e.g. split into multiple chunks. Change-Id: Ibd8f6513fae6cd02fcf889d2510dc7e0a97ce40c Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47068 Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* configs: Add TXT-enabled config for Asrock B85M Pro4Angel Pons2020-10-221-0/+10
| | | | | | | | | | | | | | | | | | This config selects the necessary options to enable Intel TXT on the Asrock B85M Pro4, and allows the code to be build-tested. Note that the current TXT code will not work, as it was written for Broadwell-DE. Subsequent commits will adapt the code as necessary to work on Haswell. Compatible BIOS and SINIT ACMs can be retrieved from a firmware update for the Supermicro X10SLH. As they are not in the blobs repository, use the STM binary as a placeholder so as to allow build-testing the code. Change-Id: Ibf8db5fdfac5b527520023277c6370f6efa71717 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46489 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* mb/emulation/qemu-i440fx: Remove TRACE=y from test buildKyösti Mälkki2020-09-261-1/+0
| | | | | | | | | | | | | | | Looks like the option is generally not compatible with garbage collections. Nothing is inlined, is_smp_boot() no longer evaluates to constant false and thus the symbols from secondary.S would need to be present for the build to pass after we set SMP=n. Change-Id: I1b76dc34b5f39d8988368f71a0a2f43d1bc4177e Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43817 Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* configs: Build test experimental x86_64 codePatrick Rudolph2020-08-191-0/+1
| | | | | | | | | | Add additional build config to test qemu-i440fx x86_64 code. Change-Id: I63f7a6e1602728e4d5ff67f9bd702efebe315c16 Signed-off-by: Patrick Rudolph <siro@das-labor.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/31472 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
* configs/config.asrock_b85m_pro4...: Select GL9763E driverAngel Pons2020-08-071-0/+2
| | | | | | | | | | | This allows build-testing the code while it isn't used anywhere. Change-Id: Ib0b78cf874ab28d2b6ed687c1a63bcca3d788d2c Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44161 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
* configs: Add a weird config for Asrock B85M Pro4Angel Pons2020-08-021-0/+42
| | | | | | | | | | | | | This config is meant to build-test several options, such as SMMSTORE, UBSAN, SIL3114 driver, EM100 support, code coverage and debug options. Please do not try to use it on real hardware. Or maybe do try. Change-Id: I8bc19a1987b405d5a654276050b00b956acbdf36 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43977 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* security/intel/txt: Add Intel TXT supportPhilipp Deppenwiese2020-07-311-0/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add TXT ramstage driver: * Show startup errors * Check for TXT reset * Check for Secrets-in-memory * Add assembly for GETSEC instruction * Check platform state if GETSEC instruction is supported * Configure TXT memory regions * Lock TXT * Protect TSEG using DMA protected regions * Place SINIT ACM * Print information about ACMs Extend the `security_clear_dram_request()` function: * Clear all DRAM if secrets are in memory Add a config so that the code gets build-tested. Since BIOS and SINIT ACM binaries are not available, use the STM binary as a placeholder. Tested on OCP Wedge100s and Facebook Watson * Able to enter a Measured Launch Environment using SINIT ACM and TBOOT * Secrets in Memory bit is set on ungraceful shutdown * Memory is cleared after ungraceful shutdown Change-Id: Iaf4be7f016cc12d3971e1e1fe171e6665e44c284 Signed-off-by: Philipp Deppenwiese <zaolin@das-labor.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37016 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Christian Walter <christian.walter@9elements.com>
* configs/config.stm: Correct config file nameAngel Pons2020-07-211-0/+0
| | | | | | | | | | | | Otherwise, Jenkins doesn't pick up the file, and STM doesn't get build-tested. Change-Id: I7cf23c8352f82b2672c7ff25efba0057b8e059cd Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43611 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eugene Myers <cedarhouse1@comcast.net> Reviewed-by: David Hendricks <david.hendricks@gmail.com>
* drivers/pc80/tpm: Remove LPC_TPMKyösti Mälkki2020-07-048-8/+0
| | | | | | | | | | | | | | Replace uses with MAINBOARD_HAS_LPC_TPM, if drivers/pc80/tpm is present in devicetree.cb it is necessary to always include the driver in the build. Change-Id: I9ab921ab70f7b527a52fbf5f775aa063d9a706ce Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41872 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Michael Niewöhner
* mb/ocp/deltalake: Add OCP Delta Lake mainboardJonathan Zhang2020-06-221-0/+17
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | OCP Delta Lake server is a one socket server platform powered by Intel Cooper Lake Scalable Processor. The Delta Lake server is a blade of OCP Yosemite V3 multi-host sled. TESTED=Successfully booted on both YV3 config A Delta Lake server and config C Delta Lake server. The coreboot payload is Linux kernel plus u-root as initramfs. Below are the logs of ssh'ing into a config C deltalake server: jonzhang@devvm2573:~$ ssh yv3-cth root@ip's password: Last login: Mon Apr 20 21:56:51 2020 from [root@dhcp-100-96-192-156 ~]# lscpu Architecture: x86_64 CPU op-mode(s): 32-bit, 64-bit Byte Order: Little Endian CPU(s): 52 On-line CPU(s) list: 0-51 ... [root@dhcp-100-96-192-156 ~]# cbmem 34 entries total: 0:1st timestamp 28,621,996 40:device configuration 178,835,602 (150,213,605) ... Total Time: 135,276,123,874,479,544 [root@dhcp-100-96-192-156 ~]# cat /proc/cmdline root=UUID=f0fc52f2-e8b8-40f8-ac42-84c9f838394c ro crashkernel=auto selinux=0 console=ttyS1,57600n1 LANG=en_US.UTF-8 earlyprintk=serial,ttyS0,57600 earlyprintk=uart8250,io,0x2f8,57600n1 console=ttyS0,57600n1 loglevel=7 systemd.log_level=debug Signed-off-by: Jonathan Zhang <jonzhang@fb.com> Signed-off-by: Reddy Chagam <anjaneya.chagam@intel.com> Change-Id: I0a5234d483e4ddea1cd37643b41f6aba65729c8e Reviewed-on: https://review.coreboot.org/c/coreboot/+/40387 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
* mb/dell/optiplex_9010: Add Dell OptiPlex 9010 SFF supportMichał Żygowski2020-05-161-0/+9
| | | | | | | | | | | | | | Based on the autoport. The OptiPlex 9010 comes in four different sizes: MT, DT, SFF and USFF. Tested on SFF only. The other PCBs are slightly different, but they are designed with intercompatibility in mind. With small devicetree overrides it should work on OptiPlex 7010 and other OptiPlex 9010 variants as well. Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com> Change-Id: I88d65cae30d08ca727d86d930707c2be25a527cf Reviewed-on: https://review.coreboot.org/c/coreboot/+/40351 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* configs/config.facebook_fbg1701: Rename fileFrans Hendriks2020-04-221-0/+0
| | | | | | | | | | | | | | | | Jenkins does not build using .config.facebook_fbg1701 on new patches. Rename the config file adding '.mboot_vboot'. Now FACEBOOK_FBG1701 and FACEBOOK_FBG1701_MBOOT_VBOOT are included in Jenkins test result. BUG=N/A TEST=Build and boot Facebook fbg1701 Change-Id: Ib54cc29e7ff34553c19fa3502872d6e7aee5fbe8 Signed-off-by: Frans Hendriks <fhendriks@eltan.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40557 Reviewed-by: Wim Vervoorn <wvervoorn@eltan.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* drivers/pc80/rtc: Drop CMOS_POST_EXTRA optionKyösti Mälkki2020-04-202-2/+0
| | | | | | | | Change-Id: I379a5664776624600ff1c2919bffa77c877d87ab Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38191 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
* configs: Add qemu aarch64 target with FIT supportPatrick Rudolph2020-04-171-0/+7
| | | | | | | | | | | | | | Add a defconfig which allows to place a large uImage/FIT payload in it to boot test the binary on qemu-system-aarch64 using u-root and kexec-tools. Change-Id: I95ca187b68ff883152421bd7612b494cd63e8d02 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40413 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
* fsp2_0: Clean up around `config FSP_USE_REPO`Nico Huber2020-04-051-2/+0
| | | | | | | | | | | | | | | | | | We can make our lifes much easier by removing its dependency on `ADD_FSP_BINARIES`. Instead, we imply the latter if the repository is to be used. We can also hide a lot of unnecessary prompts in this case. Also, remove default overrides and selects for the two that are now unnecessary. Change-Id: I8538f2e966adc9da0fbea2250c954d86e42dfeb3 Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39882 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Felix Singer <felixsinger@posteo.net> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* configs: Add builder config to create a working Cedar Island CRBAndrey Petrov2020-03-261-0/+17
| | | | | | | | | Change-Id: I2a2de7ccb96996211c45da3f9ec9bf6f71cc0c89 Signed-off-by: Andrey Petrov <anpetrov@fb.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39783 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Maxim Polyakov <max.senia.poliak@gmail.com> Reviewed-by: David Hendricks <david.hendricks@gmail.com>
* configs: Add builder Tioga Pass configAndrey Petrov2020-03-261-0/+17
| | | | | | | | | | | Add config file that can be used to build a fully working Tioga Pass image. Signed-off-by: Andrey Petrov <anpetrov@fb.com> Change-Id: Ifff3591ef9fff40117c60e85900bde9c3729bd94 Reviewed-on: https://review.coreboot.org/c/coreboot/+/39715 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: David Hendricks <david.hendricks@gmail.com>
* configs: Fix Intel RVP11 defconfigPatrick Rudolph2020-03-221-0/+0
| | | | | | | | | | It wasn't picked up by the builder due to wrong file name. Change-Id: Ia31b5d304a0cabd0d578c5ac6181cb1c8ee1c246 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39666 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
* mb/libretrend/lt1000: Add Libretrend LT1000 mainboardMichał Żygowski2020-03-101-0/+5
| | | | | | | | | Change-Id: I32fc8a7d3177ba379d04ad8b87adefcfca2b0fab Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/30360 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
* mainboard/ocp: Add support for OCP platform TiogaPassJonathan Zhang2020-03-061-0/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | OCP platform Tiogapass is a 2-socket server platform, which is based on a chipset including Intel Skylake-SP processors and a Lewisburg PCH. Skylake-SP is a processor in Intel Xeon Scalable Processor family. Following ACPI tables are added: DSDT/SSDT, MADT, FACP, FACS, HPET, MCFG, SLIT, SRAT, DMAR This patchset is tested on a Tiogapass board. It booted with Linux kernel 4.16.0; lscpu command shows all 72 cpus (2 sockets, 18 cores, 2 thread per core); ssh command shows networking is up from Mellanox ConnectX-4 PCIe NIC card. Towards successful gerrit buildbot build, note that: * microcode is in coreboot intel-microcode submodule repo. * IFD binary is included in this patch. * Dummy ME binary is used, as it may take long time for Intel ME binary to be available in public domain. * Fake FSP binary is used, as at this moment the SKX-SP FSP binary is not going to be available in public domain. Known issues (Not intend to address in this initial support for Xeon-SP processors): * c6 state is not supported. * dsdt table is not fully populated, such as processor/socket devices, some PCIe devices. * SMM handlers are not added. Following are some command execution with CentOS booted from local SATA disk: [root@localhost ~]# lscpu Architecture: x86_64 CPU op-mode(s): 32-bit, 64-bit Byte Order: Little Endian CPU(s): 72 On-line CPU(s) list: 0-71 Thread(s) per core: 2 Core(s) per socket: 18 Socket(s): 2 NUMA node(s): 2 Vendor ID: GenuineIntel CPU family: 6 Model: 85 Model name: Intel(R) Xeon(R) Gold 6139 CPU @ 2.30GHz Stepping: 4 CPU MHz: 140.415 BogoMIPS: 4626.46 Virtualization: VT-x L1d cache: 32K L1i cache: 32K L2 cache: 1024K L3 cache: 25344K NUMA node0 CPU(s): 0-17,36-53 NUMA node1 CPU(s): 18-35,54-71 [root@localhost ~]# ifconfig eth0: flags=4163<UP,BROADCAST,RUNNING,MULTICAST> mtu 1500 inet 172.23.68.190 netmask 255.255.0.0 broadcast 172.23.255.255 inet6 2620:10d:c082:9063:268a:7ff:fe57:5af0 prefixlen 64 //cut inet6 fe80::268a:7ff:fe57:5af0 prefixlen 64 scopeid 0x20<link> inet6 2620:10d:c082:9063::5d2 prefixlen 128 scopeid 0x0<global> ether 24:8a:07:57:5a:f0 txqueuelen 1000 (Ethernet) RX packets 84249 bytes 6371591 (6.0 MiB) RX errors 0 dropped 0 overruns 0 frame 0 TX packets 8418 bytes 748781 (731.2 KiB) TX errors 0 dropped 0 overruns 0 carrier 0 collisions 0 lo: flags=73<UP,LOOPBACK,RUNNING> mtu 65536 inet 127.0.0.1 netmask 255.0.0.0 inet6 ::1 prefixlen 128 scopeid 0x10<host> loop txqueuelen 1000 (Local Loopback) RX packets 613 bytes 63906 (62.4 KiB) RX errors 0 dropped 0 overruns 0 frame 0 TX packets 613 bytes 63906 (62.4 KiB) TX errors 0 dropped 0 overruns 0 carrier 0 collisions 0 [root@localhost ~]# cbmem 36 entries total: // Lines were cut to avoid checkpatch.pl warnings Total Time: 96,243,882,140,175,829 Signed-off-by: Jonathan Zhang <jonzhang@fb.com> Signed-off-by: Reddy Chagam <anjaneya.chagam@intel.com> Tested-by: johnny_lin@wiwynn.com Change-Id: I29868f03037d1887b90dfb19d15aee83c456edce Reviewed-on: https://review.coreboot.org/c/coreboot/+/38549 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: David Hendricks <david.hendricks@gmail.com>
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