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* libpayload/x86: Fix boot_device_read() and hook it upNico Huber2022-02-232-1/+3
| | | | | | | | | | Casts from integer to pointer are usually a case for phys_to_virt(). Change-Id: I861d435ff2361cdc26a2abd46d43b9346fa67ccc Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/62246 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
* libpayload: Add -Wno-address-of-packed-member for ARCH_MOCKJakub Czapiga2021-12-201-0/+2
| | | | | | | | | | | | | When compiling libpayload using x86_64 toolchain for ARCH_MOCK compiler reports an error about gerring address of packed member. Until now it had to be disabled by passing -Wno-address-of-packed-member to EXTRA_CFLAGS. This patch disables this warning. Change-Id: I9a948fabe66f7297632ecaca8ec1bfa5c842b750 Signed-off-by: Jakub Czapiga <jacz@semihalf.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60169 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
* libpayload: Add boot_device_read() functionJakub Czapiga2021-12-101-0/+17
| | | | | | | | | | | | | | | | This patch adds a new way of implementing flash access for libpayload. Until now all reads had to be performed using cbfs_media, which is obsolete. From now on all reads should be performed using boot_device_read(). This patch also provides a default implementation of boot_device_read() for x86 architecture. Change-Id: I1babd2a8414ed9de3ca49903fcb4f036997b5ff3 Signed-off-by: Jakub Czapiga <jacz@semihalf.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/59492 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
* libpayload: Add CBMEM_IMD_ENTRY support to coreboot tables parserJakub Czapiga2021-12-031-8/+0
| | | | | | | | | | | | | | | | | | coreboot stores much information in the CBMEM IMD. Until now it was ignored. This patch makes use of these coreboot tables entries. It also removes get_cbmem_addr() function as it is no longer needed. Moreover, the coreboot tables entry CB_TAG_MRC_CACHE does not exist anymore, as it is not created by the code. It was replaced by CBMEM_ID_MRCDATA entry, so MRCDATA should now be accessible through sysinfo structure field. Change-Id: I5bd02a98ba2631f34014bc0f8e7ebd5a5ddd2321 Signed-off-by: Jakub Czapiga <jacz@semihalf.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/59491 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
* libpayload: Add mock architectureJakub Czapiga2021-10-116-0/+49
| | | | | | | | | | | | | | | | | | | | Mock architecture can be used to build libpayload using host compiler. It can be enabled by setting ARCH_MOCK=y in the dotconfig. It sets LITTLE_ENDIAN=y, as most machines these days use little-endian CPUs. Libpayload will use HOSTCC as CC, HOSTLD as LD, etc. instead of tools provided by xcompile. Mock architecture configuration can be used by payloads for testing purposes. Thanks to it, tests can be architecture-independent, and can be executed without requiring compatible Kconfig options, e.g. ARCH_ARM64=y for ARM64 machine. However, one has to provide implementation for most architecture-specific functions present in arch/* directories. Signed-off-by: Jakub Czapiga <jacz@semihalf.com> Change-Id: Ie3a6e6f6cad2f8a2e48a8e546d3b79c577653080 Reviewed-on: https://review.coreboot.org/c/coreboot/+/57708 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
* payloads/libpayload/arch/arm64/mmu.c: Fix typo in commentElyes HAOUAS2021-02-051-1/+1
| | | | | | | | Change-Id: Ieb10a881ef1d983f11318f0f6934491fd19fd0bf Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50268 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
* treewide [Kconfig]: Remove useless commentElyes HAOUAS2021-02-023-3/+3
| | | | | | | | Change-Id: I3dafffa61f4fe6089fd11ef6579626aff8088df5 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50185 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
* libpayload: Provide API to expose MMU memery ranges for ARM64Meng-Huan Yu2020-12-051-0/+5
| | | | | | | | | | | | | | | | | | Provide get_mmu_ranges() for ARM64 to let payloads could get MMU ranges for all used memory regions. BUG=b:171858277 TEST=Build in x86, arm, arm64. emerge-zork libpayload depthcharge emerge-nyan libpayload depthcharge emerge-asurada libpayload depthcharge Signed-off-by: Meng-Huan Yu <menghuan@google.com> Change-Id: I39b24aefc9dbe530169b272e839d0e1e7c697742 Reviewed-on: https://review.coreboot.org/c/coreboot/+/48113 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
* libpayload/x86: Try to discover invariant TSC rateNico Huber2020-11-021-3/+116
| | | | | | | | | | | | | | | | We can skip the PIT-based TSC calibration if we can derive the invariant TSC rate from CPUID/MSR data. This is necessary if the PIT is disabled, which is the default, for instance, on Coffee Lake CPUs. This implementation should cover all Intel Core i processors at least. For older processors, we fall back to the PIT calibration. Change-Id: Ic6607ee2a8b41c2be9dc1bb4f1e23e652bb33889 Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34170 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
* libpayload/arch/x86: Introduce pacc pointer in sysinfo_t structFelix Singer2020-10-201-0/+5
| | | | | | | | | | | | | Currently, the PCI bus gets scanned multiple times for various reasons (e.g. to read the device class). Therefore, and in preparation to CB:46416, introduce the pacc pointer in the sysinfo_t struct and scan the PCI bus while gathering system information. Change-Id: I496c5a3d78c7fb5d7c9f119a0c9a0314d54e729f Signed-off-by: Felix Singer <felix.singer@secunet.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46348 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
* treewide/Kconfig: Drop unneeded empty linesElyes HAOUAS2020-09-211-1/+0
| | | | | | | | Change-Id: If8aa28a22625b7b2cf9b58958de87ee752f637f6 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45247 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
* payloads: Drop unneeded empty linesElyes HAOUAS2020-09-214-4/+0
| | | | | | | | Change-Id: I6faeb7c783052edc4217d2d301dbb905e1fc6a19 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44605 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
* libpayload: Cache physical location of CBMEM entriesNico Huber2020-08-241-1/+1
| | | | | | | | | | | | In the presence of self-relocating payloads, it's safer to keep physical addresses in `libsysinfo`. This updates all the references to CBMEM entries that are not consumed inside libpayload code. Change-Id: I3be64c8be8b46d00b457eafd7f80a8ed8e604030 Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43580 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
* libpayload: Cache copy of `cb_framebuffer` structNico Huber2020-08-241-15/+2
| | | | | | | | | | | | | | | | | | | | | | Our AArch64 code supports dynamic framebuffer allocation which makes it necessary to change the framebuffer information during runtime. Having a pointer inside `libsysinfo` made a mess of it as the pointer would either refer to the original struct inside the coreboot table or to a new struct inside payload space. The latter would be unaffected by a relocation of the payload. Instead of the pointer, we'll always keep a copy of the whole struct, which can be altered on demand without affecting the coreboot table. To align the `video/graphics` driver with the console driver, we also replace `fbaddr` with a macro `FB` that calls phys_to_virt(). Change-Id: I3edc09cdb502a71516c1ee71457c1f8dcd01c119 Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43578 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Julius Werner <jwerner@chromium.org>
* payloads/libpayload/arch/arm/cpu.S: Remove whitespaces before tabElyes HAOUAS2020-07-251-1/+1
| | | | | | | | Change-Id: I2960f95937db23aa3a38ca64085728e6d10968f8 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43714 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
* libpayload: allow nonblocking delay and more than one delayRonald G Minnich2020-07-161-3/+31
| | | | | | | | | | | | | | | | | Extend the local APIC timer delay so that it can be started, and waited for, independently. Add an EOI so that more than one APIC timer interrupt is possible. Previous to this, because there was no EOI, the first timer interrupt the CPU took was also the last it would take -- apic_delay would only work one time. Change-Id: Ib11aeee5b7da81287166ac68fc327e7ae62d1b84 Signed-off-by: Ronald G Minnich <rminnich@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43323 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: David Hendricks <david.hendricks@gmail.com> Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
* libpayload: arm64: silence libpayload main entryMichael Walle2020-07-082-23/+1
| | | | | | | | | | | | | No other architecture in libpayload outputs anything in the main entry routine. Let alone an exception test which looks like a real exception to the normal user and is most likely really misleading. Silence the startup code. Change-Id: I6e49f24ad46ce578a4bb111c2d623ca4470a1866 Signed-off-by: Michael Walle <michael@walle.cc> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43126 Reviewed-by: Julius Werner <jwerner@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* libpayload: arm64: fix OUTPUT_ARCH()Michael Walle2020-07-081-1/+1
| | | | | | | | | | | There is no bfd "arm64". The correct bfdname is "aarch64". Fix it. With this change libpayload will build with the AArch64 GCC. Change-Id: If7a6b14691107c5d4fc67c3cd3990ecc849d4af1 Signed-off-by: Michael Walle <michael@walle.cc> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43125 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
* treewide: Remove "this file is part of" linesPatrick Georgi2020-05-1148-48/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Stefan thinks they don't add value. Command used: sed -i -e '/file is part of /d' $(git grep "file is part of " |egrep ":( */\*.*\*/\$|#|;#|-- | *\* )" | cut -d: -f1 |grep -v crossgcc |grep -v gcov | grep -v /elf.h |grep -v nvramtool) The exceptions are for: - crossgcc (patch file) - gcov (imported from gcc) - elf.h (imported from GNU's libc) - nvramtool (more complicated header) The removed lines are: - fmt.Fprintln(f, "/* This file is part of the coreboot project. */") -# This file is part of a set of unofficial pre-commit hooks available -/* This file is part of coreboot */ -# This file is part of msrtool. -/* This file is part of msrtool. */ - * This file is part of ncurses, designed to be appended after curses.h.in -/* This file is part of pgtblgen. */ - * This file is part of the coreboot project. - /* This file is part of the coreboot project. */ -# This file is part of the coreboot project. -# This file is part of the coreboot project. -## This file is part of the coreboot project. --- This file is part of the coreboot project. -/* This file is part of the coreboot project */ -/* This file is part of the coreboot project. */ -;## This file is part of the coreboot project. -# This file is part of the coreboot project. It originated in the - * This file is part of the coreinfo project. -## This file is part of the coreinfo project. - * This file is part of the depthcharge project. -/* This file is part of the depthcharge project. */ -/* This file is part of the ectool project. */ - * This file is part of the GNU C Library. - * This file is part of the libpayload project. -## This file is part of the libpayload project. -/* This file is part of the Linux kernel. */ -## This file is part of the superiotool project. -/* This file is part of the superiotool project */ -/* This file is part of uio_usbdebug */ Change-Id: I82d872b3b337388c93d5f5bf704e9ee9e53ab3a9 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41194 Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* libpayload: arm64: Keep instruction cache enabled at all timesJulius Werner2020-02-173-24/+19
| | | | | | | | | | | | | | | | | | | | This patch makes libpayload enable the instruction cache as the very first thing, which is similar to how we treat it in coreboot. It also prevents the icache from being disabled again during mmu_disable() as part of the two-stage page table setup in post_sysinfo_scan_mmu_setup(). It replaces the existing mmu_disable() implementation with the assembly version from coreboot which handles certain edge cases better (see CB:27238 for details). The SCTLR flag definitions in libpayload seem to have still been copy&pasted from arm32, so replace with the actual arm64 defintions from coreboot. Change-Id: Ifdbec34f0875ecc69fedcbea5c20e943379a3d2d Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38908 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Hung-Te Lin <hungte@chromium.org>
* printf: Automatically prefix %p with 0xJulius Werner2019-12-112-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | According to the POSIX standard, %p is supposed to print a pointer "as if by %#x", meaning the "0x" prefix should automatically be prepended. All other implementations out there (glibc, Linux, even libpayload) do this, so we should make coreboot match. This patch changes vtxprintf() accordingly and removes any explicit instances of "0x%p" from existing format strings. How to handle zero padding is less clear: the official POSIX definition above technically says there should be no automatic zero padding, but in practice most other implementations seem to do it and I assume most programmers would prefer it. The way chosen here is to always zero-pad to 32 bits, even on a 64-bit system. The rationale for this is that even on 64-bit systems, coreboot always avoids using any memory above 4GB for itself, so in practice all pointers should fit in that range and padding everything to 64 bits would just hurt readability. Padding it this way also helps pointers that do exceed 4GB (e.g. prints from MMU config on some arm64 systems) stand out better from the others. Change-Id: I0171b52f7288abb40e3fc3c8b874aee14b9bdcd6 Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37626 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: David Guckian
* arm64: Bump exception stack size to 2KBJulius Werner2019-12-051-1/+1
| | | | | | | | | | | | | | | | | | | | | To avoid trampling over interesting exception artifacts on the real stack, our arm64 systems switch to a separate exception stack when entering an exception handler. We don't want that to use up too much SRAM so we just set it to 512 bytes. I mean it just prints a bunch of registers, how much stack could it need, right? Quite a bit it turns out. The whole vtxprintf() call stack goes pretty deep, and aarch64 generally seems to be very generous with stack space. Just the varargs handling seems to require 128 bytes for some reason, and the other stuff adds up too. In the end the current implementation takes 1008 bytes, so bump the exception stack size to 2K to make sure it fits. Change-Id: I910be4c5f6b29fae35eb53929c733a1bd4585377 Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37464 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Hung-Te Lin <hungte@chromium.org>
* Remove MIPS architectureJulius Werner2019-11-2016-1028/+0
| | | | | | | | | | | | | | | | | The MIPS architecture port has been added 5+ years ago in order to support a Chrome OS project that ended up going nowhere. No other board has used it since and nobody is still willing or has the expertise and hardware to maintain it. We have decided that it has become too much of a mainenance burden and the chance of anyone ever reviving it seems too slim at this point. This patch eliminates all MIPS code and MIPS-specific hacks. Change-Id: I5e49451cd055bbab0a15dcae5f53e0172e6e2ebe Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34919 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Hung-Te Lin <hungte@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* libpayload: refactor fetching cbmem pointersPatrick Georgi2019-10-031-2/+1
| | | | | | | | | | | | | | | | | | | | | | There's a recurring pattern of reading cbtable entries that point into cbmem entries. Move that pattern into its own function. Coccinelle patch used for this: @@ identifier T, T2; expression TARGET; @@ -struct cb_cbmem_tab *const T2 = (struct cb_cbmem_tab *)T; -TARGET = phys_to_virt(T2->cbmem_tab); +TARGET = get_cbmem_ptr(T); Change-Id: I7bd4a7ad8baeeaebf0fa7d4b4de6dbc719bc781f Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35756 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
* libpayload: Align main() data typesPatrick Georgi2019-04-054-4/+4
| | | | | | | | | | | | | | | One of many steps to compile with -Wconversion, as unsigned int and int aren't the same thing. BUG=b:111443775 BRANCH=none TEST=make junit.xml shows fewer warnings with -Wconversion enabled Change-Id: I9673ca70da32a1e5117b27fa89167e03379af9c1 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32183 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
* payloads: Replace all IS_ENABLED(CONFIG_XXX) with CONFIG(XXX)Julius Werner2019-03-079-14/+14
| | | | | | | | | | | | | This patch is a raw application of find payloads/ -type f | \ xargs sed -i -e 's/IS_ENABLED\s*(CONFIG_/CONFIG(/g' Change-Id: I883b03b189f59b5d998a09a2596b0391a2d5cf33 Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/31775 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
* libpayload: arm64: Add GDB supportJulius Werner2018-10-121-8/+88
| | | | | | | | | | This patch adds remote GDB support for the arm64 architecture. Change-Id: I2fa4dbca6c39f822f489a5e81bd052f53fda98a5 Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/29020 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
* libpayload: gdb: Factor out gdb_handle_reentrant_exception() from arm32Julius Werner2018-10-121-17/+1
| | | | | | | | | | | | | | The arm32 GDB architecture code contains a little hack that allows it to (sort of) correctly deal with a reentrant exception triggered from within the GDB stub. The main logic for this isn't really arm32 specific and could be useful for other architectures as well, so factor it out into a separate function. Change-Id: I3c6db8cecf1e86bba23de6fd2ac9fdf0cf69d3c6 Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/29019 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
* libpayload: arm64: Make exception handling closer to arm32Julius Werner2018-10-124-83/+105
| | | | | | | | | | | | | | | | | | | This patch reworks the arm64 exception handling to be more similar to how it works on arm32. This includes a bunch of features like actually saving and restoring more exception state in the exception_state structure and supporting the same sort of partial reentrancy that is useful for GDB. Since there's no instruction to directly load into or store out of SP on arm64, we can't do quite the same thing where we use that to read an exception_state_ptr variable right after exception entry when no other register is available. But we can do something very similar by (ab-)using the "high" stack pointer (SP_EL2) as a pointer to the exception_state struct and providing a function to change it. Change-Id: Ia16a1124be1824392a309ae1f4cb031547d184c1 Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/29018 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
* libpayload: arm64: Conform to new coreboot lib_helpers.h and assume EL2Julius Werner2018-10-1211-1802/+20
| | | | | | | | | | | | | | | | | | | | | | | | This patch adds the new, faster architectural register accessors to libpayload that were already added to coreboot in CB:27881. It also hardcodes the assumption that coreboot payloads run at EL2, which has already been hardcoded in coreboot with CB:27880 (see rationale there). This means we can drop all the read_current/write_current stuff which added a lot of unnecessary helpers to check the current exception level. This patch breaks payloads that used read_current/write_current accessors, but it seems unlikely that many payloads deal with this stuff anyway, and it should be a trivial fix (just replace them with the respective _el2 versions). Also add accessors for a couple of more registers that are required to enable debug mode while I'm here. Change-Id: Ic9dfa48411f3805747613f03611f8a134a51cc46 Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/29017 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com>
* libpayload/x86/exception: Add ability to ignore unknown interruptsRaul E Rangel2018-10-042-3/+32
| | | | | | | | | | | | | | | | | | | | This will make enabling the APIC safer by ignoring unknown interrupts and not halting the system. Once all interrupt sources have been found and handled DIE_ON_UNKNOWN_INTERRUPT can be set if desired. BUG=b:116777191 TEST=Booted grunt, halted the kernel, and pushed the power button while in S5. Verified that depthcharge logged the unknown exception. APIC Init Started APIC Configured Ignoring interrupt vector 39 Change-Id: If4ed566ec284d69786c369f37e4e331d7f892c74 Signed-off-by: Raul E Rangel <rrangel@chromium.org> Reviewed-on: https://review.coreboot.org/28882 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
* libpayload/x86/exception.c: Remove exception_install_hookRaul E Rangel2018-10-041-11/+0
| | | | | | | | | | | | | Not used by x86 code anymore. BUG=b:116777191 TEST=Validated that depthcharge can be built. Change-Id: I25ad3903989a5433ce73d657cfdb93dd1f34f7b5 Signed-off-by: Raul E Rangel <rrangel@chromium.org> Reviewed-on: https://review.coreboot.org/28881 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
* libpayload/apic: Register a spurious interrupt vectorRaul E Rangel2018-10-041-2/+21
| | | | | | | | | | | | | | | | We should have a spurious interrupt vector just incase we get one. The handler doesn't need to do anything. BUG=b:116777191 TEST=Booted depthcharge on grunt and inspected the register. I can't generate a spurious interrupt, so I can't validate that the handler gets called. Change-Id: I9e49e617f4375eb5eb00d0715c1902f77e2bf284 Signed-off-by: Raul E Rangel <rrangel@chromium.org> Reviewed-on: https://review.coreboot.org/28880 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
* libpayload/apic: Only ACK interrupts triggered by the APICRaul E Rangel2018-10-042-14/+26
| | | | | | | | | | | | | | | | Only set end of interrupt (EOI) when the APIC In-Service vector matches the interrupt vector. This makes it so we don't EOI a non APIC interrupt. BUG=b:116777191 TEST=Booted grunt with APIC enabled and verified depthcharge still works. Change-Id: I00bd1e7a0fcf2fc004feadc40d22ebfefe68b384 Signed-off-by: Raul E Rangel <rrangel@chromium.org> Reviewed-on: https://review.coreboot.org/28879 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
* src/*: normalize Google copyright headersPatrick Georgi2018-09-282-2/+2
| | | | | | | | | | | | | | | | | As per internal discussion, there's no "ChromiumOS Authors" that's meaningful outside the Chromium OS project, so change everything to the contemporary "Google LLC." While at it, also ensure consistency in the LLC variants (exactly one trailing period). "Google Inc" does not need to be touched, so leave them alone. Change-Id: Ia0780e31cdab879d2aaef62a2f0403e3db0a4ac8 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/28756 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Joel Kitching <kitching@google.com>
* libpayload/x86/delay: Make arch_ndelay call apic_delay if delay is longRaul E Rangel2018-09-122-0/+14
| | | | | | | | | | | | | | | | | This reduces power consumption on grunt by over 3W when sitting at the depthcharge recovery screen. BUG=b:109749762 TEST=Booted grunt in the recovery screen and made sure it continued to work. Change-Id: Id079c099ee4cf6a07724241af4400063f4551668 Signed-off-by: Raul E Rangel <rrangel@chromium.org> Reviewed-on: https://review.coreboot.org/28245 Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com> Reviewed-by: Julius Werner <jwerner@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* libpayload/x86/delay: Add an x86 arch_ndelayRaul E Rangel2018-09-122-0/+53
| | | | | | | | | | | | | | This method has a pause instruction to help the CPU relax a little bit. Measuring grunt it saves about 80mW. BUG=b:109749762 TEST=Made sure that grunt boots. Change-Id: I045a941ed42fcc4f2dbdd65b5cbb42d84813f50c Signed-off-by: Raul E Rangel <rrangel@chromium.org> Reviewed-on: https://review.coreboot.org/28244 Reviewed-by: Martin Roth <martinroth@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* libpayload/x86/apic: Add an apic_delay method and calibrate the timerRaul E Rangel2018-09-121-0/+77
| | | | | | | | | | | | | | | | | | The apic_delay method will halt the CPU and wait for a timer interrupt to fire. I went with usec because nsec is too granular to guarantee. This method will be called from an arch_ndelay() method when the delay is large enough to justify a sleep. BUG=b:109749762 TEST=Tested it on grunt by changing the _delay method to call apic_delay(). Change-Id: I80363f06bdb22d0907f895885e607fde1c4c468d Signed-off-by: Raul E Rangel <rrangel@chromium.org> Reviewed-on: https://review.coreboot.org/28242 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
* libpayload/arch/x86: Add support for initializing the APICRaul E Rangel2018-09-125-0/+212
| | | | | | | | | | | | | | | | | | | This is just the bare minimum required to initialize the APIC. I only support xAPIC and chose not to support x2APIC. We can add that functionality later when it's required. I also made the exception dispatcher call apic_eoi so that the callbacks won't forget to call it. BUG=b:109749762 TEST=Booted grunt and verified that depthcharge continued to function and that linux booted correctly. Also verified GDB still works. Change-Id: I420a4eadae84df088525e727b481089ef615183f Signed-off-by: Raul E Rangel <rrangel@chromium.org> Reviewed-on: https://review.coreboot.org/28241 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
* libpayload/x86/gdb: Migrate to use set_interrupt_handlerRaul E Rangel2018-09-101-6/+6
| | | | | | | | | | | | BUG=b:109749762 TEST=Verified GDB still functions by hitting Ctrl+G on the developer screen and stepping through some code. Change-Id: I723a8a95f681c500d9d8e35e49fd1d893cb1f133 Signed-off-by: Raul E Rangel <rrangel@chromium.org> Reviewed-on: https://review.coreboot.org/28240 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
* libpayload/x86/exception: Add ability to handle user defined interruptsRaul E Rangel2018-09-102-1/+43
| | | | | | | | | | | | | | | | | | | | | | I need to setup the APIC timer to fire interrupts. I would like to reuse the existing interrupt table. So I extended it to support user defined interrupts. I just added all 255 vectors so there wouldn't need to be any additional build time configuration. I'm going to deprecate exception_install_hook and remove it in a follow up. It will be replaced with set_interrupt_handler. This way the exception lookup does not have to manage a list of callbacks, or have to worry about the order they are processed. BUG=b:109749762 TEST=Wrote an interrupt handler and fired an APIC timer interrupt and verified that vector 32 was returned. Change-Id: Id9c2583c7c3d9be4a06a25e546e64399f2b0620c Signed-off-by: Raul E Rangel <rrangel@chromium.org> Reviewed-on: https://review.coreboot.org/28100 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
* libpayload/x86/exception: Add methods to enable/disable interruptsRaul E Rangel2018-08-231-0/+32
| | | | | | | | | | | | | Will be used by the APIC. BUG=b:109749762 TEST=Verified by the other cls in the stack. Change-Id: Id86f2719d98a90318ac625e09601e5dbb06e3765 Signed-off-by: Raul E Rangel <rrangel@chromium.org> Reviewed-on: https://review.coreboot.org/28239 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
* exception: Fix segment error code maskRaul E Rangel2018-08-061-1/+1
| | | | | | | | | | | | | The segment error descriptor is actually 13 bits long. BUG=b:109749762 TEST=Verified by causing a segment error Change-Id: I3439f9ce1e8cf0c472c4eb82d74a787718c9609f Signed-off-by: Raul E Rangel <rrangel@chromium.org> Reviewed-on: https://review.coreboot.org/27812 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
* libpayload/arm64: Drop unused static arrayPatrick Georgi2018-07-201-19/+0
| | | | | | | | | | | Fixes build with gcc8.1 Change-Id: I042f79ddfb4c249e00b5b259280289b8534f6854 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-on: https://review.coreboot.org/27546 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Julius Werner <jwerner@chromium.org>
* libpayload: Add raw_read_ functionsT Michael Turney2018-05-011-0/+16
| | | | | | | | | | | | Add: raw_read_cntfrq_el0() and raw_read_cntpct_el0() Required to support Arch64 Timer Change-Id: I86aa97039304b9e9336d0146febfe1811c9e075a Signed-off-by: T Michael Turney <mturney@codeaurora.org> Reviewed-on: https://review.coreboot.org/25649 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
* arch/arm64/armv8/mmu: Add support for 48bit VAPatrick Rudolph2018-03-231-12/+13
| | | | | | | | | | | | | | | | | | | The VA space needs to be extended to support 48bit, as on Cavium SoCs the MMIO starts at 1 << 47. The following changes were done to coreboot and libpayload: * Use page table lvl 0 * Increase VA bits to 48 * Enable 256TB in MMU controller * Add additional asserts Tested on Cavium SoC and two ARM64 Chromebooks. Change-Id: I89e6a4809b6b725c3945bad7fce82b0dfee7c262 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/24970 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
* Rename __attribute__((packed)) --> __packedStefan Reinauer2017-07-132-4/+4
| | | | | | | | | | | Also unify __attribute__ ((..)) to __attribute__((..)) and handle ((__packed__)) like ((packed)) Change-Id: Ie60a51c3fa92b5009724a5b7c2932e361bf3490c Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-on: https://review.coreboot.org/15921 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
* payloads: change coreboot to lowercaseMartin Roth2017-06-071-1/+1
| | | | | | | | | | | | The word 'coreboot' should always be written in lowercase, even at the start of a sentence. Change-Id: I2ec18ca55e0ea672343a951ab81a24a5630f45fd Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/20028 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Philippe Mathieu-Daudé <philippe.mathieu.daude@gmail.com> Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
* Use more secure HTTPS URLs for coreboot sitesPaul Menzel2017-06-072-2/+2
| | | | | | | | | | | | | | | | | | | The coreboot sites support HTTPS, and requests over HTTP with SSL are also redirected. So use the more secure URLs, which also saves a request most of the times, as nothing needs to be redirected. Run the command below to replace all occurences. ``` $ git grep -l -E 'http://(www.|review.|)coreboot.org' | xargs sed -i 's,http://\(.*\)coreboot.org,https://\1coreboot.org,g' ``` Change-Id: If53f8b66f1ac72fb1a38fa392b26eade9963c369 Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-on: https://review.coreboot.org/20034 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
* arm64: Align cache maintenance code with libpayload and ARM32Julius Werner2017-05-301-1/+5
| | | | | | | | | | | | | | | | | coreboot and libpayload currently use completely different code to perform a full cache flush on ARM64, with even different function names. The libpayload code is closely inspired by the ARM32 version, so for the sake of overall consistency let's sync coreboot to that. Also align a few other cache management details to work the same way as the corresponding ARM32 parts (such as only flushing but not invalidating the data cache after loading a new stage, which may have a small performance benefit). Change-Id: I9e05b425eeeaa27a447b37f98c0928fed3f74340 Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/19785 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
generated by cgit v1.2.3 (git 2.25.1) at 2024-06-29 13:59:10 +0000