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* nvramcui: reboot at the end as TODO suggestsVladimir Serbinenko2015-05-191-1/+2
| | | | | | | | | | Use cf9 to reboot at the end. Change-Id: I642a5ec89c864fb03bbcdf6e4fcbb1e28f3fc34c Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/4693 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
* libpayload: add mediatek timer driverYidi Lin2015-05-183-0/+52
| | | | | | | | | | | | | Change-Id: Ifb19cf97d4db6c7394521e549968a0cfb6ed1c75 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 0137652ca07e290bb3cb1cc82a00b44ac7bcc7bf Original-Change-Id: Ica649927d3533c847b24e520e8fe73d75fb9e786 Original-Signed-off-by: Yidi Lin <yidi.lin@mediatek.com> Original-Reviewed-on: https://chromium-review.googlesource.com/257375 Original-Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-on: http://review.coreboot.org/10170 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
* libpayload: x86: correct types used for IOAaron Durbin2015-05-131-4/+4
| | | | | | | | | | | | | | | libpayload on x86 defines u32 and uint32_t as typedefs of unsigned int. However, the readl/writel routines use long. With alias checking this throws type punning errors. Align the readl/writel/inl/outl types with the 32-bit fixed width ones that are exposed. Change-Id: Ie51cff8af4596948f6132e3cb743f1bc4ea8f204 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/10186 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
* libpayload: Fix passing BAR to EHCI driverPatrick Georgi2015-05-121-2/+2
| | | | | | | | | | | The EHCI driver never looked for the base address handed to it but instead used an uninitialized field for that information. Change-Id: I89fe0cc212092672b36e978083e3de78419b1eb5 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: http://review.coreboot.org/10179 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
* libpayload: Guard PCI using code appropriately in XHCI driverPatrick Georgi2015-05-041-0/+4
| | | | | | | | | | | Make the XHCI driver compile on ARM again. The Panther Point specific shutdown handler is certainly _not_ necessary there. Change-Id: I470afd4d82d101902b119b3ead4381e2b36a94b0 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-on: http://review.coreboot.org/10091 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marc.jones@se-eng.com>
* libpayload arm64: update mmu translation table granule size, logic and macrosJimmy Huang2015-04-273-49/+40
| | | | | | | | | | | | | | | | | | | | | | | 1. change mmu granule size from 64KB to 4KB 2. correct level 1 translation table creation logic 3. automatically calculate granule size related macros BRANCH=none BUG=none TEST=boot to kernel on oak board Change-Id: Ic62c7863dff53f566b82b68ff1d1ad9ec5d0698d Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: e5de7d942e42a8202fb879ce64b871864b1b9d38 Original-Change-Id: I78d7838921fa82a670e18ddc2de6d766dc7a2146 Original-Signed-off-by: Jimmy Huang <jimmy.huang@mediatek.com> Original-Reviewed-on: https://chromium-review.googlesource.com/266010 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Tested-by: Yidi Lin <yidi.lin@mediatek.com> Original-Commit-Queue: Yidi Lin <yidi.lin@mediatek.com> Reviewed-on: http://review.coreboot.org/10010 Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Tested-by: build bot (Jenkins)
* arm64: Add arch_program_segment_loaded call to arm64Furquan Shaikh2015-04-222-0/+9
| | | | | | | | | | | | | | | | | | | | | | | | | | arch_program_segment_loaded ensures that the program segment loaded is synced back from the cache to PoC. dcache_flush_all on arm64 does not guarantee PoC in case of MP systems. Thus, it is important to track and sync back all the required segments using arch_program_segment_loaded. BUG=chrome-os-partner:38231 BRANCH=None TEST=Compiles successfully and boots to kernel prompt on smaug Change-Id: Ic6fcc7e5e0cccbab317950f8abab0c494041d19a Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 284e3784854f764159b64286cea366c66b6bce2c Original-Change-Id: I5c35b9aa2ae9b5c1f2fcdef40ffb1cde7f49cc1a Original-Signed-off-by: Furquan Shaikh <furquan@google.com> Original-Reviewed-on: https://chromium-review.googlesource.com/263327 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Commit-Queue: Furquan Shaikh <furquan@chromium.org> Original-Trybot-Ready: Furquan Shaikh <furquan@chromium.org> Original-Tested-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: http://review.coreboot.org/9904 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
* libpayload: provide icache_invalidate_all() on ARM64Furquan Shaikh2015-04-222-3/+12
| | | | | | | | | | | | | | | | | | | | | | | | In order to not duplicate the instruction cache invalidation sequence provide a common routine to perform the necessary actions. Also, use it in the appropriate places. BUG=chrome-os-partner:38231 BRANCH=None TEST=Compiles successfully for smaug and boots kernel Change-Id: I1d311dbc70bf225f35d60bb10d8d001065322b3a Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 8ab015156713eb7531378edbd1d779522681d529 Original-Change-Id: I8da7002c56139f8f82503484bfd457a7ec20d083 Original-Signed-off-by: Furquan Shaikh <furquan@google.com> Original-Reviewed-on: https://chromium-review.googlesource.com/263326 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Commit-Queue: Furquan Shaikh <furquan@chromium.org> Original-Trybot-Ready: Furquan Shaikh <furquan@chromium.org> Original-Tested-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: http://review.coreboot.org/9903 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
* libpayload: Correct shareability mmu configuration on ARM64Furquan Shaikh2015-04-222-0/+7
| | | | | | | | | | | | | | | | | | | | BUG=chrome-os-partner:38222 BRANCH=None TEST=Compiles successfully and boots kernel Change-Id: I6e1e841d84d1a73e5c726143aeba76af933e81a1 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 59861a2700407b9e6a6209fbc45543c127b50b4b Original-Change-Id: I256d07a41bec83037f2b61a9350f903119d8c101 Original-Signed-off-by: Furquan Shaikh <furquan@google.com> Original-Reviewed-on: https://chromium-review.googlesource.com/263325 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Commit-Queue: Furquan Shaikh <furquan@chromium.org> Original-Trybot-Ready: Furquan Shaikh <furquan@chromium.org> Original-Tested-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: http://review.coreboot.org/9902 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
* libpayload: fix a mips memmove() bugVadim Bendebury2015-04-221-3/+2
| | | | | | | | | | | | | | | | | | | | | | size_t is an unsigned type and as such is a bad choice for a counting down loop counter. BRANCH=all BUG=none TEST=editing cli command line does not cause hangs any more Change-Id: I0502553b5e2143052345edeb205a01558fccd9b8 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 1c171f739497fcd26589976676ab94b23cd7ee8b Original-Change-Id: I4aa38379ac356114fc91a32cced2fa45a00a09d6 Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/262714 Original-Reviewed-by: Ionela Voinescu <ionela.voinescu@imgtec.com> Original-Tested-by: Ionela Voinescu <ionela.voinescu@imgtec.com> Original-Reviewed-by: David Hendricks <dhendrix@chromium.org> Reviewed-on: http://review.coreboot.org/9891 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
* libpayload: cros: add serial number from coreboot tableStephen Barber2015-04-223-0/+7
| | | | | | | | | | | | | | | | | | | | Add serial number to lib_sysinfo from coreboot table. BRANCH=none BUG=chrome-os-partner:37813 TEST=ryu boots and /proc/device-tree/firmware/android is populated with "compatible", "hardware", and "serialno" properties Change-Id: I565b332a16b177c51907ffab7976ebd7a665aaaf Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 5535119f5d499b04bdc178c3040241d2872c4e13 Original-Change-Id: Ie2e222780d1577689a1cbf76ae8514c74fc469f4 Original-Signed-off-by: Stephen Barber <smbarber@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/259140 Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: http://review.coreboot.org/9881 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
* libpayload: usb: fix compilation error in debug fuctionHarry Pan2015-04-221-1/+1
| | | | | | | | | | | | | | | | | | | | | | | Since CL:170664, all SC_SPEED_XXX renamed to SC_SPEED1_XXX. There is one missing in xhci_dump_slotctx() function which makes compilation error. BUG=none TEST=enable USB_DEBUG and XHCI_DUMPS macros in xhci_private.h; then emerge-auron libpayload Change-Id: Ib96805cb7fc1cad17b205277539fb2120632f6f4 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 3ca0174e93ad131309ad07187c95c1e84c7d4fc5 Original-Change-Id: Id056b4684831a5717e87969e95ab17f11db29696 Original-Reviewed-on: https://chromium-review.googlesource.com/261414 Original-Reviewed-by: Hung-Te Lin <hungte@chromium.org> Original-Reviewed-by: Julius Werner <jwerner@chromium.org> Original-Commit-Queue: Harry Pan <harry.pan@intel.com> Original-Tested-by: Harry Pan <harry.pan@intel.com> Reviewed-on: http://review.coreboot.org/9877 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
* libpayload: add timer driver for cygnusDaisuke Nojiri2015-04-212-2/+34
| | | | | | | | | | | | | | | | | | | | | | | | BUG=chrome-os-partner:36011 BRANCH=broadcom-firmware TEST=measured 10 seconds in depthcharge: Starting depthcharge on purin... dpch: time 10 9 8 7 6 5 4 3 2 1 0 Change-Id: I0bcb01c255b19518bb8440111ac81f056c07ed69 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: f5993bd400dd5d38e62d07bc8ce3513175e0d518 Original-Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org> Original-Reviewed-on: https://chrome-internal-review.googlesource.com/200569 Original-Reviewed-by: Julius Werner <jwerner@chromium.org> Original-Commit-Queue: Daisuke Nojiri <dnojiri@google.com> Original-Tested-by: Daisuke Nojiri <dnojiri@google.com> Original-Change-Id: Id83aae29cec6320d897e0b231d023a9ee885903e Original-Reviewed-on: https://chromium-review.googlesource.com/256415 Reviewed-on: http://review.coreboot.org/9850 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
* cygnus: enable serial driver for depthchargeDaisuke Nojiri2015-04-214-56/+1
| | | | | | | | | | | | | | | | | | | | | BUG=chrome-os-partner:35807 BRANCH=broadcom-firmware TEST=tested input and output by the cli in depthcharge Change-Id: Icd517a366a3fe5bdcf9e9aeb4284d7e4378ee3f2 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 02c3b6c82d9d71beb19a0879591c754fa7685362 Original-Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org> Original-Reviewed-on: https://chrome-internal-review.googlesource.com/200568 Original-Reviewed-by: Julius Werner <jwerner@chromium.org> Original-Reviewed-by: Scott Branden <sbranden@broadcom.com> Original-Commit-Queue: Daisuke Nojiri <dnojiri@google.com> Original-Tested-by: Daisuke Nojiri <dnojiri@google.com> Original-Change-Id: I97144fc6f19969b8cf3872939c9c74efaef3604b Original-Reviewed-on: https://chromium-review.googlesource.com/256413 Reviewed-on: http://review.coreboot.org/9844 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
* libpayload: mips: Do not set C0_EBase_WGAndrew Bresticker2015-04-211-4/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The WG (write gate) bit in C0_EBase allows the upper two bits of the exception base address to be set to something other than 2'b10, thus allowing it to be relocated out of the traditional KSEG{0,1} range. Since we're not using the segmentation features introduced by EVA to relocate the unmapped segments, the exception vectors should remain in KSEG0. Don't set the WG bit so that the upper two bits of the exception base (2'b00, because of the identity mapping) are ignored and we execute the exception vectors out of KSEG0. BUG=chrome-os-partner:36258 BRANCH=none TEST=Build and boot on Pistachio. Change-Id: Ie8b4eb6e41a328e7055736c9e3f6ff5ec83b9e13 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: d5b002f5ae71c7729e467d4fe3fd8db187e15dea Original-Change-Id: Id8b930db1e7a68f52dd61be4dfa9edaee2bebf7d Original-Signed-off-by: Andrew Bresticker <abrestic@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/246697 Original-Reviewed-by: Ionela Voinescu <ionela.voinescu@imgtec.com> Original-Reviewed-by: Vadim Bendebury <vbendeb@chromium.org> Original-Tested-by: Vadim Bendebury <vbendeb@chromium.org> Original-Commit-Queue: Vadim Bendebury <vbendeb@chromium.org> Reviewed-on: http://review.coreboot.org/9822 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
* libpayload: mips: Add macros to convert to/from KSEG{0,1} addressesAndrew Bresticker2015-04-213-37/+12
| | | | | | | | | | | | | | | | | | | | | | | | Add helper macros to convert between physical addresses and KSEG{0,1} addresses. Also get rid of the virt_to_{bus,phys}_offset variables as these are fixed values. As nobody seems to be using getpagesize() on MIPS, no need to keep virtual.c. BUG=chrome-os-partner:36258 BRANCH=none TEST=Build and boot on Pistachio. Change-Id: Ia26c8eae53eb8f860747a6b321363776841d1a94 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: c422b02e9a2a20d130913b1cfb835ad74c39ddca Original-Change-Id: I9476cd225a08534830c700cba7bf9d3ef871757e Original-Signed-off-by: Andrew Bresticker <abrestic@chromium.org> Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/247190 Reviewed-on: http://review.coreboot.org/9821 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
* libpayload: mips: Use KSEG1 to access DMA-coherent memoryAndrew Bresticker2015-04-211-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | Use bus_to_virt() to convert the physical address of the DMA coherent region to an address in KSEG1 which is suitable for device memory accesses. BUG=chrome-os-partner:36258 BRANCH=none TEST=Build and boot on Pistachio. Change-Id: If382feda66f6d829f8b3548ab263cf603cab2e9b Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: a88a175f6d6db81d3154fb5dd31a44363ab94653 Original-Change-Id: I9ad6435495df2c71d8f81a782f1c3dfcfd4aeb28 Original-Signed-off-by: Andrew Bresticker <abrestic@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/246696 Original-Reviewed-by: Ionela Voinescu <ionela.voinescu@imgtec.com> Original-Reviewed-by: Vadim Bendebury <vbendeb@chromium.org> Original-Commit-Queue: Vadim Bendebury <vbendeb@chromium.org> Original-Tested-by: Vadim Bendebury <vbendeb@chromium.org> Reviewed-on: http://review.coreboot.org/9818 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
* libpayload: mips: Set BASE_ADDRESS to 0Andrew Bresticker2015-04-211-1/+1
| | | | | | | | | | | | | | | | | | | | | | | Now that coreboot has identity-mapped DRAM, use base address 0 (KUSEG) instead of 0x80000000 (KSEG0). BUG=chrome-os-partner:36258 BRANCH=none TEST=Build and boot on Pistachio. Change-Id: I39845250a1b8cea6e5360efce16770751ffce13d Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: c1cbc1d7f6873c0be30d4206a2030f3b468acf24 Original-Change-Id: I76d98664f1bca73ae8acc9f545e68de9173c3cab Original-Signed-off-by: Andrew Bresticker <abrestic@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/246695 Original-Reviewed-by: Ionela Voinescu <ionela.voinescu@imgtec.com> Original-Reviewed-by: Vadim Bendebury <vbendeb@chromium.org> Original-Commit-Queue: Vadim Bendebury <vbendeb@chromium.org> Original-Tested-by: Vadim Bendebury <vbendeb@chromium.org> Reviewed-on: http://review.coreboot.org/9817 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
* libpayload udc: Support legal edge case of GET_CONFIGURATION callPatrick Georgi2015-04-181-2/+3
| | | | | | | | | | | | | | | | | | | | | | | I doubt anybody will ask for the configuration and request that 0 bytes be returned, but AFAICS that's legal, so let's support it. Should have no effect on ChipIdea since it knows not to send more data than requested by the host. BRANCH=none BUG=none TEST=none Change-Id: Ibfe57b593015fa5e0381c45ff9e39c3f912b4d4d Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 45555e929d9d07dbb58ecfd18333f26375a0e3d7 Original-Change-Id: I7432772a1812c6f52c2b1688ee4c6f67d02ccf28 Original-Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/258064 Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: http://review.coreboot.org/9790 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
* libpayload udc: Only enable configuration if it's validPatrick Georgi2015-04-181-4/+4
| | | | | | | | | | | | | | | | | | | Only set internal variables when there's no risk of breaking things. BRANCH=none BUG=none TEST=none Change-Id: I8a8b63f60bdb70fad38130ce38eef81fe3725aa2 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 7119829096b444b790937b116fb782bcb5da70cd Original-Change-Id: If698b11a7ff7688def310d8574fcfa7a40f703c1 Original-Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/258063 Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: http://review.coreboot.org/9789 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
* libpayload: Enforce strict packet handling order in ChipIdea driverPatrick Georgi2015-04-181-12/+36
| | | | | | | | | | | | | | | | | | | | | | First handle IN packets, then OUT packets and finally SETUP packets. This makes OS X happy. It isn't implemented as the data sheet recommends but it avoids implementing a state machine and should always produce observable effects identical to that of the stateful solution. BRANCH=none BUG=none TEST=`fastboot getvar version` on OSX works Change-Id: Ic7b27387771d6a7794fba12fc822fccc48770ea8 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: f0e59547519d50b1d34f6abdc6132330125f94f3 Original-Change-Id: Iada1cff011f11e7d5cb1a1b34896ab590f488ec7 Original-Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/258062 Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: http://review.coreboot.org/9788 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
* libpayload: More defensive ChipIdea initializationPatrick Georgi2015-04-181-0/+3
| | | | | | | | | | | | | | | | | | | | Mark EP0 non-stall explicitly. Shouldn't be necessary, but won't hurt either. BRANCH=none BUG=none TEST=none Change-Id: I7ecd16a2affe064918d93436aedfa07bd9a1cf56 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: a0fc237b33444fc30dc5b62e4f1afc3188f2cf43 Original-Change-Id: I1aa8742eebc4de733317600e35627631ebaf4724 Original-Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/258061 Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: http://review.coreboot.org/9787 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
* libpayload udc: Clear bit when it needs clearingPatrick Georgi2015-04-181-1/+1
| | | | | | | | | | | | | | | | | | | Trivial copy & paste error, likely with no visible effect so far. BRANCH=none BUG=none TEST=none Change-Id: Ieaf5e770ab7a8474e407012d2c11a15c46ab357d Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 90f8971500c95456ae70c6f4219b1ff9aff1c0b0 Original-Change-Id: I973573efd0effc9e0173d2b259ce577b6de38de4 Original-Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/258060 Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: http://review.coreboot.org/9786 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
* libpayload udc: Deconfigure device when necessaryPatrick Georgi2015-04-182-7/+21
| | | | | | | | | | | | | | | | | | | | SET_CONFIGURATION(0) stops operation and is moves the device to addressed mode. BRANCH=none BUG=none TEST=USB device mode still works Change-Id: I964d90ba8440b6f428896acc9fe63e1114390da6 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 402bc907222d07765b3438967edf26cc1a79d775 Original-Change-Id: Iebad024e1ed2e344dba73b73a9b385a4ac4cb450 Original-Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/250791 Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: http://review.coreboot.org/9785 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
* libpayload: Add zero length packet support to UDC frameworkPatrick Georgi2015-04-183-4/+35
| | | | | | | | | | | | | | | | | | | | | | | | | Some IN transfers must be terminated by an empty packet because otherwise the host wouldn't know. The zlp() function determines this requirement in accordance to USB rules: If the transfer's size is aligned to the maximum packet size, and the host expects a larger transfer, add the empty packet as a hint. BRANCH=none BUG=none TEST=USB device mode still works Change-Id: Ia69f3d017f72a3a0e0b21bac72fe97be184c7daa Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: fd0e946e4948a74a9ed15a5eed6ce827b7672a56 Original-Change-Id: I8153cc5bd2ff1c88e383c1dbcddaf1bf72f9194c Original-Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/250790 Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: http://review.coreboot.org/9784 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
* libpayload: Add USB device mode driverPatrick Georgi2015-04-187-0/+1164
| | | | | | | | | | | | | | | | | | | | | | | | | Add a framework for USB device mode controllers and a driver for the ChipIdea controller which is part of the tegra platform. TODO: - fix USB detach/attach - implement zero length packet handling properly BUG=chrome-os-partner:35861 TEST=none BRANCH=none Change-Id: I8defeea78b5a3bdbf9c1b1222c2702eaf3256b81 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 542332291880c4026a05a960ceb91d37891ee018 Original-Change-Id: Ib4068d201dd63ebeda80157bd3130f3059919cdd Original-Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/243272 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/8756 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
* purin: add basic set of files for libpayloadDaisuke Nojiri2015-04-175-0/+157
| | | | | | | | | | | | | | | | | BUG=none BRANCH=tot TEST=emerge-purin libpayload depthcharge coreboot chromeos-bootimage Change-Id: I6a46067a288ecea352a2724c62c62066e3f4a383 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 355371317dde0546fbab2cd109bc17463f77c4fd Original-Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org> Original-Change-Id: I8c43acc4d270c3b2d7c18af07c077a553e3c6f6f Original-Reviewed-on: https://chromium-review.googlesource.com/245492 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/9753 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
* libpayload: read register width from coreboot tableVadim Bendebury2015-04-172-0/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | Some SOCs (like pistachio, for instance) provide an 8250 compatible UART, which has the same register layout, but mapped to a bus of a different width. Instead of adding a new driver for these controllers, it is better to have coreboot report UART register width to libpayload, and have it adjust the offsets accordingly when accessing the UART. BRANCH=none BUG=chrome-os-partner:31438 TEST=with the rest of the patches integrated depthcharge console messages show up when running on the FPGA board Change-Id: I05891a9471a5369d3bfafe90cd0c9b0a7e5a667e Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 2c30845f269ec6ae1d53ddc5cda0b4320008fa42 Original-Change-Id: Ia0a37cd5f24a1ee4d0334f8a7e3da5df0069cec4 Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/240027 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/9739 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
* libpayload: sync arch/arm/cache.c with corebootDavid Hendricks2015-04-171-1/+9
| | | | | | | | | | | | | | | | | | | | | | | | There was a recent patch by Deepa Dinamani applied to coreboot's cache.c which fixed a bug that occurred when icache is on but dcache is off ("arch: armv7: Fix cache sync instructions."). Although this bug is not likely to be encountered by the time libpayload is run, it's worth applying it to keep things in sync. BUG=none BRANCH=none TEST=n/a since we have icache and dcache enabled on all ARM platforms when libpayload is run. Change-Id: I83d9f96acb702975585e5d47c90e2ddaca488f6d Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 31f985b58ac9227684fbe27481129ba01fd3ab8a Original-Signed-off-by: David Hendricks <dhendrix@chromium.org> Original-Change-Id: I4ab0d97ef3a97dcd0fa96e10273c3b32486e0b40 Original-Reviewed-on: https://chromium-review.googlesource.com/243276 Original-Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-on: http://review.coreboot.org/9737 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
* libpayload: Take flash parameters from corebootDan Ehrenberg2015-04-173-0/+26
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | A payload may want to run erase operations on SPI NOR flash without re-probing the device to get its properties. This patch passes up three properties of flash to achieve that: - The size of the flash device - The sector size, i.e., the granularity of erase - The command used for erase The patch sends the parameters through coreboot and then libpayload. The patch also includes a minor refactoring of the flash erase code. Parameters are sent up for just one flash device. If multiple SPI flash devices are probed, the second one will "win" and its parameters will be sent up to the payload. TEST=Observed parameters to be passed up to depthcharge through libpayload and be used to correctly initialize flash and do an erase. TEST=Winbond and Gigadevices spi flash drivers compile with the changes; others don't, for seemingly unrelated reasons. BRANCH=none BUG=chromium:446377 Change-Id: I92b7ff0ce66af8d096ec09a4c900829ef6c867e0 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 988c8c68bbfcdfa69d497ea5f806567bc80f8126 Original-Change-Id: Ie2b3a7f5b6e016d212f4f9bac3fabd80daf2ce72 Original-Signed-off-by: Dan Ehrenberg <dehrenberg@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/239570 Original-Reviewed-by: Vadim Bendebury <vbendeb@chromium.org> Reviewed-on: http://review.coreboot.org/9727 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
* Danger: Initial mainboard importDavid Hendricks2015-04-151-0/+78
| | | | | | | | | | | | | | | | | | | | | This adds a directory with files copied over from Brain along with build-related changes so that emerge-veyron_danger works. The next patch will account for other differences. BUG=none BRANCH=none TEST=emerge-veyron_danger coreboot works Change-Id: I7ebd431cd48e257dfa761d32013d0e251b4f155d Signed-off-by: Stefan Reinauer <reinauer@chromium.org> Original-Commit-Id: a0f7d2f96540df6fdcd7a99d9e0fa02bbc6c1f73 Original-Signed-off-by: David Hendricks <dhendrix@chromium.org> Original-Change-Id: Id265a7715f07a647a449f00097bf40f7c9b4c068 Original-Reviewed-on: https://chromium-review.googlesource.com/241711 Original-Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-on: http://review.coreboot.org/9646 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marc.jones@se-eng.com>
* Brain: Initial mainboard importDavid Hendricks2015-04-151-0/+78
| | | | | | | | | | | | | | | | | | | | | | | This adds a directory with files copied over from Jerry, in addition to build system related changes (configs/* and Kconfig stuff) necessary to emerge-veyron_brain coreboot. The next patch will account for differences between Jerry and Brain. BUG=none BRANCH=none TEST=emerge-veyron_brain coreboot works Change-Id: Ib0da9caf80f46991b96bcb5756f807237f0902e1 Signed-off-by: Stefan Reinauer <reinauer@chromium.org> Original-Commit-Id: 9509d6277dae25a78062c1301054a39f704b33fe Original-Signed-off-by: David Hendricks <dhendrix@chromium.org> Original-Change-Id: I972f2623d9b0a43e3ea5312b3c4cd34ab44edc36 Original-Reviewed-on: https://chromium-review.googlesource.com/236989 Original-Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-on: http://review.coreboot.org/9637 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marc.jones@se-eng.com>
* libpayload: avoid hanging on make junit.xmlPatrick Georgi2015-04-141-1/+1
| | | | | | | | | | | | | make oldconfig doesn't like 'y' as response to a choice item such as the architecture list. An empty response, however, is acceptable, so use that. Change-Id: Ic3164dd3f40e4a7f5d91e3a7008893655cd69ac2 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-on: http://review.coreboot.org/9676 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
* pistachio: modify timer to account for CPU counter overflowIonela Voinescu2015-04-141-1/+12
| | | | | | | | | | | | | | | | | | | | | | | Extended the 32bit CPU counter to 64bit by adding a static variable that takes into account CPU counter overflow. The varibale is updated everythime the timer_raw_value function is called so I assume that the function is called often enought to not miss an overflow of the CPU counter. BUG=chrome-os-partner:31438 TEST=tested on Pistachio bring up board; works as expected BRANCH=none Change-Id: I98bcc56e600dcff0c6da7c140dd34faec5e00885 Signed-off-by: Stefan Reinauer <reinauer@chromium.org> Original-Commit-Id: 972b105f950d800fa44f27bce090f6b89a5a84b9 Original-Change-Id: Id67b14e9d9c2354bc417b6587b615d466690c9b7 Original-Signed-off-by: Ionela Voinescu <ionela.voinescu@imgtec.com> Original-Reviewed-on: https://chromium-review.googlesource.com/247642 Original-Reviewed-by: Daniel Ehrenberg <dehrenberg@chromium.org> Reviewed-on: http://review.coreboot.org/9672 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
* arm64: Increase dma region size to 32MiBFurquan Shaikh2015-04-141-1/+1
| | | | | | | | | | | | | | | | | | | | BUG=None BRANCH=None TEST=Download and write to kernel partition successful on ryu Change-Id: I9623a0a430e95633dabbb87537a5c70bc9619dde Signed-off-by: Stefan Reinauer <reinauer@chromium.org> Original-Commit-Id: 3ba52d7c7baa42de3149cc604423a5825988401e Original-Change-Id: Ia6ba5ad52596c32cc3ad42f98c7f4f8b3e13d6c5 Original-Signed-off-by: Furquan Shaikh <furquan@google.com> Original-Reviewed-on: https://chromium-review.googlesource.com/242205 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Tested-by: Furquan Shaikh <furquan@chromium.org> Original-Commit-Queue: Furquan Shaikh <furquan@chromium.org> Original-Trybot-Ready: Furquan Shaikh <furquan@chromium.org> Reviewed-on: http://review.coreboot.org/9661 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh <furquan@google.com>
* libpayload dwc2: use bus addresses for buffersIonela Voinescu2015-04-141-1/+2
| | | | | | | | | | | | | | | | | | | | | | The address of the output buffer sent to the device should be the bus address and not the virtual address. BUG=chrome-os-partner:31438 TEST=tested on Pistachio FPGA and bring up board; USB works properly after this change BRANCH=none Change-Id: I5c9d199e17c3f4303095ad73f4980d32d04c6118 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 942c385c112c2a4e409da806548081d3e2f8f438 Original-Change-Id: I0c06196501a968a72cb3f2c7dd1027bb22cdaada Original-Signed-off-by: Ionela Voinescu <ionela.voinescu@imgtec.com> Original-Reviewed-on: https://chromium-review.googlesource.com/245387 Original-Reviewed-by: David Hendricks <dhendrix@chromium.org> Original-Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-on: http://review.coreboot.org/9455 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
* libpayload dwc2: Use a new FIFO allocation methodhuang lin2015-04-142-6/+33
| | | | | | | | | | | | | | | | | | | | | | Total FIFO length is split into 512 byte blocks. Allocate these blocks to GRXFSIZ and GNPTXFSZ evenly. This method avoids hardcoding and makes the FIFO size value work for dwc2 controllers that have a different FIFO ram size. BUG=chrome-os-partner:32634 BRANCH=None TEST=Boot kernel from USB Change-Id: I78ce0fa4c4600fb56c991874a93bdd6674e648c2 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 5645a25e95f84359cd10fc9fcf56e1f73fd6ce87 Original-Change-Id: Ib50a08c193f7f65392810ca3528a97554f2c3999 Original-Signed-off-by: huang lin <hl@rock-chips.com> Original-Reviewed-on: https://chromium-review.googlesource.com/233119 Original-Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-on: http://review.coreboot.org/9454 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
* libpayload: Add dwc2 usb driverhuang lin2015-04-1411-1/+1231
| | | | | | | | | | | | | | | | BUG=chrome-os-partner:29778 TEST=emerge-veyron libpayload Change-Id: I33f312a939e600b8f4e50a092bb61c5d6bc6d741 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 39ffe53336a2a3b2baa067cdd3dccca5ae93f68e Original-Change-Id: Idad1ad165fd44df635a0cb13bfec6fada1378bc8 Original-Signed-off-by: huang lin <hl@rock-chips.com> Original-Reviewed-on: https://chromium-review.googlesource.com/211053 Original-Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-on: http://review.coreboot.org/9453 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
* CBFS: Automate ROM image layout and remove hardcoded offsetsJulius Werner2015-04-143-29/+18
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Non-x86 boards currently need to hardcode the position of their CBFS master header in a Kconfig. This is very brittle because it is usually put in between the bootblock and the first CBFS entry, without any checks to guarantee that it won't overlap either of those. It is not fun to debug random failures that move and disappear with tiny alignment changes because someone decided to write "ORBC1112" over some part of your data section (in a way that is not visible in the symbolized .elf binaries, only in the final image). This patch seeks to prevent those issues and reduce the need for manual configuration by making the image layout a completely automated part of cbfstool. Since automated placement of the CBFS header means we can no longer hardcode its position into coreboot, this patch takes the existing x86 solution of placing a pointer to the header at the very end of the CBFS-managed section of the ROM and generalizes it to all architectures. This is now even possible with the read-only/read-write split in ChromeOS, since coreboot knows how large that section is from the CBFS_SIZE Kconfig (which is by default equal to ROM_SIZE, but can be changed on systems that place other data next to coreboot/CBFS in ROM). Also adds a feature to cbfstool that makes the -B (bootblock file name) argument on image creation optional, since we have recently found valid use cases for CBFS images that are not the first boot medium of the device (instead opened by an earlier bootloader that can already interpret CBFS) and therefore don't really need a bootblock. BRANCH=None BUG=None TEST=Built and booted on Veyron_Pinky, Nyan_Blaze and Falco. Change-Id: Ib715bb8db258e602991b34f994750a2d3e2d5adf Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: e9879c0fbd57f105254c54bacb3e592acdcad35c Original-Change-Id: Ifcc755326832755cfbccd6f0a12104cba28a20af Original-Signed-off-by: Julius Werner <jwerner@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/229975 Reviewed-on: http://review.coreboot.org/9620 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
* serial: Combine Tegra and Rockchip UARTs to generic 8250_mmio32Julius Werner2015-04-107-154/+30
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | We have two drivers for a 100%-identical peripheral right now, mostly because we couldn't come up with a good common name for it back when we checked it in. That seems like a pretty silly reason in the long run. Both Tegra and Rockchip SoCs contain UARTs that use the common 8250 register interface (at least for the very basic byte-per-byte transmit and receive parts we care about), memory-mapped with a 32-bit register stride. This patch combines them to a single 8250_mmio32 driver (which also fixes a problem when booting Rockchip without serial enabled, since that driver forgot to check for serial initialization when registering its console drivers). The register accesses are done using readl/writel (as Rockchip did before), since the registers are documented as 32-bit length (with top 24 bits RAZ/WI), although the Tegra SoC doesn't enforce APB accesses to have the full word length. Also fixed checkpatch stuff. A day may come when we can also merge this driver into the (completely different, with more complicated features and #ifdefs) 8250 driver for x86 (which has MMIO support for 8-bit register stride only), both here and in coreboot. But it is not this day. This day I just want to get rid of a 99% identical file without expending too much effort. BUG=None TEST=Booted on Veyron_Pinky and Nyan_Blaze with and without serial enabled, both worked fine (although Veyron has another kernel issue). Change-Id: I85c004a75cc5aa7cb40098002d3e00a62c1c5f2d Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: e7959c19356d2922aa414866016540ad9ee2ffa8 Original-Change-Id: Ib84d00f52ff2c48398c75f77f6a245e658ffdeb9 Original-Signed-off-by: Julius Werner <jwerner@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/225102 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/9387 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
* libpayload: PCI bus scan - Eliminate endless loopLee Leahy2015-04-091-3/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | Don't attempt to scan the PCI bus if the bridge is disabled. When the PCI bridge is not setup and enabled, it is possible for the secondary bus register to contain the value zero (0). In this case the usb_scan_pci_bus routine gets into an infinite recursive loop which ends only when the heap or stack is exhausted. This patch verifies that the PCI bridge is enabled by verifying that it is enabled for either memory or I/O operations. When enabled, the secondary bus is scanned. BRANCH=none BUG=None TEST=Build and run on Samus Change-Id: I6826dc1d73b7c24729de5ac7c4d3534922ca73c5 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 63d04b47934761351b54c847a2692bdef81ce54f Original-Change-Id: I855240c52fa3eba841e6754816ebbcb824abc4cd Original-Signed-off-by: Lee Leahy <Leroy.P.Leahy@intel.com> Original-Reviewed-on: https://chromium-review.googlesource.com/236382 Original-Commit-Queue: Leroy P Leahy <leroy.p.leahy@intel.com> Original-Tested-by: Leroy P Leahy <leroy.p.leahy@intel.com> Original-Reviewed-by: Giri P Mudusuru <giri.p.mudusuru@intel.com> Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: http://review.coreboot.org/8734 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
* libpayload: Add drivers for bg4cdDaisuke Nojiri2015-04-084-0/+85
| | | | | | | | | | | | | | | | | | | BUG=chrome-os-partner:32772 BRANCH=none TEST=Built chromeos-bootimage Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org> Change-Id: I15cb40532855c89f6fb959652a7e874897eb45bb Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 8f8419fe22cf39d827e566b8f4dbe0680e4106a1 Original-Change-Id: I97f2ac8ffc7232c7a6c6d40deb8a35630d3d62a7 Original-Reviewed-on: https://chromium-review.googlesource.com/222662 Original-Reviewed-by: Vadim Bendebury <vbendeb@chromium.org> Original-Commit-Queue: Daisuke Nojiri <dnojiri@chromium.org> Original-Tested-by: Daisuke Nojiri <dnojiri@chromium.org> Reviewed-on: http://review.coreboot.org/9360 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
* arm: Dump additional fault registers in abort handlersJulius Werner2015-04-082-0/+60
| | | | | | | | | | | | | | | | | | | | | | | | | | Paging code is tricky and figuring out what is wrong with it can be a pain. This patch tries to ease the burden by giving a little more information for prefetch and data aborts, dumping the Instruction Fault Address Register (IFAR), Instruction Fault Status Register (IFSR) and Auxiliary Instruction Fault Status Register (AIFSR) or the respective Data registers. These contain additional information about the cause of the abort (internal/external, write or read, fault subtype, etc.) and the faulting address. BUG=None TEST=I have read through enough imprecise asynchronous external abort reports with this patch that I learned the bit pattern by heart. Change-Id: If1850c4a6df29b1195714ed0bdf025e51220e8ab Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: bf3b4924121825a5ceef7e5c14b7b307d01f8e9c Original-Change-Id: I56a0557d4257f40b5b30c559c84eaf9b9f729099 Original-Signed-off-by: Julius Werner <jwerner@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/223784 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/9345 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
* libpayload: usb: xhci: set ENT flag in last Normal TRBSourabh Banerjee2015-03-232-0/+11
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | If a TD is comprised of one or more Normal TRBs and terminated with an Event Data TRB, then the transition to the Idle state (and associated Stream state save) could occur after all the data for the TD has been moved (e.g. after Transfer Event TRBs have been executed), but before the Event Data TRB is executed. Under these conditions, the execution of the Event Data TRB is necessary to complete the TD, otherwise it does not occur until the next time the Stream is scheduled. This could lead to the lock up. The Evaluate Next TRB(ENT) flag provides a means of forcing the execution of a terminating Event Data TRB. Setting ENT flag in last Normal TRB makes the xHC to evaluate the Even Data TRB. BUG=chrome-os-partner:29375 TEST=Verified kernel boot-up on storm from previously failing USB stick. USB stick model: Sandisk Ultra USB 3.0 Pen Drive 32 GB Strontium Jet USB 3.0 Pen Drive 32 GB Change-Id: I092e2109c55c2274239c493cb67b47d730304ed2 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 7eefb3b2858c841165ae839d349d2a0be50fbcc8 Original-Change-Id: I4e123577ec5a5996d87d2fc52cb6cf5c571c9fae Original-Signed-off-by: Sourabh Banerjee <sbanerje@codeaurora.org> Original-Reviewed-on: https://chromium-review.googlesource.com/220123 Original-Reviewed-by: Julius Werner <jwerner@chromium.org> Original-Commit-Queue: Vadim Bendebury <vbendeb@chromium.org> Original-Tested-by: Vadim Bendebury <vbendeb@chromium.org> Reviewed-on: http://review.coreboot.org/8736 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
* libpayload: EHCI: Support root-hub TT featureJim Lin2015-03-234-8/+34
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | If EHCI controller has TT (Transaction Translator) support in root-hub, then we need to keep control over this controller when USB keyboard (low-speed device) is connected to root-hub port. Need to add "CONFIG_LP_USB_EHCI_HOSTPC_ROOT_HUB_TT=y" to config file (e.g. payloads/libpayload/configs/config.nyan_big) to support this feature. BUG=chrome-os-partner:32355 TEST=Tested on nyan_big platform. Press ESC+REFRESH+POWER keys on internal keyboard to power up. Press Left Arrow or Right Arrow on USB keyboard to switch between "English" and "Default Locale" in coreboot UI. Or unplug and plug in device and try again. Root hub <- low-speed USB keyboard Root hub <- full-speed hub <- low-speed USB keyboard Root hub <- high-speed hub <- low-speed USB keyboard Change-Id: Iaa2823f64c8769fc808ee7a316c378f18f004e63 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 4ad57fd673d6dc8814fe99a4ac420566bb17e77b Original-Change-Id: Id86a289bc587653b85227c1d50f7a4f476f37983 Original-Signed-off-by: Jim Lin <jilin@nvidia.com> Original-Reviewed-on: https://chromium-review.googlesource.com/220125 Original-Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-on: http://review.coreboot.org/8737 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
* libpayload arm64: Allow board to define upper address limit on DMAFurquan Shaikh2015-03-233-2/+7
| | | | | | | | | | | | | | | | | | | | | | | | Instead of forcing boards to have DMA region below 4GiB, provide Kconfig option DMA_LIM_EXCL that a board can use to set the upper limit in MiB units on the address range reserved by DMA. By default, this value is 0x1000 i.e. 4GiB limit on the DMA upper address. BUG=None BRANCH=None TEST=Compiles successfully for rush. Default value is seen as 0x1000. Change-Id: Ie35d3844a0989486ae022f8922fdd4c9d7d57fb4 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 6716cf312a103bc0440a558fc43c8c77869816e3 Original-Change-Id: I3ecbb4ec90995ab1568cb0924d5ce9467492697d Original-Signed-off-by: Furquan Shaikh <furquan@google.com> Original-Reviewed-on: https://chromium-review.googlesource.com/245250 Original-Tested-by: Furquan Shaikh <furquan@chromium.org> Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Commit-Queue: Furquan Shaikh <furquan@chromium.org> Reviewed-on: http://review.coreboot.org/8800 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh <furquan@google.com>
* libpayload: whitespace cleanupPatrick Georgi2015-03-211-9/+9
| | | | | | | | | | Align struct members with tabs. Change-Id: Ie8bdbd718c7217a3f3768dd037fa7c10badbc05e Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-on: http://review.coreboot.org/8854 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
* libpayload arm64: fix mmu_disable() cache problemHC Yen2015-03-211-2/+3
| | | | | | | | | | | | | | | | | | | | | The raw_write_sctlr_current() cannot be used in mmu_disable() because it pushes some registers to cached stack, and then just after cache disabled, the value was gone. BRANCH=none BUG=none TEST=build and boot on mt8173-evb Change-Id: I512405b7917f27d16bdd3c51d9459827ad714e67 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: aafe64922cc4cd01ecb099db106d04538e3e57ff Original-Change-Id: I0dda8518d14c46fae1fe76e3629bd4ee81c1e0ee Original-Signed-off-by: HC Yen <hc.yen@mediatek.com> Original-Reviewed-on: https://chromium-review.googlesource.com/240323 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/8799 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
* libpayload arm64: Add helper functions with el argumentHC Yen2015-03-214-71/+292
| | | | | | | | | | | | | | | | | | | | Allow read/write to registers at a given el. Also, make read/write registers at current el call this newly added function. BRANCH=none BUG=none TEST=build and boot on mt8173-evb Change-Id: Id69f0fdc07193c5c7e997712f0cd99de6f41510b Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: c091917babc39d9ab997f51f81b486c9aa900c24 Original-Change-Id: I0944946642066b88331e497a92388e74e86902d0 Original-Signed-off-by: HC Yen <hc.yen@mediatek.com> Original-Reviewed-on: https://chromium-review.googlesource.com/240322 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/8798 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
* libpayload arm64: don't modify cbtable entriesAaron Durbin2015-03-211-2/+11
| | | | | | | | | | | | | | | | | | | | | | | | The framebuffer structure lives in the coreboot tables. Those tables have a checksum calculation applied over all the entries. Therefore, one shouldnot be modifying fields within the coreboot table entries because the calculated checksum would be wrong. BRANCH=none BUG=chrome-os-partner:31936 TEST=On ryu, confirmed dev screen still works as well as cbmem utility once booted. Change-Id: I93830a8efe98aa848f2b0f8388688de0e93b2f82 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 6026ca5ad0254c14c30412882dc63550656c7d16 Original-Change-Id: Ic9c164ded03d10d6f6f3ce15e9b38b1f6ce61a91 Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/230471 Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org> Original-Commit-Queue: Furquan Shaikh <furquan@chromium.org> Reviewed-on: http://review.coreboot.org/8797 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-20 03:59:27 +0000