| Commit message (Expand) | Author | Age | Files | Lines | |
|---|---|---|---|---|---|
| * | spd/lp5: Add new part MT62F2G32D8DR-031 | Amanda Huang | 2022-03-10 | 2 | -0/+33 |
| * | util/spd_tools: Encode SDRAM min cycle time (TCKMinPs) | Karthikeyan Ramasubramanian | 2022-03-08 | 3 | -6/+6 |
| * | util/spd_tools/spd_gen/lp5: Encode Bank Architecture | Karthikeyan Ramasubramanian | 2022-02-17 | 3 | -3/+3 |
| * | util/spd_tools/spd_gen/lp5: Encode Optional SDRAM features | Karthikeyan Ramasubramanian | 2022-02-17 | 3 | -3/+3 |
| * | spd/lp5: Add new part H9JCNNNBK3MLYR-N6E | Reka Norman | 2022-02-15 | 1 | -0/+1 |
| * | spd/lp5: Generate initial SPDs for Sabrina SoC | Karthikeyan Ramasubramanian | 2022-02-10 | 5 | -0/+135 |
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index : coreboot.git | |
| Coreboot firmware sources | coreboot |
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