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* drivers/intel/dptf: Add support for Battery participantVarshit B Pandya2022-04-051-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | As per Intel Dynamic Tuning revision 1.3.13 (Doc no: 541817) add support for TBAT device under \_SB.DPTF BUG=b:205928013 TEST=Build, boot brya0 and dump SSDT to check TBAT device Device (TBAT) { Name (_HID, "INTC1061") // _HID: Hardware ID Name (_UID, "TBAT") // _UID: Unique ID Name (_STR, "Battery Participant") // _STR: Description String Name (PTYP, 0xC) Method (_STA, 0, NotSerialized) // _STA: Status { Return (0x0F) } } Signed-off-by: Varshit B Pandya <varshit.b.pandya@intel.com> Change-Id: I9104318fd838f30253ab1eeac4e212b3b917f516 Reviewed-on: https://review.coreboot.org/c/coreboot/+/63315 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
* drivers/intel/dptf: Add support for Power participantVarshit B Pandya2022-04-011-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | As per Intel Dynamic Tuning revision 1.3.13 (Doc no: 541817) Add support for TPWR device under \_SB.DPTF BUG=b:205928013 TEST=Build, boot brya0 and dump SSDT to check TPWR device Device (TPWR) { Name (_HID, "INTC1060") // _HID: Hardware ID Name (_UID, "TPWR") // _UID: Unique ID Name (_STR, "Power Participant") // _STR: Description String Name (PTYP, 0x11) Method (_STA, 0, NotSerialized) // _STA: Status { Return (0x0F) } } Signed-off-by: Varshit B Pandya <varshit.b.pandya@intel.com> Change-Id: I437e509f58df1777d75e5981f0a5a63095ccb6a3 Reviewed-on: https://review.coreboot.org/c/coreboot/+/62944 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* dptf: Add support for one more temperature sensorTim Wawrzynczak2021-11-261-0/+2
| | | | | | | | | | | | | | | Some boards may use more than 4 temperature sensors for DPTF thermal control, so this patch adds support for one more temperature sensor. BUG=b:207585491 Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Change-Id: Ibf9666bade23b9bb4f740c6c4df6ecf5227cfb45 Reviewed-on: https://review.coreboot.org/c/coreboot/+/59632 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Scott Chao <scott_chao@wistron.corp-partner.google.com> Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
* acpi/acpigen_dptf: Add TPCH participant for dptfSumeet Pawnikar2021-10-011-0/+2
| | | | | | | | | | | | | | Add TPCH as participant for dptf control functionality. BUG=b:198582766 BRANCH=None TEST=Build FW and test on brya0 board Change-Id: I17c0c6cfb7804dd2caa188acc93f1a63b47cab36 Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57924 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
* src/acpi: Add missing <{stdbool,stdint}.h>Elyes HAOUAS2020-07-291-0/+2
| | | | | | | | Change-Id: Ic09c04cfa18408c61d7e99ea29bccc23acbd7144 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43956 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
* acpi: Fix dptf_write_fan_perf to include Revision fieldTim Wawrzynczak2020-07-281-1/+3
| | | | | | | | | | | | | | | | When emitting a fan's _FPS (Fan Performance States) table, the revision field was missing. According to ACPI spec 6.3, the current revision is zero, so add that Package entry before the others. BUG=b:149722146 TEST=verified first element of \_SB.DPTF.TFN1._FPS is 0 Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Change-Id: If16d4751f1d924807f5087d93b348e58d5265197 Reviewed-on: https://review.coreboot.org/c/coreboot/+/43978 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* dptf: Fix scope of TCPU deviceTim Wawrzynczak2020-07-181-12/+22
| | | | | | | | | | | | | | | | | In the initial DPTF refactor, the scope of the TCPU device was incorrectly set as \_SB, instead of \_SB.PCI0. However, because of the way that the acpi_inject_dsdt() callback currently works (it injects contents before the dsdt.aml file), the Scope where the TCPU device lives (\_SB.PCI0) doesn't exist yet. Therefore, to avoid playing games with *when* things are defined in the DSDT, switch to defining all of the DPTF devices in the SSDT. Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Change-Id: Ia4922b4dc6544d79d44d39e6ad18c6ab9fee0fd7 Reviewed-on: https://review.coreboot.org/c/coreboot/+/43529 Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* dptf: Add support for IDSPTim Wawrzynczak2020-07-071-0/+42
| | | | | | | | | | | | \_SB.DPTF.IDSP adverties to the DPTF daemon which policies the implementation supports. Added a new acpigen function to figure out which policies are used, and fills out IDSP appropriately. Change-Id: Idf67a23bf38de4481c02f98ffb27afb8ca2d1b7b Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42081 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
* dptf: Add support for Fan and TSR optionsTim Wawrzynczak2020-07-071-0/+28
| | | | | | | | | | | | | | | | | | DPTF has several options on how to control the fan (fine-grained speed control, minimum speed change in percentage points, and whether or not the DPTF device should notify the Fan if it detects low speed). Individual TSRs can also set GTSH, which is the amount of hysteresis inherent in the measurement, either from circuitry (if analog), or in firmware (if digital). BUG=b:143539650 TEST=compiles Change-Id: I42d789d877da28c163e394d7de5fb1ff339264eb Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41891 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
* dptf: Add support for Running Average Power LimitsTim Wawrzynczak2020-07-071-0/+46
| | | | | | | | | | | | | | | | | This change adds support for emitting the PPCC table, which describes the ranges available as knobs for DPTF to tune. It can support min/max power, min/max time window for averaging, and the minimum adjustment size (granularity or step size) of each power limit. The current implementation only supports PL1 and PL2. BUG=b:143539650 TEST=compiles Change-Id: I67e80d661ea5bb79980ef285eca40c9a4b0f1849 Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41890 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
* dptf: Add support for Fan Performance StatesTim Wawrzynczak2020-07-071-0/+37
| | | | | | | | | | | | | | | | | This change adds support for generating the _FPS table for the DPTF Fan object. The table describes different levels of fan activity that may be applied to the system in order to actively cool it. The information includes fan speed at a (rough) percentage level, fan speed in RPM, potential noise level in centibels, and power in mA. BUG=b:143539650 TEST=compiles Change-Id: I5591eb527f496d0c4c613352d2a87625d47d9273 Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41889 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
* dptf: Add support for Charger Performance StatesTim Wawrzynczak2020-07-071-0/+41
| | | | | | | | | | | | | | | | This change generates the DPTF TCHG.PPSS table in the SSDT. This table describes different charging rates which are available to use. DPTF can pick different rates in order to passively cool (or not) the system. BUG=b:143539650 TEST=compiles Change-Id: I6df6bfbac628fa4e4d313e38b8e6c53fce70a7f2 Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41888 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
* dptf: Add support for Critical PoliciesTim Wawrzynczak2020-07-071-0/+18
| | | | | | | | | | | | | | | | This patch adds support for DPTF Critical Policies, which are consist of Method definitions only. They are `_CRT` and `_HOT`, which are defined as temperature thresholds that, when exceeded, will execute a graceful suspend or a graceful shutdown, respectively. BUG=b:143539650 TEST=compiles Change-Id: I711ecdcf17ae8f6e653f33069201da4515ace85e Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41887 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
* dptf: Add support for Passive PoliciesTim Wawrzynczak2020-07-071-0/+98
| | | | | | | | | | | | | | | This patch adds support for emitting the Thermal Relationship Table, as well as _PSV Methods, which together form the basis for DPTF Passive Policies. BUG=b:143539650 TEST=compiles Change-Id: I82e1c9022999b0a2a733aa6cd9c98a850e6f5408 Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41886 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
* dptf: Add support for generation of Active PoliciesTim Wawrzynczak2020-07-071-0/+166
This change adds support for generating the different pieces of DPTF Active Policies. This includes the Active Relationship Table, in addition to _ACx methods. BUG=b:143539650 TEST=compiles Change-Id: Iea0ccbd96f88d0f3a8f2c77a7d0f3a284e5ee463 Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41885 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com> Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
generated by cgit v1.2.3 (git 2.25.1) at 2024-06-19 23:34:01 +0000