coreboot.git - Coreboot firmware sources

	Commit message (Expand)	Author	Age	Files	Lines
*	riscv: Add initial support for 32bit boards	Philipp Hug	2019-02-13	1	-1/+2
*	riscv: Simplify payload handling	Xiang Wang	2019-02-02	1	-0/+1
*	riscv: add support to block smp in each stage	Xiang Wang	2018-11-05	1	-7/+3
*	arch/riscv: Update comment about mstatus initialization	Jonathan Neuschäfer	2018-10-06	1	-1/+1
*	arch/riscv: Only execute on hart 0 for now	Philipp Hug	2018-09-14	1	-0/+6
*	riscv: add CAR interface	Xiang Wang	2018-07-18	1	-15/+21
*	arch/riscv: Pass the bootrom-provided FDT to the payload	Jonathan Neuschäfer	2018-02-20	1	-1/+8
*	riscv: get SBI calls to work	Ronald G. Minnich	2017-01-16	1	-6/+8
*	riscv: Add a bandaid for the new toolchain	Ronald G. Minnich	2016-11-02	1	-1/+5
*	RISCV: Clean up the common architectural code	Ronald G. Minnich	2016-10-24	1	-4/+7
*	arch/riscv: Refactor bootblock.S	Jonathan Neuschäfer	2016-07-28	1	-124/+19
*	riscv/bootblock.S: Register machine-mode, not supervisor-mode trap handler	Jonathan Neuschäfer	2016-06-28	1	-2/+2
*	arch/riscv: Move _start to the beginning of the bootblock	Jonathan Neuschäfer	2016-06-28	1	-14/+1
*	riscv-spike: Move coreboot to 0x80000000 (2GiB)	Jonathan Neuschäfer	2016-06-21	1	-2/+5
*	Change la to li (load immediate)	Ronald G. Minnich	2016-04-08	1	-2/+2
*	tree: drop last paragraph of GPL copyright header	Patrick Georgi	2015-10-31	1	-4/+0
*	riscv-memlayout: fix existing memlayout issues, add sbi interface	Thaminda Edirisooriya	2015-09-16	1	-14/+94
*	riscv-spike: support for Spike emulation of riscv	Thaminda Edirisooriya	2015-08-09	1	-15/+18
*	Remove address from GPLv2 headers	Patrick Georgi	2015-05-21	1	-2/+1
*	riscv: use new-style CBFS header lookup	Patrick Georgi	2015-04-18	1	-19/+0
*	New mechanism to define SRAM/memory map with automatic bounds checking	Julius Werner	2015-04-06	1	-1/+1
*	Add UCB RISCV support for architecture, soc, and emulation mainboard..	Ronald G. Minnich	2014-12-01	1	-0/+104