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* riscv: ARCH_RISCV_RV{32,64} selects ARCH_RISCVRonald G. Minnich2019-01-241-1/+2
* riscv: create Kconfig architecture features for new partsRonald G. Minnich2019-01-172-4/+53
* buildsystem: Promote rules.h to default includeKyösti Mälkki2019-01-162-2/+0
* arch/riscv: Don't set FPU state to "dirty"Jonathan Neuschäfer2018-12-191-5/+0
* arch/riscv: Define and use SBI_ENOSYSJonathan Neuschäfer2018-12-192-1/+3
* arch/riscv: Don't hardcode CSR numbers anymoreJonathan Neuschäfer2018-12-181-7/+2
* riscv: fix non-SMP supportPhilipp Hug2018-12-072-6/+6
* src: Add required space after "switch"Elyes HAOUAS2018-11-191-1/+1
* riscv: add support for supervisor binary interface (SBI)Xiang Wang2018-11-055-1/+187
* riscv: add support to block smp in each stageXiang Wang2018-11-054-8/+16
* riscv: add support smp_pause / smp_resumeXiang Wang2018-11-055-1/+144
* src: Add missing include <stdint.h>Elyes HAOUAS2018-10-301-0/+2
* riscv: simplify timer interrupt handlingPhilipp Hug2018-10-301-52/+9
* src/arch/riscv/misaligned.c: Fix an off-by-one error when loading the opcodePhilipp Hug2018-10-301-1/+1
* selfboot: remove bounce buffersRonald G. Minnich2018-10-111-5/+0
* riscv: add physical memory protection (PMP) supportXiang Wang2018-10-113-0/+355
* Move compiler.h to commonlibNico Huber2018-10-082-3/+0
* arch/riscv: Update comment about mstatus initializationJonathan Neuschäfer2018-10-062-2/+2
* arch/riscv: Adjust compiler flags for scan-buildJonathan Neuschäfer2018-10-041-1/+6
* arch/riscv: Advance the PC after handling misaligned load/storeJonathan Neuschäfer2018-09-261-4/+13
* arch/riscv/include/arch: Don't use device_tElyes HAOUAS2018-09-211-1/+1
* riscv: don't write to mstatus.XSXiang Wang2018-09-161-1/+0
* arch/riscv: Configure delegation only if S-mode is supportedJonathan Neuschäfer2018-09-151-5/+7
* arch/riscv: Only execute on hart 0 for nowPhilipp Hug2018-09-141-0/+6
* arch/riscv: provide a monotonic timerPhilipp Hug2018-09-145-4/+48
* arch/riscv: add missing endian.h header to io.hPhilipp Hug2018-09-141-0/+1
* complier.h: add __always_inline and use it in code baseAaron Durbin2018-09-142-7/+10
* riscv: update misaligned memory access exception handlingXiang Wang2018-09-105-68/+652
* riscv: update mtime initializationXiang Wang2018-09-102-3/+4
* riscv: add entry assembly file for RAMSTAGEXiang Wang2018-09-053-1/+60
* riscv: add support to check machine length at runtimeXiang Wang2018-09-051-0/+6
* riscv: add spin lock supportXiang Wang2018-09-041-0/+28
* riscv: Add DEFINE_MPRV_READ_MXR to read execution-only pageXiang Wang2018-09-041-3/+16
* riscv: separately define stack locations at different stagesXiang Wang2018-09-021-0/+14
* riscv: update the definition of intptr_t/uintptr_tXiang Wang2018-08-301-2/+2
* arch: Retire cache_sync_instructions() from <arch/cache.h> (except arm)Julius Werner2018-08-071-1/+0
* riscv: remove redundancy in MakefileXiang Wang2018-08-013-56/+1
* riscv: fix issues (timestrap & PRIu64)Xiang Wang2018-07-312-4/+4
* riscv: delete src/arch/riscv/prologue.incXiang Wang2018-07-301-17/+0
* arch/riscv: Fix makefile to only set flags for riscvMartin Roth2018-07-181-3/+5
* riscv: add CAR interface Xiang Wang2018-07-181-15/+21
* riscv: add support for modifying compiler optionsXiang Wang2018-07-172-12/+14
* riscv: add include/arch/smp/ directoryXiang Wang2018-07-124-30/+61
* riscv: add support to check ISA extensionXiang Wang2018-07-111-0/+7
* riscv: use __riscv_atomic to check support A extensionXiang Wang2018-07-061-1/+1
* RISC-V boards: Remove PAGETABLES section from memlayout.ldJonathan Neuschäfer2018-04-271-1/+0
* arch/riscv: Store mprv bit in size_tJonathan Neuschäfer2018-04-261-2/+2
* arch/riscv: Remove I/O space access functions (outb, etc.)Jonathan Neuschäfer2018-04-111-29/+0
* arch/riscv: Delegate the page fault exceptionsJonathan Neuschäfer2018-02-201-0/+3
* arch/riscv: Update encoding.h and adjust related codeJonathan Neuschäfer2018-02-203-83/+238
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