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riscv
Commit message (
Expand
)
Author
Age
Files
Lines
*
riscv: ARCH_RISCV_RV{32,64} selects ARCH_RISCV
Ronald G. Minnich
2019-01-24
1
-1
/
+2
*
riscv: create Kconfig architecture features for new parts
Ronald G. Minnich
2019-01-17
2
-4
/
+53
*
buildsystem: Promote rules.h to default include
Kyösti Mälkki
2019-01-16
2
-2
/
+0
*
arch/riscv: Don't set FPU state to "dirty"
Jonathan Neuschäfer
2018-12-19
1
-5
/
+0
*
arch/riscv: Define and use SBI_ENOSYS
Jonathan Neuschäfer
2018-12-19
2
-1
/
+3
*
arch/riscv: Don't hardcode CSR numbers anymore
Jonathan Neuschäfer
2018-12-18
1
-7
/
+2
*
riscv: fix non-SMP support
Philipp Hug
2018-12-07
2
-6
/
+6
*
src: Add required space after "switch"
Elyes HAOUAS
2018-11-19
1
-1
/
+1
*
riscv: add support for supervisor binary interface (SBI)
Xiang Wang
2018-11-05
5
-1
/
+187
*
riscv: add support to block smp in each stage
Xiang Wang
2018-11-05
4
-8
/
+16
*
riscv: add support smp_pause / smp_resume
Xiang Wang
2018-11-05
5
-1
/
+144
*
src: Add missing include <stdint.h>
Elyes HAOUAS
2018-10-30
1
-0
/
+2
*
riscv: simplify timer interrupt handling
Philipp Hug
2018-10-30
1
-52
/
+9
*
src/arch/riscv/misaligned.c: Fix an off-by-one error when loading the opcode
Philipp Hug
2018-10-30
1
-1
/
+1
*
selfboot: remove bounce buffers
Ronald G. Minnich
2018-10-11
1
-5
/
+0
*
riscv: add physical memory protection (PMP) support
Xiang Wang
2018-10-11
3
-0
/
+355
*
Move compiler.h to commonlib
Nico Huber
2018-10-08
2
-3
/
+0
*
arch/riscv: Update comment about mstatus initialization
Jonathan Neuschäfer
2018-10-06
2
-2
/
+2
*
arch/riscv: Adjust compiler flags for scan-build
Jonathan Neuschäfer
2018-10-04
1
-1
/
+6
*
arch/riscv: Advance the PC after handling misaligned load/store
Jonathan Neuschäfer
2018-09-26
1
-4
/
+13
*
arch/riscv/include/arch: Don't use device_t
Elyes HAOUAS
2018-09-21
1
-1
/
+1
*
riscv: don't write to mstatus.XS
Xiang Wang
2018-09-16
1
-1
/
+0
*
arch/riscv: Configure delegation only if S-mode is supported
Jonathan Neuschäfer
2018-09-15
1
-5
/
+7
*
arch/riscv: Only execute on hart 0 for now
Philipp Hug
2018-09-14
1
-0
/
+6
*
arch/riscv: provide a monotonic timer
Philipp Hug
2018-09-14
5
-4
/
+48
*
arch/riscv: add missing endian.h header to io.h
Philipp Hug
2018-09-14
1
-0
/
+1
*
complier.h: add __always_inline and use it in code base
Aaron Durbin
2018-09-14
2
-7
/
+10
*
riscv: update misaligned memory access exception handling
Xiang Wang
2018-09-10
5
-68
/
+652
*
riscv: update mtime initialization
Xiang Wang
2018-09-10
2
-3
/
+4
*
riscv: add entry assembly file for RAMSTAGE
Xiang Wang
2018-09-05
3
-1
/
+60
*
riscv: add support to check machine length at runtime
Xiang Wang
2018-09-05
1
-0
/
+6
*
riscv: add spin lock support
Xiang Wang
2018-09-04
1
-0
/
+28
*
riscv: Add DEFINE_MPRV_READ_MXR to read execution-only page
Xiang Wang
2018-09-04
1
-3
/
+16
*
riscv: separately define stack locations at different stages
Xiang Wang
2018-09-02
1
-0
/
+14
*
riscv: update the definition of intptr_t/uintptr_t
Xiang Wang
2018-08-30
1
-2
/
+2
*
arch: Retire cache_sync_instructions() from <arch/cache.h> (except arm)
Julius Werner
2018-08-07
1
-1
/
+0
*
riscv: remove redundancy in Makefile
Xiang Wang
2018-08-01
3
-56
/
+1
*
riscv: fix issues (timestrap & PRIu64)
Xiang Wang
2018-07-31
2
-4
/
+4
*
riscv: delete src/arch/riscv/prologue.inc
Xiang Wang
2018-07-30
1
-17
/
+0
*
arch/riscv: Fix makefile to only set flags for riscv
Martin Roth
2018-07-18
1
-3
/
+5
*
riscv: add CAR interface
Xiang Wang
2018-07-18
1
-15
/
+21
*
riscv: add support for modifying compiler options
Xiang Wang
2018-07-17
2
-12
/
+14
*
riscv: add include/arch/smp/ directory
Xiang Wang
2018-07-12
4
-30
/
+61
*
riscv: add support to check ISA extension
Xiang Wang
2018-07-11
1
-0
/
+7
*
riscv: use __riscv_atomic to check support A extension
Xiang Wang
2018-07-06
1
-1
/
+1
*
RISC-V boards: Remove PAGETABLES section from memlayout.ld
Jonathan Neuschäfer
2018-04-27
1
-1
/
+0
*
arch/riscv: Store mprv bit in size_t
Jonathan Neuschäfer
2018-04-26
1
-2
/
+2
*
arch/riscv: Remove I/O space access functions (outb, etc.)
Jonathan Neuschäfer
2018-04-11
1
-29
/
+0
*
arch/riscv: Delegate the page fault exceptions
Jonathan Neuschäfer
2018-02-20
1
-0
/
+3
*
arch/riscv: Update encoding.h and adjust related code
Jonathan Neuschäfer
2018-02-20
3
-83
/
+238
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