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* arch/riscv: Advance the PC after handling misaligned load/storeJonathan Neuschäfer2018-09-261-4/+13
* arch/riscv/include/arch: Don't use device_tElyes HAOUAS2018-09-211-1/+1
* riscv: don't write to mstatus.XSXiang Wang2018-09-161-1/+0
* arch/riscv: Configure delegation only if S-mode is supportedJonathan Neuschäfer2018-09-151-5/+7
* arch/riscv: Only execute on hart 0 for nowPhilipp Hug2018-09-141-0/+6
* arch/riscv: provide a monotonic timerPhilipp Hug2018-09-145-4/+48
* arch/riscv: add missing endian.h header to io.hPhilipp Hug2018-09-141-0/+1
* complier.h: add __always_inline and use it in code baseAaron Durbin2018-09-142-7/+10
* riscv: update misaligned memory access exception handlingXiang Wang2018-09-105-68/+652
* riscv: update mtime initializationXiang Wang2018-09-102-3/+4
* riscv: add entry assembly file for RAMSTAGEXiang Wang2018-09-053-1/+60
* riscv: add support to check machine length at runtimeXiang Wang2018-09-051-0/+6
* riscv: add spin lock supportXiang Wang2018-09-041-0/+28
* riscv: Add DEFINE_MPRV_READ_MXR to read execution-only pageXiang Wang2018-09-041-3/+16
* riscv: separately define stack locations at different stagesXiang Wang2018-09-021-0/+14
* riscv: update the definition of intptr_t/uintptr_tXiang Wang2018-08-301-2/+2
* arch: Retire cache_sync_instructions() from <arch/cache.h> (except arm)Julius Werner2018-08-071-1/+0
* riscv: remove redundancy in MakefileXiang Wang2018-08-013-56/+1
* riscv: fix issues (timestrap & PRIu64)Xiang Wang2018-07-312-4/+4
* riscv: delete src/arch/riscv/prologue.incXiang Wang2018-07-301-17/+0
* arch/riscv: Fix makefile to only set flags for riscvMartin Roth2018-07-181-3/+5
* riscv: add CAR interface Xiang Wang2018-07-181-15/+21
* riscv: add support for modifying compiler optionsXiang Wang2018-07-172-12/+14
* riscv: add include/arch/smp/ directoryXiang Wang2018-07-124-30/+61
* riscv: add support to check ISA extensionXiang Wang2018-07-111-0/+7
* riscv: use __riscv_atomic to check support A extensionXiang Wang2018-07-061-1/+1
* RISC-V boards: Remove PAGETABLES section from memlayout.ldJonathan Neuschäfer2018-04-271-1/+0
* arch/riscv: Store mprv bit in size_tJonathan Neuschäfer2018-04-261-2/+2
* arch/riscv: Remove I/O space access functions (outb, etc.)Jonathan Neuschäfer2018-04-111-29/+0
* arch/riscv: Delegate the page fault exceptionsJonathan Neuschäfer2018-02-201-0/+3
* arch/riscv: Update encoding.h and adjust related codeJonathan Neuschäfer2018-02-203-83/+238
* arch/riscv: Pass the bootrom-provided FDT to the payloadJonathan Neuschäfer2018-02-205-16/+78
* arch/riscv: Don't set up virtual memoryJonathan Neuschäfer2018-02-203-258/+0
* arch/riscv: Make RVC support configurableJonathan Neuschäfer2018-02-202-3/+20
* arch/riscv: Align trap_entry to 4 bytes, as required by specJonathan Neuschäfer2018-02-201-0/+1
* arch/riscv: Remove supervisor_trap_entryJonathan Neuschäfer2017-12-021-9/+1
* riscv: Remove config string supportJonathan Neuschäfer2017-12-024-14/+4
* arch/riscv: Remove the current SBI implementationJonathan Neuschäfer2017-12-027-316/+7
* arch/riscv: Return from trap_handler instead of jumping outJonathan Neuschäfer2017-12-022-7/+3
* arch/riscv: Unify trap returnJonathan Neuschäfer2017-12-022-15/+10
* Constify struct cpu_device_id instancesJonathan Neuschäfer2017-11-231-1/+1
* arch/riscv: Use a separate trap stackJonathan Neuschäfer2017-11-071-4/+8
* arch/riscv: gettimer: Don't use the config stringJonathan Neuschäfer2017-11-071-7/+9
* arch/riscv: Drop mret workaroundJonathan Neuschäfer2017-11-072-6/+3
* arch/riscv: mprv_read_*: Mark result as earlyclobberJonathan Neuschäfer2017-11-071-1/+1
* arch/riscv: Fix return type of mprv_read_u64Jonathan Neuschäfer2017-11-071-1/+1
* arch/riscv: hls_init: Initialize time{,cmp} with dummy pointersJonathan Neuschäfer2017-09-271-6/+3
* arch/riscv: Document mprv_{read,write}_* functionsJonathan Neuschäfer2017-09-271-0/+11
* arch/riscv: trap handler: Print load/store access width in bitsJonathan Neuschäfer2017-09-271-2/+2
* riscv: Update register addresswxjstz2017-09-261-3/+2
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