summaryrefslogtreecommitdiffstats
path: root/src/arch
Commit message (Expand)AuthorAgeFilesLines
* src: Add required space after "switch"Elyes HAOUAS2018-11-191-1/+1
* src: Remove unneeded include <cbmem.h>Elyes HAOUAS2018-11-163-3/+0
* src: Remove unneeded include <console/console.h>Elyes HAOUAS2018-11-164-5/+1
* src: Get rid of duplicated includesElyes HAOUAS2018-11-161-1/+0
* mb/emulation/qemu-i440fx|q35: Fix stack sizePatrick Rudolph2018-11-141-0/+3
* src: Remove unneeded include "{arch,cpu}/cpu.h"Elyes HAOUAS2018-11-123-3/+1
* arch/x86: Fix car_active for CONFIG_NO_CAR_GLOBAL_MIGRATIONFurquan Shaikh2018-11-091-2/+18
* include/program_loading: Add POSTCAR prog typePhilipp Deppenwiese2018-11-091-1/+1
* toolchain: Add POSTCAR as a stage we have a toolchain forPatrick Georgi2018-11-082-0/+12
* x86/acpi.c: Be more verbose when finding the wakeup vectorAngel Pons2018-11-061-4/+10
* riscv: add support for supervisor binary interface (SBI)Xiang Wang2018-11-055-1/+187
* riscv: add support to block smp in each stageXiang Wang2018-11-054-8/+16
* riscv: add support smp_pause / smp_resumeXiang Wang2018-11-055-1/+144
* arch/x86: clarify raw CAR_GLOBAL access guardsAaron Durbin2018-11-011-2/+2
* arch/x86: allow global .bss objects without CAR_GLOBALAaron Durbin2018-11-012-2/+17
* src: Add missing include <stdint.h>Elyes HAOUAS2018-11-011-0/+2
* src: Add missing include <stdint.h>Elyes HAOUAS2018-10-301-0/+2
* riscv: simplify timer interrupt handlingPhilipp Hug2018-10-301-52/+9
* src/arch/riscv/misaligned.c: Fix an off-by-one error when loading the opcodePhilipp Hug2018-10-301-1/+1
* arch/x86/acpi: Add TPM2 table supportPhilipp Deppenwiese2018-10-262-7/+59
* selfboot: create selfboot_check function, remove check paramRonald G. Minnich2018-10-251-1/+1
* src: Remove unneeded whitespaceElyes HAOUAS2018-10-231-1/+1
* acpi_device: Refine ACPI_IRQ_* macrosFurquan Shaikh2018-10-231-27/+38
* arch/x86: Implement common CF9 resetNico Huber2018-10-224-0/+118
* arch/x86/exception: Improve the readability of a commentJonathan Neuschäfer2018-10-171-2/+2
* libpayload: arm64: Conform to new coreboot lib_helpers.h and assume EL2Julius Werner2018-10-121-0/+4
* selfboot: remove bounce buffersRonald G. Minnich2018-10-117-228/+9
* riscv: add physical memory protection (PMP) supportXiang Wang2018-10-113-0/+355
* Move compiler.h to commonlibNico Huber2018-10-0831-40/+0
* arch/riscv: Update comment about mstatus initializationJonathan Neuschäfer2018-10-062-2/+2
* arch/x86: Make mb/romstage.c optionalRizwan Qureshi2018-10-041-1/+1
* arch/riscv: Adjust compiler flags for scan-buildJonathan Neuschäfer2018-10-041-1/+6
* arch/riscv: Advance the PC after handling misaligned load/storeJonathan Neuschäfer2018-09-261-4/+13
* arch/{mips,power8}/include/arch: Don't use device_tElyes HAOUAS2018-09-212-2/+2
* arch/riscv/include/arch: Don't use device_tElyes HAOUAS2018-09-211-1/+1
* arch/arm/include/armv7/arch: Remove dead codeElyes HAOUAS2018-09-191-10/+0
* acpi: Call acpi_gen_writeSTA by status from device treeHung-Te Lin2018-09-162-0/+10
* riscv: don't write to mstatus.XSXiang Wang2018-09-161-1/+0
* arch/x86/acpi_bert_storage.c: Fix coverity error CID 1395706Richard Spiegel2018-09-151-3/+3
* arch/riscv: Configure delegation only if S-mode is supportedJonathan Neuschäfer2018-09-151-5/+7
* arch/x86/acpigen: Fix comment in _ROM method generatorJonathan Neuschäfer2018-09-141-1/+1
* arch/riscv: Only execute on hart 0 for nowPhilipp Hug2018-09-141-0/+6
* arch/riscv: provide a monotonic timerPhilipp Hug2018-09-145-4/+48
* arch/riscv: add missing endian.h header to io.hPhilipp Hug2018-09-141-0/+1
* complier.h: add __always_inline and use it in code baseAaron Durbin2018-09-1414-56/+75
* riscv: update misaligned memory access exception handlingXiang Wang2018-09-105-68/+652
* riscv: update mtime initializationXiang Wang2018-09-102-3/+4
* x86/acpi: Add BERT tableMarshall Dawson2018-09-072-0/+29
* x86/acpi: Add BERT to the revision tableMarshall Dawson2018-09-071-0/+2
* arch/x86: Add BERT region support functionsMarshall Dawson2018-09-073-0/+714
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-10 00:52:54 +0000