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* arch/x86/acpi_bert_storage: unbreak BERT supportFelix Held2021-06-081-4/+0
| | | | | | | | | | | | | | | | | | | | commit 522e0dbdaa46dde5363ad4c50a11938ae2f17a0d (acpi: Add support for reporting CrashLog in BERT table) broke the BERT support for AMD platforms. [1] is the check in the Linux kernel that failed after that patch. CB:55006 moves the calculations that are needed by the Intel SoC BERT support to the SoC code, so this change shouldn't break it. TEST=When injecting a BERT error Linux on AMD/Mandolin is able to decode and display the error. [1] https://elixir.bootlin.com/linux/v5.12.6/source/drivers/firmware/efi/cper.c#L617 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ic2d2a115f3f2879c3d3a02f3ee8aee82f00f2ac7 Reviewed-on: https://review.coreboot.org/c/coreboot/+/54738 Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* arch/x86/include/bert_storage: introduce bert_should_generate_acpi_tableFelix Held2021-06-081-0/+5
| | | | | | | | | | | | | | | | Since bert_errors_present() is only available when ACPI_BERT is selected the ACPI table generation code needs to check that before calling the function, so add bert_should_generate_acpi_table that returns false when ACPI_BERT isn't selected or the return value of bert_errors_present() when ACPI_BERT is selected. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ia955f627c190ea38e05b5aaedc7cb2d030274e83 Reviewed-on: https://review.coreboot.org/c/coreboot/+/55024 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* arch/x86: Do not call lapicid() without SMPKyösti Mälkki2021-06-071-2/+3
| | | | | | | | | | | The LAPIC may not be enabled or implemented. Change-Id: I2e0f42641ca15d177590d1696475054eda6ce125 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55244 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
* drivers/generic/ioapic: Use arch/x86/ioapicKyösti Mälkki2021-06-072-8/+18
| | | | | | | | | Change-Id: Ibfaf6693288005463e45831fe100a5052e97cf2f Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55185 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* arch/x86/ioapic: Add write_vector() helperKyösti Mälkki2021-06-071-11/+12
| | | | | | | | | Change-Id: I4a44aada7d3dbc016e4044c351534a0d8520f0b2 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55184 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* arch/x86/ioapic: Split some ioapic utility functionsKyösti Mälkki2021-06-071-37/+40
| | | | | | | | | Change-Id: I70dfec900e8ce6630e61bc3fcbcfd88c097a5600 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55183 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* arch/x86/acpi_bert_storage: change return type of bert_errors_presentFelix Held2021-05-302-7/+8
| | | | | | | | | | | | The return value is a boolean, so use the bool type. Also add the types.h header to have the bool type defined. Also change type of bert_region_broken static variable to bool. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I13d6472deeb26ba92d257761df069e32d9b2e5d4 Reviewed-on: https://review.coreboot.org/c/coreboot/+/55023 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
* arch/x86/timestamp.inc: Remove unused fileArthur Heymans2021-05-281-23/+0
| | | | | | | | | | | This is a romcc compiled bootblock leftover. Change-Id: I8d4f8bcdac7e15d60540157e9d2ac98603320977 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55007 Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* option: Introduce `CMOS_LAYOUT_FILE` Kconfig symbolAngel Pons2021-05-181-4/+6
| | | | | | | | | | | | | | | Mainboards with variants may not always use the same cmos.layout file. Turn the hardcoded path into a Kconfig symbol to allow changing it. Tested with BUILD_TIMELESS=1: Without including the config file in the coreboot.rom and with `USE_OPTION_TABLE` selected, building for the Asus P8H61-M PRO produces an identical coreboot image. Change-Id: I4cc622dcb70855c06cb8a816c34406f8421180df Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/54366 Reviewed-by: Martin Roth <martinroth@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* cbfs: Increase mcache size defaultsJulius Werner2021-05-141-2/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The CBFS mcache size default was eyeballed to what should be "hopefully enough" for most users, but some recent Chrome OS devices have already hit the limit. Since most current (and probably all future) x86 chipsets likely have the CAR space to spare, let's just double the size default for all supporting chipsets right now so that we hopefully won't run into these issues again any time soon. The CBFS_MCACHE_RW_PERCENTAGE default for CHROMEOS was set to 25 under the assumption that Chrome OS images have historically always had a lot more files in their RO CBFS than the RW (because l10n assets were only in RO). Unfortunately, this has recently changed with the introduction of updateable assets. While hopefully not that many boards will need these, the whole idea is that you won't know whether you need them yet at the time the RO image is frozen, and mcache layout parameters cannot be changed in an RW update. So better to use the normal 50/50 split on Chrome OS devices going forward so we are prepared for the eventuality of needing RW assets again. The RW percentage should really also be menuconfig-controllable, because this is something the user may want to change on the fly depending on their payload requirements. Move the option to the vboot Kconfigs because it also kinda belongs there anyway and this makes it fit in better in menuconfig. (I haven't made the mcache size menuconfig-controllable because if anyone needs to increase this, they can just override the default in the chipset Kconfig for everyone using that chipset, under the assumption that all boards of that chipset have the same amount of available CAR space and there's no reason not to use up the available space. This seems more in line with how this would work on non-x86 platforms that define this directly in their memlayout.ld.) Also add explicit warnings to both options that they mustn't be changed in an RW update to an older RO image. BUG=b:187561710 Signed-off-by: Julius Werner <jwerner@chromium.org> Change-Id: I046ae18c9db9a5d682384edde303c07e0be9d790 Reviewed-on: https://review.coreboot.org/c/coreboot/+/54146 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
* include/console: Fix duplicate entry of postcode 0x79Subrata Banik2021-05-121-1/+1
| | | | | | | | | | | | Change POST_PRE_HARDWAREMAIN postcode value from 0x79 to 0x6e to avoid duplicate entry. Change-Id: I50cc75cd3097fba3e7faff05188511bba69ef1e7 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/52895 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
* arch/x86/walkcbfs.S: Use FMAP instead of "cbfs master header"Arthur Heymans2021-05-062-25/+6
| | | | | | | | | | | | | | Tested on qemu/i440fx on X86_64: - Page tables are found in cbfs (finding a file works) - returns 0 when a file is not found - works when there is no cbfs file at the start of the FMAP, e.g. with the cbfs master header removed. Change-Id: Ibab657cc40cd5c09c3a73c54950b98ac45a98dbf Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/52879 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* arch/x86: Always include walkcbfs.SArthur Heymans2021-05-061-1/+1
| | | | | | | | | | Let the linker decide if this code is needed. Change-Id: I26fb19d461db39ce554af7b948f0d10a12920299 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/52940 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
* arch/x86: Fix building with CONFIG_VBOOT_SEPARATE_VERSTAGE=nArthur Heymans2021-05-041-1/+1
| | | | | | | | | | | | TESTED on qemu/i440fx with VBOOT_SEPARATE_VERSTAGE commented out. Change-Id: I1227feab9ffbbc06e614f297be44fb67f13bda42 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/52784 Reviewed-by: Patrick Rudolph <siro@das-labor.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* arch/x86/smbios: Let SMBIOS type 9 be able to write slot IDJingleHsuWiwynn2021-04-221-1/+3
| | | | | | | | | | | | | | | | The slot ID can be passed in from the function caller but parsing slot ID from devicetree is not yet supported and would still be 0. Add Slot ID in SMBIOS type 9 for Delta Lake. Tested=Execute "dmidecode -t 9" to verify. Signed-off-by: JingleHsuWiwynn <jingle_hsu@wiwynn.com> Change-Id: I9bf2e3b1232637a25ee595d08f8fbbc2283fcd5d Reviewed-on: https://review.coreboot.org/c/coreboot/+/49917 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
* ChromeOS: Use CHROMEOS_NVS guardKyösti Mälkki2021-04-211-1/+1
| | | | | | | | | | | | | | | | | | | Replace CONFIG(CHROMEOS) with CONFIG(CHROMEOS_NVS) for cases where the conditional and dependency are clearly about the presence of an ACPI NVS table specified by vendorcode. For couple locations also CONFIG(HAVE_ACPI_TABLES) changes to CONFIG(CHROMEOS_NVS). This also helps find some of the CONFIG(CHROMEOS) cases that might be more FMAP and VPD related and not about ChromeOS per-se, as suggested by followup works. Change-Id: Ife888ae43093949bb2d3e397565033037396f434 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50611 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Lance Zhao Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* *x86: Support x2apic modeWonkyu Kim2021-04-151-11/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | Implement x2apic mode as existing code only supports apic mode. Use info from LAPIC_BASE_MSR (LAPIC_BASE_MSR_X2APIC_MODE) to check if apic mode or x2apic mode and implement x2apic mode according to x2apic specfication. Reference: https://software.intel.com/content/www/us/en/develop/download/intel-64-architecture-x2apic-specification.html BUG=None BRANCH=None TEST=boot to OS and check apic mode cat /proc/cpuinfo | grep "apicid" ex) can see apicid bigger than 255 apicid : 256 apicid : 260 Signed-off-by: Wonkyu Kim <wonkyu.kim@intel.com> Change-Id: I0bb729b0521fb9dc38b7981014755daeaf9ca817 Reviewed-on: https://review.coreboot.org/c/coreboot/+/51723 Reviewed-by: Ravishankar Sarawadi <ravishankar.sarawadi@intel.com> Reviewed-by: Jamie Ryu <jamie.m.ryu@intel.com> Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* arch/x86: Provide readXp/writeXp helpers in arch/mmio.hAngel Pons2021-04-061-0/+40
| | | | | | | | | | | | | | | These p-suffixed helpers allow dropping pointer casts in call-sites, which is particularly useful when accessing registers at an offset from a base address. Move existing helpers in chipset code to arch/mmio.h and create the rest accordingly. Change-Id: I36a015456f7b0af1f1bf2fdff9e1ccd1e3b11747 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51862 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Patrick Rudolph <siro@das-labor.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* cbfs: Remove prog_locate() for payloads (SELF and FIT)Julius Werner2021-03-172-6/+0
| | | | | | | | | | | This patch removes the prog_locate() call for all instances of loading payload formats (SELF and FIT), as the previous patch did for stages. Signed-off-by: Julius Werner <jwerner@chromium.org> Change-Id: I582b37f36fe6f9f26975490a823e85b130ba49a2 Reviewed-on: https://review.coreboot.org/c/coreboot/+/49336 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* cbfs: Remove prog_locate() for stages and rmodulesJulius Werner2021-03-163-9/+3
| | | | | | | | | | | | | | | | | | | | | | | | | This patch removes the prog_locate() step for stages and rmodules. Instead, the stage and rmodule loading functions will now perform the locate step directly together with the actual loading. The long-term goal of this is to eliminate prog_locate() (and the rdev member in struct prog that it fills) completely in order to make CBFS verification code safer and its security guarantees easier to follow. prog_locate() is the main remaining use case where a raw rdev of CBFS file data "leaks" out of cbfs.c into other code, and that other code needs to manually make sure that the contents of the rdev get verified during loading. By eliminating this step and moving all code that directly deals with file data into cbfs.c, we can concentrate the code that needs to worry about file data hashing (and needs access to cbfs_private.h APIs) into one file, making it easier to keep track of and reason about. This patch is the first step of this move, later patches will do the same for SELFs and other program types. Signed-off-by: Julius Werner <jwerner@chromium.org> Change-Id: Ia600e55f77c2549a00e2606f09befc1f92594a3a Reviewed-on: https://review.coreboot.org/c/coreboot/+/49335 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* arch/x86/smbios_defaults.c: Default to motherboard typeAngel Pons2021-03-121-1/+1
| | | | | | | | | | | | | Nearly every board that coreboot supports is a motherboard. Change-Id: I1419874a0ba3f2e21568fa4b07b88f2048d10203 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50180 Reviewed-by: Jonathan Zhang <jonzhang@fb.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Felix Singer <felixsinger@posteo.net> Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* mb/ocp/deltalake: Fill ECC type in romstageAngel Pons2021-03-011-6/+1
| | | | | | | | | | | | | | Fill the ECC type in `struct memory_info` in romstage, and in SoC code. The SMBIOS override is unnecessary, and this is not mainboard-specific. Change-Id: I8370b3ee7d75914b895946b53923598adf87b522 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50179 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Johnny Lin <Johnny_Lin@wiwynn.com> Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-by: Jonathan Zhang <jonzhang@fb.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* memory_info.h: Store SMBIOS error correction typeAngel Pons2021-03-011-2/+1
| | | | | | | | | | | | | | | | There are platforms that support error correction types other than single-bit ECC. Extend meminfo to accomodate additional ECC types. It is assumed that `struct memory_info` is packed to save space. Thus, use `uint8_t` instead of an enum type (which are usually 4 bytes wide). Change-Id: I863f8e34c84841d931dfb8d7067af0f12a437e36 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50178 Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* arch/x86/smbios: Update SMBIOS type 17 asset tagTim Chu2021-02-272-0/+10
| | | | | | | | | | | | | Add SMBIOS type 17 asset tag. Use dimm locator as default value. Tested=Execute "dmidecode -t 17" to check asset tag field is correct. Signed-off-by: Tim Chu <Tim.Chu@quantatw.com> Change-Id: I323e6b4cf6b11ede253d5a2a4bfc976a3f432b05 Reviewed-on: https://review.coreboot.org/c/coreboot/+/48886 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jonathan Zhang <jonzhang@fb.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
* arch/arm/armv7/thread.c: Remove stale fileAngel Pons2021-02-221-110/+0
| | | | | | | | | | This file is never built. Plus, `CONFIG_STACK_BOTTOM` does not exist. Change-Id: I111b20e3443dca701ee8666d44261a00a161d83f Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50909 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
* memlayout: Store region sizes as separate symbolsJulius Werner2021-02-192-12/+7
| | | | | | | | | | | | | | | | This patch changes the memlayout macro infrastructure so that the size of a region "xxx" (i.e. the distance between the symbols _xxx and _exxx) is stored in a separate _xxx_size symbol. This has the advantage that region sizes can be used inside static initializers, and also saves an extra subtraction at runtime. Since linker symbols can only be treated as addresses (not as raw integers) by C, retain the REGION_SIZE() accessor macro to hide the necessary typecast. Signed-off-by: Julius Werner <jwerner@chromium.org> Change-Id: Ifd89708ca9bd3937d0db7308959231106a6aa373 Reviewed-on: https://review.coreboot.org/c/coreboot/+/49332 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
* device/dram: Move SPD manufacturer names out of arch/x86Patrick Rudolph2021-02-161-35/+2
| | | | | | | | | | | Move SPD manufacturer ID decoding to device/dram. Will be used by the following patch outside of SMBIOS scope as well. Change-Id: Iec175cd6ab1d20761da955785e4bc0e87ae02dbb Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50544 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
* src: use ARRAY_SIZE where possiblePatrick Georgi2021-02-151-1/+1
| | | | | | | | | | | | | Generated with a variant of https://coccinelle.gitlabpages.inria.fr/website/rules/array.cocci Change-Id: I083704fd48faeb6c67bba3367fbcfe554a9f7c66 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50594 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* src/arch: Remove unused <console/console.h>Elyes HAOUAS2021-02-152-2/+0
| | | | | | | | Change-Id: Idb80b21bb5dc4b461f89a3414d51b7d98a8328d8 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50521 Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* arch/x86: Drop `cstates` pointer from CPU driversAngel Pons2021-02-141-1/+0
| | | | | | | | | | Nothing uses this pointer anymore. Change-Id: Id2dee8f4cb243114d6f7f7485402acb9b73b7900 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49808 Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* arch/x86/id.S: Remove unneeded whitespace before tabElyes HAOUAS2021-02-111-2/+2
| | | | | | | | | Change-Id: I053a2a8cff3fda1a1074f74e4d4c174a0cb24d86 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50429 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Frans Hendriks <fhendriks@eltan.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
* acpi: Fix Coverity Scan reportLijian Zhao2021-02-101-1/+1
| | | | | | | | | | | | | | | | Fix the issue that return value "r" in line 534 will get overwritten problem. BUG=CID 1445995 TEST=Build sucessful and boot up in QEMU Signed-off-by: Lijian Zhao <lijian.zhao@intel.com> Change-Id: Icf760b142cfecfed7c929c15ad190ac74df027b1 Reviewed-on: https://review.coreboot.org/c/coreboot/+/50352 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Francois Toguo Fotso <francois.toguo.fotso@intel.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
* arch/x86/cpu.c: Remove redundant <arch/cpu.h>Elyes HAOUAS2021-02-071-1/+0
| | | | | | | | | | <arch/cpu.h> is chain included through <cpu/cpu.h>. Change-Id: Iad7f23080814c6606603d9472a1bd34a6b1bd1a9 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50304 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* acpi: Fix BERT size_t printf format errorBenjamin Doron2021-02-071-1/+1
| | | | | | | | | | | | Fix compilation on GCC 10.2.1 and address the underlying issue. The printf format specifier for a size_t type is z. Change-Id: Ieb1db6c0c3eb4947bd3617e418bac238b70ec08f Signed-off-by: Benjamin Doron <benjamin.doron00@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50051 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
* src: Remove redundant include <rules.h>Elyes HAOUAS2021-02-071-1/+0
| | | | | | | | | Change-Id: Ie4692246d059734bb5bad6c64042b64068636ab6 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50300 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
* arch/x86/smbios: Add missing guardRaul E Rangel2021-02-071-1/+1
| | | | | | | | | | smbios_type0_bios_version is only defined if HAVE_ACPI_TABLES is set. Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: I626ab954496833f46d6a785d92cc3b7e7d87e165 Reviewed-on: https://review.coreboot.org/c/coreboot/+/50340 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
* intel: Rename config FSP_USES_MP_SERVICES_PPI to MP_SERVICES_PPIFurquan Shaikh2021-02-062-2/+2
| | | | | | | | | | | | | | | | This change renames config FSP_USES_MP_SERVICES_PPI to MP_SERVICES_PPI in preparation to allow V1 and V2 versions of MP services PPI. TEST=Verified that timeless build for brya, volteer, icelake_rvp, elkhartlake_crb and waddledee shows no change in generated coreboot.rom Change-Id: I04acf1bc3a3739b31d6e9d01b6aa97542378754f Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50275 Reviewed-by: Aamir Bohra <aamir.bohra@intel.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Subrata Banik <subrata.banik@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* arch/x86/smbios: Correct SMBIOS type 4 max speedTim Chu2021-02-051-2/+3
| | | | | | | | | | | | | | | | Now smbios type 4 max speed field will use the maximum speed of processor itself if CPUID value can be accessed. However, this field should be the maximum processor speed supported by the system. Here we use smbios_cpu_get_max_speed_mhz only to get correct value. Tested=Execute "dmidecode -t 4" to check max speed is correct. Signed-off-by: Tim Chu <Tim.Chu@quantatw.com> Change-Id: Iae8e01a5e455709a57d60a840f279685c8aab80f Reviewed-on: https://review.coreboot.org/c/coreboot/+/48636 Reviewed-by: Patrick Rudolph <siro@das-labor.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* acpi: Add support for reporting CrashLog in BERT tableFrancois Toguo2021-02-042-0/+52
| | | | | | | | | | | | | | Crash Data are collected and sent to the OS via the ACPI BERT. BUG=None TEST=Built, and BERT successfully generated in the crashLog flow. Signed-off-by: Francois Toguo <francois.toguo.fotso@intel.com> Change-Id: I00e390d735d61beac2e89a726e39119d9b06b3df Signed-off-by: Nikunj A. Dadhania <nikunj.dadhania@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49799 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
* src: Remove useless comments in "includes" linesElyes HAOUAS2021-02-041-1/+1
| | | | | | | | Change-Id: Ide5673dc99688422c5078c8c28ca5935fd39c854 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50186 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
* arch/x86/smbios: Add Number Of Power Cords field to be overridenJingleHsuWiwynn2021-02-012-0/+6
| | | | | | | | | | | | For SMBIOS type 3, add function to override number of power cords Tested=Exectute dmidecode -t 3 to verify. Signed-off-by: JingleHsuWiwynn <jingle_hsu@wiwynn.com> Change-Id: I7dee3a944a49ffcfdc2f4408d92a17aa39761bb0 Reviewed-on: https://review.coreboot.org/c/coreboot/+/50015 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
* stage_cache: Add resume_from_stage_cache()Kyösti Mälkki2021-01-291-3/+1
| | | | | | | | | | | Factor out the condition when an attempt to load stage from cache can be tried. Change-Id: I936f07bed6fc82f46118d217f1fd233e2e041405 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50000 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
* arch/x86/smbios: Update SMBIOS type 16 Extended Maximum CapacityTim Chu2021-01-281-1/+8
| | | | | | | | | | | | | Update Extended Maximum Capacity field in SMBIOS type 16 so that maximum dimm size can be over 2TB. Tested=Execute "dmidecode -t 16" to check maximum capacity is over 2TB. Signed-off-by: Tim Chu <Tim.Chu@quantatw.com> Change-Id: I61901c815f9d0daae102e5077a116c0de87240ef Reviewed-on: https://review.coreboot.org/c/coreboot/+/49828 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
* arch/x86: Remove most C_ENV_BOOTBLOCK_SIZE limitsKyösti Mälkki2021-01-281-2/+5
| | | | | | | | | | | | With top-aligned bootblock this is no longer globally needed. The default maximum is now a generous 256 KiB with couple platforms having lower limits of 32 KiB and 64 KiB. Change-Id: Ib1aee44908c0dcbc17978d3ee53bd05a6200410c Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47600 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
* arch/x86: Top-align .text in bootblockKyösti Mälkki2021-01-282-0/+18
| | | | | | | | | | | Move .text section closer to .init. This reduces the size of the flat bootblock binary and footprint in CBFS. Change-Id: I64325bd633e1104853cfb928c7f801d94ff3045a Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47971 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
* arch/x86: Top-align .init in bootblockKyösti Mälkki2021-01-282-4/+30
| | | | | | | | | | | | Link .init section near the end of bootblock program. It contains _start16bit, gdtptr and gdt that must be addressable from realmode, thus within top 64 KiB. Change-Id: If7b9737650362ac7cd82685cfdfaf18bd2429238 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47970 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
* cpu/x86: Link entry32.incKyösti Mälkki2021-01-282-55/+0
| | | | | | | | | Change-Id: Ib475f40f950f8cc54f0e3c50a80970ba3d2b628f Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47969 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
* cpu/x86: Link reset16.incKyösti Mälkki2021-01-281-1/+0
| | | | | | | | Change-Id: If2caab67286cf77e37928e03be4f581070e771d8 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47968 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* cpu/x86: Link entry16.incKyösti Mälkki2021-01-281-2/+1
| | | | | | | | | Change-Id: I78ecd15716169b58cf6696ff8c5069ac2d5038ef Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47967 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* arch/x86/car.ld: Fix up blob reserved regionsAngel Pons2021-01-261-2/+0
| | | | | | | | | | | | | | | | | | Drop duplicated assignment that rewound `.` back, and broke platforms using MRC.bin and DCACHE_RAM_MRC_VAR_SIZE. Tested on out-of-tree Acer E5-573 (Broadwell), fixes booting. Also tested on Asrock B85M Pro4 (Haswell), also fixes booting. Change-Id: I3f0153f776c07acf7cf92808b677b118c60507c3 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49909 Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
generated by cgit v1.2.3 (git 2.25.1) at 2024-08-17 21:41:41 +0000