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* drivers/smbus: initialize SC16IS7XX I2C to UART converter chipHusni Faiz2022-10-031-0/+15
| | | | | | | | | | | | | This patch adds the functionality to initialize the sc16is750 i2c to uart converter chip with a 14.7MHz input clock to support 115200 baud rate. Change-Id: Ib31188b8c0f9b0ce9454da984e630eca9101d145 Signed-off-by: Husni Faiz <ahamedhusni73@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/67342 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <inforichland@gmail.com> Reviewed-by: Raul Rangel <rrangel@chromium.org>
* drivers/smbus: add smbus console driverHusni Faiz2022-09-161-0/+24
| | | | | | | | | | | This patch adds a new smbus console driver and Kconfig options to enable the driver. Change-Id: Ife77fb2c3e1cc77678a4972701317d50624ceb95 Signed-off-by: Husni Faiz <ahamedhusni73@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/67339 Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* console: Make CONSOLE_SPI_FLASH depend on BOOT_DEVICE_SPI_FLASHArthur Heymans2022-04-271-0/+1
| | | | | | | | | | Change-Id: Ibfdbca02259a723029260dfea9f36b325414b7d3 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/52793 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Christian Walter <christian.walter@9elements.com>
* src/console/Kconfig: Add option to disable loglevel prefixIgor Bagnucki2022-03-301-0/+9
| | | | | | | | | | | | | | | | | | | | | | | This patch adds an option to disable loglevel prefixes. This patch helps to achieve clear messages when low loglevel is used and very few messages are displayed on a terminal. This option also allows to maintain compatibility with log readers and continuous integration systems that depend on fixed log content. If the code contains: printk(BIOS_DEBUG, "This is a debug message!\n") it will show as: [DEBUG] This is a debug message! but if the Kconfig contains: CONFIG_CONSOLE_USE_LOGLEVEL_PREFIX=n the same message will show up as This is a debug message! Signed-off-by: Igor Bagnucki <igor.bagnucki@3mdeb.com> Change-Id: I911bb601cf1933a4c6498b2ae1e4cb4d4bc85621 Reviewed-on: https://review.coreboot.org/c/coreboot/+/63144 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
* console: Add ANSI escape sequences for highlightingJulius Werner2022-02-071-0/+9
| | | | | | | | | | | | | | | | | | | | | | | | | | This patch adds ANSI escape sequences to highlight a log line based on its loglevel to the output of "interactive" consoles that are meant to be displayed on a terminal (e.g. UART). This should help make errors and warnings stand out better among the usual spew of debug messages. For users whose terminal or use case doesn't support these sequences for some reason (or who simply don't like them), they can be disabled with a Kconfig. While ANSI escape sequences can be used to add color, minicom (the presumably most common terminal emulator for UART endpoints?) doesn't support color output unless explicitly enabled (via -c command line flag), and other terminal emulators may have similar restrictions, so in an effort to make this as widely useful by default as possible I have chosen not to use color codes and implement this highlighting via bolding, underlining and inverting alone (which seem to go through in all cases). If desired, support for separate color highlighting could be added via Kconfig later. Signed-off-by: Julius Werner <jwerner@chromium.org> Change-Id: I868f4026918bc0e967c32e14bcf3ac05816415e8 Reviewed-on: https://review.coreboot.org/c/coreboot/+/61307 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
* lib/cbmem_console,console: Resurrect CONSOLE_CBMEM_DUMP_TO_UARTRaul E Rangel2022-01-251-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Chromebooks normally run with non-serial enabled firmware because writing to the UART console is very slow. This unfortunately makes debugging boot errors more difficult. We tend to rely on port 80s and/or the vboot recovery code. When CONSOLE_CBMEM_DUMP_TO_UART is selected it will dump the entire cbmem console to the UART whenever `vboot_reboot()` is called. We don't incur any boot time penalty in the happy path, but still retain the ability to access the logs when an error occurs. The previous implementation was using a hard coded UART index and `get_uart_baudrate` was always returning 0 since `CONFIG_TTYS0_BAUD` wasn't defined. This change makes it so the UART console properties are available when CONSOLE_CBMEM_DUMP_TO_UART is set. This results in the following .config diff: +CONFIG_UART_FOR_CONSOLE=0 +CONFIG_TTYS0_BASE=0x3f8 +CONFIG_TTYS0_LCS=3 +CONFIG_CONSOLE_SERIAL_115200=y +CONFIG_TTYS0_BAUD=115200 This functionality is especially helpful on Guybrush. PSP Verstage is run on S0i3 resume. Today, if there is an error, the cbmem console is lost since it lives in the PSP SRAM. BUG=b:213828947, b:215599230 TEST=Build non-serial guybrush FW and verify no serial output happens in happy path. Inject a vboot error and perform an S0i3 suspend/resume. Verify CBMEM console gets dumped to the correct UART. Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: I997942204603362e51876a9ae25e493fe527437b Reviewed-on: https://review.coreboot.org/c/coreboot/+/61305 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
* console: Add Kconfig to dump pre-bootblock cbmem contentsRaul E Rangel2022-01-171-0/+8
| | | | | | | | | | | | | | | | | | | | | | | Pre-bootblock stages (i.e., VBOOT_STARTS_BEFORE_BOOTBLOCK) might not have the ability to log to the UART, so their console messages are inaccessible until the boot processes gets into the payload or OS. This makes it difficult to debug verstage. This feature will dump the pre-bootblock CBMEM console immediately after the bootblock console is initialized. I chose to do this in console_init instead of bootblock_soc_init because I wanted to have the pre-bootblock contents dumped before the coreboot bootblock starting message is printed. BUG=b:213828947 TEST=Boot guybrush with PSP verstage and verify verstage logs are dumped to the UART. Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: I363c93ef3ee6c5c303a6a68f88a622e2aa62594c Reviewed-on: https://review.coreboot.org/c/coreboot/+/61012 Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* src/acpi to src/lib: Fix spelling errorsMartin Roth2021-10-051-1/+1
| | | | | | | | | | | | These issues were found and fixed by codespell, a useful tool for finding spelling errors. Signed-off-by: Martin Roth <martin@coreboot.org> Change-Id: I5b8ecdfe75d99028fee820a2034466a8ad1c5e63 Reviewed-on: https://review.coreboot.org/c/coreboot/+/58080 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* Asm code: Use NO_EARLY_BOOTBLOCK_POSTCODES to remove Asm port80sMartin Roth2021-06-251-4/+6
| | | | | | | | | | | | | | | | | Expand NO_EARLY_BOOTBLOCK_POSTCODES to all of the early assembly code in bootblock. BUG=b:191370340 TEST: Build with & without the option enabled Signed-off-by: Martin Roth <martinroth@chromium.org> Change-Id: Idb4a96820d5c391fc17a0f0dcccd519d4881b78c Reviewed-on: https://review.coreboot.org/c/coreboot/+/55731 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
* console: Override uart base addressBryant Ou2020-11-091-0/+10
| | | | | | | | | | | | | Add a new CONFIG_OVERRIDE_UART_FOR_CONSOLE token to override the index of uart port, platform use a get_uart_for_console routine to decide what index value should be used for console. Signed-off-by: Bryant Ou <Bryant.Ou.Q@gmail.com> Change-Id: I2079bd1e5ffa209553383b6aafe3b8724849ba2a Reviewed-on: https://review.coreboot.org/c/coreboot/+/45405 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marc Jones <marc@marcjonesconsulting.com> Reviewed-by: Jonathan Zhang <jonzhang@fb.com>
* src: Rename EM100Pro-specific SPI console Kconfig optionAngel Pons2020-10-131-3/+3
| | | | | | | | | | | | To avoid confusion with `flashconsole` (CONSOLE_SPI_FLASH), prefix this option with `EM100Pro`. Looks like it is not build-tested, however. Change-Id: I4868fa52250fbbf43e328dfd12e0e48fc58c4234 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45973 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
* ec/system76: Add console supportJeremy Soller2020-09-071-0/+7
| | | | | | | | | | | | | | | | | | | This adds support for line-buffered console output to System76 EC firmware. Once the print command is received, the EC firmware multiplexes the output to any enabled console on the EC. This can be a memory ringbuffer, a parallel port (using the keyboard connector), or i2c (using the battery connector). Once the entire buffer is sent, it sets the command register to 0, indicating completion. For more information, please see: https://github.com/system76/ec/blob/master/doc/debugging.md Tested on system76/lemp9 with CONSOLE_SYSTEM76_EC enabled. Signed-off-by: Jeremy Soller <jeremy@system76.com> Change-Id: I861bf3e22f40dd6c3ec7ba1d73711b399358e332 Reviewed-on: https://review.coreboot.org/c/coreboot/+/43718 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michael Niewöhner
* drivers/pc80/rtc: Drop CMOS_POST_EXTRA optionKyösti Mälkki2020-04-201-8/+0
| | | | | | | | Change-Id: I379a5664776624600ff1c2919bffa77c877d87ab Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38191 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
* treewide: Replace BOARD_EMULATION_QEMU_X86Angel Pons2020-03-031-1/+1
| | | | | | | | | | | It is equivalent to the CPU_QEMU_X86 symbol. Change-Id: Ic16233e3d80bab62cc97fd075bdcca1780a6a2b5 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39182 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
* arch/x86: Drop uses of ROMCC_BOOTBLOCKArthur Heymans2019-12-191-1/+1
| | | | | | | | | Change-Id: Ia0405fdd448cb31b3c6ca3b3d76e49e9f430bf74 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37339 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
* AGESA,binaryPI: Move PORT80 selection to C bootblockKyösti Mälkki2019-12-091-0/+5
| | | | | | | | | | | | | | | | Because the function is implemented in C, post_code() calls from cache_as_ram.S and other early assembly entry files may not currently work for cold boots. Assembly implementation needs to follow one day. This effectively removes PORT80 routing from boards with ROMCC_BOOTBLOCK. Change-Id: I71aa94b33bd6f65e243724810472a440e98e0750 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37451 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com>
* Kconfig: Drop the C_ENVIRONMENT_BOOTBLOCK symbolArthur Heymans2019-11-251-1/+1
| | | | | | | | | | | | | | | The romcc bootblock will be deprecated soon and most platforms use C_ENVIRONMENT_BOOTBLOCK already. This patch drops the CONFIG_C_ENVIRONMENT_BOOTBLOCK symbol and adds CONFIG_ROMCC_BOOTBLOCK where needed. Change-Id: I773a76aade623303b7cd95ebe9b0411e5a7ecbaf Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37154 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com>
* Kconfig: comply to Linux 5.3's Kconfig language rulesPatrick Georgi2019-11-231-2/+2
| | | | | | | | | | | Kconfig became stricter on what it accepts, so accomodate before updating to a new release. Change-Id: I92a9e9bf0d557a7532ba533cd7776c48f2488f91 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37156 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
* console/kconfig: Move ONBOARD_VGA_IS_PRIMARY to 'devices'Arthur Heymans2019-11-011-7/+0
| | | | | | | | | | | | | This has nothing to do with console options. This also improves the help text to reflect what it actually does. Change-Id: I039f4f6bbe144769d6a362192b225838ed3d9d43 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32042 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
* arch/x86: Enable POSTCAR_CONSOLE by defaultKyösti Mälkki2019-08-111-1/+1
| | | | | | | | | | | | | Almost all platforms force it on. Make it enabled by default but under user control to optionally disable it. Change-Id: I6b0f19c8bfd6ffed93023d57a1d28ca6acc06835 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34803 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Martin Roth <martinroth@google.com>
* console/Kconfig - only print UART addresses for I/O based UARTsMartin Roth2019-07-131-4/+4
| | | | | | | | | | | It doesn't make sense to print these values for memory-mapped UARTs. Change-Id: Ie2d9cf95f0b0fdcf601e74de799b1390c08f2335 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34247 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
* soc/samsung/exynos5420: Disable BOOTBLOCK_CONSOLENico Huber2019-01-161-1/+4
| | | | | | | | | | | | | Add a new Kconfig NO_BOOTBLOCK_CONSOLE to disable the BOOTBLOCK_CONSOLE option completely. The commit message of fbb11cf (ARM: Separate the early console (romstage) from the bootblock console.) states that it doesn't work before romstage on Exynos 5420. Change-Id: I9b56a52f2555b5233300f27031a9ef50e7ab7cea Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/c/30926 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
* console: Change BOOTBLOCK_CONSOLE default to `y`Nico Huber2019-01-141-1/+1
| | | | | | | | | | | | | | | | Invert the default instead of selecting it everywhere. Restores the ability to use its Kconfig prompt. Beside Qemu targets, the only platforms that didn't select it seem to be samsung/exynos5420, intel/cannonlake, and intel/icelake. The latter two were about to be patched anyway. Change-Id: I7c5b671b7dddb5c6535c97c2cbb5f5053909dc64 Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/c/30891 Reviewed-by: Lijian Zhao <lijian.zhao@intel.com> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* console/Kconfig: Fix dependency of FIXED_UART_FOR_CONSOLENico Huber2019-01-111-7/+7
| | | | | | | | | | | | | | | | | | The Kconfig declaration for FIXED_UART_FOR_CONSOLE was accidentally placed inside an `if CONSOLE_SERIAL` in a96e66a (soc/intel: Clean mess around UART_DEBUG). TEST=Start a clean config, select intel/leafhill and disable serial console. Confirm that config can be saved without error. Change-Id: Ie41687e91af11a13697cbe25938dada2c74b40fb Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/c/30829 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
* soc/intel: Clean mess around UART_DEBUGNico Huber2019-01-091-1/+9
| | | | | | | | | | | | | | | | | | Everything is wrong here, the Kconfig symbols are only the tip of the iceberg. Based on Kconfig prompts the SoC code performed pad configu- rations! I don't see why the person who configures coreboot should have the board schematics at hand. As a mitigation, we remove the prompts for UART_DEBUG, which is renamed to INTEL_LPSS_UART_FOR_CONSOLE (because the former didn't really say what it's about), and for UART_FOR_CONSOLE in case the former is selec- ted. Change-Id: Ibe2ed3cab0bb04bb23989c22da45299f088c758b Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/c/29573 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
* (console,drivers/uart)/Kconfig: Fix dependenciesNico Huber2018-11-211-1/+1
| | | | | | | | | | | | | | | | | | | The dependencies of CONSOLE_SERIAL and DRIVERS_UART were somehow backwards. Fix that. Now, CONSOLE_SERIAL depends on DRIVERS_UART, because it's using its interface. The individual UART drivers select DRIVERS_UART, because they implement the interface and depend on the common UART code. Some guards had to be fixed (using CONSOLE_SERIAL now instead of DRIVERS_UART). Some other guards that were only about compilation of units were removed. We want to build test as much as possible, right? Change-Id: I0ea73a8909f07202b23c88db93df74cf9dc8abf9 Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/c/29572 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
* console: Set default loglevel to 8 (SPEW) for CONFIG_CHROMEOSJulius Werner2018-10-181-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | CB:26053 changed coreboot's default loglevel from SPEW to DEBUG. This may be the most reasonable choice for most users that are mostly interested in the UART console. However, on Chrome OS devices the UART is disabled for production configurations anyway, and instead they rely heavily on the CBMEM console for remote debugging and bug reports. For these kinds of cases more info is almost always better, and you can't easily reproduce a remotely filed bug if you notice that you need some info that is only provided by BIOS_SPEW. On the other hand, the cost of logging extra info to the CBMEM console is pretty negligible. Therefore, let's bump the loglevel for CONFIG_CHROMEOS in particular back up to the maximum. (Unfortunately, it seems that you can't 'select' a choice option from another option, so this has to go in the console/Kconfig file.) Change-Id: I50724e3f7f8f57fdbc5846f21babc71798b21b65 Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/29144 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
* console: Enable CONSOLE_USB by defaultNico Huber2018-10-041-1/+1
| | | | | | | | | | | | | It seems to be the only user of the USB debug driver. So having to enable it separately seems wrong. It still depends on the selection of the EHCI debug driver. Change-Id: I5f5f38a912423d9b8f1e71ae875b6a14fdee651c Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/28892 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
* console: Reduce default loglevel to DEBUGNico Huber2018-05-081-1/+1
| | | | | | | | | | | | | | | | | | | The former default SPEW is very noisy, intentionally. It is usually only useful to debug specific issues and doesn't carry much infor- mational value. Reducing the loglevel should also mitigate overflows in pre-CBMEM console buffers. Change-Id: Iebcd4681572c58f1d17085c5ef01a2dd49e981ca Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: https://review.coreboot.org/26053 Reviewed-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-by: Angel Pons Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* console: Introduce a way for mainboard to override the loglevelJulien Viard de Galbert2018-02-231-0/+10
| | | | | | | | | | | | | | | | | | This change adds a config option to allow mainboard to override the console loglevel. When the option is set, the platform has to define the function get_console_loglevel returning a valid loglevel value. This allows a mainboard to sample a GPIO to switch the loglevel value between different environments (qualification vs production) without re-flashing. Change-Id: Id6cc72b8fe5c4c50a6f83ce80e6440b078eec6e2 Signed-off-by: Julien Viard de Galbert <jviarddegalbert@online.net> Reviewed-on: https://review.coreboot.org/23712 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Nico Huber <nico.h@gmx.de>
* driver/uart: Introduce a way for mainboard to override the baudrateJulien Viard de Galbert2018-02-211-0/+10
| | | | | | | | | | | | | | | The rationale is to allow the mainboard to override the default baudrate for instance by sampling GPIOs at boot. A new configuration option is available for mainboards to select this behaviour. It will then have to define the function get_uart_baudrate to return the computed baudrate. Change-Id: I970ee788bf90b9e1a8c6ccdc5eee8029d9af0ecc Signed-off-by: Julien Viard de Galbert <jviarddegalbert@online.net> Reviewed-on: https://review.coreboot.org/23713 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
* console/flashsconsole: Add spi flash console for debuggingYouness Alaoui2017-06-041-0/+31
| | | | | | | | | | | | | | | | | | | | | | | | | | | If CONSOLE_SPI_FLASH config is enabled, we write the cbmem messages to the 'CONSOLE' area in FMAP which allows us to grab the log when we read the flash. This is useful when you don't have usb debugging, and UART lines are hard to find. Since a failure to boot would require a hardware flasher anyways, we can get the log at the same time. This feature should only be used when no alternative is found and only when we can't boot the system, because excessive writes to the flash is not recommended. This has been tested on purism/librem13 v2 and librem 15 v3 which run Intel Skylake hardware. It has not been tested on other archs or with a driver other than the fast_spi. Change-Id: I74a297b94f6881d8c27cbe5168f161d8331c3df3 Signed-off-by: Youness Alaoui <youness.alaoui@puri.sm> Reviewed-on: https://review.coreboot.org/19849 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-by: Philippe Mathieu-Daudé <philippe.mathieu.daude@gmail.com>
* Hook up libhwbase in ramstageNico Huber2016-11-291-0/+9
| | | | | | | | | | | | | | | | It's hidden behind a configuration option `CONFIG_RAMSTAGE_LIBHWBASE`. This also adds some glue code to use the coreboot console for debug output and our monotonic timer framework as timer backend. v2: Also update 3rdparty/libhwbase to the latest master commit. Change-Id: I8e8d50271b46aac1141f95ab55ad323ac0889a8d Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: https://review.coreboot.org/16951 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
* Revert "[WIP] console/Kconfig: Calculate COM port base addresses only on x86"Ronald G. Minnich2016-10-181-2/+0
| | | | | | | | | | | | This reverts commit 2c8f3bd91b54e85b4d2e24894ee8bbbfb9ad8a31. I mistakenly commited a WIP, sorry. Change-Id: I3c66c688dbfd903ecf5303abcdf6b5ded84585c7 Reviewed-on: https://review.coreboot.org/17028 Tested-by: build bot (Jenkins) Reviewed-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net> Reviewed-by: Nico Huber <nico.h@gmx.de>
* [WIP] console/Kconfig: Calculate COM port base addresses only on x86Jonathan Neuschäfer2016-10-151-0/+2
| | | | | | | | | | | | | On other architectures, the serial ports aren't mapped at 0x3f8. WIP: I'm not sure how exactly the dependency should be encoded in Kconfig. Change-Id: Ia1de545325a53607f62d08e76b2f61b25edbe6ef Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net> Reviewed-on: https://review.coreboot.org/16982 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
* Kconfig: Update default hex values to start with 0xMartin Roth2016-10-021-1/+1
| | | | | | | | | | | | | | | Kconfig hex values don't need to be in quotes, and should start with '0x'. If the default value isn't set this way, Kconfig will add the 0x to the start, and the entry can be added unnecessarily to the defconfig since it's "different" than what was set by the default. A check for this has been added to the Kconfig lint tool. Change-Id: I86f37340682771700011b6285e4b4af41b7e9968 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/16834 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
* arch/x86: Enable postcar consoleLee Leahy2016-08-011-0/+7
| | | | | | | | | | | | | | Add a Kconfig value to enable the console during postcar. Add a call to console_init at the beginning of the postcar stage in exit_car.S. TEST=Build and run on Galileo Gen2 Change-Id: I66e2ec83344129ede2c7d6e5627c8062e28f50ad Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: https://review.coreboot.org/16001 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
* Kconfig: hide useless options on ARM.Vladimir Serbinenko2016-03-051-0/+5
| | | | | | | | | | | | | Those options have no effect or lead to compile error on ARM due to fundamental incompatibilities. Add proper "depends on" clauses to hide them. Change-Id: I860fbd331439c25efd8aa92023195fda3add2e2c Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: https://review.coreboot.org/13904 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Martin Roth <martinroth@google.com>
* console: Add higher baud ratesLee Leahy2016-02-221-0/+15
| | | | | | | | | | | | | | Enable baud rates of 230400, 460800 and 921600. Leave the default set to 115200. TEST=Build and run on Galileo at 921600. Change-Id: I8e3980f33665bc183b454cf97c68e297f1b0502c Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: https://review.coreboot.org/13755 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
* console: Disable SQUELCH_EARLY_SMP if SMP is not selectedLee Leahy2016-02-091-0/+1
| | | | | | | | | | | | | | Add a "depends on SMP" to the value SQUELCH_EARLY_SMP Kconfig value to disable its selection when SMP is not enabled. TEST=Build for Galileo Change-Id: Ia3aa1d2169ed793e1bb26538b74b12347453d5af Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: https://review.coreboot.org/13639 Tested-by: build bot (Jenkins) Reviewed-by: FEI WANG <wangfei.jimei@gmail.com> Reviewed-by: Martin Roth <martinroth@google.com>
* console: Simplify bootblock console Kconfig selection logicAlexandru Gagniuc2016-01-211-1/+1
| | | | | | | | | | | | Instead of depending BOOTBLOCK_CONSOLE on a set of architectures, allow the arch or platform to specify whether it can provide a C environment. This simplifies the selection logic. Change-Id: Ia3e41796d9aea197cee0a073acce63761823c3aa Signed-off-by: Alexandru Gagniuc <alexandrux.gagniuc@intel.com> Reviewed-on: https://review.coreboot.org/12871 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
* console: Allow ARM64 platforms to select bootblock consoleMartin Roth2015-12-081-1/+1
| | | | | | | | Change-Id: I09943aafe29f6e7a2a878e7b6141661982dfc645 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/12658 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
* console: Add help for serial IO port selectionMartin Roth2015-11-211-0/+12
| | | | | | | | | | | Add help and a comment about the serial IO port selection to give the user better feedback when a port index is selected. Change-Id: I4c1614be51aee0286308fbc5c24554e218120bf7 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: http://review.coreboot.org/12487 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
* x86: Add Kconfig to disable early bootblock postcodesMartin Roth2015-11-191-0/+9
| | | | | | | | | | | | | | | | | | The Intel cave creek chipset needs to have port 80 routing configured before any post codes can be sent to port 80h. Sending post codes out before the routing is done will hang the system. This patch allows us to disable the first couple of post codes that go out before the routing can be configured. The Kconfig symbol is selected by the cave creek chipset (fsp_i89xx). Change-Id: I9bf41669ec32744f87a1ed2de011d31c72ea38da Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: http://review.coreboot.org/12422 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-by: York Yang <york.yang@intel.com>
* Add EM100 'hyper term' spi console support in ramstage & smmMartin Roth2015-10-051-0/+8
| | | | | | | | | | | | | | | | | | The EM100Pro allows the debug console to be sent over the SPI bus. This is not yet working in romstage due to the use of static variables in the SPI driver code. It is also not working on chipsets that have SPI write buffers of less than 10 characters due to the 9 byte command/header length specified by the EM100 protocol. While this currently works only with the EM100, it seems like it would be useful on any logic analyzer with SPI debug - just filter on command bytes of 0x11. Change-Id: Icd42ccd96cab0a10a4e70f4b02ecf9de8169564b Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: http://review.coreboot.org/11743 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
* cbmem: add and use a function to dump console bufferVadim Bendebury2015-04-271-0/+9
| | | | | | | | | | | | | | | | | | | | | | | | The new function can be compiled in only when serial console is disabled. When invoked, this function initializes the serial interface and dumps the contents of the CBMEM console buffer to serial output. BRANCH=none BUG=chromium:475347 TEST=compiled for different platforms with and without serial console enabled. No actual test of this function yet. Change-Id: Ia8d16649dc9d09798fa6970f2cfd893438e00dc5 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: a38a8254dd788ad188ba2509b9ae117d6f699579 Original-Change-Id: Ib85759a2727e31ba1ca21da7e6c346e434f83b52 Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/265293 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/9984 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
* cbmem_console: fix it for x86Aaron Durbin2015-04-231-5/+0
| | | | | | | | | | | | The Kconfig options pertaining cbmem console in the preram environment no longer make sense with the linker script changes. Remove them and their usage within cbmem_console. Change-Id: Ibf61645ca2331e4851e748e4e7aa5059e1192ed7 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/9851 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
* New mechanism to define SRAM/memory map with automatic bounds checkingJulius Werner2015-04-061-10/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch creates a new mechanism to define the static memory layout (primarily in SRAM) for a given board, superseding the brittle mass of Kconfigs that we were using before. The core part is a memlayout.ld file in the mainboard directory (although boards are expected to just include the SoC default in most cases), which is the primary linker script for all stages (though not rmodules for now). It uses preprocessor macros from <memlayout.h> to form a different valid linker script for all stages while looking like a declarative, boilerplate-free map of memory addresses to the programmer. Linker asserts will automatically guarantee that the defined regions cannot overlap. Stages are defined with a maximum size that will be enforced by the linker. The file serves to both define and document the memory layout, so that the documentation cannot go missing or out of date. The mechanism is implemented for all boards in the ARM, ARM64 and MIPS architectures, and should be extended onto all systems using SRAM in the future. The CAR/XIP environment on x86 has very different requirements and the layout is generally not as static, so it will stay like it is and be unaffected by this patch (save for aligning some symbol names for consistency and sharing the new common ramstage linker script include). BUG=None TEST=Booted normally and in recovery mode, checked suspend/resume and the CBMEM console on Falco, Blaze (both normal and vboot2), Pinky and Pit. Compiled Ryu, Storm and Urara, manually compared the disassemblies with ToT and looked for red flags. Change-Id: Ifd2276417f2036cbe9c056f17e42f051bcd20e81 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: f1e2028e7ebceeb2d71ff366150a37564595e614 Original-Change-Id: I005506add4e8fcdb74db6d5e6cb2d4cb1bd3cda5 Original-Signed-off-by: Julius Werner <jwerner@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/213370 Reviewed-on: http://review.coreboot.org/9283 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Tauner <stefan.tauner@gmx.at> Reviewed-by: Aaron Durbin <adurbin@google.com>
* console: Allow bootblock console on MIPSPaul Burton2015-03-231-1/+1
| | | | | | | | | | | | | | | | | | | | | In addition to ARM based systems, allow MIPS based systems to select bootblock console support. BUG=chrome-os-partner:31438 TEST=none yet Change-Id: I40e5d8b651102709118878a317f7e983a617f433 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 1a41853273ef9ae716d5645379fcef79c5771b87 Original-Change-Id: I41f03ea8c8104ba2dd9f532b084696385d29636c Original-Signed-off-by: Paul Burton <paul.burton@imgtec.com> Original-Reviewed-on: https://chromium-review.googlesource.com/207973 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Tested-by: Vadim Bendebury <vbendeb@chromium.org> Original-Commit-Queue: Vadim Bendebury <vbendeb@chromium.org> Reviewed-on: http://review.coreboot.org/8769 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
* console/Kconfig: Enable CBMEM console by defaultPaul Menzel2015-03-101-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | Currently on AMD boards no romstage messages can be saved in CBMEM, so only messages from ramstage on will be stored in CBMEM. Other than that nothing changes. Enabling CBMEM console by default does not noticeably decrease boot time as the messages are directly written to CAR or RAM. The board status script under `util/board_status/` reads the coreboot messages from CBMEM, which are then uploaded to the board status repository. With CBMEM console disabled by default, currently no coreboot console messages are uploaded to the board status repository, although it is important to have those. Enabling CBMEM console by default improves this situation, so that for all boards at least ramstage messages are stored in the board status repository. Change-Id: I8d5a58c078325c43a0317bcfaafc722d039aab0b Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net> Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/5350 Reviewed-by: Aaron Durbin <adurbin@google.com> Tested-by: build bot (Jenkins)
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-18 16:52:32 +0000