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* console/vtxprintf.c: Add <stdarg.h>Elyes Haouas2022-10-061-0/+1
| | | | | | | | Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Change-Id: I221a2bdb19cc7d17265c69d3fe3e1dfb490e7186 Reviewed-on: https://review.coreboot.org/c/coreboot/+/68039 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin L Roth <gaumless@gmail.com>
* console/printk.c: Add <types.h>Elyes Haouas2022-10-061-0/+1
| | | | | | | | Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Change-Id: I55412395071f0fccb839c40fefda998befaddebb Reviewed-on: https://review.coreboot.org/c/coreboot/+/68037 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin L Roth <gaumless@gmail.com>
* console/die.c: Add <stdarg.h>Elyes Haouas2022-10-061-0/+1
| | | | | | | | Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Change-Id: I2ee8ef017d8a3409cbf47f1ed252a512dead224e Reviewed-on: https://review.coreboot.org/c/coreboot/+/68036 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin L Roth <gaumless@gmail.com>
* console/console.c: Sort includes and add <types.h>Elyes Haouas2022-10-061-4/+5
| | | | | | | | Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Change-Id: I1d2d85ff8cfca58295117b5cb625cadfc9008311 Reviewed-on: https://review.coreboot.org/c/coreboot/+/68035 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin L Roth <gaumless@gmail.com>
* console/vsprintf.c: Add <stdarg.h>Elyes Haouas2022-10-061-0/+1
| | | | | | | | Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Change-Id: I8c61f2a033f9630d3fa3eb5e364e6f38de5c7064 Reviewed-on: https://review.coreboot.org/c/coreboot/+/68038 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin L Roth <gaumless@gmail.com>
* drivers/smbus: initialize SC16IS7XX I2C to UART converter chipHusni Faiz2022-10-031-0/+15
| | | | | | | | | | | | | This patch adds the functionality to initialize the sc16is750 i2c to uart converter chip with a 14.7MHz input clock to support 115200 baud rate. Change-Id: Ib31188b8c0f9b0ce9454da984e630eca9101d145 Signed-off-by: Husni Faiz <ahamedhusni73@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/67342 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <inforichland@gmail.com> Reviewed-by: Raul Rangel <rrangel@chromium.org>
* console: attach smbus console driverHusni Faiz2022-09-161-0/+4
| | | | | | | | | | | This patch attaches the smbus console functions to the high level console interface. Change-Id: I3a9bf64e59d529253bfdcdfa565bb2bb92975728 Signed-off-by: Husni Faiz <ahamedhusni73@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/67341 Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* drivers/smbus: add smbus console driverHusni Faiz2022-09-161-0/+24
| | | | | | | | | | | This patch adds a new smbus console driver and Kconfig options to enable the driver. Change-Id: Ife77fb2c3e1cc77678a4972701317d50624ceb95 Signed-off-by: Husni Faiz <ahamedhusni73@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/67339 Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* console/vtxprintf.c: Use | operator for bit operation instead of +Elyes Haouas2022-09-141-1/+1
| | | | | | | | Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Change-Id: I478265dcd070dcf3fb2cf2c535b6ca1d86b9a3f2 Reviewed-on: https://review.coreboot.org/c/coreboot/+/67564 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
* src/console: Reformat codeElyes Haouas2022-09-132-26/+23
| | | | | | | | | | | Most of these changes are suggested by clang-format(13.0-54) tool on Debian testing. Change-Id: I68a288b3f7e911331e7324bf13cf9bde259a29de Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/64781 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
* console: Make CONSOLE_SPI_FLASH depend on BOOT_DEVICE_SPI_FLASHArthur Heymans2022-04-271-0/+1
| | | | | | | | | | Change-Id: Ibfdbca02259a723029260dfea9f36b325414b7d3 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/52793 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Christian Walter <christian.walter@9elements.com>
* src/console/Kconfig: Add option to disable loglevel prefixIgor Bagnucki2022-03-302-1/+11
| | | | | | | | | | | | | | | | | | | | | | | This patch adds an option to disable loglevel prefixes. This patch helps to achieve clear messages when low loglevel is used and very few messages are displayed on a terminal. This option also allows to maintain compatibility with log readers and continuous integration systems that depend on fixed log content. If the code contains: printk(BIOS_DEBUG, "This is a debug message!\n") it will show as: [DEBUG] This is a debug message! but if the Kconfig contains: CONFIG_CONSOLE_USE_LOGLEVEL_PREFIX=n the same message will show up as This is a debug message! Signed-off-by: Igor Bagnucki <igor.bagnucki@3mdeb.com> Change-Id: I911bb601cf1933a4c6498b2ae1e4cb4d4bc85621 Reviewed-on: https://review.coreboot.org/c/coreboot/+/63144 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
* console: Fix LOG_FAST macroMario Scheithauer2022-02-221-1/+1
| | | | | | | | | | | | | | | | | | | In the LOG_FAST macro, the comparison was incorrectly made with 'level' value. Correct is the comparison with 'speed'. With the wrong comparison you cannot set a lower level for console log, the highest level is always output. TEST: - Boot mc_ehl2 with console log level 5 and check output Change-Id: Ib5b4537ae2cbf01c51c3568d312b5242c4bee7bb Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/62261 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Patrick Georgi <patrick@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
* Use the fallthrough statement in switch loopsArthur Heymans2022-02-161-1/+2
| | | | | | | | | | | Clang does not seem to work with 'fall through' in comments. Change-Id: Idcbe373be33ef7247548f856bfaba7ceb7f749b5 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51498 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
* console: Add missing va_end() in wrap_interactive_printf()Julius Werner2022-02-091-0/+1
| | | | | | | | | | | I think this doesn't do anything on most architectures, but it should still be there just in case. Found by Coverity. Signed-off-by: Julius Werner <jwerner@chromium.org> Change-Id: I845a784d90f65610fd1e0d751ea13e9af5b970fd Reviewed-on: https://review.coreboot.org/c/coreboot/+/61724 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
* console/post: Lower post code loglevel to BIOS_INFOJulius Werner2022-02-091-1/+1
| | | | | | | | | | | | | | Post codes don't signify an emergency error, so they shouldn't be classified as BIOS_EMERG. Now that loglevels are more visible, this misclassification looks pretty glaring. This patch changes them to BIOS_INFO which seems more appropriate for an informational code that is expected to occur in the normal boot flow. Signed-off-by: Julius Werner <jwerner@chromium.org> Change-Id: I85c8768232ae0cbf65669a7ee6abd538a3b2d5e1 Reviewed-on: https://review.coreboot.org/c/coreboot/+/61692 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
* console: Add compile-time fast path when only CBMEM console is usedJulius Werner2022-02-072-4/+8
| | | | | | | | | | | | | | | | | A common use case when running coreboot on production systems is that only the CBMEM console (the one with the least impact on boot speed) is enabled. In this case, some of the code in the console subsystem has no effect. Due to the way it's all genericized over multiple consoles and tied together with function pointers, not all of this can be compile-time eliminated automatically, so this patch adds a little helper to facilitate that. This results in roughly 200 (compressed) bytes of savings per stage on an arm64 system. Signed-off-by: Julius Werner <jwerner@chromium.org> Change-Id: I1d5b8bda80d02a13ee0b7835e0805c4319fd21d8 Reviewed-on: https://review.coreboot.org/c/coreboot/+/61613 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
* console: Add loglevel marker codes to stored consolesJulius Werner2022-02-071-1/+9
| | | | | | | | | | | | | | | | | | | | | | | | | | In order to provide the same loglevel prefixes and highlighting that were recently introduced for "interactive" consoles (e.g. UART) to "stored" consoles (e.g. CBMEM) but minimize the amont of extra storage space wasted on this info, this patch will write a 1-byte control character marker indicating the loglevel to the start of every line logged in those consoles. The `cbmem` utility will then interpret those markers and translate them back into loglevel prefixes and escape sequences as needed. Since coreboot and userspace log readers aren't always in sync, occasionally an older reader may come across these markers and not know how to interpret them... but that should usually be fine, as the range chosen contains non-printable ASCII characters that normally have no effect on the terminal. At worst the outdated reader would display one garbled character at the start of every line which isn't that bad. (Older versions of the `cbmem` utility will translate non-printable characters into `?` question marks.) Signed-off-by: Julius Werner <jwerner@chromium.org> Change-Id: I86073f48aaf1e0a58e97676fb80e2475ec418ffc Reviewed-on: https://review.coreboot.org/c/coreboot/+/61308 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
* console: Add ANSI escape sequences for highlightingJulius Werner2022-02-072-1/+20
| | | | | | | | | | | | | | | | | | | | | | | | | | This patch adds ANSI escape sequences to highlight a log line based on its loglevel to the output of "interactive" consoles that are meant to be displayed on a terminal (e.g. UART). This should help make errors and warnings stand out better among the usual spew of debug messages. For users whose terminal or use case doesn't support these sequences for some reason (or who simply don't like them), they can be disabled with a Kconfig. While ANSI escape sequences can be used to add color, minicom (the presumably most common terminal emulator for UART endpoints?) doesn't support color output unless explicitly enabled (via -c command line flag), and other terminal emulators may have similar restrictions, so in an effort to make this as widely useful by default as possible I have chosen not to use color codes and implement this highlighting via bolding, underlining and inverting alone (which seem to go through in all cases). If desired, support for separate color highlighting could be added via Kconfig later. Signed-off-by: Julius Werner <jwerner@chromium.org> Change-Id: I868f4026918bc0e967c32e14bcf3ac05816415e8 Reviewed-on: https://review.coreboot.org/c/coreboot/+/61307 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
* console: Add loglevel prefix to interactive consolesJulius Werner2022-02-072-9/+42
| | | | | | | | | | | | | | | | | | | | | In an attempt to make loglevels more visible (and therefore useful, hopefully), this patch adds a prefix indicating the log level to every line sent to an "interactive" console (such as a UART). If the code contains a `printk(BIOS_DEBUG, "This is a debug message!\n"), it will now show up as [DEBUG] This is a debug message! on the UART output. "Stored" consoles (such as in CBMEM) will get a similar but more space-efficient feature in a later CL. Signed-off-by: Julius Werner <jwerner@chromium.org> Change-Id: Ic83413475400821f8097ef1819a293ee8926bb0b Reviewed-on: https://review.coreboot.org/c/coreboot/+/61306 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
* console: Pass log_state to vtxprintf()Julius Werner2022-02-041-13/+19
| | | | | | | | | | | | | | | This patch makes a slight change in the way CONSOLE_LOG_FAST and CONSOLE_LOG_ALL are differentiated, by no longer passing a different tx_byte() function pointer and instead using the `data` argument to vtxprintf() to encode the difference. It also passes the message log level through to the tx_byte() function this way, which will be needed in the next patch. Change-Id: I0bba134cd3e70c2032689abac83ff53d7cdf2d7f Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/61580 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
* lib/cbmem_console,console: Resurrect CONSOLE_CBMEM_DUMP_TO_UARTRaul E Rangel2022-01-251-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Chromebooks normally run with non-serial enabled firmware because writing to the UART console is very slow. This unfortunately makes debugging boot errors more difficult. We tend to rely on port 80s and/or the vboot recovery code. When CONSOLE_CBMEM_DUMP_TO_UART is selected it will dump the entire cbmem console to the UART whenever `vboot_reboot()` is called. We don't incur any boot time penalty in the happy path, but still retain the ability to access the logs when an error occurs. The previous implementation was using a hard coded UART index and `get_uart_baudrate` was always returning 0 since `CONFIG_TTYS0_BAUD` wasn't defined. This change makes it so the UART console properties are available when CONSOLE_CBMEM_DUMP_TO_UART is set. This results in the following .config diff: +CONFIG_UART_FOR_CONSOLE=0 +CONFIG_TTYS0_BASE=0x3f8 +CONFIG_TTYS0_LCS=3 +CONFIG_CONSOLE_SERIAL_115200=y +CONFIG_TTYS0_BAUD=115200 This functionality is especially helpful on Guybrush. PSP Verstage is run on S0i3 resume. Today, if there is an error, the cbmem console is lost since it lives in the PSP SRAM. BUG=b:213828947, b:215599230 TEST=Build non-serial guybrush FW and verify no serial output happens in happy path. Inject a vboot error and perform an S0i3 suspend/resume. Verify CBMEM console gets dumped to the correct UART. Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: I997942204603362e51876a9ae25e493fe527437b Reviewed-on: https://review.coreboot.org/c/coreboot/+/61305 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
* console: Add Kconfig to dump pre-bootblock cbmem contentsRaul E Rangel2022-01-172-0/+12
| | | | | | | | | | | | | | | | | | | | | | | Pre-bootblock stages (i.e., VBOOT_STARTS_BEFORE_BOOTBLOCK) might not have the ability to log to the UART, so their console messages are inaccessible until the boot processes gets into the payload or OS. This makes it difficult to debug verstage. This feature will dump the pre-bootblock CBMEM console immediately after the bootblock console is initialized. I chose to do this in console_init instead of bootblock_soc_init because I wanted to have the pre-bootblock contents dumped before the coreboot bootblock starting message is printed. BUG=b:213828947 TEST=Boot guybrush with PSP verstage and verify verstage logs are dumped to the UART. Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: I363c93ef3ee6c5c303a6a68f88a622e2aa62594c Reviewed-on: https://review.coreboot.org/c/coreboot/+/61012 Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* console: Make get_log_level a public functionSubrata Banik2022-01-031-1/+1
| | | | | | | | | | | | Other drivers may need to know the coreboot log level hence, export this function rather than marking it static. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: I56349f22c71c9db757b2be8eeb2dbfe959f80397 Reviewed-on: https://review.coreboot.org/c/coreboot/+/60470 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Nico Huber <nico.h@gmx.de>
* src/acpi to src/lib: Fix spelling errorsMartin Roth2021-10-051-1/+1
| | | | | | | | | | | | These issues were found and fixed by codespell, a useful tool for finding spelling errors. Signed-off-by: Martin Roth <martin@coreboot.org> Change-Id: I5b8ecdfe75d99028fee820a2034466a8ad1c5e63 Reviewed-on: https://review.coreboot.org/c/coreboot/+/58080 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* console: Remove asmlinkage from console_initRaul E Rangel2021-09-171-1/+1
| | | | | | | | | | | | | | | We never call console_init from asm, so we don't need the asmlinkage. This allows us to remove the arch/cpu.h include since we only needed it for the asmlinkage #define. BUG=b:179699789 TEST=build guybrush Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: I9a7895d4f5cba59f6b05915fa4d6c6fd6ab85773 Reviewed-on: https://review.coreboot.org/c/coreboot/+/57568 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* console/hw-debug_sink: Update for fast/slow console distinctionNico Huber2021-08-041-4/+28
| | | | | | | | Change-Id: I9ac110c7b812f912f0f87cbe4aa218d4a78e6aaf Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56665 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
* Asm code: Use NO_EARLY_BOOTBLOCK_POSTCODES to remove Asm port80sMartin Roth2021-06-251-4/+6
| | | | | | | | | | | | | | | | | Expand NO_EARLY_BOOTBLOCK_POSTCODES to all of the early assembly code in bootblock. BUG=b:191370340 TEST: Build with & without the option enabled Signed-off-by: Martin Roth <martinroth@chromium.org> Change-Id: Idb4a96820d5c391fc17a0f0dcccd519d4881b78c Reviewed-on: https://review.coreboot.org/c/coreboot/+/55731 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
* src/console/init.c: Make get_log_level static inline againJakub Czapiga2021-06-151-2/+1
| | | | | | | | | | | | | CB:55356 removed static inline declarations from get_log_level(). This commit puts them back. It also changes the method of accessing static symbols in tests/console/routing-test to source file inclusion like in CB:46458 to avoid changing tested source file. Signed-off-by: Jakub Czapiga <jacz@semihalf.com> Change-Id: Iaa5dcbccb327f819374967be51ef642b1fb25e7b Reviewed-on: https://review.coreboot.org/c/coreboot/+/55473 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* tests/console: Add tests for log message routing behaviorPatrick Georgi2021-06-101-1/+2
| | | | | | | | Change-Id: Id978cfe4fa45fef9edbc3d3b55606ff6973521c5 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55356 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jakub Czapiga <jacz@semihalf.com>
* src: Retype option API to use unsigned integersAngel Pons2021-05-061-1/+1
| | | | | | | | | | | | | The CMOS option system does not support negative integers. Thus, retype and rename the option API functions to reflect this. Change-Id: Id3480e5cfc0ec90674def7ef0919e0b7ac5b19b3 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/52672 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Felix Singer <felixsinger@posteo.net>
* src: Replace remaining {get,set}_option() instancesAngel Pons2021-04-231-1/+1
| | | | | | | | | | | | With this change, the type-unsafe {get,set}_option() API functions are no longer used directly. The old API gets dropped in a follow-up. Change-Id: Id3f3e172c850d50a7d2f348b1c3736969c73837d Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/52512 Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-by: Patrick Rudolph <siro@das-labor.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* Rename do_printk() to printk()Nico Huber2021-04-141-3/+3
| | | | | | | | | | | | | The indirection seems unnecessary. The macros throw features like `-Wmisleading-indentation` off, though. Default build for QEMU/Q35 is unchanged. Change-Id: Ie4eab935a367b5ad6b38225c4973d41d9f70ef10 Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51887 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
* console/vtxprintf.c: Add missing <types.h>Elyes HAOUAS2021-02-161-1/+1
| | | | | | | | Change-Id: Icc2b99f9125e9059dbf3de42a1b5ca9727888166 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50565 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
* lib/trace: Remove TRACE supportKyösti Mälkki2020-12-022-8/+0
| | | | | | | | | | | | | | | | | | | | | Looks like the option is generally not compatible with garbage collections. Nothing gets inlined, for example is_smp_boot() no longer evaluates to constant false and thus the symbols from secondary.S would need to be present for the build to pass even if we set SMP=n. Also the addresses of relocatable ramstage are currently not normalised on the logs, so util/genprof would be unable dress those. Change-Id: I0b6f310e15e6f4992cd054d288903fea8390e5cf Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45757 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Nico Huber <nico.h@gmx.de>
* console: Override uart base addressBryant Ou2020-11-091-0/+10
| | | | | | | | | | | | | Add a new CONFIG_OVERRIDE_UART_FOR_CONSOLE token to override the index of uart port, platform use a get_uart_for_console routine to decide what index value should be used for console. Signed-off-by: Bryant Ou <Bryant.Ou.Q@gmail.com> Change-Id: I2079bd1e5ffa209553383b6aafe3b8724849ba2a Reviewed-on: https://review.coreboot.org/c/coreboot/+/45405 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marc Jones <marc@marcjonesconsulting.com> Reviewed-by: Jonathan Zhang <jonzhang@fb.com>
* console/init: Drop CONSOLE_LEVEL_CONSTNico Huber2020-10-261-20/+5
| | | | | | | | | | | | | | | | | | | | | | We limited the configurability of the debug level to stages that have a `.data` section. This is not really a requirement, because a `.bss` section should suffice and we always have that now. We want to make the debug level configurable early but also want to avoid calling get_option() early, as an error therein could result in no console output at all. Hence, we compromise and start using get_option() from the second console init on. TEST=Booted QEMU once with `debug_level=Debug` and once with `debug_level=Notice`. On the second boot, most messages vanished for all stages but the bootblock. Change-Id: I11484fc32dcbba8d31772bd0b82785f17b2fba11 Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45765 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Marc Jones <marc@marcjonesconsulting.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* src: Rename EM100Pro-specific SPI console Kconfig optionAngel Pons2020-10-131-3/+3
| | | | | | | | | | | | To avoid confusion with `flashconsole` (CONSOLE_SPI_FLASH), prefix this option with `EM100Pro`. Looks like it is not build-tested, however. Change-Id: I4868fa52250fbbf43e328dfd12e0e48fc58c4234 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45973 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
* src/console: Drop unneeded empty linesElyes HAOUAS2020-09-212-2/+0
| | | | | | | | Change-Id: I94f92ba4385285496ede0c33fc25addd6c4bfeae Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44607 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
* ec/system76: Add console supportJeremy Soller2020-09-072-0/+11
| | | | | | | | | | | | | | | | | | | This adds support for line-buffered console output to System76 EC firmware. Once the print command is received, the EC firmware multiplexes the output to any enabled console on the EC. This can be a memory ringbuffer, a parallel port (using the keyboard connector), or i2c (using the battery connector). Once the entire buffer is sent, it sets the command register to 0, indicating completion. For more information, please see: https://github.com/system76/ec/blob/master/doc/debugging.md Tested on system76/lemp9 with CONSOLE_SYSTEM76_EC enabled. Signed-off-by: Jeremy Soller <jeremy@system76.com> Change-Id: I861bf3e22f40dd6c3ec7ba1d73711b399358e332 Reviewed-on: https://review.coreboot.org/c/coreboot/+/43718 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michael Niewöhner
* src: Remove unused 'include <stddef.h>Elyes HAOUAS2020-08-181-1/+0
| | | | | | | | Change-Id: Iae1e875b466f8a195653d897efa1b297c61ad0a5 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41912 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* console: Update for vboot before bootblockMartin Roth2020-06-151-2/+4
| | | | | | | | | | | | | | | Exclude pieces of console code from the vboot if running before bootlock. The PSP verstage code will re-implement some of these in its own code. BUG=b:123887623 TEST=Build with following patches Signed-off-by: Martin Roth <martin@coreboot.org> Change-Id: Ifc9fb0810e0816fe0a68e52287eda6145043a619 Reviewed-on: https://review.coreboot.org/c/coreboot/+/41815 Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* console, PCI: Remove EARLY_PCI_BRIDGE support in verstageKyösti Mälkki2020-06-141-1/+1
| | | | | | | | | | | | | | | | | | | The purpose of pci_early_bridge_init() is to temporarily configure PCIe rootport (or PCI bridge) on bus 0 to configure PCI device BARs on the secondary bus. Currently used and tested only with UART_OXPCIE. Since those BARs do not reset on stage changes, it is not necessary to redo those steps for verstage or postcar. Note that the option does not really work with many of the later platforms where PCIe pins/links/lanes are configured late in FSP-M or similar blob. Change-Id: I148f44c76c61edcfd8ab1c8c531cd2e6ca343130 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42227 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Furquan Shaikh <furquan@google.com>
* treewide: Remove "this file is part of" linesPatrick Georgi2020-05-119-9/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Stefan thinks they don't add value. Command used: sed -i -e '/file is part of /d' $(git grep "file is part of " |egrep ":( */\*.*\*/\$|#|;#|-- | *\* )" | cut -d: -f1 |grep -v crossgcc |grep -v gcov | grep -v /elf.h |grep -v nvramtool) The exceptions are for: - crossgcc (patch file) - gcov (imported from gcc) - elf.h (imported from GNU's libc) - nvramtool (more complicated header) The removed lines are: - fmt.Fprintln(f, "/* This file is part of the coreboot project. */") -# This file is part of a set of unofficial pre-commit hooks available -/* This file is part of coreboot */ -# This file is part of msrtool. -/* This file is part of msrtool. */ - * This file is part of ncurses, designed to be appended after curses.h.in -/* This file is part of pgtblgen. */ - * This file is part of the coreboot project. - /* This file is part of the coreboot project. */ -# This file is part of the coreboot project. -# This file is part of the coreboot project. -## This file is part of the coreboot project. --- This file is part of the coreboot project. -/* This file is part of the coreboot project */ -/* This file is part of the coreboot project. */ -;## This file is part of the coreboot project. -# This file is part of the coreboot project. It originated in the - * This file is part of the coreinfo project. -## This file is part of the coreinfo project. - * This file is part of the depthcharge project. -/* This file is part of the depthcharge project. */ -/* This file is part of the ectool project. */ - * This file is part of the GNU C Library. - * This file is part of the libpayload project. -## This file is part of the libpayload project. -/* This file is part of the Linux kernel. */ -## This file is part of the superiotool project. -/* This file is part of the superiotool project */ -/* This file is part of uio_usbdebug */ Change-Id: I82d872b3b337388c93d5f5bf704e9ee9e53ab3a9 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41194 Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* src: Replace remaining GPLv2 long form headers with SPDX headerElyes HAOUAS2020-05-102-22/+2
| | | | | | | | Change-Id: I4614e9b02a932530fc22912b5cf502d1b699b451 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41188 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
* drivers/pc80/rtc: Drop CMOS_POST_EXTRA optionKyösti Mälkki2020-04-201-8/+0
| | | | | | | | Change-Id: I379a5664776624600ff1c2919bffa77c877d87ab Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38191 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
* src/console: Use SPDX for GPL-2.0-only filesAngel Pons2020-04-047-86/+16
| | | | | | | | | | Done with sed and God Lines. Only done for C-like code for now. Change-Id: Ib8a40e5633faf840e19a35bcdc8edc7e7cdd0ad9 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40048 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
* treewide: Replace BOARD_EMULATION_QEMU_X86Angel Pons2020-03-031-1/+1
| | | | | | | | | | | It is equivalent to the CPU_QEMU_X86 symbol. Change-Id: Ic16233e3d80bab62cc97fd075bdcca1780a6a2b5 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39182 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
* console/post: NOPOST means NOPOSTPatrick Georgi2020-01-181-1/+2
| | | | | | | | | | Not "NOPOST except when the board says something else". Change-Id: I3608e9c3a7d2338363a4320c8718b20ef25a038a Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38408 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
* console/post: Split parts to arch/Kyösti Mälkki2020-01-141-14/+9
| | | | | | | | | | Both IO port and cmos are currently arch/x86 only features. Change-Id: I010af3f645c0be38dd856657874c36103aebbdc2 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38187 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
generated by cgit v1.2.3 (git 2.25.1) at 2024-09-27 16:57:21 +0000