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* treewide: Remove unused <cpu/x86/mtrr.h>Elyes Haouas2022-07-204-4/+0
| | | | | | | | Change-Id: Ib852d0b2cf4d3cbdf7475bd5493bf2e585a5894a Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/64899 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
* cpu/amd: Reformat codeElyes Haouas2022-07-197-58/+55
| | | | | | | | | | | Most of these changes are suggested by clang-format(13.0-54) tool on Debian testing. Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Change-Id: Ie4fe0e872e94f38079945970848fefd153ab7cb5 Reviewed-on: https://review.coreboot.org/c/coreboot/+/64782 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin L Roth <gaumless@tutanota.com>
* cpu/amd/pi/00730F01/update_microcode.c: Fix some white spaces issuesElyes Haouas2022-07-171-1/+1
| | | | | | | | Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Change-Id: I420b9506381758c63b88435a915672507e8bc465 Reviewed-on: https://review.coreboot.org/c/coreboot/+/65901 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
* cpu/amd: Add common helpers for TSEG and SMMArthur Heymans2022-07-136-29/+33
| | | | | | | | Change-Id: I73174766980e0405e7b8efd4f059bb400c0c0a25 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/64866 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
* device/resource: Add _kb postfix for resource allocatorsKyösti Mälkki2022-06-221-1/+1
| | | | | | | | | | | | There is a lot of going back-and-forth with the KiB arguments, start the work to migrate away from this. Change-Id: I329864d36137e9a99b5640f4f504c45a02060a40 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/64658 Reviewed-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* cpu/amd/agesa: Use common MRC_CACHE code to save S3 dataArthur Heymans2022-06-062-23/+1
| | | | | | | | | | | | | | | | Use the common code to save data for fast boot or S3 resume. An notable improvement that comes with this, is that the same 4K page is not rewritten all the time. This prolongs the hardware's life. TESTED on pcengines/apu1 and lenovo/g505s: S3 resume works fine. Change-Id: I0f4f36dcead52a6c550fb5e606772e0a99029872 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44295 Reviewed-by: Mike Banon <mikebdp2@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com>
* drivers/amd/agesa: Don't save regular boot MTRR to flashArthur Heymans2022-06-061-1/+1
| | | | | | | | | | | | | | | | | | | Save the regular boot MTRRs that are restored on the S3 path during the CPU init in cbmem instead of storing them to the SPI flash. This was probably done because historically this code run with late cbmem init (in ramstage). TESTED on pcengines/apu1 and lenovo/g505s: S3 resume works fine. Change-Id: Ia58e7cd1afb785ba0c379ba75ef6090b56cb9dc6 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44294 Reviewed-by: Mike Banon <mikebdp2@gmail.com> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com>
* cpu/amd: Remove unused <cpu/x86/pae.h>Elyes Haouas2022-05-164-4/+0
| | | | | | | | | | | Found using: diff <(git grep -l '#include <cpu/x86/pae.h>' -- src/) <(git grep -l 'memset_pae\|MEMSET_PAE_\|MAPPING_ERROR\|map_2M_page\|paging_identity_map_addr\|paging_enable_for_car\|paging_set_default_pat\|paging_set_pat\|PAT_ENCODE\|PAT_UC_MINUS\|PAT_WB\|PAT_WP\|PAT_WT\|PAT_WC\|PAT_UC\|paging_set_nxe\|paging_disable_pae\|paging_enable_pae\|paging_enable_pae_cr3' -- src/) Change-Id: I4cab4b66c3d123dbb8a948a5596aa4975b31139b Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/61047 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin L Roth <gaumless@tutanota.com>
* cpu/amd: Remove unused <cbmem.h>Elyes HAOUAS2022-04-221-1/+0
| | | | | | | | Change-Id: Ie9344da411a86186fa161e82db3c3fd3ffb911f6 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/61049 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
* cpu,mb,nb,soc: use HPET_BASE_ADDRESS instead of magic numberFelix Held2022-02-254-4/+8
| | | | | | | | | Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I570f7de90007b67d811d158ca33e099d5cc2d5d3 Reviewed-on: https://review.coreboot.org/c/coreboot/+/62308 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* cpu/x86/lapic: Move LAPIC configuration to MP initKyösti Mälkki2022-02-054-16/+0
| | | | | | | | | | | | | | | | Implementation for setup_lapic() did two things -- call enable_lapic() and virtual_wire_mode_init(). In PARALLEL_MP case enable_lapic() was redundant as it was already executed prior to initialize_cpu() call. For the !PARALLEL_MP case enable_lapic() is added to AP CPUs. Change-Id: I5caf94315776a499e9cf8f007251b61f51292dc5 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58387 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
* cpu/x86/smm: Add SMM_LEGACY_ASEGKyösti Mälkki2022-02-012-2/+2
| | | | | | | | | | | Followup will allow use of PARALLEL_MP with SMM_ASEG so some guards need to be adjusted. Change-Id: If032ce2be4749559db0d46ab5ae422afa7666785 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/61480 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
* cpu/amd/agesa/Kconfig: select NO_SMM for Family 14hMichał Kopeć2021-12-094-1/+3
| | | | | | | | | | | | | | Move the SMM Kconfig options to the specific agesa cpu families. Select NO_SMM for family14 since since no Fam14h platform uses SMM. Leave SMM_ASEG enabled for family15tn and family16kb for now. TEST=Boot Debian 11 on PC Engines apu1 Signed-off-by: Michał Kopeć <michal.kopec@3mdeb.com> Change-Id: I09bbe036a88dada847219606ec79c68e7ca8e5cc Reviewed-on: https://review.coreboot.org/c/coreboot/+/59809 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com>
* cpu/amd/pi/Kconfig: select NO_SMMMichał Kopeć2021-12-081-1/+1
| | | | | | | | | | | | | Disable SMM_ASEG and select NO_SMM since the platforms do not use SMM. TEST=Boot Debian 11 on PC Engines apu3 Signed-off-by: Michał Kopeć <michal.kopec@3mdeb.com> Change-Id: I47237421c3dd5bd043447831263d72c9956cdaf4 Reviewed-on: https://review.coreboot.org/c/coreboot/+/59810 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com> Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
* northbridge/amd/pi/00730F01: enable PARALLEL_MPMichał Kopeć2021-12-061-15/+0
| | | | | | | | | | | | | | | | | | | Disable LEGACY_SMP_INIT to enable PARALLEL_MP. Also remove a large amount of APIC code that is now unnecessary. TEST=Boot on PC Engines apu3 Boot time reduced from 1.707 seconds to 1.620 seconds average across 5 coldboots. Inspired by CB:59693 Change-Id: Ib49e7d3f5956ac7831664d50db5f233b70aa54db Signed-off-by: Michał Kopeć <michal.kopec@3mdeb.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/59808 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
* cpu/amd/mtrr: Remove topmem global variablesArthur Heymans2021-11-031-44/+1
| | | | | | | | | | | | The comments are not correct anymore. With AGESA there is no need to synchronize TOM_MEMx msr's between AP's. It's also not the best place to do so anyway. Change-Id: Iecbe1553035680b7c3780338070b852606d74d15 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58693 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
* cpu/x86/Kconfig: Remove unused CPU_ADDR_BITSArthur Heymans2021-11-034-28/+0
| | | | | | | | | Change-Id: I88f62c18b814ac0ddd356944359e727d6e3bba5a Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58688 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Mariusz Szafrański <mariuszx.szafranski@intel.com>
* cpu/amd/mtrr/amd_mtrr.c: Remove unused functionsArthur Heymans2021-11-034-96/+9
| | | | | | | | | | AGESA sets up MTRRs so these functions are now unused. Change-Id: Ic2bb36d72944ac86c75c163e130f1eb762a7ca37 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58689 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
* cpu/amd: Always fetch CPU addr bits at runtimeArthur Heymans2021-11-031-9/+2
| | | | | | | | | | | | All supported AMD CPUs support getting the physical address size from cpuid so there is no need for a Kconfig default value. Change-Id: If6f9234e091f44a2a03012e7e14c380aefbe717e Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58686 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
* src/cpu: drop CPU_X86_CACHE_HELPER and x86_enable_cache wrapper functionFelix Held2021-10-266-8/+5
| | | | | | | | | | | | | | | | | | | | | | Selecting CPU_X86_CACHE_HELPER only added the x86_enable_cache wrapper function around enable_cache which additionally wrote a POST code to port 0x80 and printed a message to the console. This function was only called during multi-processor initialization in ramstage via the init function pointer in the CPU's device operations struct and was run on all cores, so the message on the console was printed once per CPU core. This patch replaces all x86_enable_cache calls by calls to enable_cache and removes the wrapper function and the Kconfig symbol CPU_X86_CACHE_HELPER which was used to only add this when the corresponding CPUs used the x86_enable_cache wrapper function. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Suggested-by: Angel Pons <th3fanbus@gmail.com> Change-Id: I5866b6bf014821ff9e3a48052a5eaf69319b003a Reviewed-on: https://review.coreboot.org/c/coreboot/+/58579 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* cpu/x86: Introduce and use `CPU_X86_LAPIC`Felix Held2021-10-264-4/+0
| | | | | | | | | | | | | | | | | | | | | With using a Kconfig option to add the x86 LAPIC support code to the build, there's no need for adding the corresponding directory to subdirs in the CPU/SoC Makefile. Comparing which CPU/SoC Makefiles added (cpu/)x86/mtrr and (cpu/)x86/lapic before this and the corresponding MTRR code selection patch and having verified that all platforms added the MTRR code on that patch shows that soc/example/min86 and soc/intel/quark are the only platforms that don't end up selecting the LAPIC code. So for now the default value of CPU_X86_LAPIC is chosen as y which gets overridden to n in the Kconfig of the two SoCs mentioned above. Change-Id: I6f683ea7ba92c91117017ebc6ad063ec54902b0a Signed-off-by: Angel Pons <th3fanbus@gmail.com> Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44228 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
* cpu/x86: Introduce `CPU_X86_CACHE_HELPER`Felix Held2021-10-266-3/+3
| | | | | | | | | | | | There's no need for relative paths with Kconfig options. Change-Id: Ib9b9b29a158c34a30480aaabf6d0b23819d28427 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44226 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
* cpu/amd,intel/*/Makefile: don't add cpu/x86/cacheFelix Held2021-10-261-1/+0
| | | | | | | | | | | | | Some CPUs don't use the ramstage-only x86_enable_cache helper function to call enable_cache with some added port 0x80 and console output. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Suggested-by: Angel Pons <th3fanbus@gmail.com> Change-Id: Ia44c7b150cd12d76e463903966f67d86750cbdd9 Reviewed-on: https://review.coreboot.org/c/coreboot/+/58548 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
* cpu,soc/amd/*/Makefile: don't add cpu/x86/pae a second timeFelix Held2021-10-254-4/+0
| | | | | | | | | | | | Since cpu/x86/Makefile.inc already adds the pae sub-directory, there is no need to include it in the Makefile of a CPU or SoC, so remove it from those Makefiles. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I78368f7eb880fb64f511a2fa8c8acde222d0dca3 Reviewed-on: https://review.coreboot.org/c/coreboot/+/58546 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
* cpu,soc/x86: always include cpu/x86/mtrr on x86 CPUs/SoCsFelix Held2021-10-254-4/+0
| | | | | | | | | | | | | | | | | | | | | | | | | All x86-based CPUs and SoCs in the coreboot tree end up including the Makefile in cpu/x86/mtrr, so include this directly in the Makefile in cpu/x86 to add it for all x86 CPUs/SoCs. In the unlikely case that a new x86 CPU/SoC will be added, a CPU_X86_MTRR Kconfig option that is selected be default could be added and the new CPU/SoC without MTRR support can override this option that then will be used in the Makefile to guard adding the Makefile from the cpu/x86/mtrr sub-directory. In cpu/intel all models except model 2065X and 206AX are selcted by a socket and rely on the socket's Makefile.inc to add x86/mtrr to the subdirs, so those models don't add x86/mtrr themselves. The Intel Broadwell SoC selects CPU_INTEL_HASWELL and which added x86/mtrr to the subdirs. The Intel Xeon SP SoC directory contains two sub-folders for different versions or generations which both add x86/mtrr to the subdirs in their Makefiles. Change-Id: I743eaac99a85a5c712241ba48a320243c5a51f76 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44230 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
* cpu: add missing arch/cpu.h includesFelix Held2021-09-171-0/+1
| | | | | | | | | | Including arch/cpu.h is needed to have the declaration for cpuid_eax. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ic22aba062117e3afa818fa2fc39cb0738e6a1612 Reviewed-on: https://review.coreboot.org/c/coreboot/+/57725 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
* cpu/x86/tsc: Deduplicate Makefile logicAngel Pons2021-09-084-4/+0
| | | | | | | | | | | | | | | | | The code under `cpu/x86/tsc` is only compiled in when its `Makefile.inc` is included from platform (CPU/SoC) code and the `UDELAY_TSC` Kconfig option is enabled. Include `cpu/x86/tsc/Makefile.inc` once from `cpu/x86/Makefile.inc` and drop the now-redundant inclusions from platform code. Also, deduplicate the `UDELAY_TSC` guards. Change-Id: I41e96026f37f19de954fd5985b92a08cb97876c1 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57456 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* AGESA f15tn: Hook up IDS options to KconfigAngel Pons2021-08-221-0/+1
| | | | | | | | | | | | | | | IDS (Integrated Debug Services) options are meant to be enabled when one wants to debug AGESA. Since they are compile-time options, using Kconfig is the logical choice. Currently, none of the options builds. Tested with BUILD_TIMELESS=1 without adding the configuration options into the binary, and Asus A88XM-E does not change. Change-Id: I465627c19c9856e58ca94aa0efedbddb6baaf3f6 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/53985 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: David Hendricks <david.hendricks@gmail.com>
* include/cpu/amd/msr: don't redefine the IA32_BIOS_SIGN_ID MSRFelix Held2021-07-161-1/+1
| | | | | | | | Change-Id: Iff19ae495fb9c0795dae4b2844dc8e0220a57b2c Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56310 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
* src: use mca_clear_status function instead of open codingFelix Held2021-07-144-28/+4
| | | | | | | | Change-Id: I53413b4051b79d7c2f24b1191ce877155e654400 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56259 Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* include/cpu/x86/msr: introduce IA32_MC_*(x) macrosFelix Held2021-07-144-4/+4
| | | | | | | | | | | | When accessing the MCA MSRs, the MCA bank number gets multiplied by 4 and added to the IA32_MC0_* define to get the MSR number. Add a macro that already does this calculation to avoid open coding this repeatedly. Change-Id: I2de753b8c8ac8dcff5a94d5bba43aa13bbf94b99 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56243 Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* cpu/amd/*/model_*_init: use mca_get_bank_count()Felix Held2021-07-124-12/+8
| | | | | | | | | | | | | Use the common mca_get_bank_count function instead of open-coding the functionality to get the MCA bank number. Also re-type the num_banks variable from signed in to unsigned int, since the number of MCA bank is always positive. Change-Id: I70ad423aab484cf4ec8f51b43624cd434647aad4 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56184 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com>
* src: Introduce `ARCH_ALL_STAGES_X86`Angel Pons2021-07-022-2/+0
| | | | | | | | | | | | | | | Introduce the `ARCH_ALL_STAGES_X86` Kconfig symbol to automatically select the per-stage arch options. Subsequent commits will leverage this to allow choosing between 32-bit and 64-bit coreboot where all stages are x86. AMD Picasso and AMD Cezanne are the only exceptions to this rule: they disable `ARCH_ALL_STAGES_X86` and explicitly set the per-stage arch options accordingly. Change-Id: Ia2ddbae8c0dfb5301352d725032f6ebd370428c9 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55759 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
* src: Move `select ARCH_X86` to platformsAngel Pons2021-06-302-0/+2
| | | | | | | | | | | | To generalise the choice of 32-bit or 64-bit coreboot on x86 hardware, have platforms select `ARCH_X86` directly instead of through per-stage Kconfig options, effectively reversing the dependency order. Change-Id: If15436817ba664398055e9efc6c7c656de3bf3e4 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55758 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
* cpu/amd/pi/00630F01: Remove unused directory and codeMichał Żygowski2021-05-279-310/+0
| | | | | | | | | | No board currently uses AMD PI 00630F01 so remove it. Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com> Change-Id: If270c2a979346029748230952caba78a5e763d75 Reviewed-on: https://review.coreboot.org/c/coreboot/+/53993 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
* cpu/x86: Only include smm code if CONFIG_HAVE_SMI_HANDLER=yArthur Heymans2021-05-185-5/+0
| | | | | | | | | | | This removes the need to include this code separately on each platform. Change-Id: I3d848b1adca4921d7ffa2203348073f0a11d090e Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46380 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
* cpu/amd/pi/00730F01/model_16_init.c: create correct MTRR solutionMichał Żygowski2021-05-131-37/+28
| | | | | | | | | | | | | | | | | | | Create the correct MTRR solution based on the physical address space provided by RESOURCE_ALLOCATOR_V4. Previously CPU initialization did not account for lost C6 DRAM storage MTRR during postcar frame creation. The BSP on 2GB has been stripped from UC MTRR covering C6 DRAM and overlapping with usable DRAM WB MTRR. However this UC MTRR remained on APs which caused inconsistent MTRRs warning in Linux. Use generic MTRR function to create correct MTRR solution that propagates to APs. This also fixes the inconsistent MTRRs warning. TEST=boot Debian with Linux 4.14 on apu2 4GB ECC and apu3 2GB no-ECC Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com> Change-Id: Ie2d7a75affd7d3d3a1bc6327fb423e206b28562f Reviewed-on: https://review.coreboot.org/c/coreboot/+/52762 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* cpu/amd/agesa/family15tn/fixme.cFrans Hendriks2021-01-281-7/+7
| | | | | | | | | | | | | | | | lint report errors and warnings Solve the next issues: - BRACES BUG = N/A TEST = N/A Change-Id: I27a712ec93c216fc3aa836baa53d6e2f2e68d3a3 Signed-off-by: Frans Hendriks <fhendriks@eltan.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49969 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
* arch/x86: Remove most C_ENV_BOOTBLOCK_SIZE limitsKyösti Mälkki2021-01-282-8/+0
| | | | | | | | | | | | With top-aligned bootblock this is no longer globally needed. The default maximum is now a generous 256 KiB with couple platforms having lower limits of 32 KiB and 64 KiB. Change-Id: Ib1aee44908c0dcbc17978d3ee53bd05a6200410c Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47600 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
* ACPI: Remove ACPI_NO_SMI_GNVSKyösti Mälkki2021-01-072-2/+0
| | | | | | | | | | | | | This was used as a guard to not raise SMI with APM_CNT_GNVS_UPDATE. The handler has been removed now completely. Change-Id: I7726367fd16630aa4b4b25b24b05f740645066db Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49127 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Nico Huber <nico.h@gmx.de>
* cbfs: Simplify load/map API names, remove type argumentsJulius Werner2020-12-021-2/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch renames cbfs_boot_map_with_leak() and cbfs_boot_load_file() to cbfs_map() and cbfs_load() respectively. This is supposed to be the start of a new, better organized CBFS API where the most common operations have the most simple and straight-forward names. Less commonly used variants of these operations (e.g. cbfs_ro_load() or cbfs_region_load()) can be introduced later. It seems unnecessary to keep carrying around "boot" in the names of most CBFS APIs if the vast majority of accesses go to the boot CBFS (instead, more unusual operations should have longer names that describe how they diverge from the common ones). cbfs_map() is paired with a new cbfs_unmap() to allow callers to cleanly reap mappings when desired. A few new cbfs_unmap() calls are added to generic code where it makes sense, but it seems unnecessary to introduce this everywhere in platform or architecture specific code where the boot medium is known to be memory-mapped anyway. In fact, even for non-memory-mapped platforms, sometimes leaking a mapping to the CBFS cache is a much cleaner solution than jumping through hoops to provide some other storage for some long-lived file object, and it shouldn't be outright forbidden when it makes sense. Additionally, remove the type arguments from these function signatures. The goal is to eventually remove type arguments for lookup from the whole CBFS API. Filenames already uniquely identify CBFS files. The type field is just informational, and there should be APIs to allow callers to check it when desired, but it's not clear what we gain from forcing this as a parameter into every single CBFS access when the vast majority of the time it provides no additional value and is just clutter. Signed-off-by: Julius Werner <jwerner@chromium.org> Change-Id: Ib24325400815a9c3d25f66c61829a24a239bb88e Reviewed-on: https://review.coreboot.org/c/coreboot/+/39304 Reviewed-by: Hung-Te Lin <hungte@chromium.org> Reviewed-by: Wim Vervoorn <wvervoorn@eltan.com> Reviewed-by: Mariusz Szafrański <mariuszx.szafranski@intel.com> Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* cpu/amd/microcode: Remove dead MakefileArthur Heymans2020-11-221-2/+0
| | | | | | | | Change-Id: If9d1e28ac50b8ca227b2c09dbbfdd3c9b60aca6a Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47718 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
* cpu/amd/pi: Remove unused cpu code 00660F01Martin Roth2020-11-228-259/+0
| | | | | | | | | | Remove the processor directory and references to the Kconfig symbol. Signed-off-by: Martin Roth <martin@coreboot.org> Change-Id: I403a453362fd76d6ef2a5b75728a362efa4f2491 Reviewed-on: https://review.coreboot.org/c/coreboot/+/47652 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
* ACPI S3: Replace acpi_is_wakeup()Kyösti Mälkki2020-11-193-3/+3
| | | | | | | | | | | | It was supposed to return true for both S2 and S3, but level S2 was never stored in acpi_slp_type or otherwise implemented. Change-Id: Ida0165e647545069c0d42d38b9f45a95e78dacbe Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47693 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
* arch/x86: Introduce `ARCH_ALL_STAGES_X86_32`Angel Pons2020-09-262-8/+2
| | | | | | | | | | | | | Nearly every x86 platform uses the same arch for all stages. The only exception is Picasso. So, factor out redundant symbols from the rest. Alder Lake is not yet complete, so it has been skipped for now. Change-Id: I7cff9efbc44546807d9af089292c69fb0acc7bad Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45731 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
* src/cpu: Drop unneeded empty linesElyes HAOUAS2020-09-211-1/+0
| | | | | | | | Change-Id: I116b15c83fcc5d69d3f80a2e6cf0fb085064d9a6 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44604 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
* arch/x86: Drop CBMEM_TOP_BACKUPKyösti Mälkki2020-07-111-1/+1
| | | | | | | | | | | | | Code has evolved such that there seems to be little use for global definition of cbmem_top_chipset(). Even for AMD we had three different implementations. Change-Id: I44805aa49eab526b940e57bd51cd1d9ae0377b4b Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43326 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* ACPI: Replace smm_setup_structures()Kyösti Mälkki2020-06-242-0/+2
| | | | | | | | | | | | | | Except for whitespace and varying casts the codes were the same when implemented. Platforms that did not implement this are tagged with ACPI_NO_SMI_GNVS. Change-Id: I31ec85ebce03d0d472403806969f863e4ca03b6b Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42362 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
* arch/x86: Remove NO_FIXED_XIP_ROM_SIZEKyösti Mälkki2020-06-152-2/+0
| | | | | | | | | | | The variable SETUP_XIP_CACHE provides us a working alternative. Change-Id: I6e3befedbbc7967b71409640dc81a0c2a9b3e511 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41821 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
* amd/00730F01: Clean the Microcode updatingZheng Bao2020-06-104-157/+116
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | According to the comments of https://review.coreboot.org/c/coreboot/+/41719 , which is about Microcode patch for amd/picasso. Change the code with the same way. The changes include: 1. combine the microcode_xxx.c and update_microcode.c into one source. 2. Redefine the microcode updating function to eliminate the parameter. Get the revision ID in the black box. Reduce the depth of function calls. 3. Get the revision ID by bitwise calculation instead of lookup table. 4. Reduce the confusing type casts. 5. Squash some lines. We do not change the way it used to be. The code assume only one microcode is integrated in CBFS. If needed in future, 41719 is the example of integrating multiple binaries. And, 41719 depends on the definition in this patch. Change-Id: I8b0da99db0d3189058f75e199f05492c4e6c5881 Signed-off-by: Zheng Bao <zheng.bao@amd.com> Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42094 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
generated by cgit v1.2.3 (git 2.25.1) at 2024-06-19 23:49:37 +0000