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* cpu/intel/model_2065x: Read CPU voltage for SMBIOSPatrick Rudolph2023-11-141-0/+1
* cpu/x86/smm: Fix get_save_state calculationEugene D. Myers2023-11-102-5/+4
* Allow to build romstage sources inside the bootblockArthur Heymans2023-11-091-1/+1
* Revert "Kconfig: Bring HEAP_SIZE to a common, large value"Patrick Georgi2023-11-071-0/+3
* cpu/intel/common: Define build time physical address reserved bitsJeremy Compostella2023-10-202-0/+11
* x86: Add pre-memory stages CBFS cache scratchpad supportJeremy Compostella2023-10-207-0/+21
* Kconfig: Bring HEAP_SIZE to a common, large valuePatrick Georgi2023-10-111-3/+0
* cpu/intel/model_206ax: Only use supported C-statesPatrick Rudolph2023-10-061-5/+59
* cpu/intel/model_206ax: Use haswell cstate_mapPatrick Rudolph2023-10-062-50/+37
* cpu/intel/model_206ax: Print supported C-statesPatrick Rudolph2023-10-061-1/+21
* cpu/intel/socket_BGA956: Double DCACHE_RAM_SIZE to 64 kBArthur Heymans2023-10-051-1/+1
* arch/x86/Kconfig: introduce RESERVED_PHYSICAL_ADDRESS_BITS_SUPPORTFelix Held2023-09-291-0/+1
* */include/cpu: use unsigned int for number of address bitsFelix Held2023-09-291-2/+2
* cpu/x86/mtrr/debug: rename variables in display_variable_mtrrFelix Held2023-09-201-10/+10
* cpu/x86/mtrr/debug: use MTRR_PHYS_MASKFelix Held2023-09-201-3/+2
* cpu/x86/mtrr/debug: use msr_t parameter in display_mtrr_fixed_typesFelix Held2023-09-201-6/+6
* cpu/x86/mtrr/debug: make local MSR variables constFelix Held2023-09-201-7/+7
* cpu/x86/mtrr/debug: drop unnecessary MSR unionFelix Held2023-09-201-55/+25
* x86: Add .data section support for pre-memory stagesJeremy Compostella2023-09-146-0/+53
* arch/x86: Reduce max phys address size for Intel TME capable SoCsJeremy Compostella2023-09-122-0/+27
* cpu/intel: Move is_tme_supported() from soc/intel to cpu/intelJeremy Compostella2023-09-123-0/+20
* arch to drivers/intel: Fix misspellings & capitalization issuesMartin Roth2023-09-082-2/+2
* cpu/x86/smm: Don't save EFERArthur Heymans2023-08-211-38/+5
* cpu/amd/pi/00730F01: Use common code for mp_initArthur Heymans2023-08-081-0/+1
* cpu: Add SPDX license headers to MakefilesMartin Roth2023-08-0638-0/+76
* src/*/post_code.h: Change post code prefix to POSTCODEYuchen He2023-08-056-45/+45
* cpu: Get rid of CPU_SPECIFIC_OPTIONSElyes Haouas2023-08-0411-54/+21
* cpu/amd/mtrr: Use newer function for resource declarationArthur Heymans2023-07-121-1/+1
* cpu/intel/microcode: Drop unnecessary alignment for split microcodeSubrata Banik2023-07-121-1/+1
* cpu/x86/lapic: Fix regression with X2APIC_LATE_WORKAROUNDKyösti Mälkki2023-07-081-1/+7
* cpu: Enable per-CPUID microcode loading in CBFSSubrata Banik2023-07-085-6/+110
* cpu/intel/microcode: Avoid Pre-RAM microcode update if FIT enableSubrata Banik2023-07-081-0/+1
* cpu/x86: Add some notes about XAPIC/X2APICKyösti Mälkki2023-07-061-0/+10
* cpu/x86/lapic: Fix X2APIC_ONLY regressionKyösti Mälkki2023-07-061-0/+2
* cpu/x86: Reduce scope of MTRR functions used locallyKyösti Mälkki2023-07-031-2/+2
* commonlib/console/post_code.h: Change post code prefix to POSTCODElilacious2023-06-237-12/+12
* cpu/x86/smm: Drop fxsave/fxrstor logicArthur Heymans2023-06-042-72/+15
* cpu/x86/mp_init: Use clflush to write SIPI data back to RAMJeremy Compostella2023-05-312-11/+12
* libpayload;arch,cpu/x86: drop USE_MARCH_586 Kconfig optionFelix Held2023-05-271-2/+0
* cpu/intel/haswell: Add Broadwell Trad µcode updatesAngel Pons2023-05-271-0/+2
* cpu/x86/sse_enable.inc: Remove unused fileArthur Heymans2023-05-261-12/+0
* cpu/Kconfig: Remove MMX config optionArthur Heymans2023-05-2510-15/+0
* cpu/x86/smm_stub.S: Fix commentArthur Heymans2023-05-231-1/+1
* cpu/x86/smm_stub.S: Update commentArthur Heymans2023-05-231-1/+1
* Kconfig: Get rid of named choice LAPIC_ACCESS_MODEMartin Roth2023-05-211-4/+4
* cpu/qemu-x86/cache_as_ram_bootblock: drop duplicated post codeAlexander Goncharov2023-05-181-2/+0
* cpu/amd/pi/00730f01/Kconfig: use hexadecimal CPU number in ACPIFelix Held2023-05-161-1/+1
* acpi/Kconfig: move \_SB scope out of ACPI_CPU_STRINGFelix Held2023-05-131-1/+1
* cpu,nb/amd/pi/00730F01: dynamically generate CPU devicesFelix Held2023-05-132-48/+8
* treewide: Add missing include guards to chip.hJan Samek2023-04-283-0/+15
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