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* Remove CACHE_ROM.Vladimir Serbinenko2014-02-254-101/+0
| | | | | | | | | | | | | | | | | | | | | | | | With the recent improvement 3d6ffe76f8a505c2dff5d5c6146da3d63dad6e82, speedup by CACHE_ROM is reduced a lot. On the other hand this makes coreboot run out of MTRRs depending on system configuration, hence screwing up I/O access and cache coherency in worst cases. CACHE_ROM requires the user to sanity check their boot output because the feature is brittle. The working configuration is dependent on I/O hole size, ram size, and chipset. Because of this the current implementation can leave a system configured in an inconsistent state leading to unexpected results such as poor performance and/or inconsistent cache-coherency Remove this as a buggy feature until we figure out how to do it properly if necessary. Change-Id: I858d78a907bf042fcc21fdf7a2bf899e9f6b591d Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/5146 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@google.com>
* TI am335x: Apply Kconfig use conventionsKyösti Mälkki2014-02-242-11/+13
| | | | | | | | Change-Id: Ic3c26fd7b1dd8a6731abc9a63b9ca17e084074b2 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/5291 Tested-by: build bot (Jenkins) Reviewed-by: Vladimir Serbinenko <phcoder@gmail.com>
* CAR_GLOBAL: enforce compiler to check if _start != _endEdward O'Callaghan2014-02-241-2/+1
| | | | | | | | | | | | | | There are some fun rules C compilers can use to optimize their code. One of them is the assumption that two symbols point to two different addresses. In this case this wasn't true, resulting in unintended code execution (and later, a crash) with a clang build. Change-Id: I1496b22e1d1869ed0610e321b6ec6a83252e9d8b Signed-off-by: Patrick Georgi <patrick@georgi-clan.de> Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-on: http://review.coreboot.org/4719 Tested-by: build bot (Jenkins)
* intel/model_2065x: Fix APICID generation.Vladimir Serbinenko2014-02-201-5/+2
| | | | | | | | | | APIC IDs always step by 4 on 2065x independently of number of threads. Change-Id: I5abd4005c8ce1740bb0862d952af66236b609aa8 Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/5262 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
* SMM: Fixes for DEBUG_SMIKyösti Mälkki2014-02-201-3/+2
| | | | | | | | | | | | Get the required UART includes directly. The ne2k part is old copy-paste leftover. Change-Id: Ifd9253abb5a50b515887459faf06b63f907eeda9 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/5258 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Aaron Durbin <adurbin@google.com>
* x86 bootblock: improve clang compatibilityPatrick Georgi2014-02-192-3/+3
| | | | | | | | | | | | Its linker doesn't like "." arithmetics, so use .org, while its assembler doesn't like data32 prefixes. Change-Id: I3f5bbb350493d6510b8013df15d44c44c5db63c7 Signed-off-by: Patrick Georgi <patrick@georgi-clan.de> Reviewed-on: http://review.coreboot.org/4714 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
* haswell: backup the default SMM region on resumeAaron Durbin2014-02-162-0/+9
| | | | | | | | | | | | | | Haswell CPUs need to use the default SMM region for relocating to the desired SMM location. Back up that memory on resume instead of reserving the default region. This makes the haswell support more forgiving to software which expects PC-compatible memory layouts. Change-Id: I9ae74f1f14fe07ba9a0027260d6e65faa6ea2aed Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/5217 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@google.com>
* x86: provide infrastructure to backup default SMM regionAaron Durbin2014-02-163-0/+76
| | | | | | | | | | | | | | Certain CPUs require the default SMM region to be backed up on resume after a suspend. The reason is that in order to relocate the SMM region the default SMM region has to be used. As coreboot is unaware of how that memory is used it needs to be backed up. Therefore provide a common method for doing this. Change-Id: I65fe1317dc0b2203cb29118564fdba995770ffea Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/5216 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@google.com>
* coreboot: infrastructure for different ramstage loadersAaron Durbin2014-02-151-2/+0
| | | | | | | | | | | | | | | | | | | | | | There are 2 methods currently available in coreboot to load ramstage from romstage: cbfs and vboot. The vboot path had to be explicitly enabled and code needed to be added to each chipset to support both. Additionally, many of the paths were duplicated between the two. An additional complication is the presence of having a relocatable ramstage which creates another path with duplication. To rectify this situation provide a common API through the use of a callback to load the ramstage. The rest of the existing logic to handle all the various cases is put in a common place. Change-Id: I5268ce70686cc0d121161a775c3a86ea38a4d8ae Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/5087 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
* cpu/allwinner/a10: Add minimal ramstage driverAlexandru Gagniuc2014-02-135-0/+110
| | | | | | | | | Change-Id: I857755976b17b0e492c086162f395a77933eeed8 Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Reviewed-on: http://review.coreboot.org/4698 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
* PCI: Drop includes under cpuKyösti Mälkki2014-02-1235-39/+0
| | | | | | | | | | | | | The files affected do not make any PCI configuration calls. If they did, the more correct includes would be pci_ops.h, pci_defs.h and pci_ids.h. Change-Id: I3e7f009371be6ea50318eaabf0c15500cb3f1210 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/5200 Reviewed-by: Aaron Durbin <adurbin@google.com> Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Tested-by: build bot (Jenkins)
* SMP: Add arch-agnostic boot_cpu()Kyösti Mälkki2014-02-111-1/+1
| | | | | | | | | | | We should not have x86 specific includes in lib/. Change-Id: I18fa9c8017d65c166ffd465038d71f35b30d6f3d Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/5156 Tested-by: build bot (Jenkins) Reviewed-by: David Hendricks <dhendrix@chromium.org> Reviewed-by: Aaron Durbin <adurbin@google.com>
* mtrr: only add prefetchable resources as WRCOMB for VGA devicesAaron Durbin2014-02-091-2/+17
| | | | | | | | | | | | | | | | | Be more conservative and only add VGA devices' prefetchable resources as write-combining in the address space. Previously all prefetchable memory was added as a write-combining memory type. Some hardware incorrectly advertises its BAR as prefetchable when it shouldn't be. A new memranges_add_resources_filter() function is added to provide additional filtering on device and resource. Change-Id: I3fc55b90d8c5b694c5aa9e2f34db1b4ef845ce10 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/5169 Reviewed-by: Vladimir Serbinenko <phcoder@gmail.com> Tested-by: build bot (Jenkins)
* ARMv7: Remove static CBMEM allocationKyösti Mälkki2014-02-063-13/+0
| | | | | | | | | | | The calculations for static allocation are no longer valid. Change-Id: I6740cdcec789abddf78485a0edaf24882ef8c2a5 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/4569 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: David Hendricks <dhendrix@chromium.org>
* usbdebug: Drop obsolete codeKyösti Mälkki2014-02-061-16/+0
| | | | | | | | | Change-Id: I918ca1d0d0d7bcb7e16d41a12830a0357f15b8ed Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/5130 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
* MTRR: Mark all prefetchable resources as WRCOMB.Vladimir Serbinenko2014-02-061-3/+2
| | | | | | | | Change-Id: I2ecfd9733b65b6160bc2232d22db7b16692a847f Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/5149 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@google.com>
* mtrr: retry fitting w/o WRCOMB if usage exceeds BIOS allocationAaron Durbin2014-02-061-2/+25
| | | | | | | | | | | If the MTRR usage exceeds the BIOS allocation for MTRR usage re-try without the WRCOMB type. Change-Id: Ie70ce84994428ff6700c36310264c3c44d9ed128 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/5151 Reviewed-by: Vladimir Serbinenko <phcoder@gmail.com> Tested-by: build bot (Jenkins)
* cpu/amd/model_fxx: Add coolnquiet for two new (old) AMD K8 modelsOskar Enoksson2014-02-031-0/+8
| | | | | | | | | | | | | | | | The added CPU's are OSA248CEP5AU and a OSP280 processors. The OSP280 VID/FID numbers have been found by experimentation and extrapolation/guesses from similar models. It has been verified to work fine under Linux (OpenSuse 12.2, kernel 3.4.63-2.44) with four different test-processors. Windows is untested. Change-Id: I3afa1cba5f55c8a78917b3636382af7706a80fee Signed-off-by: Oskar Enoksson <enok@lysator.liu.se> Reviewed-on: http://review.coreboot.org/5095 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Rudolf Marek <r.marek@assembler.cz>
* cpu/intel/model_2065x: Add model 20652Vladimir Serbinenko2014-02-011-0/+1
| | | | | | | | | | | Found in some X201t. Tested on X201t. Change-Id: I3fc4c3f5b1abf9fe61746ab8f401d1b6ee67f3ea Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/5090 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
* cpu/intel: allow non-packaged scoped turbo settingAaron Durbin2014-01-303-2/+32
| | | | | | | | | | | | | | | | | | | | | | | In the past the turbo disable setting (bit 38) of the IA32_MISC_ENABLES msr has been package scoped. That means knocking the turbo disable bit down enabled turbo for the entire package. Sadly, that's no longer true on all Intel processors. Therefore, allow non-packaged scoped turbo setting by introducing the CPU_INTEL_TURBO_NOT_PACKAGE_SCOPED Kconfig option. It defaults to false which was the original assumption. BUG=chrome-os-partner:25014 BRANCH=baytrail TEST=Built and ran both ways successfully. Change-Id: I71a31e76ff47878023081fc47da643187517b597 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/182405 Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: http://review.coreboot.org/5047 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
* x86: Add SMM helper functions to MP infrastructureAaron Durbin2014-01-301-0/+31
| | | | | | | | | | | | | | | | | | | | | In order for the cpu code to start SMM relocation 2 new functions are added to be shared: - void smm_initiate_relocation_parallel() - void smm_initiate_relocation() The both initiate an SMI on the currently running cpu. The 2 variants allow for parallel relocation or serialized relocation. BUG=chrome-os-partner:22862 BRANCH=None TEST=Built and booted rambi using these functions. Change-Id: I325777bac27e9a0efc3f54f7223c38310604c5a2 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/173982 Reviewed-on: http://review.coreboot.org/4891 Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Tested-by: build bot (Jenkins)
* x86: parallel MP initializationAaron Durbin2014-01-305-0/+816
| | | | | | | | | | | | | | | | | | | | | | | | | | | Provide a common entry point for bringing up the APs in parallel. This work is based off of the Haswell one which can be moved over to this in the future. The APs are brought up and have the BSP's MTRRs duplicated in their own MTRRs. Additionally, Microcode is loaded before enabling caching. However, the current microcode loading support assumes Intel's mechanism. The infrastructure provides a notion of a flight plan for the BSP and APs. This allows for flexibility in the order of operations for a given architecture/chip without providing any specific policy. Therefore, the chipset caller can provide the order that is required. BUG=chrome-os-partner:22862 BRANCH=None TEST=Built and booted on rambi with baytrail specific patches. Change-Id: I0539047a1b24c13ef278695737cdba3b9344c820 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/173703 Reviewed-on: http://review.coreboot.org/4888 Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Tested-by: build bot (Jenkins)
* coreboot: config to cache ramstage outside CBMEMAaron Durbin2014-01-302-72/+10
| | | | | | | | | | | | | | | | | | | | | | Haswell was the original chipset to store the cache in another area besides CBMEM. However, it was specific to the implementation. Instead, provide a generic way to obtain the location of the ramstage cache. This option is selected using the CACHE_RELOCATED_RAMSTAGE_OUTSIDE_CBMEM Kconfig option. BUG=chrome-os-partner:23249 BRANCH=None TEST=Built and booted with baytrail support. Also built for falco successfully. Change-Id: I70d0940f7a8f73640c92a75fd22588c2c234241b Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/172602 Reviewed-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/4876 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
* vboot: provide empty vboot_verify_firmware()Aaron Durbin2014-01-301-2/+0
| | | | | | | | | | | | | | | | | | | | In the case of CONFIG_VBOOT_VERIFY_FIRMWARE not being selected allow for calling vboot_verify_firmware() with an empty implementation. This allows for one not to clutter the source with ifdefs. BUG=chrome-os-partner:23249 BRANCH=None TEST=Built with a !CONFIG_VBOOT_VERIFY_FIRMWARE and non-guarded call to vboot_verify_firmware(). Change-Id: I72af717ede3c5d1db2a1f8e586fefcca82b191d5 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/172711 Reviewed-by: Shawn Nematbakhsh <shawnn@chromium.org> Reviewed-on: http://review.coreboot.org/4879 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
* x86: add common definitions for control registersAaron Durbin2014-01-281-23/+4
| | | | | | | | | | | | | | | | | | | The access to control registers were scattered about. Provide a single header file to provide the correct access function and definitions. BUG=chrome-os-partner:22991 BRANCH=None TEST=Built and booted using this infrastructure. Also objdump'd the assembly to ensure consistency (objdump -d -r -S | grep xmm). Change-Id: Iff7a043e4e5ba930a6a77f968f1fcc14784214e9 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/172641 Reviewed-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/4873 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
* intel: fix microcode compilation failure in bootblockAaron Durbin2014-01-281-10/+8
| | | | | | | | | | | | | | When not building with CONFIG_SSE there are not enough registers for ROMCC to use for spilling. The previous changes to this file had too many local variables that needed to be tracked -- thus causing romcc compilation issues. Change-Id: I3dd4b48be707f41ce273285e98ebd397c32a6a25 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/4845 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
* src/cpu: Fix spelling of MTTR to MTRRPaul Menzel2014-01-265-28/+28
| | | | | | | | Change-Id: Ia4718ac31a5b2bd12f8cda5e107aa878d74d2a03 Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-on: http://review.coreboot.org/4805 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
* intel/microcode: Remove leftover MICROCODE_INCLUDE_PATH.Vladimir Serbinenko2014-01-233-11/+0
| | | | | | | | | | Not used anymore since microcode was moved. Change-Id: Id666c80cb20e90e3664c4dcfcc0c41a4aeb4864c Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/4788 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
* AMD K8/fam10: Fix CBMEM on S3 resumeKyösti Mälkki2014-01-221-1/+1
| | | | | | | | | | | Change to use cbmem_recovery() to wipe CBMEM region and reset ACPI wakeup if CBMEM TOC was not found. Change-Id: Ic362253eaa00bd442d4cc0514632f9096e20bfa6 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/4673 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@google.com>
* AMD AGESA: Fix CBMEM on S3 resumeKyösti Mälkki2014-01-221-1/+1
| | | | | | | | | | | Change to use cbmem_recovery() to wipe CBMEM region and reset ACPI wakeup if CBMEM TOC was not found. Change-Id: I6648570d76b5c137f50addcc5bce9c126d179c65 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/4672 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@google.com>
* cpu/intel: Remove dummy terminators from microcode blobsAlexandru Gagniuc2014-01-1620-138/+0
| | | | | | | | | | | | Now that CBFS microcode no longer requires a NULL termination, remove the dummy terminators from all microcode blobs. This also enables microcode blobs from different CPU models to be linked in the same cpu_microcode_blob.bin without the terminators getting in the way. Change-Id: I25a6454780fd5d56ae7660b0733ac4f8c4d90096 Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Reviewed-on: http://review.coreboot.org/4506 Tested-by: build bot (Jenkins)
* cpu/intel: Make all Intel CPUs load microcode from CBFSAlexandru Gagniuc2014-01-1672-434/+390
| | | | | | | | | | | | | | | | | | | | | The sequence to inject microcode updates is virtually the same for all Intel CPUs. The same function is used to inject the update in both CBFS and hardcoded cases, and in both of these cases, the microcode resides in the ROM. This should be a safe change across the board. The function which loaded compiled-in microcode is also removed here in order to prevent it from being used in the future. The dummy terminators from microcode need to be removed if this change is to work when generating microcode from several microcode_blob.c files, as is the case for older socketed CPUs. Removal of dummy terminators is done in a subsequent patch. Change-Id: I2cc8220cc4cd4a87aa7fc750e6c60ccdfa9986e9 Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Reviewed-on: http://review.coreboot.org/4495 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@gmail.com>
* cpu/amd/model_fxx/powernow_acpi.c: Comment out set but unused variable ↵Paul Menzel2014-01-151-2/+2
| | | | | | | | | | | | | | | | `Start_vid` When adding support for PSS object generation for AMD pre Family Fh CPUs (199c694f) the function `pstates_algorithm` was copied and adapted, but `Start_vid` is not needed anymore as a static table is used. I’d remove the variable, but Ron Minnich requested to leave it there for documentation purposes. So just comment it out. Change-Id: I3002951d168cade6461941c16d78373c47792e13 Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-on: http://review.coreboot.org/4036 Tested-by: build bot (Jenkins) Reviewed-by: Rudolf Marek <r.marek@assembler.cz>
* nehalem/sandy/ivy/haswell: Enable WRPROT cache for all of flashKyösti Mälkki2014-01-153-4/+3
| | | | | | | | | | | | | CBFS could start from below 4MB, and should be cacheable for the purpose of early microcode update and CBFS search for romstage file. Change-Id: Ia2a1c6e5fdcc3201fafc8cf5c841cebbbf0b30c9 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/4626 Tested-by: build bot (Jenkins) Reviewed-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Aaron Durbin <adurbin@google.com>
* Re-declare CACHE_ROM_SIZE as aligned ROM_SIZE for MTRRKyösti Mälkki2014-01-157-14/+14
| | | | | | | | | | | | | | | | | | | | | | | | This change allows Kconfig options ROM_SIZE and CBFS_SIZE to be set with values that are not power of 2. The region programmed as WB cacheable will include all of ROM_SIZE. Side-effects to consider: Memory region below flash may be tagged WRPROT cacheable. As an example, with ROM_SIZE of 12 MB, CACHE_ROM_SIZE would be 16 MB. Since this can overlap CAR, we add an explicit test and fail on compile should this happen. To work around this problem, one needs to use CACHE_ROM_SIZE_OVERRIDE in the mainboard Kconfig and define a smaller region for WB cache. With this change flash regions outside CBFS are also tagged WRPROT cacheable. This covers IFD and ME and sections ChromeOS may use. Change-Id: I5e577900ff7e91606bef6d80033caaed721ce4bf Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/4625 Tested-by: build bot (Jenkins) Reviewed-by: Vladimir Serbinenko <phcoder@gmail.com>
* cpu/allwinner/a10: Clarify positioning of boot stagesAlexandru Gagniuc2014-01-141-4/+8
| | | | | | | | | | | This fixes a number of potential issues, such as generating a build failure if the bootblock is too large, and making sure romstage and ramstage cannot overlap in memory. Change-Id: I4ca9ad097b145445316bcd962e007731b08a7fda Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Reviewed-on: http://review.coreboot.org/4687 Tested-by: build bot (Jenkins)
* cpu/allwinner/a10: Add helper to configure CPU clockAlexandru Gagniuc2014-01-142-0/+158
| | | | | | | | Change-Id: I5a3bb3220aeefdd6822a7dbecf210ff77095dad6 Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Reviewed-on: http://review.coreboot.org/4685 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
* cpu/allwinner/a10: Provide utility to make a bootable imageAlexandru Gagniuc2014-01-131-10/+19
| | | | | | | | | | | | | | | | | | Up until now, we relied on mksunxiboot to prepend the header which makes coreboot.rom bootable on Allwinner SoCs. If that tool was not present, the build silently failed. Integrate this tool into our util/ package, so that we do not have to rely on mksunxiboot being in PATH. Our version of mksunxiboot also eliminates some limitations of the original tool, so we no longer have to use 'dd' to limit the file size. Change-Id: Id5a4b1e2a3cb00cd1d6c70e6cbc3cfd8587e8a24 Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Reviewed-on: http://review.coreboot.org/4656 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
* cpu/allwinner/a10: Clean up include order in Makefile.incAlexandru Gagniuc2014-01-131-8/+12
| | | | | | | | | | | Alphabetize the sources for each stage (bootblock, rom, ram), and include twi.c in both romstage and ramstage. Change-Id: I5526f5a66f6600560005731a3ee536eb858f4ff0 Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Reviewed-on: http://review.coreboot.org/4639 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
* CBFS: use cbfs_get_file_content whenever possible rather than cbfs_get_fileVladimir Serbinenko2014-01-121-10/+10
| | | | | | | | | | | Number one reason to use cbfs_get_file was to get file length. With previous patch no more need for this. Change-Id: I330dda914d800c991757c5967b11963276ba9e00 Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/4674 Reviewed-by: Patrick Georgi <patrick@georgi-clan.de> Tested-by: build bot (Jenkins)
* intel/fsp: Fix microcode includingPatrick Georgi2014-01-111-2/+0
| | | | | | | | | | | IS_ENABLED() requires the full define (incl. CONFIG_ prefix) but isn't needed here. Change-Id: I91d504367c75ce3fcecc6fa2499afaa0896595d3 Signed-off-by: Patrick Georgi <patrick@georgi-clan.de> Reviewed-on: http://review.coreboot.org/4646 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
* cpu/allwinner/a10: Import raminit code from ubootAlexandru Gagniuc2014-01-092-0/+644
| | | | | | | | | | | | | | | | The memory initialization code is a work in progress for uboot, so we only import the bits needed to get RAM up and running. Any refactoring is cosmetic, and any functional refactoring should be done in separate patches, and preferably, in coordination with the sunxi team. Since it's not yet determined if we should initialize memory during the bootblock or romstage, we don't add raminit to the build just yet. Change-Id: I2ec1821942c6970150a02fa3806a257da649e1c9 Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Reviewed-on: http://review.coreboot.org/4597 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: David Hendricks <dhendrix@chromium.org>
* cpu/allwinner/a10: Add low-level helpers for DRAM clock controlAlexandru Gagniuc2014-01-092-0/+109
| | | | | | | | | | | | PLL5 is special in that it controls the DRAM clock, and requires a fine-grained low-level control which will be needed by raminit code. This change also brings functionality which will be needed by raminit. Change-Id: I25ecc91aa2154e504ceebb9003a5e5728d47f4a3 Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Reviewed-on: http://review.coreboot.org/4593 Tested-by: build bot (Jenkins)
* cubieboard: Initialize memory in bootblockAlexandru Gagniuc2014-01-091-0/+2
| | | | | | | | | | | | | | Even though the Allwinner A10 is limited to a 24KiB bootblock, the memory initialization takes only about 3KiB and leaves enough room for an MMC or NAND driver, so init the memory early on. The advantage is that we can eliminate complicated logistics of where to cache CBFS and where to load the ramstage in SRAM. Change-Id: Id549552ed509434e831db60deaef28e04d62417f Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Reviewed-on: http://review.coreboot.org/4630 Tested-by: build bot (Jenkins) Reviewed-by: David Hendricks <dhendrix@chromium.org>
* cpu/allwinner/a10: Add functions for driving GPIO pinsAlexandru Gagniuc2014-01-093-0/+107
| | | | | | | | | Change-Id: I9473a6e574c3af02d154a7e30245f0dc0b238300 Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Reviewed-on: http://review.coreboot.org/4599 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: David Hendricks <dhendrix@chromium.org>
* cpu/allwinner/a10: Add definitions for in/output GPIO functionsAlexandru Gagniuc2014-01-091-0/+4
| | | | | | | | | Change-Id: I2b857d3b4c01e39c62e54f753e400e6049f1dbc9 Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Reviewed-on: http://review.coreboot.org/4598 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: David Hendricks <dhendrix@chromium.org>
* cpu/allwinner/a10: Add function for reading chip revisionAlexandru Gagniuc2014-01-092-0/+20
| | | | | | | | | Change-Id: Iafbd253235db3914b9382fdb41de2622ef83c6d8 Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Reviewed-on: http://review.coreboot.org/4596 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: David Hendricks <dhendrix@chromium.org>
* cpu/allwinner/a10: Implement udelay using timer 0Alexandru Gagniuc2014-01-093-3/+130
| | | | | | | | | Change-Id: I4825f0d57696cd28751c59ae133b7e3315fb78e5 Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Reviewed-on: http://review.coreboot.org/4595 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: David Hendricks <dhendrix@chromium.org>
* cpu/allwinner/a10: Add definition for gating GPIO S clockAlexandru Gagniuc2014-01-091-0/+2
| | | | | | | | | | | | This bit is not documented in the datasheet, but is used in the upcoming RAM init code. Change-Id: I697ec222496236ac7690460ee62313ab8b1a2f0b Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Reviewed-on: http://review.coreboot.org/4592 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: David Hendricks <dhendrix@chromium.org>
* cpu/allwinner/a10: Add basic TWI (I²C) driverAlexandru Gagniuc2014-01-083-0/+265
| | | | | | | | | Change-Id: I11b10301199e5ff1a45d9b7d2958cc7b6667a29c Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Reviewed-on: http://review.coreboot.org/4588 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
generated by cgit v1.2.3 (git 2.25.1) at 2024-08-10 03:19:58 +0000