summaryrefslogtreecommitdiffstats
path: root/src/drivers
Commit message (Collapse)AuthorAgeFilesLines
* payloads/tianocore: Remove the option for CorebootPayloadPkgSean Rhodes2022-08-071-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | Recent changes to both coreboot and edk2 means that UefiPayloadPkg seems to work on all hardware. It has been tested on: * Intel Core 2nd, 3rd, 4th, 5th, 6th, 8th, 8th, 9th, 10th, 11th and 12th generation processors * Intel Small Core BYT, BSW, APL, GLK and GLK-R processors * AMD Stoney Ridge and Picasso This includes the problematic Lenovo X230s. The most likely fixes are: * Configuring the PCI Base and Length in edk2 * Fixes to the HostBridgeLib in edk2 * Adjustment to the SD/eMMC initialisation timeout This means we can now remove the already deprecated option for CorebootPayloadPkg and the legacy 8254 timer build option. Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: Ice7b7576eb3d32ea46e5138266b7df3fbcdcf7ea Reviewed-on: https://review.coreboot.org/c/coreboot/+/65721 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
* drivers/i2c/dw_i2c: Re-add check for empty i2c transfer listNico Huber2022-08-031-1/+1
| | | | | | | | | | | | | The check was recently removed to allow callers to pass `count == 0`. Dereferencing the `msg` array is invalid in that case, though. Linux, where we borrowed the i2c interface from, also treats this with -EINVAL. Change-Id: I1eec02dd3a3fcf2d477a62cc65292fca40e469d3 Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/66341 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-by: Tim Crawford <tcrawford@system76.com>
* drivers/elog: Use format stringMatei Dibu2022-08-011-1/+1
| | | | | | | | | | | | | | | | | | clang shows the warning below: src/drivers/elog/elog.c:171:13: error: format string is not a string literal (potentially insecure) [-Werror,-Wformat-security] elog_debug(msg); ^~~ Found-by: clang (13.0.1) Change-Id: I3f8949f9ce0c4ef4823530c61c503b0883bb5efc Signed-off-by: Matei Dibu <matdibu@protonmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/66262 Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
* drivers/wifi/generic: Revert changes to generate missing SSDT for PCIeReka Norman2022-07-272-28/+17
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | wifi This reverts commit 5e6fd360de7fe92f1e8b1b3eb20241809e2a6aff. On nereid, the SSDT entry for the PCIe wifi device is missing, causing wake-on-WLAN not to work since the _PRW is missing. It seems like when commit 5e6fd360de changed the SSDT generation logic for CNVi and PCIe wifi, it broke the PCIe case. `wifi_pcie_ops` are never assigned to any device, so `parent && parent->ops == &wifi_pcie_ops` always returns false, and the `wifi_cnvi_ops` are used even for PCIe devices. Undo the changes in that CL. This allows both the CNVi and PCIe cases to work. That CL was meant to fix an issue with the CNVi _PRW containing garbage, but I can't reproduce this when the change is undone. It was also meant to fix the following error on CNVi devices, but I don't see any errors with this change: [ERROR] NONE missing set_resources BUB=b:233325709 TEST=On both nivviks (CNVi) and nereid (PCIe), check that the SSDT contains the correct wifi device entries (below), including a _PRW containing the correct GPE, and check that wake-on-WLAN works. nivviks: ``` Scope (\_SB.PCI0.CNVW) { Name (_PRW, Package (0x02) // _PRW: Power Resources for Wake { 0x6D, 0x03 }) Method (_DSM, 4, Serialized) // _DSM: Device-Specific Method { <snip> } } ``` nereid: ``` Device (\_SB.PCI0.RP01.WF00) { Name (_UID, 0x923ACF1C) // _UID: Unique ID Name (_DDN, "WIFI Device") // _DDN: DOS Device Name Name (_ADR, 0x0000000000000000) // _ADR: Address } Scope (\_SB.PCI0.RP01.WF00) { Name (_PRW, Package (0x02) // _PRW: Power Resources for Wake { 0x23, 0x03 }) Method (_DSM, 4, Serialized) // _DSM: Device-Specific Method { <snip> } } ``` Fixes: 5e6fd360de ("drivers/wifi/generic: Fix properties in generic-under-PCI device case") Change-Id: I100c5ee3842997c50444e5ce68d583834ed3a8ad Signed-off-by: Reka Norman <rekanorman@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/66063 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Kangheui Won <khwon@chromium.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* drivers/pci/generic: Add support for `_PRW`Robert Zieba2022-07-202-0/+5
| | | | | | | | | | | | | This commit adds support for `_PRW` in this driver. BUG=b:237682766 TEST=Built and booted on Skyrim device, dumped SSDT Change-Id: Ife4ba48994cbf993bc88df8354576336438e4258 Signed-off-by: Robert Zieba <robertzieba@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/65799 Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* drivers/pcie/generic: Add support for custom ACPI nameRobert Zieba2022-07-202-1/+7
| | | | | | | | | | | | | | This commit adds code to allow the driver to use an ACPI device name that is set in the device tree. BUG=b:237682766 TEST=Boot changes on Skyrim device, dumped SSDT Signed-off-by: Robert Zieba <robertzieba@google.com> Change-Id: Ie40a335e35b8ac83658e67d7cfba0750dd4784ad Reviewed-on: https://review.coreboot.org/c/coreboot/+/65798 Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* drivers/pcie/generic: Clean up driverRobert Zieba2022-07-202-29/+7
| | | | | | | | | | | | | | | | | | This removes unneeded and unused functionality in the driver as part of an effort to make the driver more generic and useful. The things that have been removed are: `DmaProperty` and its associated `is_untrusted` config, `_DSD` generation, and the companion device functionality. This driver isn't currently used anywhere so there won't be any issues from removing the above functionality. BUG=b:237682766 TEST=Built and booted coreboot on Skyrim device Change-Id: I0abd9148ab66ea9426069102ecc8c2fa77fea98e Signed-off-by: Robert Zieba <robertzieba@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/65797 Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* drivers/amd/agesa: Fix some white spaces issuesElyes Haouas2022-07-176-44/+44
| | | | | | | | Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Change-Id: I0a11d303d2e2c83cb72773656f5caedec666dc66 Reviewed-on: https://review.coreboot.org/c/coreboot/+/65898 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
* src/drivers/intel/i210: Remove unuseful 'return' in void functionElyes HAOUAS2022-07-171-1/+0
| | | | | | | | Change-Id: Id33ef66e7388df2173ee8888265ed4379f05a93e Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/61548 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <felixsinger@posteo.net>
* drivers: Get rid of unnecessary blank lines {before,after} braceElyes HAOUAS2022-07-1722-29/+1
| | | | | | | | Change-Id: Ic1b38e93d919c1286a8d130700a4a2bfd6b55258 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/61557 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <felixsinger@posteo.net>
* drivers/intel/dptf: Correct UID for TBAT deviceVarshit B Pandya2022-07-161-1/+1
| | | | | | | | | | | | | | | | | | | | As per Intel Dynamic Tuning Spec revision 1.3.13, section 14.1.2 TBAT _UID should match the _UID implemented for battery device ACPI object for OS _UID for TBAT is currently set to "TBAT" but should be 1. Battery device is define at src/ec/google/chromeec/acpi/battery.asl Setting _UID to 1 because right now ChromeOS is the only user of DPTF driver TEST: Build and boot brya0 Signed-off-by: Varshit B Pandya <varshit.b.pandya@intel.com> Change-Id: I1e4474e59cf01f937fbd51e5b674a609f0c47625 Reviewed-on: https://review.coreboot.org/c/coreboot/+/65605 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
* driver/wifi: Remove unused function wifi_emit_dsmVarshit B Pandya2022-07-161-23/+0
| | | | | | | | | | | | | As part of this CL https://review.coreboot.org/c/coreboot/+/61020 this function was decoupled and support for new DSM was added. This function is no longer used so remove it. Signed-off-by: Varshit B Pandya <varshit.b.pandya@intel.com> Change-Id: Iad9dca8e50bad87178dfcc1951276703721d5f60 Reviewed-on: https://review.coreboot.org/c/coreboot/+/65850 Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Meera Ravindranath <meera.ravindranath@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* arch/x86: Mark prepare_and_run_postcar noreturnArthur Heymans2022-07-141-1/+0
| | | | | | | | | | | This moves the die() statement to a common place. Change-Id: I24c9f00bfee169b4ca57b469c089188ec62ddada Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/65812 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Julius Werner <jwerner@chromium.org>
* commonlib: Substitude macro "__unused" in compiler.hBill XIE2022-07-142-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | Since there are many identifiers whose name contain "__unused" in headers of musl libc, introducing a macro which expands "__unused" to the source of a util may have disastrous effect during its compiling under a musl-based platform. However, it is hard to detect musl at build time as musl is notorious for having explicitly been refusing to add a macro like "__MUSL__" to announce its own presence. Using __always_unused and __maybe_unused for everything may be a good idea. This is how it works in the Linux kernel, so that would at least make us match some other standard rather than doing our own thing (especially since the other compiler.h shorthand macros are also inspired by Linux). Signed-off-by: Bill XIE <persmule@hardenedlinux.org> Change-Id: I547ae3371d7568f5aed732ceefe0130a339716a9 Reviewed-on: https://review.coreboot.org/c/coreboot/+/65717 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <felixsinger@posteo.net> Reviewed-by: Julius Werner <jwerner@chromium.org>
* */fsp/exit_car: Push stack address into %espArthur Heymans2022-07-091-1/+1
| | | | | | | | | | | | | | | | | | | | | | | Fixes: 5315e96abf ("arch/x86/postcar: Use a separate stack for C execution") Resolves: https://mail.coreboot.org/hyperkitty/list/coreboot@coreboot.org/ thread/TGIWAKZKELJRAEMKJNYRJ55MX2CXYNCV/ Link: https://mail.coreboot.org/hyperkitty/list/coreboot@coreboot.org/ thread/2JC3GNJSGXUD6DRVUY7O2O3W6OM3E2MY/ 5315e96abf broke platforms using FSP-M to tear down CAR. It was pushing the value at '_estack' into %esp rather than the address '_estack'. Change-Id: Ie1fc70bd60fe3a2519ffb71625a35630fa732ff6 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/65716 Reviewed-by: Patrick Georgi <patrick@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Raul Rangel <rrangel@chromium.org>
* treewide: Unify Google brandingJon Murphy2022-07-042-2/+2
| | | | | | | | | | | | | | | | | Branding changes to unify and update Chrome OS to ChromeOS (removing the space). This CL also includes changing Chromium OS to ChromiumOS as well. BUG=None TEST=N/A Change-Id: I39af9f1069b62747dbfeebdd62d85fabfa655dcd Signed-off-by: Jon Murphy <jpmurphy@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/65479 Reviewed-by: Jack Rosenthal <jrosenth@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <felixsinger@posteo.net>
* src/driver/intel/mipi_camera: Update ACPI entry to provide silicon infozhixingma2022-07-041-1/+3
| | | | | | | | | | | | | | CPUID_RAPTORLAKE_P_Q0 is ES. Add it to generate is_es = 1 in ACPI BUG=b:229134437 BRANCH=firmware-brya-14505.B TEST=Booted to OS on adlrvp + rpl silicon Signed-off-by: zhixingma <zhixing.ma@intel.com> Change-Id: I67d70dc7e916a4818869aef86e7e642b66ea5dae Reviewed-on: https://review.coreboot.org/c/coreboot/+/65118 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
* drivers/mrc_cache: Do not verify TPM MRC hash if secdata is mockedMichał Żygowski2022-06-241-1/+1
| | | | | | | | | | | | | | | | | | | Having PTT means mocking secdata, so saving/reading the hash always succeeds, but there is no data stored/read from/to TPM. The code comparing MRC hashes did not care if secdata mocking was enabled and failed during hash comparison with invalid data. This broke the fastboot even if the MRC cache data was filled and correctly checksummed. If mocking is enabled simply fallback to checksum computing to proceed with fastboot. TEST=Boot MSI PRO Z690-A WIFI DDR4 in fastboot mode with PTT and vboot enabled. Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com> Change-Id: Ic0cf04b129fe1c5e94cd8a803bb21aa350c3f8da Reviewed-on: https://review.coreboot.org/c/coreboot/+/64221 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
* drivers/crb: Generate TPM PPI ACPI codeMichał Żygowski2022-06-231-0/+4
| | | | | | | | | | | | The TPM PPI code was only generated for memory mapped non-CRB TPMs. There is no reason why CRB TPM should not have the PPI, e.g. PTT. Call the relevant method to add the PPI to SSDT. Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com> Change-Id: I3d3f08ea686c95ef75ae8fe7a5dcf16f7492ce68 Reviewed-on: https://review.coreboot.org/c/coreboot/+/64422 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sean Rhodes <sean@starlabs.systems>
* device/resource: Add _kb postfix for resource allocatorsKyösti Mälkki2022-06-222-2/+2
| | | | | | | | | | | | There is a lot of going back-and-forth with the KiB arguments, start the work to migrate away from this. Change-Id: I329864d36137e9a99b5640f4f504c45a02060a40 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/64658 Reviewed-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* drivers/usb/gadget.c: Use 'printk()' instead of 'dprintk()'Elyes HAOUAS2022-06-201-20/+18
| | | | | | | | | | | dprintk(BIOS_,...) was probably useed for debug print, so use printk(BIOS_, ...) instead. Change-Id: Ia4171c8b4b42f6b0c1c9c0438bab2eef73f8c416 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/61405 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
* drivers/intel/gma/acpi: Replace LNotEqual(a,b) with ASL 2.0 syntaxFelix Singer2022-06-091-2/+2
| | | | | | | | | | Replace `LNotEqual(a, b)` with `a != b`. Change-Id: Ib1b3f85f95511e903948b385e86e5102d5b43add Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60698 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sean Rhodes <sean@starlabs.systems>
* drivers/intel/gma/acpi: Replace LGreater(a,b) with ASL 2.0 syntaxFelix Singer2022-06-091-2/+2
| | | | | | | | | | Replace `LGreater(a, b)` with `a > b`. Change-Id: I56479726f91f33e1d3062a31f1efb82c0814316c Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60681 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sean Rhodes <sean@starlabs.systems>
* drivers/intel/gma/acpi: Replace LLess(a,b) with ASL 2.0 syntaxFelix Singer2022-06-091-3/+3
| | | | | | | | | | Replace `LLess(a, b)` with `a < b`. Change-Id: I043ffad90737f4217d01c49e03af81549a0ffb1b Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60677 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sean Rhodes <sean@starlabs.systems>
* drivers/intel/gma/acpi: Replace LEqual(a,b) with ASL 2.0 syntaxFelix Singer2022-06-092-7/+7
| | | | | | | | | | Replace `LEqual(a, b)` with `a == b`. Change-Id: I965a0718f6bca1dc27b928bdd9374857f5ea3215 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60660 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sean Rhodes <sean@starlabs.systems>
* drivers/tpm/cr50: Add TPM IRQ timeout Kconfig optionYu-Ping Wu2022-06-084-38/+29
| | | | | | | | | | | | | | | | | | | | | | | The current 10ms timeout for SPI TPM IRQ is not enough for platforms using ti50 (such as corsola). Therefore, introduce a new Kconfig option 'GOOGLE_TPM_IRQ_TIMEOUT_MS'. For platforms using cr50, we need to support legacy pre-ready-IRQ cr50 factory images during the initial boot, so the timeout remains 100ms for I2C TPM and 10ms for SPI TPM. For all the other platforms using ti50, the default timeout is increased to 750ms, as suggested by the ti50 team (apronin@google.com). BUG=b:232327704 TEST=emerge-corsola coreboot BRANCH=none Change-Id: I8dbb919e4a421a99a994913613a33738a49f5956 Signed-off-by: Yu-Ping Wu <yupingso@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/64412 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Hung-Te Lin <hungte@chromium.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
* arch/x86: Add a common romstage entryArthur Heymans2022-06-071-10/+3
| | | | | | | | | | | It might be possible to have this used for more than x86, but that will be for a later commit. Change-Id: I4968364a95b5c69c21d3915d302d23e6f1ca182f Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55067 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
* Replace some ENV_ROMSTAGE with ENV_RAMINITKyösti Mälkki2022-06-074-7/+7
| | | | | | | | | | | | | With a combined bootblock+romstage ENV_ROMSTAGE might no longer evaluate true. Change-Id: I733cf4e4ab177e35cd260318556ece1e73d082dc Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/63376 Reviewed-by: Julius Werner <jwerner@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-by: Raul Rangel <rrangel@chromium.org>
* cpu/amd/agesa: Use common MRC_CACHE code to save S3 dataArthur Heymans2022-06-061-61/+19
| | | | | | | | | | | | | | | | Use the common code to save data for fast boot or S3 resume. An notable improvement that comes with this, is that the same 4K page is not rewritten all the time. This prolongs the hardware's life. TESTED on pcengines/apu1 and lenovo/g505s: S3 resume works fine. Change-Id: I0f4f36dcead52a6c550fb5e606772e0a99029872 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44295 Reviewed-by: Mike Banon <mikebdp2@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com>
* drivers/amd/agesa: Don't save regular boot MTRR to flashArthur Heymans2022-06-062-51/+17
| | | | | | | | | | | | | | | | | | | Save the regular boot MTRRs that are restored on the S3 path during the CPU init in cbmem instead of storing them to the SPI flash. This was probably done because historically this code run with late cbmem init (in ramstage). TESTED on pcengines/apu1 and lenovo/g505s: S3 resume works fine. Change-Id: Ia58e7cd1afb785ba0c379ba75ef6090b56cb9dc6 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44294 Reviewed-by: Mike Banon <mikebdp2@gmail.com> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com>
* drivers/amd/agesa/s3_mtrr.c: Save MSR for S3 using an arrayArthur Heymans2022-06-062-93/+55
| | | | | | | | | | | | | | | | | | | | The size of the data used is fixed in this function so there is no need for this aritmetic. The function signature will be changed in a followup commit. The cache_disable call is dropped as all the codepaths calling the restore_mtrr function do this already. TESTED on pcengines/apu1 and lenovo/g505s: S3 resume works fine. Change-Id: I3c6df8951d39695cddd4635360d6407d4d001b0a Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44293 Reviewed-by: Mike Banon <mikebdp2@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com>
* drivers/wifi: Move MTL Magnetar CNVi DIDs from SoC to generic driverSubrata Banik2022-06-031-0/+5
| | | | | | | | | | | | | | | | | | | | | This patch removes the MTL CNVi DIDs macros from IA common code and is added into the generic wifi driver. As per Intel Connectivity Platform BIOS Guide, Connectivity Controller IP for MTL-P is `Magnetar` and supported CRF is `Typhoon Peak 2`. Previously Garfield Peak DIDs for Alder Lake SoC also added similarly to generic wifi drivers. BUG=b:224325352 TEST=Able to build and boot on MTL emulator. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: Ib98762749c71f63df3e8d03be910539469359c68 Reviewed-on: https://review.coreboot.org/c/coreboot/+/64592 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tarun Tuli <taruntuli@google.com> Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com>
* driver/intel/fsp2_0: Disable NULL deref code when calling FSPArthur Heymans2022-06-013-5/+17
| | | | | | | | | | | | | FSP needs interrupts disable so also disable generating exceptions around debug registers. Change-Id: Ia49dde68d45b71e231aaf32a0e6fd847f0e06146 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/64426 Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com> Reviewed-by: Uwe Poeche <uwe.poeche@siemens.com> Reviewed-by: Sean Rhodes <sean@starlabs.systems> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* drivers/i2c/generic: Add support for i2c device detectionMatt DeVillier2022-05-312-0/+23
| | | | | | | | | | | | | | | | | | Add 'detect' flag which can be attached to devices which may or may not be present at runtime, and for which coreboot should probe the i2c bus to confirm device presence prior to adding an entry for it in the SSDT. This is useful for boards which may utilize touchpads/touchscreens from multiple vendors, so that only the device(s) present are added to the SSDT. This relieves the burden from the OS to detect/probe if a device is actually present and allows the OS to trust the ACPI _STA value. Change-Id: I1a4169ed6416d544773a37d29cdcc154d3c28519 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/63211 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin L Roth <gaumless@tutanota.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
* drivers/i2c/dw_i2c: Adjust to handle 0-byte transfersMatt DeVillier2022-05-311-3/+8
| | | | | | | | | | | | | | | | | 0-byte writes can be used as a way to probe/check presence of an i2c device, so adjust _dw_i2c_transfer() to immediately set the STOP bit and raise logger level for TX abort messages when the segment length is zero. Adjust dw_i2c_transfer() to allow zero-segment-length messages to be passed thru to _dw_i2c_transfer(). Tested as part of entire i2c-detect patch train. Change-Id: I518e849f4c476c264a1464886b1853af66c0b29d Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/63561 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin L Roth <gaumless@tutanota.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
* drivers/spi: Add Winbond W25Q256JW detailsRitul Guru2022-05-311-0/+9
| | | | | | | | | | Add winbond W25Q256JW chip details. Change-Id: I0dab96701285be95a76cee674f83339bc63d9f82 Signed-off-by: Ritul Guru <ritul.bits@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/64634 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
* drivers/i2c/cs35l53: Add device description and UIDVitaly Rodionov2022-05-282-2/+11
| | | | | | | | | | | | | BUG=b:207333035 BRANCH=none TEST=built and verified speaker Signed-off-by: Vitaly Rodionov <vitalyr@opensource.cirrus.com> Change-Id: I0dd39760dc5f44f46838c07d2e52946edc2a6d7e Reviewed-on: https://review.coreboot.org/c/coreboot/+/64638 Reviewed-by: Vitaly Rodionov <vitaly.rodionov@cirrus.corp-partner.google.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* CBMEM: Change declarations for initialization hooksKyösti Mälkki2022-05-203-7/+5
| | | | | | | | | | | | | | | | | | There are efforts to have bootflows that do not follow a traditional bootblock-romstage-postcar-ramstage model. As part of that CBMEM initialisation hooks will need to move from romstage to bootblock. The interface towards platforms and drivers will change to use one of CBMEM_CREATION_HOOK() or CBMEM_READY_HOOK(). Former will only be called in the first stage with CBMEM available. Change-Id: Ie24bf4e818ca69f539196c3a814f3c52d4103d7e Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/63375 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
* drivers/intel/fsp2_0: Avoid hardcoding `log_level` for FSP debug handlerSubrata Banik2022-05-191-1/+1
| | | | | | | | | | | | | | | | | | | | This patch fixes a potential corner case scenario where the value of CONFIG_DEFAULT_CONSOLE_LOGLEVEL is less than `BIOS_SPEW` hence, coreboot is unable to redirect FSP serial messages over UART. Rather than passing hard coded `BIOS_SPEW` for the FSP debug handler, this patch now calls get_log_level() function to pass the supported log level while printing FSP serial msg. BUG=b:225544587 TEST=Able to build and boot taeko. Also, able to see FSP debug log with CONFIG_DEFAULT_CONSOLE_LOGLEVEL=7. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: I8a18101f5c3004252205387bde28590c72e05b9d Reviewed-on: https://review.coreboot.org/c/coreboot/+/64460 Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* amd/agesa/heapmanager.c: Avoid pragma pack on the rest of the fileArthur Heymans2022-05-171-0/+3
| | | | | | | | | | | | AGESA.h has a '#pragma pack' nested somewhere. The pack pragma packs all structs which is not what is expected in the structs inside the headers included below AGESA.h. Change-Id: Ia70f68ea0ece7c097a37517206d75b71d695561f Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/64382 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
* drivers/wifi/generic: Add new device IDBora Guvendik2022-05-161-0/+1
| | | | | | | | | | New device id 0x51f1 is added. Signed-off-by: Bora Guvendik <bora.guvendik@intel.com> Change-Id: I695309d529a117bad68fc89a7f136e69cecb95d9 Reviewed-on: https://review.coreboot.org/c/coreboot/+/64001 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
* src/driver/intel/mipi_camera: Update ACPI entry to provide silicon infoBora Guvendik2022-05-161-1/+1
| | | | | | | | | | CPUID_RAPTORLAKE_P_J0 is ES. Add it to generate is_es = 1 in ACPI Signed-off-by: Bora Guvendik <bora.guvendik@intel.com> Change-Id: Ib8d57f7fb0b3d15bc4bcdeae47bfbdde17e13118 Reviewed-on: https://review.coreboot.org/c/coreboot/+/64000 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
* arch/x86/postcar_loader.c: Change prepare_and_run_postcar signatureArthur Heymans2022-05-161-2/+1
| | | | | | | | | | The postcar frame can now be a local variable to that function. Change-Id: I873298970fff76b9ee1cae7da156613eb557ffbc Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/61964 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
* drivers/amd/agesa: Use prepare_and_run_postcarArthur Heymans2022-05-162-5/+10
| | | | | | | | | | This removes some of the postcar setup boilerplate. Change-Id: I4f8f92b88ac16dd70ff4878dfc14e676386d4703 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/61962 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com>
* arch/x86/postcar: Set up postcar MTRR in C codeArthur Heymans2022-05-162-2/+2
| | | | | | | | | | | | | | | | | Setting up postcar MTRRs is done when invd is already called so there is no reason to do this in assembly anymore. This also drops the custom code for Quark to set up MTRRs. TESTED on foxconn/g41m and hermes/prodrive that MTRR are properly set in postcar & ramstage. Change-Id: I5ec10e84118197a04de0a5194336ef8bb049bba4 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/54299 Reviewed-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* drivers/ipmi: Fix header guardDavid Hendricks2022-05-161-1/+1
| | | | | | | | | | Change-Id: Ic1f33ce883443da1c68627e4c1db10871deecd0d Signed-off-by: David Hendricks <david.hendricks@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/64364 Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* drivers/i2c/tpm: Work around missing firmware_version in Ti50 < 0.0.15Reka Norman2022-05-161-0/+7
| | | | | | | | | | | | | | | | | | | | | | | | Ti50 firmware versions below 0.0.15 don't support the firmware_version register and trying to access it causes I2C errors. Some nissa boards are still using Ti50 0.0.12, so add a workaround Kconfig to skip reading the firmware version and select it for nissa. The firmware version is only read to print it to the console, so it's fine to skip this. This workaround will be removed once all ODM stocks are updated to 0.0.15 or higher. A similar workaround Kconfig was added in CB:63011 then removed in CB:63158 which added support for separate handling of Cr50 and Ti50. But we actually still need this workaround until all Ti50 stocks are upgraded to 0.0.15 or higher. BUG=b:224650720 TEST=Boot to OS on nereid with Ti50 0.0.14 Change-Id: Ia30d44ac231c42eba3ffb1cb1e6d83bb6593f926 Signed-off-by: Reka Norman <rekanorman@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/64202 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
* drivers/intel/fsp1_1: Use C over CPPArthur Heymans2022-05-131-19/+19
| | | | | | | | | | This fixes building with clang. Change-Id: Ida464d9ff96af3ff485682fbbf904bb2253ec44f Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/63065 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
* drivers/usb: Add chip driver for external USB hubKarthikeyan Ramasubramanian2022-05-124-0/+109
| | | | | | | | | | | | | | | Add chip driver for soldered down external USB hub. This driver adds ACPI objects for the hub and any downstream facing ports. BUG=b:227761300 TEST=Build and boot to OS in Skyrim. Ensure that the hub and any configured ports have ACPI devices defined in SSDT. Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Change-Id: I11d7ccc42d3dce8e136eb771f120825980e5c027 Reviewed-on: https://review.coreboot.org/c/coreboot/+/63968 Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* drivers/intel/gma/opregion.c: Fix uninitialised variable useArthur Heymans2022-05-111-2/+2
| | | | | | | | Change-Id: I87cff1e0360e23e37201381ed8a6920ee36b2747 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/61892 Reviewed-by: Matt DeVillier <matt.devillier@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
generated by cgit v1.2.3 (git 2.25.1) at 2024-05-23 12:45:28 +0000