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* src/drivers: Remove unused <console/console.h>Elyes HAOUAS2021-02-1510-10/+0
| | | | | | | | Change-Id: I38d565f82d078cb75f74f8502fcafdedd907b97d Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50523 Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* drivers/spi: Stop using a variable-length arrayAngel Pons2021-02-152-8/+8
| | | | | | | | | | | | | | | | | | | | | | | | | Only the call in `spi_flash_cmd_write_page_program` uses non-constant values for the array length. However, the value for `data_len` has an upper bound: `flash->page_size` is set to `1U << vi->page_size_shift` which depends on the flash chip vendor info, and the largest value it can currently have is 8. Thus, the maximum page size is currently 256. Define the `MAX_FLASH_CMD_DATA_SIZE` macro to place an upper bound on the amount of data that can be written in one command. Then, use this value to allocate a fixed-size buffer in `spi_flash_cmd_write`. Also, add a check to prevent buffer overflow problems. Finally, ensure that the `spi_flash_cmd_write_page_program` function always writes no more than 256 bytes of data when using the `spi_flash_cmd_write` function. Tested on Asrock B85M Pro4 (Winbond W25Q64FV), MRC cache still works. Change-Id: Ib630bff1b496bc276616989d4506a3c96f242e26 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50480 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-by: Jacob Garber <jgarber1@ualberta.ca> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
* src: Remove unused <boot_device.h>Elyes HAOUAS2021-02-102-2/+1
| | | | | | | | Change-Id: Idbb4d72e1ba620f71e8bf882d434c103cb422615 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50201 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* soc/amd,intel: Drop s3_resume parameter on FSP-S functionsKyösti Mälkki2021-02-094-8/+7
| | | | | | | | | | | | ACPI S3 is a global state and it is no longer needed to pass it as a parameter. Change-Id: Id0639a47ea65c210b9a79e6ca89cee819e7769b1 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50360 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
* drivers/intel/fsp1_1,fsp2_0: Refactor logo displayKyösti Mälkki2021-02-0910-75/+19
| | | | | | | | | | | | | | Hide the detail of allocation from cbmem from the FSP. Loading of a BMP logo file from CBFS is not tied to FSP version and we do not need two copies of the code, move it under lib/. Change-Id: I909f2771af534993cf8ba99ff0acd0bbd2c78f04 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50359 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
* src: Remove redundant <commonlib/bsd/compiler.h>Elyes HAOUAS2021-02-071-1/+0
| | | | | | | | Change-Id: Icb3108a281dfb3f21248a7065821b8237143be1a Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50301 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
* src: Remove redundant include <rules.h>Elyes HAOUAS2021-02-071-1/+0
| | | | | | | | | Change-Id: Ie4692246d059734bb5bad6c64042b64068636ab6 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50300 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
* drivers/intel/fsp2_0: Add support for MP services2 PPIAamir Bohra2021-02-067-62/+243
| | | | | | | | | | | | | | | | | | Add support for MP services2 PPIs, which is slight modification over MP services 1 PPIs. A new API StartupAllCPUs have been added to allow running a task on BSP and all APs. Also the EFI_PEI_SERVICES parameter has been removed from all MP PPI APIs. This implementation also selects the respective MP services PPI version supported for SoCs BUG=b:169196864 Change-Id: Id74baf17fb90147d229c78be90268fdc3ec1badc Signed-off-by: Aamir Bohra <aamir.bohra@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49474 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
* intel: Rename config FSP_USES_MP_SERVICES_PPI to MP_SERVICES_PPIFurquan Shaikh2021-02-062-2/+2
| | | | | | | | | | | | | | | | This change renames config FSP_USES_MP_SERVICES_PPI to MP_SERVICES_PPI in preparation to allow V1 and V2 versions of MP services PPI. TEST=Verified that timeless build for brya, volteer, icelake_rvp, elkhartlake_crb and waddledee shows no change in generated coreboot.rom Change-Id: I04acf1bc3a3739b31d6e9d01b6aa97542378754f Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50275 Reviewed-by: Aamir Bohra <aamir.bohra@intel.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Subrata Banik <subrata.banik@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* intel: Drop FSP_PEIM_TO_PEIM_INTERFACEFurquan Shaikh2021-02-062-14/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This change drops the config FSP_PEIM_TO_PEIM_INTERFACE. FSP_PEIM_TO_PEIM_INTERFACE is used for: * Auto-selecting FSP_USES_MP_SERVICES_PPI * Including src/drivers/intel/fsp2_0/ppi/Kconfig * Adding ppi to subdirs-y * Setting USE_INTEL_FSP_TO_CALL_COREBOOT_PUBLISH_MP_PPI to y and is selected by SoCs that want to enable MP PPI services. Instead of using the indirect path of selecting MP PPI services, this change allows SoC to select FSP_USES_MP_SERVICES_PPI directly. The above uses are handled as follows: * Auto-selecting FSP_USES_MP_SERVICES_PPI --> This is handled by SoC selection of FSP_USES_MP_SERVICES_PPI. * Including src/drivers/intel/fsp2_0/ppi/Kconfig --> The guard isn't really required. The Kconfig options in this file don't present user prompts and don't really need to be guarded. * Adding ppi to subdirs-y --> Makefile under ppi/ already has conditional inclusion of files and does not require a top-level conditional. * Setting USE_INTEL_FSP_TO_CALL_COREBOOT_PUBLISH_MP_PPI to y --> This is set to y if FSP_USES_MP_SERVICES_PPI is selected by SoC. TEST=Verified that timeless build for brya, volteer, icelake_rvp, elkhartlake_crb and waddledee shows no change in generated coreboot.rom Change-Id: I0664f09d85f5be372d19925d47034c76aeeef2ae Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50274 Reviewed-by: Aamir Bohra <aamir.bohra@intel.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Subrata Banik <subrata.banik@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* drivers/generic/bayhub_lv2: Add driver for BayHub lv2John Su2021-02-045-0/+123
| | | | | | | | | | | | | | | Add a driver which puts the device into power-saving mode. BUG=b:177955523 BRANCH=zork TEST=boot and see this message: BayHub LV2: Power-saving enabled 110102 Signed-off-by: John Su <john_su@compal.corp-partner.google.com> Change-Id: Idc1340b1a6fe7063d16c8ea16488d6e2b8b308cc Reviewed-on: https://review.coreboot.org/c/coreboot/+/49783 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
* drivers/intel/fsp2_0: Fix running on x86_64Patrick Rudolph2021-02-047-33/+51
| | | | | | | | | | | | | | | | | | | | | | Add new Kconfig symbols to mark FSP binary as x86_32. Fix the FSP headers and replace void pointers by fixed sized integers depending on the used mode to compile the FSP. This issue has been reported here: https://github.com/intel/FSP/issues/59 This is necessary to run on x86_64, as pointers have different size. Add preprocessor error to warn that x86_64 FSP isn't supported by the current code. Tested on Intel Skylake. FSP-M no longer returns the error "Invalid Parameter". Change-Id: I6015005c4ee3fc2f361985cf8cff896bcefd04fb Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48174 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
* src: Remove useless comments in "includes" linesElyes HAOUAS2021-02-043-3/+3
| | | | | | | | Change-Id: Ide5673dc99688422c5078c8c28ca5935fd39c854 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50186 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
* drivers/aspeed: Fix some issuesPatrick Rudolph2021-02-031-9/+4
| | | | | | | | | | | | | | | | | | | * Use probe_resource instead of find_resource. This prevents a call to die and instead returns NULL. * Handle the case where BAR2 isn't present * Don't hardcode legacy VGA when BAR2 is present. This fixes graphic initialisation when the Aspeed isn't the primary GPU and thus doesn't decode VGA cycles. This makes the coreboot code more similar to the Linux kernel code. Change-Id: I2a99712a562a57c65f1cd0df7b1d7606681afe9b Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50195 Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* bayhub bh720: Add helpers to access PCR registersAngel Pons2021-02-011-30/+26
| | | | | | | | | | | | | The BH720 PCR registers are accessed using an index/data register pair. Introduce some helper functions to clarify the PCR register operations. Change-Id: I1a48b10071af20dca61b7dd90c5a70bc9d1089b4 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49925 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
* ipmi/ocp: Move common OCP/Facebook IPMI OEM codes into drivers/ipmi/ocpJohnny Lin2021-02-014-0/+136
| | | | | | | | | | | | | | | | | 1. These are common OCP/Facebook IPMI OEM commands, move from mainboard into drivers/ipmi/ocp to avoid code duplication and provide better reusability. 2. OCP Tioga Pass enables IPMI_OCP driver. Tested=On OCP Delta Lake and Tioga Pass verify the commands still work correctly. Change-Id: Idd116a89239273fd5cc7b06c7768146085a3ed69 Signed-off-by: Johnny Lin <johnny_lin@wiwynn.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49235 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
* drivers/intel/fsp2_0: Use CBFS_MCACHE when coreboot tears down CARArthur Heymans2021-02-011-1/+1
| | | | | | | | | | TESTED on ocp/tiogapass. Change-Id: I30560149eeaec62af4c8a982815618be5546531c Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49877 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
* drivers/intel/fsp2_0: Use coreboot postcar with FSP-TArthur Heymans2021-02-012-0/+9
| | | | | | | | | | | | | | | | | | | | Allow platforms to use the coreboot postcar code instead of calling into FSP-M TempRamExit API. There are several reasons to do this: - Tearing down CAR is easy. - Allows having control over MTRR's and caching in general. - The MTRR's set up in postcar be it by coreboot or FSP-M are overwritten later on during CPU init so it does not matter. - Avoids having to find a CBFS file before cbmem is up (this causes problems with cbfs_mcache) Change-Id: I6cf10c7580f3183bfee1cd3c827901cbcf695db7 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48466 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* drivers/intel/fsp2_0: factor out and improve UPD signature checkFelix Held2021-01-304-6/+19
| | | | | | | | | | | | | | In case of a mismatch print both the UPD signature in the FSP and the expected signature and then calls die(), since it shouldn't try calling into the wrong FSP binary for the platform. Signed-off-by: Justin Frodsham <justin.frodsham@protonmail.com> Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I469836e09db6024ecb448a5261439c66d8e65daf Reviewed-on: https://review.coreboot.org/c/coreboot/+/50090 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-by: Furquan Shaikh <furquan@google.com>
* stage_cache: Add resume_from_stage_cache()Kyösti Mälkki2021-01-292-20/+5
| | | | | | | | | | | Factor out the condition when an attempt to load stage from cache can be tried. Change-Id: I936f07bed6fc82f46118d217f1fd233e2e041405 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50000 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
* drivers/intel/fsp1_1: Drop s3_resume parameter to load_vbt()Kyösti Mälkki2021-01-293-4/+5
| | | | | | | | Change-Id: Iaba88026906132b96fe3db3f05950df0e7eef896 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50002 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
* intel/fsp1_1: Declare fsp_load() as staticKyösti Mälkki2021-01-292-13/+1
| | | | | | | | | | | The function has only one local call-site. Change-Id: I623953796e6cd3a8e5b4f72293d953b61f14a5a1 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49999 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* bayhub bh720: Factor out common HS200 init codeAngel Pons2021-01-283-4/+49
| | | | | | | | | | | Except for one debug print in sarien, both functions are identical. Move them to driver code to avoid unnecessary redundancy. Change-Id: I82635a289e3c05119eab4ee1f7a6bf3a8a1725c1 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49833 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
* drivers/elog: Correct code styleFrans Hendriks2021-01-282-4/+4
| | | | | | | | | | | | | | | | lint report errors Solve the POINTER_LOCATION errors BUG = N/A TEST = N/A Change-Id: I65926abd6bbaff1efce39efad9ec92c4f364b533 Signed-off-by: Frans Hendriks <fhendriks@eltan.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49971 Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* cpu/x86: Rename __protected_start symbolKyösti Mälkki2021-01-281-1/+1
| | | | | | | | | | | | | | | It was confusing to have this defined while there was another symbol bootblock_protected_mode_entry that was not really used as an entry point. Change-Id: I3da07ba9c0a9fc15b1515452adfb27f963659951 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48404 Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-by: Jason Glenesk <jason.glenesk@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* drivers/intel/fsp2_0/header_display.c: Correct component_attribute checkBenjamin Doron2021-01-251-1/+1
| | | | | | | | | | | According to FSP_INFO_HEADER structure in FSP EAS v2.0-v2.2, BIT1 indicates an "official" build. Change-Id: I94df6050a1ad756bbeff60cda0ebac76ae5f8249 Signed-off-by: Benjamin Doron <benjamin.doron00@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49650 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
* bayhub bh720: Configure VIH tuning via devicetreeAngel Pons2021-01-252-0/+16
| | | | | | | | | | | | There's no need to repeat the same code on every board. Change-Id: I2e19decfe8609fa644e609673a56ee5109bafefa Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49831 Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Martin Roth <martinroth@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* drivers/intel/gma/opregion.c: Use __func__Elyes HAOUAS2021-01-241-1/+1
| | | | | | | | | Change-Id: Ia45825ade0c9d24d5b87882e21bfc6df82a693e6 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49550 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <felixsinger@posteo.net> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
* drivers/elog/elog.c: Use __func__Elyes HAOUAS2021-01-241-8/+8
| | | | | | | | | Change-Id: I024a0c2d7c53634c58d5d80522933ecad554d7c9 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49546 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <felixsinger@posteo.net> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
* arch/x86/car.ld: Account for FSP-T reserved areaArthur Heymans2021-01-241-0/+9
| | | | | | | | | | | | Tested - on ocp/deltalake: boots (with FSP-T). - qemu/i440fx: BUILD_TIMELESS=1 results in the same binary. Change-Id: I7e364ab039b65766eb95538db6b3507bbfbfb487 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49084 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
* drivers/intel/fsp2_0: Add meaningful ERROR messageSubrata Banik2021-01-231-4/+3
| | | | | | | | | | | | | | Add the "ERROR:" tag so that it ease debug effect. TEST=Test tools like "suspend_stress_test" (specific to Chrome OS) can identify the obvious coreboot ERROR prior running S3 resume test. Change-Id: I64717ce0412d43697f42ea2122b932037d28dd48 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49798 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* drivers/intel/usb4: Enable retimer FW upgrade mux interactionBrandon Breitenstein2021-01-222-6/+49
| | | | | | | | | | | | | | | | | | | In order to update the BB retimers for usb4/tbt they need to be turned on and into TBT mode. Expand the current DSM to allow for the use of an EC RAM byte RFWU to get the current state of each port and whether or not it has a retimer. It also allows Kernel to issue state transitions for the retimer to be put into TBT mode for firmware update. BUG=b:162528867 TEST=Along with work in progress kernel and EC patches, the Retimer firmware update is verified under device attached and no device attached scenarios. Change-Id: I768cfb56790049c231173b0ea0f8e08fe6b64b93 Signed-off-by: Brandon Breitenstein <brandon.breitenstein@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48630 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
* src/drivers/smmstore: Fix SMMSTOREv1 clear commandTim Crawford2021-01-211-1/+1
| | | | | | | | | | The `clear` command for SMMSTORE version 1 does not require a parameter. Change-Id: I992b7ce5962bf7ee62b7e1970ae7aa1b975ef42e Signed-off-by: Tim Crawford <tcrawford@system76.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49724 Reviewed-by: Jeremy Soller <jeremy@system76.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* drivers/intel/fsp1_1/temp_ram_exit.c: Initialize CBMEMFrans Hendriks2021-01-211-0/+5
| | | | | | | | | | | | | | | | | | | prog_locate() will load FSP, before CBMEM is initialized. The vboot workbuffer is used for loading, but CBMEM_ID_VBOOT_WORKBUF is not available. A NULL pointer is returned as workbuffer resulting in error 'Ramstage was not loaded!' at second boot. Initialize CBMEM before calling prog_locate(). BUG = N/A TEST = Build and boot on Facebook FBG1701 Change-Id: I2f04a326a95840937b71f6ad65a7c011268ec6d6 Signed-off-by: Frans Hendriks <fhendriks@eltan.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49639 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
* drivers/spi/tpm/tpm.c: Use __func__Elyes HAOUAS2021-01-191-1/+2
| | | | | | | | Change-Id: I8a8b0575689d7b63fd37edc457abc42710a13e97 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49552 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Christian Walter <christian.walter@9elements.com>
* drivers/spi/tpm/tis.c: Use __func__Elyes HAOUAS2021-01-191-1/+1
| | | | | | | | Change-Id: I2941d4480a7c88b6c020a9da584135a0030fccfe Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49551 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Christian Walter <christian.walter@9elements.com>
* drivers/i2c/tpm/cr50.c: Use __func__Elyes HAOUAS2021-01-191-1/+2
| | | | | | | | Change-Id: If2751f3672072b7fa421ae33dc6e1490fdf35247 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49547 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Christian Walter <christian.walter@9elements.com>
* drivers/i2c/tpm/tpm.c: Use __func__Elyes HAOUAS2021-01-191-4/+3
| | | | | | | | Change-Id: I28f976118a380ef05a98257e9d57aadc26b69cb5 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49549 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Christian Walter <christian.walter@9elements.com>
* drivers/i2c/tpm/tis.c: Use __func__Elyes HAOUAS2021-01-191-7/+7
| | | | | | | | Change-Id: I598d27995fad7582ff41f4e7deaeb2e75e8ebde9 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49548 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Christian Walter <christian.walter@9elements.com>
* drivers/ocp/dmi/Kconfig: Set FRU_DEVICE_ID depend on OCP_DMIElyes HAOUAS2021-01-181-0/+1
| | | | | | | | | | This will remove "CONFIG_FRU_DEVICE_ID=0" from ".config" when unused. Change-Id: Ic50de165c1f3de3886d3cd1ae66853c9fad35ed2 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49571 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
* drivers/ti/sn65dsi86bridge: Add parentheses to MacrosElyes HAOUAS2021-01-181-2/+2
| | | | | | | | Change-Id: I2f3a9885171995633d0bfb22b7ff8ef8a68683b8 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49508 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
* drivers/maxim/max77686/max77686.h: Remove repeated wordElyes HAOUAS2021-01-181-1/+1
| | | | | | | | Change-Id: Iac77f401d80027231f8b6a3449cb57abf3d337ed Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49525 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jacob Garber <jgarber1@ualberta.ca>
* drivers/intel/gma/intel_bios.h: Remove repeated wordElyes HAOUAS2021-01-181-2/+2
| | | | | | | | Change-Id: I5866a5e3240e49119e29f728202b33dd82ceaf77 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49514 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jacob Garber <jgarber1@ualberta.ca>
* drivers/i2c/sx9324: Add IrqCfg1 registerStanley Wu2021-01-181-0/+1
| | | | | | | | | | | | | | Add IrqCfg1 register for proximity IRQ function and polarity setting. BUG=b:175932166 BRANCH=dedede TEST=Build passed. Change-Id: I3cee84a5658fecf55d2d8b8621879588ffe0158d Signed-off-by: Stanley Wu <stanley1.wu@lcfc.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49220 Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* ACPI: Select ACPI_SOC_NVS only where suitableKyösti Mälkki2021-01-182-10/+0
| | | | | | | | | | | | | | | | | Having some symmetry with <soc/nvs.h> now allows to reduce the amount of gluelogic to determine the size and cbmc field of struct global_nvs. Since GNVS creation is now controlled by ACPI_SOC_NVS, drivers/amd/agesa/nvs.c becomes obsolete and soc/amd/cezanne cannot have this selected until <soc/nvs.h> exists. Change-Id: Ia9ec853ff7f5e7908f7e8fc179ac27d0da08e19d Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49344 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Lance Zhao
* drivers/genesyslogic/gl9763e: Add HS400ES compatibility settingsBen Chuang2021-01-122-0/+9
| | | | | | | | | | | | | By default, the HS400 mode of GL9763E is slow mode (150MHz). Therefore, the slow mode is disabled for HS400 running at 200MHz. For eMMCs such as Hynix (H26M74002HMR) on HS400, adjust the internal Rx latch dealy of HS400 to have better compatibility. Signed-off-by: Ben Chuang <benchuanggli@gmail.com> Change-Id: I84844c2432d4223d9929182c5c430915e52875b7 Reviewed-on: https://review.coreboot.org/c/coreboot/+/49079 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
* drivers/genesyslogic/gl9763e: Fix boot on eMMC failed issue on VolteerRenius Chen2021-01-112-0/+16
| | | | | | | | | | | | | | Booting on Kingston (EMMC64G-TA29/TX29-HP) and Hynix (H26M74002HMR) eMMC currently fails due to R/W error. This is a workaround to finetune the data latch timing by verdor-specific setting of GL9763E. For improving the compatibility of GL9763E with these two eMMC. Signed-off-by: Renius Chen <reniuschengl@gmail.com> Change-Id: Iddb145ed6a9edb2d7a50248e64659cda78b88ae6 Reviewed-on: https://review.coreboot.org/c/coreboot/+/48941 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: YH Lin <yueherngl@google.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
* ACPI: Drop redundant CBMEM_ID_ACPI_GNVS allocationsKyösti Mälkki2021-01-102-0/+10
| | | | | | | | | | | | | | | | | Allocation now happens prior to device enumeration. The step cbmem_add() is a no-op here, if reached for some boards. The memset() here is also redundant and becomes harmful with followup works, as it would wipe out the CBMEM console and ChromeOS related fields without them being set again. Change-Id: I9b2625af15cae90b9c1eb601e606d0430336609f Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48701 Reviewed-by: Lance Zhao Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* arch/x86: Move prologue to .init sectionKyösti Mälkki2021-01-072-2/+7
| | | | | | | | | | | | | | | | | | | | | | | | For arch/x86 the realmode part has to be located within the same 64 KiB as the reset vector. Some older intel platforms also require 4 KiB alignment for _start16bit. To enforce the above, and to separate required parts of .text without matching *(.text.*) rules in linker scripts, tag the pre-C environment assembly code with section .init directive. Description of .init section for ELF: This section holds executable instructions that contribute to the process initialization code. When a program starts to run, the system arranges to execute the code in this section before calling the main program entry point (called main for C programs). Change-Id: If32518b1c19d08935727330314904b52a246af3c Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47599 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* drivers/vpd: Add support to read device serial from VPDMatt DeVillier2021-01-043-0/+32
| | | | | | | | | | | | | | | | | | | Add functions to read the system and mainboard serial numbers from VPD tables stored in flash. Remove board-specific implementations for google/drallion and google/sarien and select the new Kconfig instead. Test: build/boot google/akemi with RO_VPD region persisted from stock Google firmware, verify system/mainboard serial numbers present via dmidecode. Change-Id: I14ae07cd8b764e1e22d58577c7cc697ca1496bd5 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49050 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
generated by cgit v1.2.3 (git 2.25.1) at 2024-10-07 13:47:46 +0000