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* drivers/intel/usb4: Add Type-C port device attachment checkJohn2022-05-062-11/+51
| | | | | | | | | | | | | | | | | | | When fwupd Retimer firmware update is enabled, it needs to differentiate the Type-C port NDA and USB/DP/TBT/USB4 DA scenarios. This change adds support to query devices attachment. If DA, it deasserts the Retimer power and promptly returns -1 accordingly without impacting the flow of Retimer firmware update under NDA. Additionally, this patch deasserts the Retimer power during error conditions. BUG=b:212235056, 224923449, 211790542 TEST=Validated Retimer firmware update under NDA and TBT3 docks enumeration on Type-C ports under DA. Change-Id: I5392d0d3a947dbf172cadfe03fc708f6e2e87210 Signed-off-by: John Zhao <john.zhao@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/63848 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
* drivers/spi: Add better error reporting to spi_flash_cmd_poll_bitRaul E Rangel2022-05-021-2/+11
| | | | | | | | | | | | | | It's useful to know how many attempts were made at polling the status bit. BUG=b:228289365 TEST=Boot guybrush Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: Ifcc79a339707fbaab33e128807d4c0b26aa90108 Reviewed-on: https://review.coreboot.org/c/coreboot/+/63959 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Rob Barnes <robbarnes@google.com>
* drivers/spi: Convert spi_flash_cmd_poll_bit to use stopwatch APIRaul E Rangel2022-05-021-8/+5
| | | | | | | | | | | | | | | The previous code required a bit too much effort to read. It also didn't print out the actual duration. BUG=b:228289365 TEST=Boot guybrush Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: Ia620e789c5186f2e1d3cf3c548bda00a294d23bf Reviewed-on: https://review.coreboot.org/c/coreboot/+/63939 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Rob Barnes <robbarnes@google.com> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
* tpm: Allow separate handling of Google Ti50 TPMJes Klinke2022-04-245-36/+29
| | | | | | | | | | | | | | | A new iteration of Google's TPM implementation will advertize a new DID:VID, but otherwise follow the same protocol as the earlier design. This change makes use of Kconfigs TPM_GOOGLE_CR50 and TPM_GOOGLE_TI50 to be able to take slightly different code paths, when e.g. evaluating whether TPM firmware is new enough to support certain features. Change-Id: I1e1f8eb9b94fc2d5689656335dc1135b47880986 Signed-off-by: Jes B. Klinke <jbk@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/63158 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
* {drivers,northbridge,security}: Remove unused <cpu/x86/lapic.h>Elyes HAOUAS2022-04-242-2/+0
| | | | | | | | | | | Found using: diff <(git grep -l '#include <cpu/x86/lapic.h>' -- src/) <(git grep -l 'xapic_read\|xapic_write\|xapic_send_ipi\|xapic_busy\|x2apic_read\|x2apic_write\|x2apic_send_ipi\|is_x2apic_mode\|lapic_read\|lapic_write\|lapic_update32\|lapic_send_ipi\|lapic_busy\|initial_lapicid\|lapicid\|stop_this_cpu\|enable_lapic\|disable_lapic\|setup_lapic' -- src/) |grep ">" Change-Id: Ie8fcf61a0604281c23cd3f589f1aa0cdbbd9366b Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/61048 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin L Roth <martinroth@google.com>
* drivers: Remove unused <acpi/acpi.h>Elyes HAOUAS2022-04-2412-12/+0
| | | | | | | | | | | Found using: diff <(git grep -l '#include <acpi/acpi.h>' -- src/) <(git grep -l 'SLP_EN\|SLP_TYP_SHIFT\|SLP_TYP\|SLP_TYP_S\|ACPI_TABLE_CREATOR\|OEM_ID\|ACPI_DSDT_REV_\|acpi_device_sleep_states\|ACPI_DEVICE_SLEEP\|RSDP_SIG\|ASLC\|ACPI_NAME_BUFFER_SIZE\|COREBOOT_ACPI_ID\|acpi_tables\|acpi_rsdp\|acpi_gen_regaddr\|ACPI_ADDRESS_SPACE\|ACPI_FFIXEDHW_\|ACPI_ACCESS_SIZE_\|ACPI_REG_MSR\|ACPI_REG_UNSUPPORTED\|ACPI_HID_\|acpi_table_header\|MAX_ACPI_TABLES\|acpi_rsdt\|acpi_xsdt\|acpi_hpet\|acpi_mcfg\|acpi_tcpa\|acpi_tpm2\|acpi_mcfg_mmconfig\|acpi_hmat\|acpi_hmat_mpda\|acpi_hmat_sllbi\|acpi_hmat_msci\|acpi_srat\|ACPI_SRAT_STRUCTURE_\|acpi_srat_lapic\|acpi_srat_mem\|acpi_srat_gia\|CPI_SRAT_GIA_DEV_HANDLE_\|acpi_slit\|acpi_madt\|acpi_lpit\|acpi_lpi_flags\|acpi_lpi_desc_type\|ACPI_LPI_DESC_TYPE_\|acpi_lpi_desc_hdr\|ACPI_LPIT_CTR_FREQ_TSC\|acpi_lpi_desc_ncst\|acpi_vfct_image_hdr\|acpi_vfct\|acpi_ivrs_info\|acpi_ivrs_ivhd\|acpi_ivrs\|acpi_crat_header\|ivhd11_iommu_attr\|acpi_ivrs_ivhd_11\|dev_scope_type\|SCOPE_PCI_\|SCOPE_IOAPIC\|SCOPE_MSI_HPET\|SCOPE_ACPI_NAMESPACE_DEVICE\|dev_scope\|dmar_type\|DMAR_\|DRHD_INCLUDE_PCI_ALL\|ATC_REQUIRED\|DMA_CTRL_PLATFORM_OPT_IN_FLAG\|dmar_entry\|dmar_rmrr_entry\|dmar_atsr_entry\|dmar_rhsa_entry\|dmar_andd_entry\|dmar_satc_entry\|acpi_dmar\|acpi_apic_types\|LOCAL_APIC,\|IO_APIC\|IRQ_SOURCE_OVERRIDE\|NMI_TYPE\|LOCAL_APIC_NMI\|LAPIC_ADDRESS_\|IO_SAPIC\|LOCAL_SAPIC\|PLATFORM_IRQ_SOURCES\|LOCAL_X2APIC\|GICC\|GICD\|GIC_MSI_FRAME\|GICR\|GIC_ITS\|acpi_madt_lapic\|acpi_madt_lapic_nmi\|ACPI_MADT_LAPIC_NMI_ALL_PROCESSORS\|acpi_madt_ioapic\|acpi_madt_irqoverride\|acpi_madt_lx2apic\|acpi_madt_lx2apic_nmi\|ACPI_DBG2_PORT_\|acpi_dbg2_header\|acpi_dbg2_device\|acpi_fadt\|ACPI_FADT_\|PM_UNSPECIFIED\|PM_DESKTOP\|PM_MOBILE\|PM_WORKSTATION\|PM_ENTERPRISE_SERVER\|PM_SOHO_SERVER\|PM_APPLIANCE_PC\|PM_PERFORMANCE_SERVER\|PM_TABLET\|acpi_facs\|ACPI_FACS_\|acpi_ecdt\|acpi_hest\|acpi_hest_esd\|acpi_hest_hen\|acpi_bert\|acpi_hest_generic_data\|acpi_hest_generic_data_v300\|HEST_GENERIC_ENTRY_V300\|ACPI_GENERROR_\|acpi_generic_error_status\|GENERIC_ERR_STS_\|acpi_cstate\|acpi_sw_pstate\|acpi_xpss_sw_pstate\|acpi_tstate\|acpi_lpi_state_flags\|ACPI_LPI_STATE_\|acpi_lpi_state\|acpi_upc_type\|UPC_TYPE_\|acpi_ipmi_interface_type\|IPMI_INTERFACE_\|ACPI_IPMI_\|acpi_spmi\|ACPI_EINJ_\|ACTION_COUNT\|BEGIN_INJECT_OP\|GET_TRIGGER_ACTION_TABLE\|SET_ERROR_TYPE\|GET_ERROR_TYPE\|END_INJECT_OP\|EXECUTE_INJECT_OP\|CHECK_BUSY_STATUS\|GET_CMD_STATUS\|SET_ERROR_TYPE_WITH_ADDRESS\|TRIGGER_ERROR\|READ_REGISTER\|READ_REGISTER_VALUE\|WRITE_REGISTER\|WRITE_REGISTER_VALUE\|NO_OP\|acpi_gen_regaddr1\|acpi_einj_action_table\|acpi_injection_header\|acpi_einj_trigger_table\|set_error_type\|EINJ_PARAM_NUM\|acpi_einj_smi\|EINJ_DEF_TRIGGER_PORT\|FLAG_PRESERVE\|FLAG_IGNORE\|EINJ_REG_MEMORY\|EINJ_REG_IO\|acpi_einj\|acpi_create_einj\|fw_cfg_acpi_tables\|preload_acpi_dsdt\|write_acpi_tables\|acpi_fill_madt\|acpi_fill_ivrs_ioapic\|acpi_create_ssdt_generator\|acpi_write_bert\|acpi_create_fadt\|acpi_fill_fadt\|arch_fill_fadt\|soc_fill_fadt\|mainboard_fill_fadt\|acpi_fill_gnvs\|acpi_fill_cnvs\|update_ssdt\|update_ssdtx\|acpi_fill_lpit\|acpi_checksum\|acpi_add_table\|acpi_create_madt_lapic\|acpi_create_madt_ioapic\|acpi_create_madt_irqoverride\|acpi_create_madt_lapic_nmi\|acpi_create_madt\|acpi_create_madt_lapics\|acpi_create_madt_lapic_nmis\|acpi_create_madt_lx2apic\|acpi_create_srat_lapic\|acpi_create_srat_mem\|acpi_create_srat_gia_pci\|acpi_create_mcfg_mmconfig\|acpi_create_srat_lapics\|acpi_create_srat\|acpi_create_slit\|acpi_create_hmat_mpda\|acpi_create_hmat\|acpi_create_vfct\|acpi_create_ipmi\|acpi_create_ivrs\|acpi_create_crat\|acpi_create_hpet\|acpi_write_hpet\|generate_cpu_entries\|acpi_create_mcfg\|acpi_create_facs\|acpi_create_dbg2\|acpi_write_dbg2_pci_uart\|acpi_create_dmar\|acpi_create_dmar_drhd\|acpi_create_dmar_rmrr\|acpi_create_dmar_atsr\|acpi_create_dmar_rhsa\|acpi_create_dmar_andd\|acpi_create_dmar_satc\|cpi_dmar_\|acpi_create_\|acpi_write_hest\|acpi_soc_get_bert_region\|acpi_resume\|mainboard_suspend_resume\|acpi_find_wakeup_vector\|ACPI_S\|acpi_sleep_from_pm1\|acpi_get_preferred_pm_profile\|acpi_get_sleep_type\|acpi_get_gpe\|permanent_smi_handler\|acpi_s3_resume_allowed\|acpi_is_wakeup_s3\|acpi_align_current\|get_acpi_table_revision' -- src/) |grep "<" Change-Id: Ic890dc7c0ed02891d3144210016cd96f01c344d5 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60632 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin L Roth <martinroth@google.com>
* drivers: Remove unused <cbmem.h>Elyes HAOUAS2022-04-222-2/+0
| | | | | | | | Change-Id: I1d4473d297871b2bc8b614926bcf7390660a3d0d Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/61051 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
* tpm: Refactor TPM Kconfig dimensionsJes B. Klinke2022-04-2110-90/+39
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Break TPM related Kconfig into the following dimensions: TPM transport support: config CRB_TPM config I2C_TPM config SPI_TPM config MEMORY_MAPPED_TPM (new) TPM brand, not defining any of these is valid, and result in "generic" support: config TPM_ATMEL (new) config TPM_GOOGLE (new) config TPM_GOOGLE_CR50 (new, implies TPM_GOOGLE) config TPM_GOOGLE_TI50 (new to be used later, implies TPM_GOOGLE) What protocol the TPM chip supports: config MAINBOARD_HAS_TPM1 config MAINBOARD_HAS_TPM2 What the user chooses to compile (restricted by the above): config NO_TPM config TPM1 config TPM2 The following Kconfigs will be replaced as indicated: config TPM_CR50 -> TPM_GOOGLE config MAINBOARD_HAS_CRB_TPM -> CRB_TPM config MAINBOARD_HAS_I2C_TPM_ATMEL -> I2C_TPM && TPM_ATMEL config MAINBOARD_HAS_I2C_TPM_CR50 -> I2C_TPM && TPM_GOOGLE config MAINBOARD_HAS_I2C_TPM_GENERIC -> I2C_TPM && !TPM_GOOGLE && !TPM_ATMEL config MAINBOARD_HAS_LPC_TPM -> MEMORY_MAPPED_TPM config MAINBOARD_HAS_SPI_TPM -> SPI_TPM && !TPM_GOOGLE && !TPM_ATMEL config MAINBOARD_HAS_SPI_TPM_CR50 -> SPI_TPM && TPM_GOOGLE Signed-off-by: Jes B. Klinke <jbk@chromium.org> Change-Id: I4656b2b90363b8dfd008dc281ad591862fe2cc9e Reviewed-on: https://review.coreboot.org/c/coreboot/+/63424 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
* drivers/intel/dptf: Add support for PROP methodVarshit B Pandya2022-04-202-4/+17
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add PROP method under \_SB.DPTF.TPWR scope which will return static worst case rest of platform power in miliWatts. This value is static, which has to configured from devicetree of overridetree for each platform BUG=b:205928013 TEST=Build, boot brya0 and dump SSDT to check PROP method Scope (\_SB) { Device (DPTF) { Device (TPWR) { Method (PROP, 0, Serialized) { Return (XXXX) } } } } Signed-off-by: Varshit B Pandya <varshit.b.pandya@intel.com> Change-Id: I1415d2a9eb55cfadc3a7b41b53ecbec657002759 Reviewed-on: https://review.coreboot.org/c/coreboot/+/63697 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
* drivers/usb/pci_xhci: Add Sabrina xhci pci device idKarthikeyan Ramasubramanian2022-04-191-0/+3
| | | | | | | | | | | | | | BUG=None TEST=Build and boot to OS in Skyrim. Ensure that the XHCI controllers are enumerated successfully and ACPI device objects are added in SSDT. Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Change-Id: I7ad4555212ed38ea0f9029275345e4945855a8c3 Reviewed-on: https://review.coreboot.org/c/coreboot/+/63641 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jon Murphy <jpmurphy@google.com> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
* drivers/usb/acpi: acpi_power_res_params: Add use_gpio_for_statusTim Van Patten2022-04-142-1/+8
| | | | | | | | | | | | | | | | | | | | | | Add the member `use_gpio_for_status` to the structure `drivers_usb_acpi_config`, so the `devicetree.cb` can specify it. This field is then used to initialize the corresponding field in the structure `acpi_power_res_params` in `usb_acpi_fill_ssdt_generator()`. The member `acpi_power_res_params::use_gpio_for_status()` is already being used by `acpi_device_add_power_res()` to determine which version of the `_STA()` method to output. BRANCH=None BUG=b:225022810 TEST=Dump SSDT table for guybrush Signed-off-by: Tim Van Patten <timvp@google.com> Change-Id: I69eb5f1ad79f3b2980f43dcf4a36585fca198ec9 Reviewed-on: https://review.coreboot.org/c/coreboot/+/63558 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
* drivers/i2c/designware/dw_i2c: Remove unnecessary tabs in debug logReka Norman2022-04-131-1/+1
| | | | | | | | | | | | | | | | | | | | | | Before: [DEBUG] dw_i2c: SoC 400/3000 ns Bus: 400/1000000 ns [DEBUG] dw_i2c: period 334 rise 13 fall 2 tlow 174 thigh 80 spk 7 [DEBUG] dw_i2c: hcnt = 104 lcnt = 202 sda hold = 7 After: [DEBUG] dw_i2c: SoC 400/3000 ns Bus: 400/1000000 ns [DEBUG] dw_i2c: period 334 rise 13 fall 2 tlow 174 thigh 80 spk 7 [DEBUG] dw_i2c: hcnt = 104 lcnt = 202 sda hold = 7 BUG=None TEST=Check that the formatting looks correct, as above. Change-Id: I6703a5d6512cee7848edae27afcfd82eb89bcacb Signed-off-by: Reka Norman <rekanorman@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/63563 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kangheui Won <khwon@chromium.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
* drivers/intel/fsp2_0: Allow coreboot to control FSP serial redirectionSubrata Banik2022-04-111-0/+12
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Commit 3ba6f8cdf (drivers/intel/fsp2_0: Add native implementation for FSP Debug Handler) implements a native FSP debug handler. However, coreboot still can't control when to redirect FSP debug output to the serial console, i.e., at present, integrating a FSP debug binary is enough to output FSP serial messages irrespective of whether user is intended to see FSP debug log. coreboot needs additional mechanism to control FSP debug binary to redirect debug messages over serial port. This patch introduces a config `FSP_ENABLE_SERIAL_DEBUG` to control the FSP debug output, user to enable this config from site-local config file in case like to override the default FSP serial redirection behaviour in more controlled way from coreboot. There could be scenarios as below: Scenario 1: coreboot release image integrated with the FSP debug binaries, is capable of redirecting to the serial console, but coreboot decides to override the config as below to skip FSP debug output redirection to the serial port. `#`FSP Serial console disabled by default (do not remove) `#`CONFIG_FSP_ENABLE_SERIAL_DEBUG is not set Scenario 2: For coreboot serial image with FSP debug binaries integrated but coreboot decides to skip FSP debug output redirection to the serial port. `#`FSP Serial console disabled by default (do not remove) `#`CONFIG_FSP_ENABLE_SERIAL_DEBUG is not set CONFIG_CONSOLE_SERIAL=y CONFIG_CONSOLE_SERIAL_115200=y CONFIG_UART_DEBUG=y CONFIG_UART_FOR_CONSOLE=0 Scenario 3: The final image could be a coreboot serial image with FSP serial redirection enabled to output to the serial port. CONFIG_FSP_ENABLE_SERIAL_DEBUG=y CONFIG_CONSOLE_SERIAL=y CONFIG_CONSOLE_SERIAL_115200=y CONFIG_UART_DEBUG=y CONFIG_UART_FOR_CONSOLE=0 BUG=b:227151510 TEST=Able to build and boot google/redrix with all scenarios between #1--#3 and able to meet the expectation as mentioned above. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: I0b008ca9d4f40bfa6a989a6fd655c234f91fde65 Reviewed-on: https://review.coreboot.org/c/coreboot/+/63166 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
* drivers/amd/agesa/romstage.c: Move timestamp and console init upArthur Heymans2022-04-071-4/+4
| | | | | | | | | | Follow-up commits move this to a common place. Change-Id: I26a37f9384a581a8a750efccc2100a5c6a6f0f85 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55066 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
* drivers/intel/fsp1_1: Rename hob finding functionsArthur Heymans2022-04-065-12/+12
| | | | | | | | | | | The hob finding functions are never looped over so there is no point for the 'next' inside their name. Change-Id: I18e452d313612ba14edda479d43f2797f6c84034 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/63204 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
* drivers/intel/dptf: Add support for Battery participantVarshit B Pandya2022-04-053-0/+33
| | | | | | | | | | | | | | | | | | | | | | | | | | | As per Intel Dynamic Tuning revision 1.3.13 (Doc no: 541817) add support for TBAT device under \_SB.DPTF BUG=b:205928013 TEST=Build, boot brya0 and dump SSDT to check TBAT device Device (TBAT) { Name (_HID, "INTC1061") // _HID: Hardware ID Name (_UID, "TBAT") // _UID: Unique ID Name (_STR, "Battery Participant") // _STR: Description String Name (PTYP, 0xC) Method (_STA, 0, NotSerialized) // _STA: Status { Return (0x0F) } } Signed-off-by: Varshit B Pandya <varshit.b.pandya@intel.com> Change-Id: I9104318fd838f30253ab1eeac4e212b3b917f516 Reviewed-on: https://review.coreboot.org/c/coreboot/+/63315 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
* drivers/wifi/generic/acpi.c: NULL-check pointers before dereferencingAngel Pons2022-04-041-4/+4
| | | | | | | | | | | | | | Checking whether a pointer is NULL after it has been dereferenced makes zero sense. Make sure the `wifi_ssdt_write_properties()` function never gets invoked with a NULL argument for the `dev` parameter, and simplify the logic around the `is_cnvi_ddr_rfim_enabled` variable accordingly. Change-Id: I3fbc9565e7e9b4e1c14a68f6a5fd779577045236 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/63340 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <felixsinger@posteo.net> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
* soc/intel/alderlake: Update CPU IDs with correct steppingsLean Sheng Tan2022-04-041-1/+1
| | | | | | | | | | | | Update ADL CPU IDs per correct steppings listed in Intel Doc 626774. Signed-off-by: Lean Sheng Tan <sheng.tan@9elements.com> Change-Id: I722043c493b8c3de8965bcaa13f33c907d51f284 Reviewed-on: https://review.coreboot.org/c/coreboot/+/63299 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
* {cpu/x86, drivers/amd}: Use `get_var_mtrr_count()` to get MTRR countSubrata Banik2022-04-021-2/+1
| | | | | | | | | | | | | | | | | This patch replaces the implementation that is used to get the number of variable MTRRs with `get_var_mtrr_count()` function. BUG=b:225766934 TEST=Able to build and boot google/redrix board to ChromeOS. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: I4751add9c45374e60b7a425df87d06f52e6fcb8c Reviewed-on: https://review.coreboot.org/c/coreboot/+/63219 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
* drivers/intel/fsp2_0: Add provision to extract FSP Performance DataSubrata Banik2022-04-025-0/+125
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch enriches coreboot FSP2.0 driver to extract the FSP timestamp from FPDT (Firmware Performance Data Table) and display right after FSP-S exits (from `fsp_silicon_init()` function), based on SoC user selects the required `DISPLAY_FSP_TIMESTAMPS` config. The prerequisite to this implementation is to have FSP binary built with `PcdFspPerformanceEnable` PCD set to `TRUE` to allow FSP to populate the FPDT HOB. BUG=b:216635831 TEST=Able to dump FSP performance data with DISPLAY_FSP_TIMESTAMPS Kconfig selected and met the FSP prerequisites. +--------------------------------------------------+ |------ FSP Performance Timestamp Table Dump ------| +--------------------------------------------------+ | Perf-ID Timestamp(ms) String/GUID | +--------------------------------------------------+ 0 460253 SEC/52c05b14-0b98-496c-bc3b04b50211d680 50 460263 PEI/52c05b14-0b98-496c-bc3b04b50211d680 40 460274 PreMem/52c05b14-0b98-496c-bc3b04b50211d680 1 495803 9b3ada4f-ae56-4c24-8deaf03b7558ae50 2 508959 9b3ada4f-ae56-4c24-8deaf03b7558ae50 1 515253 6141e486-7543-4f1a-a579ff532ed78e75 2 525453 6141e486-7543-4f1a-a579ff532ed78e75 1 532059 baeb5bee-5b33-480a-8ab7b29c85e7ceab 2 546806 baeb5bee-5b33-480a-8ab7b29c85e7ceab 1 553302 1b04374d-fa9c-420f-ac62fee6d45e8443 2 563859 1b04374d-fa9c-420f-ac62fee6d45e8443 1 569955 88c17e54-ebfe-4531-a992581029f58126 2 575753 88c17e54-ebfe-4531-a992581029f58126 1 582099 a8499e65-a6f6-48b0-96db45c266030d83 50f0 599599 unknown name/3112356f-cc77-4e82-86d53e25ee8192a4 50f1 716649 unknown name/3112356f-cc77-4e82-86d53e25ee8192a4 2 728507 a8499e65-a6f6-48b0-96db45c266030d83 1 734755 9e1cc850-6731-4848-87526673c7005eee .... Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: Ia1b7f6b98bafeec0afe843f0f78c99c2f34f50b3 Reviewed-on: https://review.coreboot.org/c/coreboot/+/62942 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kangheui Won <khwon@chromium.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
* arch/x86/postcar: Use a separate stack for C executionArthur Heymans2022-04-011-1/+1
| | | | | | | | | | | | Add a stack in .bss for C execution. This will make it easier to move the setup of MTRRs in C code. Change-Id: I67cbc988051036b1a0519cec9ed614acede31fd7 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/54298 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Raul Rangel <rrangel@chromium.org>
* drivers/intel/dptf: Add support for Power participantVarshit B Pandya2022-04-013-0/+31
| | | | | | | | | | | | | | | | | | | | | | | | | | As per Intel Dynamic Tuning revision 1.3.13 (Doc no: 541817) Add support for TPWR device under \_SB.DPTF BUG=b:205928013 TEST=Build, boot brya0 and dump SSDT to check TPWR device Device (TPWR) { Name (_HID, "INTC1060") // _HID: Hardware ID Name (_UID, "TPWR") // _UID: Unique ID Name (_STR, "Power Participant") // _STR: Description String Name (PTYP, 0x11) Method (_STA, 0, NotSerialized) // _STA: Status { Return (0x0F) } } Signed-off-by: Varshit B Pandya <varshit.b.pandya@intel.com> Change-Id: I437e509f58df1777d75e5981f0a5a63095ccb6a3 Reviewed-on: https://review.coreboot.org/c/coreboot/+/62944 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* drivers/intel/fsp1_1: Reduce scope of functionsArthur Heymans2022-04-012-30/+1
| | | | | | | | | | Reduce scope of get_next_hob and drop unused functions. Change-Id: I81007295ed2d1592c4d829cbb277c0726d89ea4b Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/63203 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
* drivers/intel/fsp1_1: Fix code not working with strict-aliasing rulesPatrick Rudolph2022-03-311-17/+5
| | | | | | | | | Change-Id: Ifc95a093cf86c834d63825bf76312ed21ec68215 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/62995 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Frans Hendriks <fhendriks@eltan.com> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
* drivers/tpm: Force enable long IRQ pulses for Ti50 versions under 0.15.Reka Norman2022-03-301-0/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Only Cr50 versions starting at 0.5.5 support long IRQ pulses, so this feature is enabled based on the value of the board_cfg register (see CB:61722). However, Ti50 versions below 0.0.15 don't support the board_cfg register, and trying to access it will cause I2C errors (see CB:63011). Also, all Ti50 versions only support long IRQ pulses. Therefore, add a workaround to force enable long IRQ pulses for boards using Ti50 versions under 0.0.15, instead of enabling it based on board_cfg. This workaround will be removed once all Ti50 stocks are updated to 0.0.15 or higher. BUG=b:225941781 TEST=Boot nivviks and nereid to OS with Ti50 0.0.14 and check there are none of these I2C errors: [ERROR] I2C stop bit not received [ERROR] cr50_i2c_read: Address write failed [ERROR] cr50_i2c_tis_status: Failed to read status Change-Id: Iaba71461d8ec79e8d6efddbd505339cdf1176485 Signed-off-by: Reka Norman <rekanorman@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/63160 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Kangheui Won <khwon@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* src: Remove unused <bootmode.h>Elyes HAOUAS2022-03-271-1/+0
| | | | | | | | | | | Found using: diff <(git grep -l '#include <bootmode.h>' -- src/) <(git grep -l 'platform_is_resuming\|gfx_set_init_done\|gfx_get_init_done\|display_init_required\|get_ec_is_trusted\|get_lid_switch\|get_wipeout_mode_switch\|clear_recovery_mode_switch\|get_recovery_mode_retrain_switch\|get_recovery_mode_switch\|get_recovery_mode_retrain_switch\|get_recovery_mode_switch\|get_write_protect_state\|init_bootmode_straps' -- src/) |grep "<" Change-Id: I2ebd472e0cfc641bd7e465b8d29272fd2f7520a1 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60911 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Hung-Te Lin <hungte@chromium.org>
* drivers/intel/fsp2_0: Add native implementation for FSP Debug HandlerSubrata Banik2022-03-254-0/+56
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch implements coreboot native debug handler to manage the FSP event messages. `FSP Event Handlers` feature introduced in FSP to generate event messages to aid in the debugging of firmware issues. This eliminates the need for FSP to directly write debug messages to the UART and FSP might not need to know the board related UART port configuration. Instead FSP signals the bootloader to inform it of a new debug message. This allows the coreboot to provide board specific methods of reporting debug messages, example: legacy UART or LPSS UART etc. This implementation has several advantages as: 1. FSP relies on XIP `DebugLib` driver even while printing FSP-S debug messages, hence, without ROM being cached, post `romstage` would results into sluggish boot with FSP debug enabled. This patch utilities coreboot native debug implementation which is XIP during FSP-M and relocatable to DRAM based resource for FSP-S. 2. This patch simplifies the FSP DebugLib implementation and remove the need to have serial port library. Instead coreboot `printk` can be used for display FSP serial messages. Additionally, unifies the debug library between coreboot and FSP. 3. This patch is also useful to get debug prints even with FSP non-serial image (refer to `Note` below) as FSP PEIMs are now leveraging coreboot debug library instead FSP `NULL` DebugLib reference for release build. 4. Can optimize the FSP binary size by removing the DebugLib dependency from most of FSP PEIMs, for example: on Alder Lake FSP-M debug binary size is reduced by ~100KB+ and FSP-S debug library size is also reduced by ~300KB+ (FSP-S debug and release binary size is exactly same with this code changes). The total savings is ~400KB for each FSP copy, and in case of Chrome AP firmware with 3 copies, the total savings would be 400KB * 3 = ~1.2MB. Note: Need to modify FSP source code to remove `MDEPKG_NDEBUG` as compilation flag for release build and generate FSP binary with non-NULL FSP debug wrapper module injected (to allow FSP event handler to execute even with FSP non-serial image) in the final FSP.fd. BUG=b:225544587 TEST=Able to build and boot brya. Also, verified the FSP debug log is exactly same before and with this code change. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: I1018e67d70492b18c76531f9e78d3b58fa435cd4 Reviewed-on: https://review.coreboot.org/c/coreboot/+/63007 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
* drivers/intel/fsp2_0: Add support for FSP_NON_VOLATILE_STORAGE_HOB2Anil Kumar2022-03-252-0/+21
| | | | | | | | | | | | | | | | | | | | | | | | | | | | FSP 2.3 spec introduced new version of NV storage HOB FSP_NON_VOLATILE_STORAGE_HOB2. This new HOB addresses the limitation of FSP_NON_VOLATILE_STORAGE_HOB which can support data length upto 64KB. FSP_NON_VOLATILE_STORAGE_HOB2 allows >64KB of NVS data to be stored by specifying a pointer to the NVS data. FSP_NON_VOLATILE_STORAGE_HOB HOB is deprecated from FSP 2.3 onwards and is maintained for backward compatibility only. This patch implements the parsing method for FSP_NON_VOLATILE_STORAGE_HOB2 HOB structure .The HOB list is first searched for FSP_NON_VOLATILE_STORAGE_HOB2. If not found we continue to search for FSP_NON_VOLATILE_STORAGE_HOB HOB. BUG=b:200113959 TEST=Verified on sapphire rapids and meteor lake FSP platform that introduces FSP_NON_VOLATILE_STORAGE_HOB2 for retrieving MRC cached data. Signed-off-by: Anil Kumar <anil.kumar.k@intel.com> Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: I27647e9ac1a4902256b3f1c34b60e1f0b787a06e Reviewed-on: https://review.coreboot.org/c/coreboot/+/59638 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
* drivers/i2c/tpm: Work around missing board_cfg in Ti50 FW under 0.15Eric Lai2022-03-252-1/+12
| | | | | | | | | | | | | | | | | | Ti50 FW under 0.15 is not support board cfg command which causes I2C errors and entering recovery mode. And ODM stocks are 0.12 pre-flashed. Add workaround for the old Ti50 chip. BUG=b:224650720 TEST=no I2C errors in coreboot. [ERROR] cr50_i2c_read: Address write failed [INFO ] .I2C stop bit not received Signed-off-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Change-Id: Ieec7842ca66b4c690df04a400cebcf45138c745d Reviewed-on: https://review.coreboot.org/c/coreboot/+/63011 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Kangheui Won <khwon@chromium.org>
* drivers/net/r8168: Add support for Realtek RTL8111KRaihow Shi2022-03-241-0/+1
| | | | | | | | | | | | | | The Realtek RT8168 and RTL8111K have a similar programming interface, therefore add the PCI device ID for the RTL8111K into driver for support. BUG=b:226253265 TEST=emerge-brask coreboot chromeos-bootimage. Signed-off-by: Raihow Shi <raihow_shi@wistron.corp-partner.google.com> Change-Id: I5ad8f14483393d6f25026847cc0d4229d362bba0 Reviewed-on: https://review.coreboot.org/c/coreboot/+/63013 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Zhuohao Lee <zhuohao@google.com>
* driver/wifi: Add _DSM method for DDRRFIMVarshit B Pandya2022-03-241-6/+66
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | coreboot needs to propagate the CnviDdrRfim value info of the feature enable/disable state into the CNVi via the WiFi DSM ACPI object. This will be consumed by the Wi-Fi driver and it will act according to CB enablement configuration. This patch adds _DSM method for that. Add support for following 2 functions in _DSM method - Function 0: Function Support Query Returns a bitmask of functions supported. - Function 3: RFI enablement 0 Feature Enable 1 Feature Disable Note: Wifi Dsm already has provision for SAR. This patch will add additional support to return RFIM structure based on UUID. BUG=b:201724512 TEST=Build, boot brya0 and dump SSDT entries Method (_DSM, 4, Serialized) // _DSM: Device-Specific Method { ToBuffer (Arg0, Local0) If ((Local0 == ToUUID ("7266172c-220b-4b29-814f-75e4dd26b5fd"))) { ToInteger (Arg2, Local1) If ((Local1 == Zero)) { Return (Buffer (One) { 0x09 }) } If ((Local1 == One)){} If ((Local1 == 0x02)){} If ((Local1 == 0x03)) { Return (Zero) } Return (Buffer (One) { 0x00 }) } Return (Buffer (One) { 0x00 }) } Signed-off-by: Varshit B Pandya <varshit.b.pandya@intel.com> Change-Id: I217b736df3d4224a6732d1941a160abcddbd8f37 Reviewed-on: https://review.coreboot.org/c/coreboot/+/61020 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Ronak Kanabar <ronak.kanabar@intel.com> Reviewed-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
* drivers/pc80/tpm/tis.c: Use fixed TPM ACPI pathMichał Kopeć2022-03-231-6/+2
| | | | | | | | | | | | | | | | | | Windows 11 installer expects the TPM to reside under \\_SB_.PCI0 in ACPI device hierarchy, otherwise the TPM is not detected. Hardcode the path to fix the issue. TEST=Boot Windows 11 on Clevo NV41MZ and see the TPM is detected correctly TEST=Boot Ubuntu 20.04 on Clevo NV41MZ and see the TPM is detected correctly Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com> Signed-off-by: Michał Kopeć <michal.kopec@3mdeb.com> Change-Id: If0b3136e3eb8eb1bb132132a5f3a7034bdd3b424 Reviewed-on: https://review.coreboot.org/c/coreboot/+/62493 Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* drivers/tpm/cr50: Use cr50_get_firmware_version in get_board_cfgTim Wawrzynczak2022-03-221-5/+13
| | | | | | | | | | | | | | | | | | | | | | | | cr50_get_board_cfg() may be called in ramstage for some mainboards in order to determine the BOARD_CFG register's value. The code was written assuming that the firmware version was already retrieved, but for boards calling this in ramstage, this is not the case. Therefore, instead of using the cached cr50_firmware_version (which is all 0s in ramstage at that time), use the cr50_get_firmware_version function instead. BUG=b:225206079, b:220685274 BRANCH=firmware-brya-14505.B TEST=boot on brya0 and see: [INFO ] Firmware version: B2-C:0 RO_B:0.0.11/4d655eab RW_B:0.6.93/cr50_v3.94 [INFO ] Enabling GPIO PM b/c CR50 has long IRQ pulse support in the logs. Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Change-Id: Ia6e5f4965a8852793d2f95e6eb21ea87860335a9 Reviewed-on: https://review.coreboot.org/c/coreboot/+/62964 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-by: Subrata Banik <subratabanik@google.com>
* drivers/genesyslogic/gl9763e: Add set L1 entry delay to Max for GL9763EBen Chuang2022-03-223-1/+13
| | | | | | | | | | | | | | | | | | | Add an option to set L1 entry delay to Max for GL9763E. The L1 entry delay will be changed to expected value by sdhci-pci-gli driver in Linux v5.14. BUG=b:220079865 TEST=build and verify the value of GL9763E's 0x8A4[28:19] register is 0x3FF. Change-Id: I19d4dfb7b873d09ff30ad4d2d63b876047c21601 Signed-off-by: Ben Chuang <benchuanggli@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/62917 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Peichao Wang <pwang12@lenovo.corp-partner.google.com> Reviewed-by: Martin L Roth <martinroth@google.com>
* drivers/i2c/cs35l53: Add driver for generating device in SSDTStefan Binding2022-03-184-0/+300
| | | | | | | | | | | | | | | | | | | This patch is adding support for Cirrus Logic CS35l41/CS35l53 smart amplifier. This part is now used in number of new chromebook's HW designs by several vendors. This driver uses the ACPI Device Property interface to generate the required parameters into the _DSD table format expected by the kernel. For detailed information about these properties, please check Linux kernel documentation: /Documentation/devicetree/bindings/sound/cirrus,cs35l41.yaml Change-Id: I2cbb1cef89f8d56ee73fab06c68933a2ab8c3606 Signed-off-by: Stefan Binding <sbinding@opensource.cirrus.com> Signed-off-by: Vitaly Rodionov <vitaly.rodionov@cirrus.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/61448 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
* Revert "Revert "drivers/intel/fsp2_0: Allow `mp_startup_all_cpus()` to run ↵Nick Vaccaro2022-03-181-4/+17
| | | | | | | | | | | | | | | | | | | | | | | | | | | | serially"" This reverts a change that was causing hangs and exceptions during boot on an ADL brya4es. The hang (or APIC exception) occurs at what appears to be the FSP MP initialization sequence, prior to the "Display FSP Version Info HOB" log being displayed : [DEBUG] Detected 10 core, 12 thread CPU. [DEBUG] Display FSP Version Info HOB This reverts commit 40ca79714ad7d5f2aa201d83db4d97f21260d924. BUG=b:224873032 TEST=`emerge-brya coreboot chromeos-bootimage`, flash and verify brya4es is able to successfully reboot 200 times without any issues. Change-Id: I88c15a51c5d27fbd243478c923e75962d3f8d67d Signed-off-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/62907 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Ronak Kanabar <ronak.kanabar@intel.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
* drivers/wifi/generic: Fix properties in generic-under-PCI device caseTim Wawrzynczak2022-03-172-26/+31
| | | | | | | | | | | | | | | | | | | | | | In the devicetree case where a generic device underneath the Intel PCI CNVi device carries the device properties, the incorrect device was passed to wifi_ssdt_write_properties. Also while here, update the UUID for `DmaProperty` to match what Microsoft defined here: https://docs.microsoft.com/en-us/windows-hardware/drivers/pci/dsd-for-pcie-root-ports BUG=b:215424986, b:220639445 TEST=dump SSDT and see that _PRW for CNVi device is no longer garbage, but contains the value from the devicetree (GPE0_PME_B0). Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Change-Id: Iafd86458d2f65ccb7e74d1308d37fd3ebbf7f520 Reviewed-on: https://review.coreboot.org/c/coreboot/+/62746 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: YH Lin <yueherngl@google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Varshit B Pandya <varshit.b.pandya@intel.com>
* driver/intel/usb4/retimer: Change loglevel prefixWisley Chen2022-03-171-1/+1
| | | | | | | | | | | | | | | | In usb4_retimer_fill_ssdt(), it search all dpf ports and shows message in not support dpf ports. It's not error and changes the loglevel prefix to BIOS_INFO. BUG=b:222038287 BRANCH=firmware-brya-14505.B TEST=emerge-brya coreboot Signed-off-by: Wisley Chen <wisley.chen@quanta.corp-partner.google.com> Change-Id: I508ec7662e078893f944edb3d68364c57d5c5a73 Reviewed-on: https://review.coreboot.org/c/coreboot/+/62822 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
* drivers/wifi/generic: Fix is_cnvi functionEric Lai2022-03-171-4/+0
| | | | | | | | | | | | | | | | dev->ops = &wifi_cnvi_ops need is_cnvi be true. This cause the exclusive statement so is_cnvi never be true in !DEVTREE_EARLY. BUG=b:224317408 TEST=no assertion in coreboot. [EMERG] ASSERTION ERROR: file 'src/acpi/acpigen_pci.c', line 24 Signed-off-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Change-Id: I1ca6312ce164c43021686b483f6579164614cede Reviewed-on: https://review.coreboot.org/c/coreboot/+/62784 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kangheui Won <khwon@chromium.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
* i2c: Add configurable I2C transfer timeoutJes Klinke2022-03-151-4/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | This patch introduces CONFIG_I2C_TRANSFER_TIMEOUT_US, which controls how long to wait for an I2C devices to produce/accept all the data bytes in a single transfer. (The device can delay transfer by stretching the clock of the ack bit.) The default value of this new setting is 500ms. Existing code had timeouts anywhere from tens of milliseconds to a full second beween various drivers. Drivers can still have their own shorter timeouts for setup/communication with the I2C host controller (as opposed to transactions with I2C devices on the bus.) In general, the timeout is not meant to be reached except in situations where there is already serious problem with the boot, and serves to make sure that some useful diagnostic output is produced on the console. Change-Id: I6423122f32aad1dbcee0bfe240cdaa8cb512791f Signed-off-by: Jes B. Klinke <jbk@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/62278 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
* drivers/pcie/generic: Add support to generate code under companion device ↵Cliff Huang2022-03-102-8/+27
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | instead Only one ACPI device should be added to a PCIe root port. For the root ports which already have device created, the generated code from this driver needs to be merged with the existing device. By default, this driver will create new device named DEV0. This change allows to generate code under an existing device. ex: (generate code under PXSX): Scope (\_SB.PCI0.RP01.PXSX) { Name (_DSD, Package (0x02) // _DSD: Device-Specific Data { ToUUID ("daffd814-6eba-4d8c-8a91-bc9bbf4aa301") Package (0x01) { Package (0x02) { "UntrustedDevice", One } } }) } BUG=b:221250331 BRANCH=firmware-brya-14505.B Signed-off-by: Cliff Huang <cliff.huang@intel.com> Change-Id: I80634bbfc2927f26f2a55a9c244eca517c437079 Reviewed-on: https://review.coreboot.org/c/coreboot/+/62301 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
* Revert "drivers/intel/fsp2_0: Allow `mp_startup_all_cpus()` to run serially"Ronak Kanabar2022-03-101-17/+4
| | | | | | | | | | | This reverts commit 6af980a2aeca9b8cedfb3d7734389e6e36099c88. BUG=b:199246420 Change-Id: Iddb7aa6d52b563485a496798f2fe31ed64b4f4a8 Signed-off-by: Ronak Kanabar <ronak.kanabar@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/61498 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
* soc/intel/common: Include Meteor Lake device IDsWonkyu Kim2022-03-091-0/+1
| | | | | | | | | | Reference: chapter2 in Meteor Lake EDS vol1 (640228) Signed-off-by: Wonkyu Kim <wonkyu.kim@intel.com> Change-Id: Ie71abb70b88db0acec8a320c3e2c20c54bbb4a8a Reviewed-on: https://review.coreboot.org/c/coreboot/+/62581 Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* drivers/wifi,soc/intel/adl: Move CnviDdrRfim property to driversTim Wawrzynczak2022-03-094-4/+46
| | | | | | | | | | | | | | Some non-SoC code might want to know whether or not the CNVi DDR RFIM feature is enabled. Also note that future SoCs may also support this feature. To make the CnviDdrRfim property generic, move it from soc/intel/alderlake to drivers/wifi/generic instead. Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Change-Id: Idf9fba0a79d1f431269be5851b026ed966600160 Reviewed-on: https://review.coreboot.org/c/coreboot/+/61638 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com> Reviewed-by: Varshit B Pandya <varshit.b.pandya@intel.com>
* {drivers/security}: Replace `cb_err_t` with `enum cb_err`Subrata Banik2022-03-094-11/+11
| | | | | | | | | | | | | | | | This patch replaces remaining `cb_err_t` with `enum cb_err` after commit hash 69cc557c (commonlib/bsd: Remove cb_err_t) removes majority of `cb_err_t` instances. TEST=Able to build the brya. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: I3392f9c2cfb4a889a999c8ea25066c89979f0900 Reviewed-on: https://review.coreboot.org/c/coreboot/+/62676 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
* commonlib/bsd: Remove cb_err_tJulius Werner2022-03-093-16/+16
| | | | | | | | | | | | | | | | | cb_err_t was meant to be used in place of `enum cb_err` in all situations, but the choice to use a typedef here seems to be controversial. We should not be arbitrarily using two different identifiers for the same thing across the codebase, so since there are no use cases for serializing enum cb_err at the moment (which would be the primary reason to typedef a fixed-width integer instead), remove cb_err_t again for now. Signed-off-by: Julius Werner <jwerner@chromium.org> Change-Id: Iaec36210d129db26d51f0a105d3de070c03b686b Reviewed-on: https://review.coreboot.org/c/coreboot/+/62600 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
* timestamps: Rename timestamps to make names more consistentJakub Czapiga2022-03-087-31/+31
| | | | | | | | | | | | | | | | | | This patch aims to make timestamps more consistent in naming, to follow one pattern. Until now there were many naming patterns: - TS_START_*/TS_END_* - TS_BEFORE_*/TS_AFTER_* - TS_*_START/TS_*_END This change also aims to indicate, that these timestamps can be used to create time-ranges, e.g. from TS_BOOTBLOCK_START to TS_BOOTBLOCK_END. Signed-off-by: Jakub Czapiga <jacz@semihalf.com> Change-Id: I533e32392224d9b67c37e6a67987b09bf1cf51c6 Reviewed-on: https://review.coreboot.org/c/coreboot/+/62019 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com> Reviewed-by: Raul Rangel <rrangel@chromium.org>
* drivers/intel/i210: Set log level to BIOS_NOTICE on missing MAC addressWerner Zeh2022-03-081-1/+1
| | | | | | | | | | | | | | | Set the log level to BIOS_NOTICE for the case where the mainboard can not provide a MAC address since this can be a valid case. Showing this message with log level BIOS_ERR is not appropriate. In addition, rephrase the message to make clear that if the mainboard does not provide a MAC address the one stored in the MAC will be used. Change-Id: Ibfc58845f0ea47ced048b446e685c4860a29f075 Signed-off-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/62008 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
* drivers/tpm/cr50: Add I2C bus support to cr50 driverTim Wawrzynczak2022-03-072-5/+36
| | | | | | | | | | | | | | This allows mainboards using an I2C bus to communicate with the cr50 to reuse the functionality related to firmware version and BOARD_CFG. BUG=b:202246591 TEST=boot on brya0, see cr50 FW version in logs Change-Id: Ide1a7299936193da3cd3d15fdfd1a80994d70da0 Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/62059 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
* drivers/tpm/spi: Refactor out some cr50-specific logicTim Wawrzynczak2022-03-075-161/+243
| | | | | | | | | | | | | | | | | | | Mainboards accessing the cr50 over an I2C bus may want to reuse some of the same firmware version and BOARD_CFG logic, therefore refactor this logic out into a bus-agnostic file, drivers/tpm/cr50.c. This file uses the new tis_vendor_read/write() functions in order to access the cr50 regardless of the bus which is physically used. In order to leave SPI devices intact, the tis_vendor_* functions are added to the SPI driver. BUG=b:202246591 TEST=boot to OS on google/dratini, see the same FW version and board_cfg console prints as before the change. Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Change-Id: Ie68618cbe026a2b9221f93d0fe41d0b2054e8091 Reviewed-on: https://review.coreboot.org/c/coreboot/+/61977 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com>
generated by cgit v1.2.3 (git 2.25.1) at 2024-06-19 00:08:58 +0000